drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 /* definitions used for the EHCI driver */
  23
  24 /* statistics can be kept for for tuning/monitoring */
  25 struct ehci_stats {
  26         /* irq usage */
  27         unsigned long           normal;
  28         unsigned long           error;
  29         unsigned long           reclaim;
  30         unsigned long           lost_iaa;
  31
  32         /* termination of urbs from core */
  33         unsigned long           complete;
  34         unsigned long           unlink;
  35 };
  36
  37 /* ehci_hcd->lock guards shared data against other CPUs:
  38  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  39  *   usb_host_endpoint: hcpriv
  40  *   ehci_qh:   qh_next, qtd_list
  41  *   ehci_qtd:  qtd_list
  42  *
  43  * Also, hold this lock when talking to HC registers or
  44  * when updating hw_* fields in shared qh/qtd/... structures.
  45  */
  46
  47 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  48
  49 struct ehci_hcd {                       /* one per controller */
  50         /* glue to PCI and HCD framework */
  51         struct ehci_caps __iomem *caps;
  52         struct ehci_regs __iomem *regs;
  53         struct ehci_dbg_port __iomem *debug;
  54
  55         __u32                   hcs_params;     /* cached register copy */
  56         spinlock_t              lock;
  57
  58         /* async schedule support */
  59         struct ehci_qh          *async;
  60         struct ehci_qh          *reclaim;
  61         unsigned                reclaim_ready : 1;
  62         unsigned                scanning : 1;
  63
  64         /* periodic schedule support */
  65 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  66         unsigned                periodic_size;
  67         __le32                  *periodic;      /* hw periodic table */
  68         dma_addr_t              periodic_dma;
  69         unsigned                i_thresh;       /* uframes HC might cache */
  70
  71         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  72         int                     next_uframe;    /* scan periodic, start here */
  73         unsigned                periodic_sched; /* periodic activity count */
  74
  75         /* per root hub port */
  76         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
  77         /* bit vectors (one bit per port) */
  78         unsigned long           bus_suspended;          /* which ports were
  79                         already suspended at the start of a bus suspend */
  80         unsigned long           companion_ports;        /* which ports are
  81                         dedicated to the companion controller */
  82
  83         /* per-HC memory pools (could be per-bus, but ...) */
  84         struct dma_pool         *qh_pool;       /* qh per active urb */
  85         struct dma_pool         *qtd_pool;      /* one or more per qh */
  86         struct dma_pool         *itd_pool;      /* itd per iso urb */
  87         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
  88
  89         struct timer_list       watchdog;
  90         unsigned long           actions;
  91         unsigned                stamp;
  92         unsigned long           next_statechange;
  93         u32                     command;
  94
  95         /* SILICON QUIRKS */
  96         unsigned                is_tdi_rh_tt:1; /* TDI roothub with TT */
  97         unsigned                no_selective_suspend:1;
  98         unsigned                has_fsl_port_bug:1; /* FreeScale */
  99         unsigned                big_endian_mmio:1;
 100
 101         u8                      sbrn;           /* packed release number */
 102
 103         /* irq statistics */
 104 #ifdef EHCI_STATS
 105         struct ehci_stats       stats;
 106 #       define COUNT(x) do { (x)++; } while (0)
 107 #else
 108 #       define COUNT(x) do {} while (0)
 109 #endif
 110 };
 111
 112 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 113 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 114 {
 115         return (struct ehci_hcd *) (hcd->hcd_priv);
 116 }
 117 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 118 {
 119         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 120 }
 121
 122
 123 enum ehci_timer_action {
 124         TIMER_IO_WATCHDOG,
 125         TIMER_IAA_WATCHDOG,
 126         TIMER_ASYNC_SHRINK,
 127         TIMER_ASYNC_OFF,
 128 };
 129
 130 static inline void
 131 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 132 {
 133         clear_bit (action, &ehci->actions);
 134 }
 135
 136 static inline void
 137 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
 138 {
 139         if (!test_and_set_bit (action, &ehci->actions)) {
 140                 unsigned long t;
 141
 142                 switch (action) {
 143                 case TIMER_IAA_WATCHDOG:
 144                         t = EHCI_IAA_JIFFIES;
 145                         break;
 146                 case TIMER_IO_WATCHDOG:
 147                         t = EHCI_IO_JIFFIES;
 148                         break;
 149                 case TIMER_ASYNC_OFF:
 150                         t = EHCI_ASYNC_JIFFIES;
 151                         break;
 152                 // case TIMER_ASYNC_SHRINK:
 153                 default:
 154                         t = EHCI_SHRINK_JIFFIES;
 155                         break;
 156                 }
 157                 t += jiffies;
 158                 // all timings except IAA watchdog can be overridden.
 159                 // async queue SHRINK often precedes IAA.  while it's ready
 160                 // to go OFF neither can matter, and afterwards the IO
 161                 // watchdog stops unless there's still periodic traffic.
 162                 if (action != TIMER_IAA_WATCHDOG
 163                                 && t > ehci->watchdog.expires
 164                                 && timer_pending (&ehci->watchdog))
 165                         return;
 166                 mod_timer (&ehci->watchdog, t);
 167         }
 168 }
 169
 170 /*-------------------------------------------------------------------------*/
 171
 172 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 173
 174 /* Section 2.2 Host Controller Capability Registers */
 175 struct ehci_caps {
 176         /* these fields are specified as 8 and 16 bit registers,
 177          * but some hosts can't perform 8 or 16 bit PCI accesses.
 178          */
 179         u32             hc_capbase;
 180 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 181 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 182         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 183 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 184 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 185 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 186 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 187 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 188 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 189 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 190
 191         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 192 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 193 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 194 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 195 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 196 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 197 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 198         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 199 } __attribute__ ((packed));
 200
 201
 202 /* Section 2.3 Host Controller Operational Registers */
 203 struct ehci_regs {
 204
 205         /* USBCMD: offset 0x00 */
 206         u32             command;
 207 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 208 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 209 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 210 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 211 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 212 #define CMD_ASE         (1<<5)          /* async schedule enable */
 213 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 214 /* 3:2 is periodic frame list size */
 215 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 216 #define CMD_RUN         (1<<0)          /* start/stop HC */
 217
 218         /* USBSTS: offset 0x04 */
 219         u32             status;
 220 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 221 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 222 #define STS_RECL        (1<<13)         /* Reclamation */
 223 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 224 /* some bits reserved */
 225         /* these STS_* flags are also intr_enable bits (USBINTR) */
 226 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 227 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 228 #define STS_FLR         (1<<3)          /* frame list rolled over */
 229 #define STS_PCD         (1<<2)          /* port change detect */
 230 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 231 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 232
 233         /* USBINTR: offset 0x08 */
 234         u32             intr_enable;
 235
 236         /* FRINDEX: offset 0x0C */
 237         u32             frame_index;    /* current microframe number */
 238         /* CTRLDSSEGMENT: offset 0x10 */
 239         u32             segment;        /* address bits 63:32 if needed */
 240         /* PERIODICLISTBASE: offset 0x14 */
 241         u32             frame_list;     /* points to periodic list */
 242         /* ASYNCLISTADDR: offset 0x18 */
 243         u32             async_next;     /* address of next async queue head */
 244
 245         u32             reserved [9];
 246
 247         /* CONFIGFLAG: offset 0x40 */
 248         u32             configured_flag;
 249 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 250
 251         /* PORTSC: offset 0x44 */
 252         u32             port_status [0];        /* up to N_PORTS */
 253 /* 31:23 reserved */
 254 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 255 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 256 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 257 /* 19:16 for port testing */
 258 #define PORT_LED_OFF    (0<<14)
 259 #define PORT_LED_AMBER  (1<<14)
 260 #define PORT_LED_GREEN  (2<<14)
 261 #define PORT_LED_MASK   (3<<14)
 262 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 263 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 264 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 265 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 266 /* 9 reserved */
 267 #define PORT_RESET      (1<<8)          /* reset port */
 268 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 269 #define PORT_RESUME     (1<<6)          /* resume it */
 270 #define PORT_OCC        (1<<5)          /* over current change */
 271 #define PORT_OC         (1<<4)          /* over current active */
 272 #define PORT_PEC        (1<<3)          /* port enable change */
 273 #define PORT_PE         (1<<2)          /* port enable */
 274 #define PORT_CSC        (1<<1)          /* connect status change */
 275 #define PORT_CONNECT    (1<<0)          /* device connected */
 276 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 277 } __attribute__ ((packed));
 278
 279 /* Appendix C, Debug port ... intended for use with special "debug devices"
 280  * that can help if there's no serial console.  (nonstandard enumeration.)
 281  */
 282 struct ehci_dbg_port {
 283         u32     control;
 284 #define DBGP_OWNER      (1<<30)
 285 #define DBGP_ENABLED    (1<<28)
 286 #define DBGP_DONE       (1<<16)
 287 #define DBGP_INUSE      (1<<10)
 288 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 289 #       define DBGP_ERR_BAD     1
 290 #       define DBGP_ERR_SIGNAL  2
 291 #define DBGP_ERROR      (1<<6)
 292 #define DBGP_GO         (1<<5)
 293 #define DBGP_OUT        (1<<4)
 294 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 295         u32     pids;
 296 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 297 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 298         u32     data03;
 299         u32     data47;
 300         u32     address;
 301 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 302 } __attribute__ ((packed));
 303
 304 /*-------------------------------------------------------------------------*/
 305
 306 #define QTD_NEXT(dma)   cpu_to_le32((u32)dma)
 307
 308 /*
 309  * EHCI Specification 0.95 Section 3.5
 310  * QTD: describe data transfer components (buffer, direction, ...)
 311  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 312  *
 313  * These are associated only with "QH" (Queue Head) structures,
 314  * used with control, bulk, and interrupt transfers.
 315  */
 316 struct ehci_qtd {
 317         /* first part defined by EHCI spec */
 318         __le32                  hw_next;          /* see EHCI 3.5.1 */
 319         __le32                  hw_alt_next;      /* see EHCI 3.5.2 */
 320         __le32                  hw_token;         /* see EHCI 3.5.3 */
 321 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 322 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 323 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 324 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 325 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 326 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 327 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 328 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 329 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 330 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 331 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 332 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 333 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 334         __le32                  hw_buf [5];        /* see EHCI 3.5.4 */
 335         __le32                  hw_buf_hi [5];        /* Appendix B */
 336
 337         /* the rest is HCD-private */
 338         dma_addr_t              qtd_dma;                /* qtd address */
 339         struct list_head        qtd_list;               /* sw qtd list */
 340         struct urb              *urb;                   /* qtd's urb */
 341         size_t                  length;                 /* length of buffer */
 342 } __attribute__ ((aligned (32)));
 343
 344 /* mask NakCnt+T in qh->hw_alt_next */
 345 #define QTD_MASK __constant_cpu_to_le32 (~0x1f)
 346
 347 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 348
 349 /*-------------------------------------------------------------------------*/
 350
 351 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 352 #define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
 353
 354 /* values for that type tag */
 355 #define Q_TYPE_ITD      __constant_cpu_to_le32 (0 << 1)
 356 #define Q_TYPE_QH       __constant_cpu_to_le32 (1 << 1)
 357 #define Q_TYPE_SITD     __constant_cpu_to_le32 (2 << 1)
 358 #define Q_TYPE_FSTN     __constant_cpu_to_le32 (3 << 1)
 359
 360 /* next async queue entry, or pointer to interrupt/periodic QH */
 361 #define QH_NEXT(dma)    (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
 362
 363 /* for periodic/async schedules and qtd lists, mark end of list */
 364 #define EHCI_LIST_END   __constant_cpu_to_le32(1) /* "null pointer" to hw */
 365
 366 /*
 367  * Entries in periodic shadow table are pointers to one of four kinds
 368  * of data structure.  That's dictated by the hardware; a type tag is
 369  * encoded in the low bits of the hardware's periodic schedule.  Use
 370  * Q_NEXT_TYPE to get the tag.
 371  *
 372  * For entries in the async schedule, the type tag always says "qh".
 373  */
 374 union ehci_shadow {
 375         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 376         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 377         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 378         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 379         __le32                  *hw_next;       /* (all types) */
 380         void                    *ptr;
 381 };
 382
 383 /*-------------------------------------------------------------------------*/
 384
 385 /*
 386  * EHCI Specification 0.95 Section 3.6
 387  * QH: describes control/bulk/interrupt endpoints
 388  * See Fig 3-7 "Queue Head Structure Layout".
 389  *
 390  * These appear in both the async and (for interrupt) periodic schedules.
 391  */
 392
 393 struct ehci_qh {
 394         /* first part defined by EHCI spec */
 395         __le32                  hw_next;         /* see EHCI 3.6.1 */
 396         __le32                  hw_info1;        /* see EHCI 3.6.2 */
 397 #define QH_HEAD         0x00008000
 398         __le32                  hw_info2;        /* see EHCI 3.6.2 */
 399 #define QH_SMASK        0x000000ff
 400 #define QH_CMASK        0x0000ff00
 401 #define QH_HUBADDR      0x007f0000
 402 #define QH_HUBPORT      0x3f800000
 403 #define QH_MULT         0xc0000000
 404         __le32                  hw_current;      /* qtd list - see EHCI 3.6.4 */
 405
 406         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 407         __le32                  hw_qtd_next;
 408         __le32                  hw_alt_next;
 409         __le32                  hw_token;
 410         __le32                  hw_buf [5];
 411         __le32                  hw_buf_hi [5];
 412
 413         /* the rest is HCD-private */
 414         dma_addr_t              qh_dma;         /* address of qh */
 415         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 416         struct list_head        qtd_list;       /* sw qtd list */
 417         struct ehci_qtd         *dummy;
 418         struct ehci_qh          *reclaim;       /* next to reclaim */
 419
 420         struct ehci_hcd         *ehci;
 421         struct kref             kref;
 422         unsigned                stamp;
 423
 424         u8                      qh_state;
 425 #define QH_STATE_LINKED         1               /* HC sees this */
 426 #define QH_STATE_UNLINK         2               /* HC may still see this */
 427 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 428 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 429 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 430
 431         /* periodic schedule info */
 432         u8                      usecs;          /* intr bandwidth */
 433         u8                      gap_uf;         /* uframes split/csplit gap */
 434         u8                      c_usecs;        /* ... split completion bw */
 435         u16                     tt_usecs;       /* tt downstream bandwidth */
 436         unsigned short          period;         /* polling interval */
 437         unsigned short          start;          /* where polling starts */
 438 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 439         struct usb_device       *dev;           /* access to TT */
 440 } __attribute__ ((aligned (32)));
 441
 442 /*-------------------------------------------------------------------------*/
 443
 444 /* description of one iso transaction (up to 3 KB data if highspeed) */
 445 struct ehci_iso_packet {
 446         /* These will be copied to iTD when scheduling */
 447         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 448         __le32                  transaction;    /* itd->hw_transaction[i] |= */
 449         u8                      cross;          /* buf crosses pages */
 450         /* for full speed OUT splits */
 451         u32                     buf1;
 452 };
 453
 454 /* temporary schedule data for packets from iso urbs (both speeds)
 455  * each packet is one logical usb transaction to the device (not TT),
 456  * beginning at stream->next_uframe
 457  */
 458 struct ehci_iso_sched {
 459         struct list_head        td_list;
 460         unsigned                span;
 461         struct ehci_iso_packet  packet [0];
 462 };
 463
 464 /*
 465  * ehci_iso_stream - groups all (s)itds for this endpoint.
 466  * acts like a qh would, if EHCI had them for ISO.
 467  */
 468 struct ehci_iso_stream {
 469         /* first two fields match QH, but info1 == 0 */
 470         __le32                  hw_next;
 471         __le32                  hw_info1;
 472
 473         u32                     refcount;
 474         u8                      bEndpointAddress;
 475         u8                      highspeed;
 476         u16                     depth;          /* depth in uframes */
 477         struct list_head        td_list;        /* queued itds/sitds */
 478         struct list_head        free_list;      /* list of unused itds/sitds */
 479         struct usb_device       *udev;
 480         struct usb_host_endpoint *ep;
 481
 482         /* output of (re)scheduling */
 483         unsigned long           start;          /* jiffies */
 484         unsigned long           rescheduled;
 485         int                     next_uframe;
 486         __le32                  splits;
 487
 488         /* the rest is derived from the endpoint descriptor,
 489          * trusting urb->interval == f(epdesc->bInterval) and
 490          * including the extra info for hw_bufp[0..2]
 491          */
 492         u8                      interval;
 493         u8                      usecs, c_usecs;
 494         u16                     tt_usecs;
 495         u16                     maxp;
 496         u16                     raw_mask;
 497         unsigned                bandwidth;
 498
 499         /* This is used to initialize iTD's hw_bufp fields */
 500         __le32                  buf0;
 501         __le32                  buf1;
 502         __le32                  buf2;
 503
 504         /* this is used to initialize sITD's tt info */
 505         __le32                  address;
 506 };
 507
 508 /*-------------------------------------------------------------------------*/
 509
 510 /*
 511  * EHCI Specification 0.95 Section 3.3
 512  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 513  *
 514  * Schedule records for high speed iso xfers
 515  */
 516 struct ehci_itd {
 517         /* first part defined by EHCI spec */
 518         __le32                  hw_next;           /* see EHCI 3.3.1 */
 519         __le32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 520 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 521 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 522 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 523 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 524 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 525 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 526
 527 #define ITD_ACTIVE      __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
 528
 529         __le32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 530         __le32                  hw_bufp_hi [7]; /* Appendix B */
 531
 532         /* the rest is HCD-private */
 533         dma_addr_t              itd_dma;        /* for this itd */
 534         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 535
 536         struct urb              *urb;
 537         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 538         struct list_head        itd_list;       /* list of stream's itds */
 539
 540         /* any/all hw_transactions here may be used by that urb */
 541         unsigned                frame;          /* where scheduled */
 542         unsigned                pg;
 543         unsigned                index[8];       /* in urb->iso_frame_desc */
 544         u8                      usecs[8];
 545 } __attribute__ ((aligned (32)));
 546
 547 /*-------------------------------------------------------------------------*/
 548
 549 /*
 550  * EHCI Specification 0.95 Section 3.4
 551  * siTD, aka split-transaction isochronous Transfer Descriptor
 552  *       ... describe full speed iso xfers through TT in hubs
 553  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 554  */
 555 struct ehci_sitd {
 556         /* first part defined by EHCI spec */
 557         __le32                  hw_next;
 558 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 559         __le32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 560         __le32                  hw_uframe;              /* EHCI table 3-10 */
 561         __le32                  hw_results;             /* EHCI table 3-11 */
 562 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 563 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 564 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 565 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 566 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 567 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 568 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 569 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 570 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 571 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 572
 573 #define SITD_ACTIVE     __constant_cpu_to_le32(SITD_STS_ACTIVE)
 574
 575         __le32                  hw_buf [2];             /* EHCI table 3-12 */
 576         __le32                  hw_backpointer;         /* EHCI table 3-13 */
 577         __le32                  hw_buf_hi [2];          /* Appendix B */
 578
 579         /* the rest is HCD-private */
 580         dma_addr_t              sitd_dma;
 581         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 582
 583         struct urb              *urb;
 584         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 585         struct list_head        sitd_list;      /* list of stream's sitds */
 586         unsigned                frame;
 587         unsigned                index;
 588 } __attribute__ ((aligned (32)));
 589
 590 /*-------------------------------------------------------------------------*/
 591
 592 /*
 593  * EHCI Specification 0.96 Section 3.7
 594  * Periodic Frame Span Traversal Node (FSTN)
 595  *
 596  * Manages split interrupt transactions (using TT) that span frame boundaries
 597  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 598  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 599  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 600  */
 601 struct ehci_fstn {
 602         __le32                  hw_next;        /* any periodic q entry */
 603         __le32                  hw_prev;        /* qh or EHCI_LIST_END */
 604
 605         /* the rest is HCD-private */
 606         dma_addr_t              fstn_dma;
 607         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 608 } __attribute__ ((aligned (32)));
 609
 610 /*-------------------------------------------------------------------------*/
 611
 612 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 613
 614 /*
 615  * Some EHCI controllers have a Transaction Translator built into the
 616  * root hub. This is a non-standard feature.  Each controller will need
 617  * to add code to the following inline functions, and call them as
 618  * needed (mostly in root hub code).
 619  */
 620
 621 #define ehci_is_TDI(e)                  ((e)->is_tdi_rh_tt)
 622
 623 /* Returns the speed of a device attached to a port on the root hub. */
 624 static inline unsigned int
 625 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 626 {
 627         if (ehci_is_TDI(ehci)) {
 628                 switch ((portsc>>26)&3) {
 629                 case 0:
 630                         return 0;
 631                 case 1:
 632                         return (1<<USB_PORT_FEAT_LOWSPEED);
 633                 case 2:
 634                 default:
 635                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 636                 }
 637         }
 638         return (1<<USB_PORT_FEAT_HIGHSPEED);
 639 }
 640
 641 #else
 642
 643 #define ehci_is_TDI(e)                  (0)
 644
 645 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 646 #endif
 647
 648 /*-------------------------------------------------------------------------*/
 649
 650 #ifdef CONFIG_PPC_83xx
 651 /* Some Freescale processors have an erratum in which the TT
 652  * port number in the queue head was 0..N-1 instead of 1..N.
 653  */
 654 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 655 #else
 656 #define ehci_has_fsl_portno_bug(e)              (0)
 657 #endif
 658
 659 /*
 660  * While most USB host controllers implement their registers in
 661  * little-endian format, a minority (celleb companion chip) implement
 662  * them in big endian format.
 663  *
 664  * This attempts to support either format at compile time without a
 665  * runtime penalty, or both formats with the additional overhead
 666  * of checking a flag bit.
 667  */
 668
 669 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 670 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 671 #else
 672 #define ehci_big_endian_mmio(e)         0
 673 #endif
 674
 675 static inline unsigned int ehci_readl (const struct ehci_hcd *ehci,
 676                                        __u32 __iomem * regs)
 677 {
 678 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 679         return ehci_big_endian_mmio(ehci) ?
 680                 readl_be((__force u32 *)regs) :
 681                 readl((__force u32 *)regs);
 682 #else
 683         return readl((__force u32 *)regs);
 684 #endif
 685 }
 686
 687 static inline void ehci_writel (const struct ehci_hcd *ehci,
 688                                 const unsigned int val, __u32 __iomem *regs)
 689 {
 690 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 691         ehci_big_endian_mmio(ehci) ?
 692                 writel_be(val, (__force u32 *)regs) :
 693                 writel(val, (__force u32 *)regs);
 694 #else
 695         writel(val, (__force u32 *)regs);
 696 #endif
 697 }
 698
 699 /*-------------------------------------------------------------------------*/
 700
 701 #ifndef DEBUG
 702 #define STUB_DEBUG_FILES
 703 #endif  /* DEBUG */
 704
 705 /*-------------------------------------------------------------------------*/
 706
 707 #endif /* __LINUX_EHCI_HCD_H */