2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/smp_lock.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/reboot.h>
34 #include <linux/usb.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
38 #include "../core/hcd.h"
40 #include <asm/byteorder.h>
43 #include <asm/system.h>
44 #include <asm/unaligned.h>
47 /*-------------------------------------------------------------------------*/
50 * EHCI hc_driver implementation ... experimental, incomplete.
51 * Based on the final 1.0 register interface specification.
53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 * Next comes "CardBay", using USB 2.0 signals.
57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 * Special thanks to Intel and VIA for providing host controllers to
59 * test this driver on, and Cypress (including In-System Design) for
60 * providing early devices for those host controllers to talk to!
64 * 2004-05-10 Root hub and PCI suspend/resume support; remote wakeup. (db)
65 * 2004-02-24 Replace pci_* with generic dma_* API calls (dsaxena@plexity.net)
66 * 2003-12-29 Rewritten high speed iso transfer support (by Michal Sojka,
67 * <sojkam@centrum.cz>, updates by DB).
69 * 2002-11-29 Correct handling for hw async_next register.
70 * 2002-08-06 Handling for bulk and interrupt transfers is mostly shared;
71 * only scheduling is different, no arbitrary limitations.
72 * 2002-07-25 Sanity check PCI reads, mostly for better cardbus support,
73 * clean up HC run state handshaking.
74 * 2002-05-24 Preliminary FS/LS interrupts, using scheduling shortcuts
75 * 2002-05-11 Clear TT errors for FS/LS ctrl/bulk. Fill in some other
76 * missing pieces: enabling 64bit dma, handoff from BIOS/SMM.
77 * 2002-05-07 Some error path cleanups to report better errors; wmb();
78 * use non-CVS version id; better iso bandwidth claim.
79 * 2002-04-19 Control/bulk/interrupt submit no longer uses giveback() on
80 * errors in submit path. Bugfixes to interrupt scheduling/processing.
81 * 2002-03-05 Initial high-speed ISO support; reduce ITD memory; shift
82 * more checking to generic hcd framework (db). Make it work with
83 * Philips EHCI; reduce PCI traffic; shorten IRQ path (Rory Bolt).
84 * 2002-01-14 Minor cleanup; version synch.
85 * 2002-01-08 Fix roothub handoff of FS/LS to companion controllers.
86 * 2002-01-04 Control/Bulk queuing behaves.
88 * 2001-12-12 Initial patch version for Linux 2.5.1 kernel.
89 * 2001-June Works with usb-storage and NEC EHCI on 2.4
92 #define DRIVER_VERSION "10 Dec 2004"
93 #define DRIVER_AUTHOR "David Brownell"
94 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
96 static const char hcd_name
[] = "ehci_hcd";
99 #undef EHCI_VERBOSE_DEBUG
100 #undef EHCI_URB_TRACE
106 /* magic numbers that can affect system performance */
107 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
108 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
109 #define EHCI_TUNE_RL_TT 0
110 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
111 #define EHCI_TUNE_MULT_TT 1
112 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
114 #define EHCI_IAA_JIFFIES (HZ/100) /* arbitrary; ~10 msec */
115 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
116 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
117 #define EHCI_SHRINK_JIFFIES (HZ/200) /* async qh unlink delay */
119 /* Initial IRQ latency: faster than hw default */
120 static int log2_irq_thresh
= 0; // 0 to 6
121 module_param (log2_irq_thresh
, int, S_IRUGO
);
122 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
124 /* initial park setting: slower than hw default */
125 static unsigned park
= 0;
126 module_param (park
, uint
, S_IRUGO
);
127 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
129 /* for flakey hardware, ignore overcurrent indicators */
130 static int ignore_oc
= 0;
131 module_param (ignore_oc
, bool, S_IRUGO
);
132 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
134 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
136 /*-------------------------------------------------------------------------*/
139 #include "ehci-dbg.c"
141 /*-------------------------------------------------------------------------*/
144 * handshake - spin reading hc until handshake completes or fails
145 * @ptr: address of hc register to be read
146 * @mask: bits to look at in result of read
147 * @done: value of those bits when handshake succeeds
148 * @usec: timeout in microseconds
150 * Returns negative errno, or zero on success
152 * Success happens when the "mask" bits have the specified value (hardware
153 * handshake done). There are two failure modes: "usec" have passed (major
154 * hardware flakeout), or the register reads as all-ones (hardware removed).
156 * That last failure should_only happen in cases like physical cardbus eject
157 * before driver shutdown. But it also seems to be caused by bugs in cardbus
158 * bridge shutdown: shutting down the bridge before the devices using it.
160 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
161 u32 mask
, u32 done
, int usec
)
166 result
= ehci_readl(ehci
, ptr
);
167 if (result
== ~(u32
)0) /* card removed */
178 /* force HC to halt state from unknown (EHCI spec section 2.3) */
179 static int ehci_halt (struct ehci_hcd
*ehci
)
181 u32 temp
= ehci_readl(ehci
, &ehci
->regs
->status
);
183 /* disable any irqs left enabled by previous code */
184 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
186 if ((temp
& STS_HALT
) != 0)
189 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
191 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
192 return handshake (ehci
, &ehci
->regs
->status
,
193 STS_HALT
, STS_HALT
, 16 * 125);
196 /* put TDI/ARC silicon into EHCI mode */
197 static void tdi_reset (struct ehci_hcd
*ehci
)
199 u32 __iomem
*reg_ptr
;
202 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + 0x68);
203 tmp
= ehci_readl(ehci
, reg_ptr
);
205 ehci_writel(ehci
, tmp
, reg_ptr
);
208 /* reset a non-running (STS_HALT == 1) controller */
209 static int ehci_reset (struct ehci_hcd
*ehci
)
212 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
214 command
|= CMD_RESET
;
215 dbg_cmd (ehci
, "reset", command
);
216 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
217 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
218 ehci
->next_statechange
= jiffies
;
219 retval
= handshake (ehci
, &ehci
->regs
->command
,
220 CMD_RESET
, 0, 250 * 1000);
225 if (ehci_is_TDI(ehci
))
231 /* idle the controller (from running) */
232 static void ehci_quiesce (struct ehci_hcd
*ehci
)
237 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
241 /* wait for any schedule enables/disables to take effect */
242 temp
= ehci_readl(ehci
, &ehci
->regs
->command
) << 10;
243 temp
&= STS_ASS
| STS_PSS
;
244 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
245 temp
, 16 * 125) != 0) {
246 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
250 /* then disable anything that's still active */
251 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
252 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
253 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
255 /* hardware can take 16 microframes to turn off ... */
256 if (handshake (ehci
, &ehci
->regs
->status
, STS_ASS
| STS_PSS
,
258 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
263 /*-------------------------------------------------------------------------*/
265 static void ehci_work(struct ehci_hcd
*ehci
);
267 #include "ehci-hub.c"
268 #include "ehci-mem.c"
270 #include "ehci-sched.c"
272 /*-------------------------------------------------------------------------*/
274 static void ehci_watchdog (unsigned long param
)
276 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
279 spin_lock_irqsave (&ehci
->lock
, flags
);
281 /* lost IAA irqs wedge things badly; seen with a vt8235 */
283 u32 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
284 if (status
& STS_IAA
) {
285 ehci_vdbg (ehci
, "lost IAA\n");
286 COUNT (ehci
->stats
.lost_iaa
);
287 ehci_writel(ehci
, STS_IAA
, &ehci
->regs
->status
);
288 ehci
->reclaim_ready
= 1;
292 /* stop async processing after it's idled a bit */
293 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
294 start_unlink_async (ehci
, ehci
->async
);
296 /* ehci could run by timer, without IRQs ... */
299 spin_unlock_irqrestore (&ehci
->lock
, flags
);
302 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
303 * This forcibly disables dma and IRQs, helping kexec and other cases
304 * where the next system software may expect clean state.
307 ehci_shutdown (struct usb_hcd
*hcd
)
309 struct ehci_hcd
*ehci
;
311 ehci
= hcd_to_ehci (hcd
);
312 (void) ehci_halt (ehci
);
314 /* make BIOS/etc use companion controller during reboot */
315 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
318 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
322 if (!HCS_PPC (ehci
->hcs_params
))
325 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
326 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
327 (void) ehci_hub_control(ehci_to_hcd(ehci
),
328 is_on
? SetPortFeature
: ClearPortFeature
,
334 /*-------------------------------------------------------------------------*/
337 * ehci_work is called from some interrupts, timers, and so on.
338 * it calls driver completion functions, after dropping ehci->lock.
340 static void ehci_work (struct ehci_hcd
*ehci
)
342 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
343 if (ehci
->reclaim_ready
)
344 end_unlink_async (ehci
);
346 /* another CPU may drop ehci->lock during a schedule scan while
347 * it reports urb completions. this flag guards against bogus
348 * attempts at re-entrant schedule scanning.
354 if (ehci
->next_uframe
!= -1)
355 scan_periodic (ehci
);
358 /* the IO watchdog guards against hardware or driver bugs that
359 * misplace IRQs, and should let us run completely without IRQs.
360 * such lossage has been observed on both VT6202 and VT8235.
362 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
363 (ehci
->async
->qh_next
.ptr
!= NULL
||
364 ehci
->periodic_sched
!= 0))
365 timer_action (ehci
, TIMER_IO_WATCHDOG
);
368 static void ehci_stop (struct usb_hcd
*hcd
)
370 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
372 ehci_dbg (ehci
, "stop\n");
374 /* Turn off port power on all root hub ports. */
375 ehci_port_power (ehci
, 0);
377 /* no more interrupts ... */
378 del_timer_sync (&ehci
->watchdog
);
380 spin_lock_irq(&ehci
->lock
);
381 if (HC_IS_RUNNING (hcd
->state
))
385 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
386 spin_unlock_irq(&ehci
->lock
);
388 /* let companion controllers work when we aren't */
389 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
391 remove_companion_file(ehci
);
392 remove_debug_files (ehci
);
394 /* root hub is shut down separately (first, when possible) */
395 spin_lock_irq (&ehci
->lock
);
398 spin_unlock_irq (&ehci
->lock
);
399 ehci_mem_cleanup (ehci
);
402 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
403 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
404 ehci
->stats
.lost_iaa
);
405 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
406 ehci
->stats
.complete
, ehci
->stats
.unlink
);
409 dbg_status (ehci
, "ehci_stop completed",
410 ehci_readl(ehci
, &ehci
->regs
->status
));
413 /* one-time init, only for memory state */
414 static int ehci_init(struct usb_hcd
*hcd
)
416 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
421 spin_lock_init(&ehci
->lock
);
423 init_timer(&ehci
->watchdog
);
424 ehci
->watchdog
.function
= ehci_watchdog
;
425 ehci
->watchdog
.data
= (unsigned long) ehci
;
428 * hw default: 1K periodic list heads, one per frame.
429 * periodic_size can shrink by USBCMD update if hcc_params allows.
431 ehci
->periodic_size
= DEFAULT_I_TDPS
;
432 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
435 /* controllers may cache some of the periodic schedule ... */
436 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
437 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
439 else // N microframes cached
440 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
442 ehci
->reclaim
= NULL
;
443 ehci
->reclaim_ready
= 0;
444 ehci
->next_uframe
= -1;
447 * dedicate a qh for the async ring head, since we couldn't unlink
448 * a 'real' qh without stopping the async schedule [4.8]. use it
449 * as the 'reclamation list head' too.
450 * its dummy is used in hw_alt_next of many tds, to prevent the qh
451 * from automatically advancing to the next td after short reads.
453 ehci
->async
->qh_next
.qh
= NULL
;
454 ehci
->async
->hw_next
= QH_NEXT(ehci
->async
->qh_dma
);
455 ehci
->async
->hw_info1
= cpu_to_le32(QH_HEAD
);
456 ehci
->async
->hw_token
= cpu_to_le32(QTD_STS_HALT
);
457 ehci
->async
->hw_qtd_next
= EHCI_LIST_END
;
458 ehci
->async
->qh_state
= QH_STATE_LINKED
;
459 ehci
->async
->hw_alt_next
= QTD_NEXT(ehci
->async
->dummy
->qtd_dma
);
461 /* clear interrupt enables, set irq latency */
462 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
464 temp
= 1 << (16 + log2_irq_thresh
);
465 if (HCC_CANPARK(hcc_params
)) {
466 /* HW default park == 3, on hardware that supports it (like
467 * NVidia and ALI silicon), maximizes throughput on the async
468 * schedule by avoiding QH fetches between transfers.
470 * With fast usb storage devices and NForce2, "park" seems to
471 * make problems: throughput reduction (!), data errors...
474 park
= min(park
, (unsigned) 3);
478 ehci_dbg(ehci
, "park %d\n", park
);
480 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
481 /* periodic schedule size can be smaller than default */
483 temp
|= (EHCI_TUNE_FLS
<< 2);
484 switch (EHCI_TUNE_FLS
) {
485 case 0: ehci
->periodic_size
= 1024; break;
486 case 1: ehci
->periodic_size
= 512; break;
487 case 2: ehci
->periodic_size
= 256; break;
491 ehci
->command
= temp
;
496 /* start HC running; it's halted, ehci_init() has been run (once) */
497 static int ehci_run (struct usb_hcd
*hcd
)
499 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
504 /* EHCI spec section 4.1 */
505 if ((retval
= ehci_reset(ehci
)) != 0) {
506 ehci_mem_cleanup(ehci
);
509 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
510 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
513 * hcc_params controls whether ehci->regs->segment must (!!!)
514 * be used; it constrains QH/ITD/SITD and QTD locations.
515 * pci_pool consistent memory always uses segment zero.
516 * streaming mappings for I/O buffers, like pci_map_single(),
517 * can return segments above 4GB, if the device allows.
519 * NOTE: the dma mask is visible through dma_supported(), so
520 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
521 * Scsi_Host.highmem_io, and so forth. It's readonly to all
522 * host side drivers though.
524 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
525 if (HCC_64BIT_ADDR(hcc_params
)) {
526 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
528 // this is deeply broken on almost all architectures
529 if (!dma_set_mask(hcd
->self
.controller
, DMA_64BIT_MASK
))
530 ehci_info(ehci
, "enabled 64bit DMA\n");
535 // Philips, Intel, and maybe others need CMD_RUN before the
536 // root hub will detect new devices (why?); NEC doesn't
537 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
538 ehci
->command
|= CMD_RUN
;
539 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
540 dbg_cmd (ehci
, "init", ehci
->command
);
543 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
544 * are explicitly handed to companion controller(s), so no TT is
545 * involved with the root hub. (Except where one is integrated,
546 * and there's no companion controller unless maybe for USB OTG.)
548 hcd
->state
= HC_STATE_RUNNING
;
549 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
550 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
552 temp
= HC_VERSION(ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
554 "USB %x.%x started, EHCI %x.%02x, driver %s%s\n",
555 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
556 temp
>> 8, temp
& 0xff, DRIVER_VERSION
,
557 ignore_oc
? ", overcurrent ignored" : "");
559 ehci_writel(ehci
, INTR_MASK
,
560 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
562 /* GRR this is run-once init(), being done every time the HC starts.
563 * So long as they're part of class devices, we can't do it init()
564 * since the class device isn't created that early.
566 create_debug_files(ehci
);
567 create_companion_file(ehci
);
572 /*-------------------------------------------------------------------------*/
574 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
576 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
580 spin_lock (&ehci
->lock
);
582 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
584 /* e.g. cardbus physical eject */
585 if (status
== ~(u32
) 0) {
586 ehci_dbg (ehci
, "device removed\n");
591 if (!status
) { /* irq sharing? */
592 spin_unlock(&ehci
->lock
);
596 /* clear (just) interrupts */
597 ehci_writel(ehci
, status
, &ehci
->regs
->status
);
598 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted write */
601 #ifdef EHCI_VERBOSE_DEBUG
602 /* unrequested/ignored: Frame List Rollover */
603 dbg_status (ehci
, "irq", status
);
606 /* INT, ERR, and IAA interrupt rates can be throttled */
608 /* normal [4.15.1.2] or error [4.15.1.1] completion */
609 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
610 if (likely ((status
& STS_ERR
) == 0))
611 COUNT (ehci
->stats
.normal
);
613 COUNT (ehci
->stats
.error
);
617 /* complete the unlinking of some qh [4.15.2.3] */
618 if (status
& STS_IAA
) {
619 COUNT (ehci
->stats
.reclaim
);
620 ehci
->reclaim_ready
= 1;
624 /* remote wakeup [4.3.1] */
625 if (status
& STS_PCD
) {
626 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
628 /* resume root hub? */
629 if (!(ehci_readl(ehci
, &ehci
->regs
->command
) & CMD_RUN
))
630 usb_hcd_resume_root_hub(hcd
);
633 int pstatus
= ehci_readl(ehci
,
634 &ehci
->regs
->port_status
[i
]);
636 if (pstatus
& PORT_OWNER
)
638 if (!(pstatus
& PORT_RESUME
)
639 || ehci
->reset_done
[i
] != 0)
642 /* start 20 msec resume signaling from this port,
643 * and make khubd collect PORT_STAT_C_SUSPEND to
644 * stop that signaling.
646 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
647 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
651 /* PCI errors [4.15.2.4] */
652 if (unlikely ((status
& STS_FATAL
) != 0)) {
653 /* bogus "fatal" IRQs appear on some chips... why? */
654 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
655 dbg_cmd (ehci
, "fatal", ehci_readl(ehci
,
656 &ehci
->regs
->command
));
657 dbg_status (ehci
, "fatal", status
);
658 if (status
& STS_HALT
) {
659 ehci_err (ehci
, "fatal error\n");
662 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
663 /* generic layer kills/unlinks all urbs, then
664 * uses ehci_stop to clean up the rest
672 spin_unlock (&ehci
->lock
);
676 /*-------------------------------------------------------------------------*/
679 * non-error returns are a promise to giveback() the urb later
680 * we drop ownership so next owner (or urb unlink) can get it
682 * urb + dev is in hcd.self.controller.urb_list
683 * we're queueing TDs onto software and hardware lists
685 * hcd-specific init for hcpriv hasn't been done yet
687 * NOTE: control, bulk, and interrupt share the same code to append TDs
688 * to a (possibly active) QH, and the same QH scanning code.
690 static int ehci_urb_enqueue (
692 struct usb_host_endpoint
*ep
,
696 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
697 struct list_head qtd_list
;
699 INIT_LIST_HEAD (&qtd_list
);
701 switch (usb_pipetype (urb
->pipe
)) {
702 // case PIPE_CONTROL:
705 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
707 return submit_async (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
710 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
712 return intr_submit (ehci
, ep
, urb
, &qtd_list
, mem_flags
);
714 case PIPE_ISOCHRONOUS
:
715 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
716 return itd_submit (ehci
, urb
, mem_flags
);
718 return sitd_submit (ehci
, urb
, mem_flags
);
722 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
724 /* if we need to use IAA and it's busy, defer */
725 if (qh
->qh_state
== QH_STATE_LINKED
727 && HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
)) {
728 struct ehci_qh
*last
;
730 for (last
= ehci
->reclaim
;
732 last
= last
->reclaim
)
734 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
737 /* bypass IAA if the hc can't care */
738 } else if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
739 end_unlink_async (ehci
);
741 /* something else might have unlinked the qh by now */
742 if (qh
->qh_state
== QH_STATE_LINKED
)
743 start_unlink_async (ehci
, qh
);
746 /* remove from hardware lists
747 * completions normally happen asynchronously
750 static int ehci_urb_dequeue (struct usb_hcd
*hcd
, struct urb
*urb
)
752 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
756 spin_lock_irqsave (&ehci
->lock
, flags
);
757 switch (usb_pipetype (urb
->pipe
)) {
758 // case PIPE_CONTROL:
761 qh
= (struct ehci_qh
*) urb
->hcpriv
;
764 unlink_async (ehci
, qh
);
768 qh
= (struct ehci_qh
*) urb
->hcpriv
;
771 switch (qh
->qh_state
) {
772 case QH_STATE_LINKED
:
773 intr_deschedule (ehci
, qh
);
776 qh_completions (ehci
, qh
);
779 ehci_dbg (ehci
, "bogus qh %p state %d\n",
784 /* reschedule QH iff another request is queued */
785 if (!list_empty (&qh
->qtd_list
)
786 && HC_IS_RUNNING (hcd
->state
)) {
789 status
= qh_schedule (ehci
, qh
);
790 spin_unlock_irqrestore (&ehci
->lock
, flags
);
793 // shouldn't happen often, but ...
794 // FIXME kill those tds' urbs
795 err ("can't reschedule qh %p, err %d",
802 case PIPE_ISOCHRONOUS
:
805 // wait till next completion, do it then.
806 // completion irqs can wait up to 1024 msec,
810 spin_unlock_irqrestore (&ehci
->lock
, flags
);
814 /*-------------------------------------------------------------------------*/
816 // bulk qh holds the data toggle
819 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
821 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
823 struct ehci_qh
*qh
, *tmp
;
825 /* ASSERT: any requests/urbs are being unlinked */
826 /* ASSERT: nobody can be submitting urbs for this any more */
829 spin_lock_irqsave (&ehci
->lock
, flags
);
834 /* endpoints can be iso streams. for now, we don't
835 * accelerate iso completions ... so spin a while.
837 if (qh
->hw_info1
== 0) {
838 ehci_vdbg (ehci
, "iso delay\n");
842 if (!HC_IS_RUNNING (hcd
->state
))
843 qh
->qh_state
= QH_STATE_IDLE
;
844 switch (qh
->qh_state
) {
845 case QH_STATE_LINKED
:
846 for (tmp
= ehci
->async
->qh_next
.qh
;
848 tmp
= tmp
->qh_next
.qh
)
850 /* periodic qh self-unlinks on empty */
853 unlink_async (ehci
, qh
);
855 case QH_STATE_UNLINK
: /* wait for hw to finish? */
857 spin_unlock_irqrestore (&ehci
->lock
, flags
);
858 schedule_timeout_uninterruptible(1);
860 case QH_STATE_IDLE
: /* fully unlinked */
861 if (list_empty (&qh
->qtd_list
)) {
865 /* else FALL THROUGH */
868 /* caller was supposed to have unlinked any requests;
869 * that's not our job. just leak this memory.
871 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
872 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
873 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
878 spin_unlock_irqrestore (&ehci
->lock
, flags
);
882 static int ehci_get_frame (struct usb_hcd
*hcd
)
884 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
885 return (ehci_readl(ehci
, &ehci
->regs
->frame_index
) >> 3) %
889 /*-------------------------------------------------------------------------*/
891 #define DRIVER_INFO DRIVER_VERSION " " DRIVER_DESC
893 MODULE_DESCRIPTION (DRIVER_INFO
);
894 MODULE_AUTHOR (DRIVER_AUTHOR
);
895 MODULE_LICENSE ("GPL");
898 #include "ehci-pci.c"
899 #define PCI_DRIVER ehci_pci_driver
902 #ifdef CONFIG_MPC834x
903 #include "ehci-fsl.c"
904 #define PLATFORM_DRIVER ehci_fsl_driver
907 #ifdef CONFIG_SOC_AU1200
908 #include "ehci-au1xxx.c"
909 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
912 #ifdef CONFIG_PPC_PS3
913 #include "ehci-ps3.c"
914 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_sb_driver
917 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
918 !defined(PS3_SYSTEM_BUS_DRIVER)
919 #error "missing bus glue for ehci-hcd"
922 static int __init
ehci_hcd_init(void)
926 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
928 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
929 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
931 #ifdef PLATFORM_DRIVER
932 retval
= platform_driver_register(&PLATFORM_DRIVER
);
938 retval
= pci_register_driver(&PCI_DRIVER
);
940 #ifdef PLATFORM_DRIVER
941 platform_driver_unregister(&PLATFORM_DRIVER
);
947 #ifdef PS3_SYSTEM_BUS_DRIVER
948 retval
= ps3_system_bus_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
950 #ifdef PLATFORM_DRIVER
951 platform_driver_unregister(&PLATFORM_DRIVER
);
954 pci_unregister_driver(&PCI_DRIVER
);
962 module_init(ehci_hcd_init
);
964 static void __exit
ehci_hcd_cleanup(void)
966 #ifdef PLATFORM_DRIVER
967 platform_driver_unregister(&PLATFORM_DRIVER
);
970 pci_unregister_driver(&PCI_DRIVER
);
972 #ifdef PS3_SYSTEM_BUS_DRIVER
973 ps3_system_bus_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
976 module_exit(ehci_hcd_cleanup
);