drivers/staging/brcm80211/util/aiutils.c

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/string.h>
  19 #include <bcmdefs.h>
  20 #ifdef BRCM_FULLMAC
  21 #include <linux/netdevice.h>
  22 #endif
  23 #include <osl.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <bcmutils.h>
  27 #include <siutils.h>
  28 #include <hndsoc.h>
  29 #include <sbchipc.h>
  30 #include <pcicfg.h>
  31 #include <bcmdevs.h>
  32
  33 #define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
  34                 (CHIPREV(sih->chiprev) == 0) && \
  35                 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
  36
  37 /* EROM parsing */
  38
  39 static u32
  40 get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
  41 {
  42         u32 ent;
  43         uint inv = 0, nom = 0;
  44
  45         while (true) {
  46                 ent = R_REG(si_osh(sih), *eromptr);
  47                 (*eromptr)++;
  48
  49                 if (mask == 0)
  50                         break;
  51
  52                 if ((ent & ER_VALID) == 0) {
  53                         inv++;
  54                         continue;
  55                 }
  56
  57                 if (ent == (ER_END | ER_VALID))
  58                         break;
  59
  60                 if ((ent & mask) == match)
  61                         break;
  62
  63                 nom++;
  64         }
  65
  66         SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
  67         if (inv + nom) {
  68                 SI_VMSG(("  after %d invalid and %d non-matching entries\n",
  69                          inv, nom));
  70         }
  71         return ent;
  72 }
  73
  74 static u32
  75 get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
  76         u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
  77 {
  78         u32 asd, sz, szd;
  79
  80         asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
  81         if (((asd & ER_TAG1) != ER_ADD) ||
  82             (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
  83             ((asd & AD_ST_MASK) != st)) {
  84                 /* This is not what we want, "push" it back */
  85                 (*eromptr)--;
  86                 return 0;
  87         }
  88         *addrl = asd & AD_ADDR_MASK;
  89         if (asd & AD_AG32)
  90                 *addrh = get_erom_ent(sih, eromptr, 0, 0);
  91         else
  92                 *addrh = 0;
  93         *sizeh = 0;
  94         sz = asd & AD_SZ_MASK;
  95         if (sz == AD_SZ_SZD) {
  96                 szd = get_erom_ent(sih, eromptr, 0, 0);
  97                 *sizel = szd & SD_SZ_MASK;
  98                 if (szd & SD_SG32)
  99                         *sizeh = get_erom_ent(sih, eromptr, 0, 0);
 100         } else
 101                 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
 102
 103         SI_VMSG(("  SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
 104                  sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
 105
 106         return asd;
 107 }
 108
 109 static void ai_hwfixup(si_info_t *sii)
 110 {
 111 }
 112
 113 /* parse the enumeration rom to identify all cores */
 114 void ai_scan(si_t *sih, void *regs, uint devid)
 115 {
 116         si_info_t *sii = SI_INFO(sih);
 117         chipcregs_t *cc = (chipcregs_t *) regs;
 118         u32 erombase, *eromptr, *eromlim;
 119
 120         erombase = R_REG(sii->osh, &cc->eromptr);
 121
 122         switch (BUSTYPE(sih->bustype)) {
 123         case SI_BUS:
 124                 eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
 125                 break;
 126
 127         case PCI_BUS:
 128                 /* Set wrappers address */
 129                 sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);
 130
 131                 /* Now point the window at the erom */
 132                 pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, erombase);
 133                 eromptr = regs;
 134                 break;
 135
 136 #ifdef BCMSDIO
 137         case SPI_BUS:
 138         case SDIO_BUS:
 139 #endif                          /* BCMSDIO */
 140                 eromptr = (u32 *)(unsigned long)erombase;
 141                 break;
 142
 143         default:
 144                 SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
 145                           sih->bustype));
 146                 ASSERT(0);
 147                 return;
 148         }
 149         eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
 150
 151         SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
 152         while (eromptr < eromlim) {
 153                 u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
 154                 u32 mpd, asd, addrl, addrh, sizel, sizeh;
 155                 u32 *base;
 156                 uint i, j, idx;
 157                 bool br;
 158
 159                 br = false;
 160
 161                 /* Grok a component */
 162                 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
 163                 if (cia == (ER_END | ER_VALID)) {
 164                         SI_VMSG(("Found END of erom after %d cores\n",
 165                                  sii->numcores));
 166                         ai_hwfixup(sii);
 167                         return;
 168                 }
 169                 base = eromptr - 1;
 170                 cib = get_erom_ent(sih, &eromptr, 0, 0);
 171
 172                 if ((cib & ER_TAG) != ER_CI) {
 173                         SI_ERROR(("CIA not followed by CIB\n"));
 174                         goto error;
 175                 }
 176
 177                 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
 178                 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
 179                 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
 180                 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
 181                 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
 182                 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
 183                 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
 184
 185                 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
 186
 187                 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
 188                         continue;
 189                 if ((nmw + nsw == 0)) {
 190                         /* A component which is not a core */
 191                         if (cid == OOB_ROUTER_CORE_ID) {
 192                                 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
 193                                               &addrl, &addrh, &sizel, &sizeh);
 194                                 if (asd != 0) {
 195                                         sii->oob_router = addrl;
 196                                 }
 197                         }
 198                         continue;
 199                 }
 200
 201                 idx = sii->numcores;
 202 /*              sii->eromptr[idx] = base; */
 203                 sii->cia[idx] = cia;
 204                 sii->cib[idx] = cib;
 205                 sii->coreid[idx] = cid;
 206
 207                 for (i = 0; i < nmp; i++) {
 208                         mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
 209                         if ((mpd & ER_TAG) != ER_MP) {
 210                                 SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
 211                                 goto error;
 212                         }
 213                         SI_VMSG(("  Master port %d, mp: %d id: %d\n", i,
 214                                  (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
 215                                  (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
 216                 }
 217
 218                 /* First Slave Address Descriptor should be port 0:
 219                  * the main register space for the core
 220                  */
 221                 asd =
 222                     get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
 223                             &sizel, &sizeh);
 224                 if (asd == 0) {
 225                         /* Try again to see if it is a bridge */
 226                         asd =
 227                             get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
 228                                     &addrh, &sizel, &sizeh);
 229                         if (asd != 0)
 230                                 br = true;
 231                         else if ((addrh != 0) || (sizeh != 0)
 232                                  || (sizel != SI_CORE_SIZE)) {
 233                                 SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
 234                                 goto error;
 235                         }
 236                 }
 237                 sii->coresba[idx] = addrl;
 238                 sii->coresba_size[idx] = sizel;
 239                 /* Get any more ASDs in port 0 */
 240                 j = 1;
 241                 do {
 242                         asd =
 243                             get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
 244                                     &addrh, &sizel, &sizeh);
 245                         if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
 246                                 sii->coresba2[idx] = addrl;
 247                                 sii->coresba2_size[idx] = sizel;
 248                         }
 249                         j++;
 250                 } while (asd != 0);
 251
 252                 /* Go through the ASDs for other slave ports */
 253                 for (i = 1; i < nsp; i++) {
 254                         j = 0;
 255                         do {
 256                                 asd =
 257                                     get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
 258                                             &addrl, &addrh, &sizel, &sizeh);
 259                         } while (asd != 0);
 260                         if (j == 0) {
 261                                 SI_ERROR((" SP %d has no address descriptors\n",
 262                                           i));
 263                                 goto error;
 264                         }
 265                 }
 266
 267                 /* Now get master wrappers */
 268                 for (i = 0; i < nmw; i++) {
 269                         asd =
 270                             get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
 271                                     &addrh, &sizel, &sizeh);
 272                         if (asd == 0) {
 273                                 SI_ERROR(("Missing descriptor for MW %d\n", i));
 274                                 goto error;
 275                         }
 276                         if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
 277                                 SI_ERROR(("Master wrapper %d is not 4KB\n", i));
 278                                 goto error;
 279                         }
 280                         if (i == 0)
 281                                 sii->wrapba[idx] = addrl;
 282                 }
 283
 284                 /* And finally slave wrappers */
 285                 for (i = 0; i < nsw; i++) {
 286                         uint fwp = (nsp == 1) ? 0 : 1;
 287                         asd =
 288                             get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
 289                                     &addrl, &addrh, &sizel, &sizeh);
 290                         if (asd == 0) {
 291                                 SI_ERROR(("Missing descriptor for SW %d\n", i));
 292                                 goto error;
 293                         }
 294                         if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
 295                                 SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
 296                                 goto error;
 297                         }
 298                         if ((nmw == 0) && (i == 0))
 299                                 sii->wrapba[idx] = addrl;
 300                 }
 301
 302                 /* Don't record bridges */
 303                 if (br)
 304                         continue;
 305
 306                 /* Done with core */
 307                 sii->numcores++;
 308         }
 309
 310         SI_ERROR(("Reached end of erom without finding END"));
 311
 312  error:
 313         sii->numcores = 0;
 314         return;
 315 }
 316
 317 /* This function changes the logical "focus" to the indicated core.
 318  * Return the current core's virtual address.
 319  */
 320 void *ai_setcoreidx(si_t *sih, uint coreidx)
 321 {
 322         si_info_t *sii = SI_INFO(sih);
 323         u32 addr = sii->coresba[coreidx];
 324         u32 wrap = sii->wrapba[coreidx];
 325         void *regs;
 326
 327         if (coreidx >= sii->numcores)
 328                 return NULL;
 329
 330         /*
 331          * If the user has provided an interrupt mask enabled function,
 332          * then assert interrupts are disabled before switching the core.
 333          */
 334         ASSERT((sii->intrsenabled_fn == NULL)
 335                || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
 336
 337         switch (BUSTYPE(sih->bustype)) {
 338         case SI_BUS:
 339                 /* map new one */
 340                 if (!sii->regs[coreidx]) {
 341                         sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
 342                         ASSERT(GOODREGS(sii->regs[coreidx]));
 343                 }
 344                 sii->curmap = regs = sii->regs[coreidx];
 345                 if (!sii->wrappers[coreidx]) {
 346                         sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
 347                         ASSERT(GOODREGS(sii->wrappers[coreidx]));
 348                 }
 349                 sii->curwrap = sii->wrappers[coreidx];
 350                 break;
 351
 352         case PCI_BUS:
 353                 /* point bar0 window */
 354                 pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, addr);
 355                 regs = sii->curmap;
 356                 /* point bar0 2nd 4KB window */
 357                 pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN2, wrap);
 358                 break;
 359
 360 #ifdef BCMSDIO
 361         case SPI_BUS:
 362         case SDIO_BUS:
 363 #endif                          /* BCMSDIO */
 364                 sii->curmap = regs = (void *)(unsigned long)addr;
 365                 sii->curwrap = (void *)(unsigned long)wrap;
 366                 break;
 367
 368         default:
 369                 ASSERT(0);
 370                 regs = NULL;
 371                 break;
 372         }
 373
 374         sii->curmap = regs;
 375         sii->curidx = coreidx;
 376
 377         return regs;
 378 }
 379
 380 /* Return the number of address spaces in current core */
 381 int ai_numaddrspaces(si_t *sih)
 382 {
 383         return 2;
 384 }
 385
 386 /* Return the address of the nth address space in the current core */
 387 u32 ai_addrspace(si_t *sih, uint asidx)
 388 {
 389         si_info_t *sii;
 390         uint cidx;
 391
 392         sii = SI_INFO(sih);
 393         cidx = sii->curidx;
 394
 395         if (asidx == 0)
 396                 return sii->coresba[cidx];
 397         else if (asidx == 1)
 398                 return sii->coresba2[cidx];
 399         else {
 400                 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
 401                 return 0;
 402         }
 403 }
 404
 405 /* Return the size of the nth address space in the current core */
 406 u32 ai_addrspacesize(si_t *sih, uint asidx)
 407 {
 408         si_info_t *sii;
 409         uint cidx;
 410
 411         sii = SI_INFO(sih);
 412         cidx = sii->curidx;
 413
 414         if (asidx == 0)
 415                 return sii->coresba_size[cidx];
 416         else if (asidx == 1)
 417                 return sii->coresba2_size[cidx];
 418         else {
 419                 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
 420                 return 0;
 421         }
 422 }
 423
 424 uint ai_flag(si_t *sih)
 425 {
 426         si_info_t *sii;
 427         aidmp_t *ai;
 428
 429         sii = SI_INFO(sih);
 430         if (BCM47162_DMP()) {
 431                 SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
 432                 return sii->curidx;
 433         }
 434         ai = sii->curwrap;
 435
 436         return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
 437 }
 438
 439 void ai_setint(si_t *sih, int siflag)
 440 {
 441 }
 442
 443 void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
 444 {
 445         si_info_t *sii = SI_INFO(sih);
 446         u32 *w = (u32 *) sii->curwrap;
 447         W_REG(sii->osh, w + (offset / 4), val);
 448         return;
 449 }
 450
 451 uint ai_corevendor(si_t *sih)
 452 {
 453         si_info_t *sii;
 454         u32 cia;
 455
 456         sii = SI_INFO(sih);
 457         cia = sii->cia[sii->curidx];
 458         return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
 459 }
 460
 461 uint ai_corerev(si_t *sih)
 462 {
 463         si_info_t *sii;
 464         u32 cib;
 465
 466         sii = SI_INFO(sih);
 467         cib = sii->cib[sii->curidx];
 468         return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
 469 }
 470
 471 bool ai_iscoreup(si_t *sih)
 472 {
 473         si_info_t *sii;
 474         aidmp_t *ai;
 475
 476         sii = SI_INFO(sih);
 477         ai = sii->curwrap;
 478
 479         return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
 480                  SICF_CLOCK_EN)
 481                 && ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
 482 }
 483
 484 /*
 485  * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
 486  * switch back to the original core, and return the new value.
 487  *
 488  * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
 489  *
 490  * Also, when using pci/pcie, we can optimize away the core switching for pci registers
 491  * and (on newer pci cores) chipcommon registers.
 492  */
 493 uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
 494 {
 495         uint origidx = 0;
 496         u32 *r = NULL;
 497         uint w;
 498         uint intr_val = 0;
 499         bool fast = false;
 500         si_info_t *sii;
 501
 502         sii = SI_INFO(sih);
 503
 504         ASSERT(GOODIDX(coreidx));
 505         ASSERT(regoff < SI_CORE_SIZE);
 506         ASSERT((val & ~mask) == 0);
 507
 508         if (coreidx >= SI_MAXCORES)
 509                 return 0;
 510
 511         if (BUSTYPE(sih->bustype) == SI_BUS) {
 512                 /* If internal bus, we can always get at everything */
 513                 fast = true;
 514                 /* map if does not exist */
 515                 if (!sii->regs[coreidx]) {
 516                         sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
 517                                                      SI_CORE_SIZE);
 518                         ASSERT(GOODREGS(sii->regs[coreidx]));
 519                 }
 520                 r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
 521         } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
 522                 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
 523
 524                 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
 525                         /* Chipc registers are mapped at 12KB */
 526
 527                         fast = true;
 528                         r = (u32 *) ((char *)sii->curmap +
 529                                         PCI_16KB0_CCREGS_OFFSET + regoff);
 530                 } else if (sii->pub.buscoreidx == coreidx) {
 531                         /* pci registers are at either in the last 2KB of an 8KB window
 532                          * or, in pcie and pci rev 13 at 8KB
 533                          */
 534                         fast = true;
 535                         if (SI_FAST(sii))
 536                                 r = (u32 *) ((char *)sii->curmap +
 537                                                 PCI_16KB0_PCIREGS_OFFSET +
 538                                                 regoff);
 539                         else
 540                                 r = (u32 *) ((char *)sii->curmap +
 541                                                 ((regoff >= SBCONFIGOFF) ?
 542                                                  PCI_BAR0_PCISBR_OFFSET :
 543                                                  PCI_BAR0_PCIREGS_OFFSET) +
 544                                                 regoff);
 545                 }
 546         }
 547
 548         if (!fast) {
 549                 INTR_OFF(sii, intr_val);
 550
 551                 /* save current core index */
 552                 origidx = si_coreidx(&sii->pub);
 553
 554                 /* switch core */
 555                 r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
 556                                 regoff);
 557         }
 558         ASSERT(r != NULL);
 559
 560         /* mask and set */
 561         if (mask || val) {
 562                 w = (R_REG(sii->osh, r) & ~mask) | val;
 563                 W_REG(sii->osh, r, w);
 564         }
 565
 566         /* readback */
 567         w = R_REG(sii->osh, r);
 568
 569         if (!fast) {
 570                 /* restore core index */
 571                 if (origidx != coreidx)
 572                         ai_setcoreidx(&sii->pub, origidx);
 573
 574                 INTR_RESTORE(sii, intr_val);
 575         }
 576
 577         return w;
 578 }
 579
 580 void ai_core_disable(si_t *sih, u32 bits)
 581 {
 582         si_info_t *sii;
 583         volatile u32 dummy;
 584         aidmp_t *ai;
 585
 586         sii = SI_INFO(sih);
 587
 588         ASSERT(GOODREGS(sii->curwrap));
 589         ai = sii->curwrap;
 590
 591         /* if core is already in reset, just return */
 592         if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
 593                 return;
 594
 595         W_REG(sii->osh, &ai->ioctrl, bits);
 596         dummy = R_REG(sii->osh, &ai->ioctrl);
 597         udelay(10);
 598
 599         W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
 600         udelay(1);
 601 }
 602
 603 /* reset and re-enable a core
 604  * inputs:
 605  * bits - core specific bits that are set during and after reset sequence
 606  * resetbits - core specific bits that are set only during reset sequence
 607  */
 608 void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
 609 {
 610         si_info_t *sii;
 611         aidmp_t *ai;
 612         volatile u32 dummy;
 613
 614         sii = SI_INFO(sih);
 615         ASSERT(GOODREGS(sii->curwrap));
 616         ai = sii->curwrap;
 617
 618         /*
 619          * Must do the disable sequence first to work for arbitrary current core state.
 620          */
 621         ai_core_disable(sih, (bits | resetbits));
 622
 623         /*
 624          * Now do the initialization sequence.
 625          */
 626         W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
 627         dummy = R_REG(sii->osh, &ai->ioctrl);
 628         W_REG(sii->osh, &ai->resetctrl, 0);
 629         udelay(1);
 630
 631         W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
 632         dummy = R_REG(sii->osh, &ai->ioctrl);
 633         udelay(1);
 634 }
 635
 636 void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
 637 {
 638         si_info_t *sii;
 639         aidmp_t *ai;
 640         u32 w;
 641
 642         sii = SI_INFO(sih);
 643
 644         if (BCM47162_DMP()) {
 645                 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
 646                           __func__));
 647                 return;
 648         }
 649
 650         ASSERT(GOODREGS(sii->curwrap));
 651         ai = sii->curwrap;
 652
 653         ASSERT((val & ~mask) == 0);
 654
 655         if (mask || val) {
 656                 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
 657                 W_REG(sii->osh, &ai->ioctrl, w);
 658         }
 659 }
 660
 661 u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
 662 {
 663         si_info_t *sii;
 664         aidmp_t *ai;
 665         u32 w;
 666
 667         sii = SI_INFO(sih);
 668         if (BCM47162_DMP()) {
 669                 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
 670                           __func__));
 671                 return 0;
 672         }
 673
 674         ASSERT(GOODREGS(sii->curwrap));
 675         ai = sii->curwrap;
 676
 677         ASSERT((val & ~mask) == 0);
 678
 679         if (mask || val) {
 680                 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
 681                 W_REG(sii->osh, &ai->ioctrl, w);
 682         }
 683
 684         return R_REG(sii->osh, &ai->ioctrl);
 685 }
 686
 687 u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
 688 {
 689         si_info_t *sii;
 690         aidmp_t *ai;
 691         u32 w;
 692
 693         sii = SI_INFO(sih);
 694         if (BCM47162_DMP()) {
 695                 SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
 696                 return 0;
 697         }
 698
 699         ASSERT(GOODREGS(sii->curwrap));
 700         ai = sii->curwrap;
 701
 702         ASSERT((val & ~mask) == 0);
 703         ASSERT((mask & ~SISF_CORE_BITS) == 0);
 704
 705         if (mask || val) {
 706                 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
 707                 W_REG(sii->osh, &ai->iostatus, w);
 708         }
 709
 710         return R_REG(sii->osh, &ai->iostatus);
 711 }
 712