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ath9k_hw: prevent a fast channel change after a rx DMA stuck issue
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
blob079b9638bef51f48bfea280f0bafa78c238497dd
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 #define ATH9K_CLOCK_RATE_CCK 22
27 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
28 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
29 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32
33 MODULE_AUTHOR("Atheros Communications");
34 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
35 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
36 MODULE_LICENSE("Dual BSD/GPL");
37
38 static int __init ath9k_init(void)
39 {
40 return 0;
41 }
42 module_init(ath9k_init);
43
44 static void __exit ath9k_exit(void)
45 {
46 return;
47 }
48 module_exit(ath9k_exit);
49
50 /* Private hardware callbacks */
51
52 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
55 }
56
57 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
58 {
59 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
60 }
61
62 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
63 {
64 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
65
66 return priv_ops->macversion_supported(ah->hw_version.macVersion);
67 }
68
69 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
70 struct ath9k_channel *chan)
71 {
72 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
73 }
74
75 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
76 {
77 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
78 return;
79
80 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
81 }
82
83 /********************/
84 /* Helper Functions */
85 /********************/
86
87 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
88 {
89 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
90
91 if (!ah->curchan) /* should really check for CCK instead */
92 return usecs *ATH9K_CLOCK_RATE_CCK;
93 if (conf->channel->band == IEEE80211_BAND_2GHZ)
94 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
95
96 if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
97 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
98 else
99 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
100 }
101
102 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
103 {
104 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
105
106 if (conf_is_ht40(conf))
107 return ath9k_hw_mac_clks(ah, usecs) * 2;
108 else
109 return ath9k_hw_mac_clks(ah, usecs);
110 }
111
112 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
113 {
114 int i;
115
116 BUG_ON(timeout < AH_TIME_QUANTUM);
117
118 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
119 if ((REG_READ(ah, reg) & mask) == val)
120 return true;
121
122 udelay(AH_TIME_QUANTUM);
123 }
124
125 ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
126 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
127 timeout, reg, REG_READ(ah, reg), mask, val);
128
129 return false;
130 }
131 EXPORT_SYMBOL(ath9k_hw_wait);
132
133 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
134 {
135 u32 retval;
136 int i;
137
138 for (i = 0, retval = 0; i < n; i++) {
139 retval = (retval << 1) | (val & 1);
140 val >>= 1;
141 }
142 return retval;
143 }
144
145 bool ath9k_get_channel_edges(struct ath_hw *ah,
146 u16 flags, u16 *low,
147 u16 *high)
148 {
149 struct ath9k_hw_capabilities *pCap = &ah->caps;
150
151 if (flags & CHANNEL_5GHZ) {
152 *low = pCap->low_5ghz_chan;
153 *high = pCap->high_5ghz_chan;
154 return true;
155 }
156 if ((flags & CHANNEL_2GHZ)) {
157 *low = pCap->low_2ghz_chan;
158 *high = pCap->high_2ghz_chan;
159 return true;
160 }
161 return false;
162 }
163
164 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
165 u8 phy, int kbps,
166 u32 frameLen, u16 rateix,
167 bool shortPreamble)
168 {
169 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
170
171 if (kbps == 0)
172 return 0;
173
174 switch (phy) {
175 case WLAN_RC_PHY_CCK:
176 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
177 if (shortPreamble)
178 phyTime >>= 1;
179 numBits = frameLen << 3;
180 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
181 break;
182 case WLAN_RC_PHY_OFDM:
183 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
184 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
185 numBits = OFDM_PLCP_BITS + (frameLen << 3);
186 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
187 txTime = OFDM_SIFS_TIME_QUARTER
188 + OFDM_PREAMBLE_TIME_QUARTER
189 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
190 } else if (ah->curchan &&
191 IS_CHAN_HALF_RATE(ah->curchan)) {
192 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
193 numBits = OFDM_PLCP_BITS + (frameLen << 3);
194 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
195 txTime = OFDM_SIFS_TIME_HALF +
196 OFDM_PREAMBLE_TIME_HALF
197 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
198 } else {
199 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
200 numBits = OFDM_PLCP_BITS + (frameLen << 3);
201 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
202 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
203 + (numSymbols * OFDM_SYMBOL_TIME);
204 }
205 break;
206 default:
207 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
208 "Unknown phy %u (rate ix %u)\n", phy, rateix);
209 txTime = 0;
210 break;
211 }
212
213 return txTime;
214 }
215 EXPORT_SYMBOL(ath9k_hw_computetxtime);
216
217 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
218 struct ath9k_channel *chan,
219 struct chan_centers *centers)
220 {
221 int8_t extoff;
222
223 if (!IS_CHAN_HT40(chan)) {
224 centers->ctl_center = centers->ext_center =
225 centers->synth_center = chan->channel;
226 return;
227 }
228
229 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
230 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
231 centers->synth_center =
232 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
233 extoff = 1;
234 } else {
235 centers->synth_center =
236 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
237 extoff = -1;
238 }
239
240 centers->ctl_center =
241 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
242 /* 25 MHz spacing is supported by hw but not on upper layers */
243 centers->ext_center =
244 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
245 }
246
247 /******************/
248 /* Chip Revisions */
249 /******************/
250
251 static void ath9k_hw_read_revisions(struct ath_hw *ah)
252 {
253 u32 val;
254
255 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
256
257 if (val == 0xFF) {
258 val = REG_READ(ah, AR_SREV);
259 ah->hw_version.macVersion =
260 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
261 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
262 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
263 } else {
264 if (!AR_SREV_9100(ah))
265 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
266
267 ah->hw_version.macRev = val & AR_SREV_REVISION;
268
269 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
270 ah->is_pciexpress = true;
271 }
272 }
273
274 /************************************/
275 /* HW Attach, Detach, Init Routines */
276 /************************************/
277
278 static void ath9k_hw_disablepcie(struct ath_hw *ah)
279 {
280 if (AR_SREV_9100(ah))
281 return;
282
283 ENABLE_REGWRITE_BUFFER(ah);
284
285 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
286 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
287 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
288 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
289 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
290 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
291 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
292 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
293 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
294
295 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
296
297 REGWRITE_BUFFER_FLUSH(ah);
298 DISABLE_REGWRITE_BUFFER(ah);
299 }
300
301 /* This should work for all families including legacy */
302 static bool ath9k_hw_chip_test(struct ath_hw *ah)
303 {
304 struct ath_common *common = ath9k_hw_common(ah);
305 u32 regAddr[2] = { AR_STA_ID0 };
306 u32 regHold[2];
307 u32 patternData[4] = { 0x55555555,
308 0xaaaaaaaa,
309 0x66666666,
310 0x99999999 };
311 int i, j, loop_max;
312
313 if (!AR_SREV_9300_20_OR_LATER(ah)) {
314 loop_max = 2;
315 regAddr[1] = AR_PHY_BASE + (8 << 2);
316 } else
317 loop_max = 1;
318
319 for (i = 0; i < loop_max; i++) {
320 u32 addr = regAddr[i];
321 u32 wrData, rdData;
322
323 regHold[i] = REG_READ(ah, addr);
324 for (j = 0; j < 0x100; j++) {
325 wrData = (j << 16) | j;
326 REG_WRITE(ah, addr, wrData);
327 rdData = REG_READ(ah, addr);
328 if (rdData != wrData) {
329 ath_print(common, ATH_DBG_FATAL,
330 "address test failed "
331 "addr: 0x%08x - wr:0x%08x != "
332 "rd:0x%08x\n",
333 addr, wrData, rdData);
334 return false;
335 }
336 }
337 for (j = 0; j < 4; j++) {
338 wrData = patternData[j];
339 REG_WRITE(ah, addr, wrData);
340 rdData = REG_READ(ah, addr);
341 if (wrData != rdData) {
342 ath_print(common, ATH_DBG_FATAL,
343 "address test failed "
344 "addr: 0x%08x - wr:0x%08x != "
345 "rd:0x%08x\n",
346 addr, wrData, rdData);
347 return false;
348 }
349 }
350 REG_WRITE(ah, regAddr[i], regHold[i]);
351 }
352 udelay(100);
353
354 return true;
355 }
356
357 static void ath9k_hw_init_config(struct ath_hw *ah)
358 {
359 int i;
360
361 ah->config.dma_beacon_response_time = 2;
362 ah->config.sw_beacon_response_time = 10;
363 ah->config.additional_swba_backoff = 0;
364 ah->config.ack_6mb = 0x0;
365 ah->config.cwm_ignore_extcca = 0;
366 ah->config.pcie_powersave_enable = 0;
367 ah->config.pcie_clock_req = 0;
368 ah->config.pcie_waen = 0;
369 ah->config.analog_shiftreg = 1;
370 ah->config.ofdm_trig_low = 200;
371 ah->config.ofdm_trig_high = 500;
372 ah->config.cck_trig_high = 200;
373 ah->config.cck_trig_low = 100;
374
375 /*
376 * For now ANI is disabled for AR9003, it is still
377 * being tested.
378 */
379 if (!AR_SREV_9300_20_OR_LATER(ah))
380 ah->config.enable_ani = 1;
381
382 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
383 ah->config.spurchans[i][0] = AR_NO_SPUR;
384 ah->config.spurchans[i][1] = AR_NO_SPUR;
385 }
386
387 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
388 ah->config.ht_enable = 1;
389 else
390 ah->config.ht_enable = 0;
391
392 ah->config.rx_intr_mitigation = true;
393
394 /*
395 * Tx IQ Calibration (ah->config.tx_iq_calibration) is only
396 * used by AR9003, but it is showing reliability issues.
397 * It will take a while to fix so this is currently disabled.
398 */
399
400 /*
401 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
402 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
403 * This means we use it for all AR5416 devices, and the few
404 * minor PCI AR9280 devices out there.
405 *
406 * Serialization is required because these devices do not handle
407 * well the case of two concurrent reads/writes due to the latency
408 * involved. During one read/write another read/write can be issued
409 * on another CPU while the previous read/write may still be working
410 * on our hardware, if we hit this case the hardware poops in a loop.
411 * We prevent this by serializing reads and writes.
412 *
413 * This issue is not present on PCI-Express devices or pre-AR5416
414 * devices (legacy, 802.11abg).
415 */
416 if (num_possible_cpus() > 1)
417 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
418 }
419
420 static void ath9k_hw_init_defaults(struct ath_hw *ah)
421 {
422 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
423
424 regulatory->country_code = CTRY_DEFAULT;
425 regulatory->power_limit = MAX_RATE_POWER;
426 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
427
428 ah->hw_version.magic = AR5416_MAGIC;
429 ah->hw_version.subvendorid = 0;
430
431 ah->ah_flags = 0;
432 if (!AR_SREV_9100(ah))
433 ah->ah_flags = AH_USE_EEPROM;
434
435 ah->atim_window = 0;
436 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
437 ah->beacon_interval = 100;
438 ah->enable_32kHz_clock = DONT_USE_32KHZ;
439 ah->slottime = (u32) -1;
440 ah->globaltxtimeout = (u32) -1;
441 ah->power_mode = ATH9K_PM_UNDEFINED;
442 }
443
444 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
445 {
446 struct ath_common *common = ath9k_hw_common(ah);
447 u32 sum;
448 int i;
449 u16 eeval;
450 u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
451
452 sum = 0;
453 for (i = 0; i < 3; i++) {
454 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
455 sum += eeval;
456 common->macaddr[2 * i] = eeval >> 8;
457 common->macaddr[2 * i + 1] = eeval & 0xff;
458 }
459 if (sum == 0 || sum == 0xffff * 3)
460 return -EADDRNOTAVAIL;
461
462 return 0;
463 }
464
465 static int ath9k_hw_post_init(struct ath_hw *ah)
466 {
467 int ecode;
468
469 if (!AR_SREV_9271(ah)) {
470 if (!ath9k_hw_chip_test(ah))
471 return -ENODEV;
472 }
473
474 if (!AR_SREV_9300_20_OR_LATER(ah)) {
475 ecode = ar9002_hw_rf_claim(ah);
476 if (ecode != 0)
477 return ecode;
478 }
479
480 ecode = ath9k_hw_eeprom_init(ah);
481 if (ecode != 0)
482 return ecode;
483
484 ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
485 "Eeprom VER: %d, REV: %d\n",
486 ah->eep_ops->get_eeprom_ver(ah),
487 ah->eep_ops->get_eeprom_rev(ah));
488
489 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
490 if (ecode) {
491 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
492 "Failed allocating banks for "
493 "external radio\n");
494 return ecode;
495 }
496
497 if (!AR_SREV_9100(ah)) {
498 ath9k_hw_ani_setup(ah);
499 ath9k_hw_ani_init(ah);
500 }
501
502 return 0;
503 }
504
505 static void ath9k_hw_attach_ops(struct ath_hw *ah)
506 {
507 if (AR_SREV_9300_20_OR_LATER(ah))
508 ar9003_hw_attach_ops(ah);
509 else
510 ar9002_hw_attach_ops(ah);
511 }
512
513 /* Called for all hardware families */
514 static int __ath9k_hw_init(struct ath_hw *ah)
515 {
516 struct ath_common *common = ath9k_hw_common(ah);
517 int r = 0;
518
519 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
520 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
521
522 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
523 ath_print(common, ATH_DBG_FATAL,
524 "Couldn't reset chip\n");
525 return -EIO;
526 }
527
528 ath9k_hw_init_defaults(ah);
529 ath9k_hw_init_config(ah);
530
531 ath9k_hw_attach_ops(ah);
532
533 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
534 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
535 return -EIO;
536 }
537
538 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
539 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
540 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
541 !ah->is_pciexpress)) {
542 ah->config.serialize_regmode =
543 SER_REG_MODE_ON;
544 } else {
545 ah->config.serialize_regmode =
546 SER_REG_MODE_OFF;
547 }
548 }
549
550 ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
551 ah->config.serialize_regmode);
552
553 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
554 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
555 else
556 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
557
558 if (!ath9k_hw_macversion_supported(ah)) {
559 ath_print(common, ATH_DBG_FATAL,
560 "Mac Chip Rev 0x%02x.%x is not supported by "
561 "this driver\n", ah->hw_version.macVersion,
562 ah->hw_version.macRev);
563 return -EOPNOTSUPP;
564 }
565
566 if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
567 ah->is_pciexpress = false;
568
569 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
570 ath9k_hw_init_cal_settings(ah);
571
572 ah->ani_function = ATH9K_ANI_ALL;
573 if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
574 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
575
576 ath9k_hw_init_mode_regs(ah);
577
578 /*
579 * Configire PCIE after Ini init. SERDES values now come from ini file
580 * This enables PCIe low power mode.
581 */
582 if (AR_SREV_9300_20_OR_LATER(ah)) {
583 u32 regval;
584 unsigned int i;
585
586 /* Set Bits 16 and 17 in the AR_WA register. */
587 regval = REG_READ(ah, AR_WA);
588 regval |= 0x00030000;
589 REG_WRITE(ah, AR_WA, regval);
590
591 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
592 REG_WRITE(ah,
593 INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
594 INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
595 }
596 }
597
598 if (ah->is_pciexpress)
599 ath9k_hw_configpcipowersave(ah, 0, 0);
600 else
601 ath9k_hw_disablepcie(ah);
602
603 if (!AR_SREV_9300_20_OR_LATER(ah))
604 ar9002_hw_cck_chan14_spread(ah);
605
606 r = ath9k_hw_post_init(ah);
607 if (r)
608 return r;
609
610 ath9k_hw_init_mode_gain_regs(ah);
611 r = ath9k_hw_fill_cap_info(ah);
612 if (r)
613 return r;
614
615 r = ath9k_hw_init_macaddr(ah);
616 if (r) {
617 ath_print(common, ATH_DBG_FATAL,
618 "Failed to initialize MAC address\n");
619 return r;
620 }
621
622 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
623 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
624 else
625 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
626
627 if (AR_SREV_9300_20_OR_LATER(ah))
628 ar9003_hw_set_nf_limits(ah);
629
630 ath9k_init_nfcal_hist_buffer(ah);
631
632 common->state = ATH_HW_INITIALIZED;
633
634 return 0;
635 }
636
637 int ath9k_hw_init(struct ath_hw *ah)
638 {
639 int ret;
640 struct ath_common *common = ath9k_hw_common(ah);
641
642 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
643 switch (ah->hw_version.devid) {
644 case AR5416_DEVID_PCI:
645 case AR5416_DEVID_PCIE:
646 case AR5416_AR9100_DEVID:
647 case AR9160_DEVID_PCI:
648 case AR9280_DEVID_PCI:
649 case AR9280_DEVID_PCIE:
650 case AR9285_DEVID_PCIE:
651 case AR9287_DEVID_PCI:
652 case AR9287_DEVID_PCIE:
653 case AR2427_DEVID_PCIE:
654 case AR9300_DEVID_PCIE:
655 break;
656 default:
657 if (common->bus_ops->ath_bus_type == ATH_USB)
658 break;
659 ath_print(common, ATH_DBG_FATAL,
660 "Hardware device ID 0x%04x not supported\n",
661 ah->hw_version.devid);
662 return -EOPNOTSUPP;
663 }
664
665 ret = __ath9k_hw_init(ah);
666 if (ret) {
667 ath_print(common, ATH_DBG_FATAL,
668 "Unable to initialize hardware; "
669 "initialization status: %d\n", ret);
670 return ret;
671 }
672
673 return 0;
674 }
675 EXPORT_SYMBOL(ath9k_hw_init);
676
677 static void ath9k_hw_init_qos(struct ath_hw *ah)
678 {
679 ENABLE_REGWRITE_BUFFER(ah);
680
681 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
682 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
683
684 REG_WRITE(ah, AR_QOS_NO_ACK,
685 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
686 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
687 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
688
689 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
690 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
691 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
692 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
693 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
694
695 REGWRITE_BUFFER_FLUSH(ah);
696 DISABLE_REGWRITE_BUFFER(ah);
697 }
698
699 static void ath9k_hw_init_pll(struct ath_hw *ah,
700 struct ath9k_channel *chan)
701 {
702 u32 pll = ath9k_hw_compute_pll_control(ah, chan);
703
704 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
705
706 /* Switch the core clock for ar9271 to 117Mhz */
707 if (AR_SREV_9271(ah)) {
708 udelay(500);
709 REG_WRITE(ah, 0x50040, 0x304);
710 }
711
712 udelay(RTC_PLL_SETTLE_DELAY);
713
714 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
715 }
716
717 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
718 enum nl80211_iftype opmode)
719 {
720 u32 imr_reg = AR_IMR_TXERR |
721 AR_IMR_TXURN |
722 AR_IMR_RXERR |
723 AR_IMR_RXORN |
724 AR_IMR_BCNMISC;
725
726 if (AR_SREV_9300_20_OR_LATER(ah)) {
727 imr_reg |= AR_IMR_RXOK_HP;
728 if (ah->config.rx_intr_mitigation)
729 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
730 else
731 imr_reg |= AR_IMR_RXOK_LP;
732
733 } else {
734 if (ah->config.rx_intr_mitigation)
735 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
736 else
737 imr_reg |= AR_IMR_RXOK;
738 }
739
740 if (ah->config.tx_intr_mitigation)
741 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
742 else
743 imr_reg |= AR_IMR_TXOK;
744
745 if (opmode == NL80211_IFTYPE_AP)
746 imr_reg |= AR_IMR_MIB;
747
748 ENABLE_REGWRITE_BUFFER(ah);
749
750 REG_WRITE(ah, AR_IMR, imr_reg);
751 ah->imrs2_reg |= AR_IMR_S2_GTT;
752 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
753
754 if (!AR_SREV_9100(ah)) {
755 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
756 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
757 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
758 }
759
760 REGWRITE_BUFFER_FLUSH(ah);
761 DISABLE_REGWRITE_BUFFER(ah);
762
763 if (AR_SREV_9300_20_OR_LATER(ah)) {
764 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
765 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
766 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
767 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
768 }
769 }
770
771 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
772 {
773 u32 val = ath9k_hw_mac_to_clks(ah, us);
774 val = min(val, (u32) 0xFFFF);
775 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
776 }
777
778 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
779 {
780 u32 val = ath9k_hw_mac_to_clks(ah, us);
781 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
782 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
783 }
784
785 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
786 {
787 u32 val = ath9k_hw_mac_to_clks(ah, us);
788 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
789 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
790 }
791
792 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
793 {
794 if (tu > 0xFFFF) {
795 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
796 "bad global tx timeout %u\n", tu);
797 ah->globaltxtimeout = (u32) -1;
798 return false;
799 } else {
800 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
801 ah->globaltxtimeout = tu;
802 return true;
803 }
804 }
805
806 void ath9k_hw_init_global_settings(struct ath_hw *ah)
807 {
808 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
809 int acktimeout;
810 int slottime;
811 int sifstime;
812
813 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
814 ah->misc_mode);
815
816 if (ah->misc_mode != 0)
817 REG_WRITE(ah, AR_PCU_MISC,
818 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
819
820 if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
821 sifstime = 16;
822 else
823 sifstime = 10;
824
825 /* As defined by IEEE 802.11-2007 17.3.8.6 */
826 slottime = ah->slottime + 3 * ah->coverage_class;
827 acktimeout = slottime + sifstime;
828
829 /*
830 * Workaround for early ACK timeouts, add an offset to match the
831 * initval's 64us ack timeout value.
832 * This was initially only meant to work around an issue with delayed
833 * BA frames in some implementations, but it has been found to fix ACK
834 * timeout issues in other cases as well.
835 */
836 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
837 acktimeout += 64 - sifstime - ah->slottime;
838
839 ath9k_hw_setslottime(ah, slottime);
840 ath9k_hw_set_ack_timeout(ah, acktimeout);
841 ath9k_hw_set_cts_timeout(ah, acktimeout);
842 if (ah->globaltxtimeout != (u32) -1)
843 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
844 }
845 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
846
847 void ath9k_hw_deinit(struct ath_hw *ah)
848 {
849 struct ath_common *common = ath9k_hw_common(ah);
850
851 if (common->state < ATH_HW_INITIALIZED)
852 goto free_hw;
853
854 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
855
856 free_hw:
857 ath9k_hw_rf_free_ext_banks(ah);
858 }
859 EXPORT_SYMBOL(ath9k_hw_deinit);
860
861 /*******/
862 /* INI */
863 /*******/
864
865 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
866 {
867 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
868
869 if (IS_CHAN_B(chan))
870 ctl |= CTL_11B;
871 else if (IS_CHAN_G(chan))
872 ctl |= CTL_11G;
873 else
874 ctl |= CTL_11A;
875
876 return ctl;
877 }
878
879 /****************************************/
880 /* Reset and Channel Switching Routines */
881 /****************************************/
882
883 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
884 {
885 struct ath_common *common = ath9k_hw_common(ah);
886 u32 regval;
887
888 ENABLE_REGWRITE_BUFFER(ah);
889
890 /*
891 * set AHB_MODE not to do cacheline prefetches
892 */
893 if (!AR_SREV_9300_20_OR_LATER(ah)) {
894 regval = REG_READ(ah, AR_AHB_MODE);
895 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
896 }
897
898 /*
899 * let mac dma reads be in 128 byte chunks
900 */
901 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
902 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
903
904 REGWRITE_BUFFER_FLUSH(ah);
905 DISABLE_REGWRITE_BUFFER(ah);
906
907 /*
908 * Restore TX Trigger Level to its pre-reset value.
909 * The initial value depends on whether aggregation is enabled, and is
910 * adjusted whenever underruns are detected.
911 */
912 if (!AR_SREV_9300_20_OR_LATER(ah))
913 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
914
915 ENABLE_REGWRITE_BUFFER(ah);
916
917 /*
918 * let mac dma writes be in 128 byte chunks
919 */
920 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
921 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
922
923 /*
924 * Setup receive FIFO threshold to hold off TX activities
925 */
926 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
927
928 if (AR_SREV_9300_20_OR_LATER(ah)) {
929 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
930 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
931
932 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
933 ah->caps.rx_status_len);
934 }
935
936 /*
937 * reduce the number of usable entries in PCU TXBUF to avoid
938 * wrap around issues.
939 */
940 if (AR_SREV_9285(ah)) {
941 /* For AR9285 the number of Fifos are reduced to half.
942 * So set the usable tx buf size also to half to
943 * avoid data/delimiter underruns
944 */
945 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
946 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
947 } else if (!AR_SREV_9271(ah)) {
948 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
949 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
950 }
951
952 REGWRITE_BUFFER_FLUSH(ah);
953 DISABLE_REGWRITE_BUFFER(ah);
954
955 if (AR_SREV_9300_20_OR_LATER(ah))
956 ath9k_hw_reset_txstatus_ring(ah);
957 }
958
959 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
960 {
961 u32 val;
962
963 val = REG_READ(ah, AR_STA_ID1);
964 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
965 switch (opmode) {
966 case NL80211_IFTYPE_AP:
967 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
968 | AR_STA_ID1_KSRCH_MODE);
969 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
970 break;
971 case NL80211_IFTYPE_ADHOC:
972 case NL80211_IFTYPE_MESH_POINT:
973 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
974 | AR_STA_ID1_KSRCH_MODE);
975 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
976 break;
977 case NL80211_IFTYPE_STATION:
978 case NL80211_IFTYPE_MONITOR:
979 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
980 break;
981 }
982 }
983
984 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
985 u32 *coef_mantissa, u32 *coef_exponent)
986 {
987 u32 coef_exp, coef_man;
988
989 for (coef_exp = 31; coef_exp > 0; coef_exp--)
990 if ((coef_scaled >> coef_exp) & 0x1)
991 break;
992
993 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
994
995 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
996
997 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
998 *coef_exponent = coef_exp - 16;
999 }
1000
1001 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1002 {
1003 u32 rst_flags;
1004 u32 tmpReg;
1005
1006 if (AR_SREV_9100(ah)) {
1007 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1008 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1009 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1010 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1011 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1012 }
1013
1014 ENABLE_REGWRITE_BUFFER(ah);
1015
1016 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1017 AR_RTC_FORCE_WAKE_ON_INT);
1018
1019 if (AR_SREV_9100(ah)) {
1020 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1021 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1022 } else {
1023 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1024 if (tmpReg &
1025 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1026 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1027 u32 val;
1028 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1029
1030 val = AR_RC_HOSTIF;
1031 if (!AR_SREV_9300_20_OR_LATER(ah))
1032 val |= AR_RC_AHB;
1033 REG_WRITE(ah, AR_RC, val);
1034
1035 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1036 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1037
1038 rst_flags = AR_RTC_RC_MAC_WARM;
1039 if (type == ATH9K_RESET_COLD)
1040 rst_flags |= AR_RTC_RC_MAC_COLD;
1041 }
1042
1043 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1044
1045 REGWRITE_BUFFER_FLUSH(ah);
1046 DISABLE_REGWRITE_BUFFER(ah);
1047
1048 udelay(50);
1049
1050 REG_WRITE(ah, AR_RTC_RC, 0);
1051 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1052 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1053 "RTC stuck in MAC reset\n");
1054 return false;
1055 }
1056
1057 if (!AR_SREV_9100(ah))
1058 REG_WRITE(ah, AR_RC, 0);
1059
1060 if (AR_SREV_9100(ah))
1061 udelay(50);
1062
1063 return true;
1064 }
1065
1066 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1067 {
1068 ENABLE_REGWRITE_BUFFER(ah);
1069
1070 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1071 AR_RTC_FORCE_WAKE_ON_INT);
1072
1073 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1074 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1075
1076 REG_WRITE(ah, AR_RTC_RESET, 0);
1077
1078 REGWRITE_BUFFER_FLUSH(ah);
1079 DISABLE_REGWRITE_BUFFER(ah);
1080
1081 if (!AR_SREV_9300_20_OR_LATER(ah))
1082 udelay(2);
1083
1084 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1085 REG_WRITE(ah, AR_RC, 0);
1086
1087 REG_WRITE(ah, AR_RTC_RESET, 1);
1088
1089 if (!ath9k_hw_wait(ah,
1090 AR_RTC_STATUS,
1091 AR_RTC_STATUS_M,
1092 AR_RTC_STATUS_ON,
1093 AH_WAIT_TIMEOUT)) {
1094 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1095 "RTC not waking up\n");
1096 return false;
1097 }
1098
1099 ath9k_hw_read_revisions(ah);
1100
1101 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1102 }
1103
1104 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1105 {
1106 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1107 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1108
1109 switch (type) {
1110 case ATH9K_RESET_POWER_ON:
1111 return ath9k_hw_set_reset_power_on(ah);
1112 case ATH9K_RESET_WARM:
1113 case ATH9K_RESET_COLD:
1114 return ath9k_hw_set_reset(ah, type);
1115 default:
1116 return false;
1117 }
1118 }
1119
1120 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1121 struct ath9k_channel *chan)
1122 {
1123 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1124 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1125 return false;
1126 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1127 return false;
1128
1129 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1130 return false;
1131
1132 ah->chip_fullsleep = false;
1133 ath9k_hw_init_pll(ah, chan);
1134 ath9k_hw_set_rfmode(ah, chan);
1135
1136 return true;
1137 }
1138
1139 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1140 struct ath9k_channel *chan)
1141 {
1142 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1143 struct ath_common *common = ath9k_hw_common(ah);
1144 struct ieee80211_channel *channel = chan->chan;
1145 u32 qnum;
1146 int r;
1147
1148 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1149 if (ath9k_hw_numtxpending(ah, qnum)) {
1150 ath_print(common, ATH_DBG_QUEUE,
1151 "Transmit frames pending on "
1152 "queue %d\n", qnum);
1153 return false;
1154 }
1155 }
1156
1157 if (!ath9k_hw_rfbus_req(ah)) {
1158 ath_print(common, ATH_DBG_FATAL,
1159 "Could not kill baseband RX\n");
1160 return false;
1161 }
1162
1163 ath9k_hw_set_channel_regs(ah, chan);
1164
1165 r = ath9k_hw_rf_set_freq(ah, chan);
1166 if (r) {
1167 ath_print(common, ATH_DBG_FATAL,
1168 "Failed to set channel\n");
1169 return false;
1170 }
1171
1172 ah->eep_ops->set_txpower(ah, chan,
1173 ath9k_regd_get_ctl(regulatory, chan),
1174 channel->max_antenna_gain * 2,
1175 channel->max_power * 2,
1176 min((u32) MAX_RATE_POWER,
1177 (u32) regulatory->power_limit));
1178
1179 ath9k_hw_rfbus_done(ah);
1180
1181 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1182 ath9k_hw_set_delta_slope(ah, chan);
1183
1184 ath9k_hw_spur_mitigate_freq(ah, chan);
1185
1186 if (!chan->oneTimeCalsDone)
1187 chan->oneTimeCalsDone = true;
1188
1189 return true;
1190 }
1191
1192 bool ath9k_hw_check_alive(struct ath_hw *ah)
1193 {
1194 int count = 50;
1195 u32 reg;
1196
1197 if (AR_SREV_9285_10_OR_LATER(ah))
1198 return true;
1199
1200 do {
1201 reg = REG_READ(ah, AR_OBS_BUS_1);
1202
1203 if ((reg & 0x7E7FFFEF) == 0x00702400)
1204 continue;
1205
1206 switch (reg & 0x7E000B00) {
1207 case 0x1E000000:
1208 case 0x52000B00:
1209 case 0x18000B00:
1210 continue;
1211 default:
1212 return true;
1213 }
1214 } while (count-- > 0);
1215
1216 return false;
1217 }
1218 EXPORT_SYMBOL(ath9k_hw_check_alive);
1219
1220 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1221 bool bChannelChange)
1222 {
1223 struct ath_common *common = ath9k_hw_common(ah);
1224 u32 saveLedState;
1225 struct ath9k_channel *curchan = ah->curchan;
1226 u32 saveDefAntenna;
1227 u32 macStaId1;
1228 u64 tsf = 0;
1229 int i, r;
1230
1231 ah->txchainmask = common->tx_chainmask;
1232 ah->rxchainmask = common->rx_chainmask;
1233
1234 if (!ah->chip_fullsleep) {
1235 ath9k_hw_abortpcurecv(ah);
1236 if (!ath9k_hw_stopdmarecv(ah)) {
1237 ath_print(common, ATH_DBG_XMIT,
1238 "Failed to stop receive dma\n");
1239 bChannelChange = false;
1240 }
1241 }
1242
1243 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1244 return -EIO;
1245
1246 if (curchan && !ah->chip_fullsleep)
1247 ath9k_hw_getnf(ah, curchan);
1248
1249 if (bChannelChange &&
1250 (ah->chip_fullsleep != true) &&
1251 (ah->curchan != NULL) &&
1252 (chan->channel != ah->curchan->channel) &&
1253 ((chan->channelFlags & CHANNEL_ALL) ==
1254 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1255 !AR_SREV_9280(ah)) {
1256
1257 if (ath9k_hw_channel_change(ah, chan)) {
1258 ath9k_hw_loadnf(ah, ah->curchan);
1259 ath9k_hw_start_nfcal(ah);
1260 return 0;
1261 }
1262 }
1263
1264 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1265 if (saveDefAntenna == 0)
1266 saveDefAntenna = 1;
1267
1268 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1269
1270 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1271 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1272 tsf = ath9k_hw_gettsf64(ah);
1273
1274 saveLedState = REG_READ(ah, AR_CFG_LED) &
1275 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1276 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1277
1278 ath9k_hw_mark_phy_inactive(ah);
1279
1280 /* Only required on the first reset */
1281 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1282 REG_WRITE(ah,
1283 AR9271_RESET_POWER_DOWN_CONTROL,
1284 AR9271_RADIO_RF_RST);
1285 udelay(50);
1286 }
1287
1288 if (!ath9k_hw_chip_reset(ah, chan)) {
1289 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1290 return -EINVAL;
1291 }
1292
1293 /* Only required on the first reset */
1294 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1295 ah->htc_reset_init = false;
1296 REG_WRITE(ah,
1297 AR9271_RESET_POWER_DOWN_CONTROL,
1298 AR9271_GATE_MAC_CTL);
1299 udelay(50);
1300 }
1301
1302 /* Restore TSF */
1303 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1304 ath9k_hw_settsf64(ah, tsf);
1305
1306 if (AR_SREV_9280_10_OR_LATER(ah))
1307 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1308
1309 r = ath9k_hw_process_ini(ah, chan);
1310 if (r)
1311 return r;
1312
1313 /* Setup MFP options for CCMP */
1314 if (AR_SREV_9280_20_OR_LATER(ah)) {
1315 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1316 * frames when constructing CCMP AAD. */
1317 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1318 0xc7ff);
1319 ah->sw_mgmt_crypto = false;
1320 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1321 /* Disable hardware crypto for management frames */
1322 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1323 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1324 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1325 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1326 ah->sw_mgmt_crypto = true;
1327 } else
1328 ah->sw_mgmt_crypto = true;
1329
1330 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1331 ath9k_hw_set_delta_slope(ah, chan);
1332
1333 ath9k_hw_spur_mitigate_freq(ah, chan);
1334 ah->eep_ops->set_board_values(ah, chan);
1335
1336 ath9k_hw_set_operating_mode(ah, ah->opmode);
1337
1338 ENABLE_REGWRITE_BUFFER(ah);
1339
1340 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1341 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1342 | macStaId1
1343 | AR_STA_ID1_RTS_USE_DEF
1344 | (ah->config.
1345 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1346 | ah->sta_id1_defaults);
1347 ath_hw_setbssidmask(common);
1348 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1349 ath9k_hw_write_associd(ah);
1350 REG_WRITE(ah, AR_ISR, ~0);
1351 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1352
1353 REGWRITE_BUFFER_FLUSH(ah);
1354 DISABLE_REGWRITE_BUFFER(ah);
1355
1356 r = ath9k_hw_rf_set_freq(ah, chan);
1357 if (r)
1358 return r;
1359
1360 ENABLE_REGWRITE_BUFFER(ah);
1361
1362 for (i = 0; i < AR_NUM_DCU; i++)
1363 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1364
1365 REGWRITE_BUFFER_FLUSH(ah);
1366 DISABLE_REGWRITE_BUFFER(ah);
1367
1368 ah->intr_txqs = 0;
1369 for (i = 0; i < ah->caps.total_queues; i++)
1370 ath9k_hw_resettxqueue(ah, i);
1371
1372 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1373 ath9k_hw_init_qos(ah);
1374
1375 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1376 ath9k_enable_rfkill(ah);
1377
1378 ath9k_hw_init_global_settings(ah);
1379
1380 if (!AR_SREV_9300_20_OR_LATER(ah)) {
1381 ar9002_hw_enable_async_fifo(ah);
1382 ar9002_hw_enable_wep_aggregation(ah);
1383 }
1384
1385 REG_WRITE(ah, AR_STA_ID1,
1386 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1387
1388 ath9k_hw_set_dma(ah);
1389
1390 REG_WRITE(ah, AR_OBS, 8);
1391
1392 if (ah->config.rx_intr_mitigation) {
1393 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1394 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1395 }
1396
1397 if (ah->config.tx_intr_mitigation) {
1398 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1399 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1400 }
1401
1402 ath9k_hw_init_bb(ah, chan);
1403
1404 if (!ath9k_hw_init_cal(ah, chan))
1405 return -EIO;
1406
1407 ENABLE_REGWRITE_BUFFER(ah);
1408
1409 ath9k_hw_restore_chainmask(ah);
1410 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1411
1412 REGWRITE_BUFFER_FLUSH(ah);
1413 DISABLE_REGWRITE_BUFFER(ah);
1414
1415 /*
1416 * For big endian systems turn on swapping for descriptors
1417 */
1418 if (AR_SREV_9100(ah)) {
1419 u32 mask;
1420 mask = REG_READ(ah, AR_CFG);
1421 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1422 ath_print(common, ATH_DBG_RESET,
1423 "CFG Byte Swap Set 0x%x\n", mask);
1424 } else {
1425 mask =
1426 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1427 REG_WRITE(ah, AR_CFG, mask);
1428 ath_print(common, ATH_DBG_RESET,
1429 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1430 }
1431 } else {
1432 /* Configure AR9271 target WLAN */
1433 if (AR_SREV_9271(ah))
1434 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1435 #ifdef __BIG_ENDIAN
1436 else
1437 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1438 #endif
1439 }
1440
1441 if (ah->btcoex_hw.enabled)
1442 ath9k_hw_btcoex_enable(ah);
1443
1444 if (AR_SREV_9300_20_OR_LATER(ah)) {
1445 ath9k_hw_loadnf(ah, curchan);
1446 ath9k_hw_start_nfcal(ah);
1447 }
1448
1449 return 0;
1450 }
1451 EXPORT_SYMBOL(ath9k_hw_reset);
1452
1453 /************************/
1454 /* Key Cache Management */
1455 /************************/
1456
1457 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1458 {
1459 u32 keyType;
1460
1461 if (entry >= ah->caps.keycache_size) {
1462 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1463 "keychache entry %u out of range\n", entry);
1464 return false;
1465 }
1466
1467 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1468
1469 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1470 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1471 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1472 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1473 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1474 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1475 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1476 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1477
1478 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1479 u16 micentry = entry + 64;
1480
1481 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1482 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1483 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1484 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1485
1486 }
1487
1488 return true;
1489 }
1490 EXPORT_SYMBOL(ath9k_hw_keyreset);
1491
1492 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1493 {
1494 u32 macHi, macLo;
1495
1496 if (entry >= ah->caps.keycache_size) {
1497 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1498 "keychache entry %u out of range\n", entry);
1499 return false;
1500 }
1501
1502 if (mac != NULL) {
1503 macHi = (mac[5] << 8) | mac[4];
1504 macLo = (mac[3] << 24) |
1505 (mac[2] << 16) |
1506 (mac[1] << 8) |
1507 mac[0];
1508 macLo >>= 1;
1509 macLo |= (macHi & 1) << 31;
1510 macHi >>= 1;
1511 } else {
1512 macLo = macHi = 0;
1513 }
1514 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1515 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
1516
1517 return true;
1518 }
1519 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1520
1521 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1522 const struct ath9k_keyval *k,
1523 const u8 *mac)
1524 {
1525 const struct ath9k_hw_capabilities *pCap = &ah->caps;
1526 struct ath_common *common = ath9k_hw_common(ah);
1527 u32 key0, key1, key2, key3, key4;
1528 u32 keyType;
1529
1530 if (entry >= pCap->keycache_size) {
1531 ath_print(common, ATH_DBG_FATAL,
1532 "keycache entry %u out of range\n", entry);
1533 return false;
1534 }
1535
1536 switch (k->kv_type) {
1537 case ATH9K_CIPHER_AES_OCB:
1538 keyType = AR_KEYTABLE_TYPE_AES;
1539 break;
1540 case ATH9K_CIPHER_AES_CCM:
1541 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1542 ath_print(common, ATH_DBG_ANY,
1543 "AES-CCM not supported by mac rev 0x%x\n",
1544 ah->hw_version.macRev);
1545 return false;
1546 }
1547 keyType = AR_KEYTABLE_TYPE_CCM;
1548 break;
1549 case ATH9K_CIPHER_TKIP:
1550 keyType = AR_KEYTABLE_TYPE_TKIP;
1551 if (ATH9K_IS_MIC_ENABLED(ah)
1552 && entry + 64 >= pCap->keycache_size) {
1553 ath_print(common, ATH_DBG_ANY,
1554 "entry %u inappropriate for TKIP\n", entry);
1555 return false;
1556 }
1557 break;
1558 case ATH9K_CIPHER_WEP:
1559 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1560 ath_print(common, ATH_DBG_ANY,
1561 "WEP key length %u too small\n", k->kv_len);
1562 return false;
1563 }
1564 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1565 keyType = AR_KEYTABLE_TYPE_40;
1566 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1567 keyType = AR_KEYTABLE_TYPE_104;
1568 else
1569 keyType = AR_KEYTABLE_TYPE_128;
1570 break;
1571 case ATH9K_CIPHER_CLR:
1572 keyType = AR_KEYTABLE_TYPE_CLR;
1573 break;
1574 default:
1575 ath_print(common, ATH_DBG_FATAL,
1576 "cipher %u not supported\n", k->kv_type);
1577 return false;
1578 }
1579
1580 key0 = get_unaligned_le32(k->kv_val + 0);
1581 key1 = get_unaligned_le16(k->kv_val + 4);
1582 key2 = get_unaligned_le32(k->kv_val + 6);
1583 key3 = get_unaligned_le16(k->kv_val + 10);
1584 key4 = get_unaligned_le32(k->kv_val + 12);
1585 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1586 key4 &= 0xff;
1587
1588 /*
1589 * Note: Key cache registers access special memory area that requires
1590 * two 32-bit writes to actually update the values in the internal
1591 * memory. Consequently, the exact order and pairs used here must be
1592 * maintained.
1593 */
1594
1595 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1596 u16 micentry = entry + 64;
1597
1598 /*
1599 * Write inverted key[47:0] first to avoid Michael MIC errors
1600 * on frames that could be sent or received at the same time.
1601 * The correct key will be written in the end once everything
1602 * else is ready.
1603 */
1604 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1605 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1606
1607 /* Write key[95:48] */
1608 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1609 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1610
1611 /* Write key[127:96] and key type */
1612 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1613 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1614
1615 /* Write MAC address for the entry */
1616 (void) ath9k_hw_keysetmac(ah, entry, mac);
1617
1618 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1619 /*
1620 * TKIP uses two key cache entries:
1621 * Michael MIC TX/RX keys in the same key cache entry
1622 * (idx = main index + 64):
1623 * key0 [31:0] = RX key [31:0]
1624 * key1 [15:0] = TX key [31:16]
1625 * key1 [31:16] = reserved
1626 * key2 [31:0] = RX key [63:32]
1627 * key3 [15:0] = TX key [15:0]
1628 * key3 [31:16] = reserved
1629 * key4 [31:0] = TX key [63:32]
1630 */
1631 u32 mic0, mic1, mic2, mic3, mic4;
1632
1633 mic0 = get_unaligned_le32(k->kv_mic + 0);
1634 mic2 = get_unaligned_le32(k->kv_mic + 4);
1635 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1636 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1637 mic4 = get_unaligned_le32(k->kv_txmic + 4);
1638
1639 /* Write RX[31:0] and TX[31:16] */
1640 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1641 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1642
1643 /* Write RX[63:32] and TX[15:0] */
1644 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1645 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1646
1647 /* Write TX[63:32] and keyType(reserved) */
1648 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1649 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1650 AR_KEYTABLE_TYPE_CLR);
1651
1652 } else {
1653 /*
1654 * TKIP uses four key cache entries (two for group
1655 * keys):
1656 * Michael MIC TX/RX keys are in different key cache
1657 * entries (idx = main index + 64 for TX and
1658 * main index + 32 + 96 for RX):
1659 * key0 [31:0] = TX/RX MIC key [31:0]
1660 * key1 [31:0] = reserved
1661 * key2 [31:0] = TX/RX MIC key [63:32]
1662 * key3 [31:0] = reserved
1663 * key4 [31:0] = reserved
1664 *
1665 * Upper layer code will call this function separately
1666 * for TX and RX keys when these registers offsets are
1667 * used.
1668 */
1669 u32 mic0, mic2;
1670
1671 mic0 = get_unaligned_le32(k->kv_mic + 0);
1672 mic2 = get_unaligned_le32(k->kv_mic + 4);
1673
1674 /* Write MIC key[31:0] */
1675 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1676 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1677
1678 /* Write MIC key[63:32] */
1679 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1680 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1681
1682 /* Write TX[63:32] and keyType(reserved) */
1683 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1684 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1685 AR_KEYTABLE_TYPE_CLR);
1686 }
1687
1688 /* MAC address registers are reserved for the MIC entry */
1689 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1690 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1691
1692 /*
1693 * Write the correct (un-inverted) key[47:0] last to enable
1694 * TKIP now that all other registers are set with correct
1695 * values.
1696 */
1697 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1698 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1699 } else {
1700 /* Write key[47:0] */
1701 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1702 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1703
1704 /* Write key[95:48] */
1705 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1706 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1707
1708 /* Write key[127:96] and key type */
1709 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1710 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1711
1712 /* Write MAC address for the entry */
1713 (void) ath9k_hw_keysetmac(ah, entry, mac);
1714 }
1715
1716 return true;
1717 }
1718 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1719
1720 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1721 {
1722 if (entry < ah->caps.keycache_size) {
1723 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1724 if (val & AR_KEYTABLE_VALID)
1725 return true;
1726 }
1727 return false;
1728 }
1729 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1730
1731 /******************************/
1732 /* Power Management (Chipset) */
1733 /******************************/
1734
1735 /*
1736 * Notify Power Mgt is disabled in self-generated frames.
1737 * If requested, force chip to sleep.
1738 */
1739 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1740 {
1741 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1742 if (setChip) {
1743 /*
1744 * Clear the RTC force wake bit to allow the
1745 * mac to go to sleep.
1746 */
1747 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1748 AR_RTC_FORCE_WAKE_EN);
1749 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1750 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1751
1752 /* Shutdown chip. Active low */
1753 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1754 REG_CLR_BIT(ah, (AR_RTC_RESET),
1755 AR_RTC_RESET_EN);
1756 }
1757 }
1758
1759 /*
1760 * Notify Power Management is enabled in self-generating
1761 * frames. If request, set power mode of chip to
1762 * auto/normal. Duration in units of 128us (1/8 TU).
1763 */
1764 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1765 {
1766 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1767 if (setChip) {
1768 struct ath9k_hw_capabilities *pCap = &ah->caps;
1769
1770 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1771 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1772 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1773 AR_RTC_FORCE_WAKE_ON_INT);
1774 } else {
1775 /*
1776 * Clear the RTC force wake bit to allow the
1777 * mac to go to sleep.
1778 */
1779 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1780 AR_RTC_FORCE_WAKE_EN);
1781 }
1782 }
1783 }
1784
1785 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1786 {
1787 u32 val;
1788 int i;
1789
1790 if (setChip) {
1791 if ((REG_READ(ah, AR_RTC_STATUS) &
1792 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1793 if (ath9k_hw_set_reset_reg(ah,
1794 ATH9K_RESET_POWER_ON) != true) {
1795 return false;
1796 }
1797 if (!AR_SREV_9300_20_OR_LATER(ah))
1798 ath9k_hw_init_pll(ah, NULL);
1799 }
1800 if (AR_SREV_9100(ah))
1801 REG_SET_BIT(ah, AR_RTC_RESET,
1802 AR_RTC_RESET_EN);
1803
1804 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1805 AR_RTC_FORCE_WAKE_EN);
1806 udelay(50);
1807
1808 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1809 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1810 if (val == AR_RTC_STATUS_ON)
1811 break;
1812 udelay(50);
1813 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1814 AR_RTC_FORCE_WAKE_EN);
1815 }
1816 if (i == 0) {
1817 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1818 "Failed to wakeup in %uus\n",
1819 POWER_UP_TIME / 20);
1820 return false;
1821 }
1822 }
1823
1824 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1825
1826 return true;
1827 }
1828
1829 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1830 {
1831 struct ath_common *common = ath9k_hw_common(ah);
1832 int status = true, setChip = true;
1833 static const char *modes[] = {
1834 "AWAKE",
1835 "FULL-SLEEP",
1836 "NETWORK SLEEP",
1837 "UNDEFINED"
1838 };
1839
1840 if (ah->power_mode == mode)
1841 return status;
1842
1843 ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1844 modes[ah->power_mode], modes[mode]);
1845
1846 switch (mode) {
1847 case ATH9K_PM_AWAKE:
1848 status = ath9k_hw_set_power_awake(ah, setChip);
1849 break;
1850 case ATH9K_PM_FULL_SLEEP:
1851 ath9k_set_power_sleep(ah, setChip);
1852 ah->chip_fullsleep = true;
1853 break;
1854 case ATH9K_PM_NETWORK_SLEEP:
1855 ath9k_set_power_network_sleep(ah, setChip);
1856 break;
1857 default:
1858 ath_print(common, ATH_DBG_FATAL,
1859 "Unknown power mode %u\n", mode);
1860 return false;
1861 }
1862 ah->power_mode = mode;
1863
1864 return status;
1865 }
1866 EXPORT_SYMBOL(ath9k_hw_setpower);
1867
1868 /*******************/
1869 /* Beacon Handling */
1870 /*******************/
1871
1872 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1873 {
1874 int flags = 0;
1875
1876 ah->beacon_interval = beacon_period;
1877
1878 ENABLE_REGWRITE_BUFFER(ah);
1879
1880 switch (ah->opmode) {
1881 case NL80211_IFTYPE_STATION:
1882 case NL80211_IFTYPE_MONITOR:
1883 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1884 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1885 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1886 flags |= AR_TBTT_TIMER_EN;
1887 break;
1888 case NL80211_IFTYPE_ADHOC:
1889 case NL80211_IFTYPE_MESH_POINT:
1890 REG_SET_BIT(ah, AR_TXCFG,
1891 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1892 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1893 TU_TO_USEC(next_beacon +
1894 (ah->atim_window ? ah->
1895 atim_window : 1)));
1896 flags |= AR_NDP_TIMER_EN;
1897 case NL80211_IFTYPE_AP:
1898 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1899 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1900 TU_TO_USEC(next_beacon -
1901 ah->config.
1902 dma_beacon_response_time));
1903 REG_WRITE(ah, AR_NEXT_SWBA,
1904 TU_TO_USEC(next_beacon -
1905 ah->config.
1906 sw_beacon_response_time));
1907 flags |=
1908 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1909 break;
1910 default:
1911 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1912 "%s: unsupported opmode: %d\n",
1913 __func__, ah->opmode);
1914 return;
1915 break;
1916 }
1917
1918 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1919 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1920 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1921 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1922
1923 REGWRITE_BUFFER_FLUSH(ah);
1924 DISABLE_REGWRITE_BUFFER(ah);
1925
1926 beacon_period &= ~ATH9K_BEACON_ENA;
1927 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1928 ath9k_hw_reset_tsf(ah);
1929 }
1930
1931 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1932 }
1933 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1934
1935 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1936 const struct ath9k_beacon_state *bs)
1937 {
1938 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1939 struct ath9k_hw_capabilities *pCap = &ah->caps;
1940 struct ath_common *common = ath9k_hw_common(ah);
1941
1942 ENABLE_REGWRITE_BUFFER(ah);
1943
1944 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1945
1946 REG_WRITE(ah, AR_BEACON_PERIOD,
1947 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1948 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1949 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1950
1951 REGWRITE_BUFFER_FLUSH(ah);
1952 DISABLE_REGWRITE_BUFFER(ah);
1953
1954 REG_RMW_FIELD(ah, AR_RSSI_THR,
1955 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1956
1957 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1958
1959 if (bs->bs_sleepduration > beaconintval)
1960 beaconintval = bs->bs_sleepduration;
1961
1962 dtimperiod = bs->bs_dtimperiod;
1963 if (bs->bs_sleepduration > dtimperiod)
1964 dtimperiod = bs->bs_sleepduration;
1965
1966 if (beaconintval == dtimperiod)
1967 nextTbtt = bs->bs_nextdtim;
1968 else
1969 nextTbtt = bs->bs_nexttbtt;
1970
1971 ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1972 ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1973 ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1974 ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1975
1976 ENABLE_REGWRITE_BUFFER(ah);
1977
1978 REG_WRITE(ah, AR_NEXT_DTIM,
1979 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1980 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1981
1982 REG_WRITE(ah, AR_SLEEP1,
1983 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1984 | AR_SLEEP1_ASSUME_DTIM);
1985
1986 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1987 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1988 else
1989 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1990
1991 REG_WRITE(ah, AR_SLEEP2,
1992 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1993
1994 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1995 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1996
1997 REGWRITE_BUFFER_FLUSH(ah);
1998 DISABLE_REGWRITE_BUFFER(ah);
1999
2000 REG_SET_BIT(ah, AR_TIMER_MODE,
2001 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2002 AR_DTIM_TIMER_EN);
2003
2004 /* TSF Out of Range Threshold */
2005 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2006 }
2007 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2008
2009 /*******************/
2010 /* HW Capabilities */
2011 /*******************/
2012
2013 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2014 {
2015 struct ath9k_hw_capabilities *pCap = &ah->caps;
2016 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2017 struct ath_common *common = ath9k_hw_common(ah);
2018 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2019
2020 u16 capField = 0, eeval;
2021
2022 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2023 regulatory->current_rd = eeval;
2024
2025 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2026 if (AR_SREV_9285_10_OR_LATER(ah))
2027 eeval |= AR9285_RDEXT_DEFAULT;
2028 regulatory->current_rd_ext = eeval;
2029
2030 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2031
2032 if (ah->opmode != NL80211_IFTYPE_AP &&
2033 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2034 if (regulatory->current_rd == 0x64 ||
2035 regulatory->current_rd == 0x65)
2036 regulatory->current_rd += 5;
2037 else if (regulatory->current_rd == 0x41)
2038 regulatory->current_rd = 0x43;
2039 ath_print(common, ATH_DBG_REGULATORY,
2040 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2041 }
2042
2043 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2044 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2045 ath_print(common, ATH_DBG_FATAL,
2046 "no band has been marked as supported in EEPROM.\n");
2047 return -EINVAL;
2048 }
2049
2050 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2051
2052 if (eeval & AR5416_OPFLAGS_11A) {
2053 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2054 if (ah->config.ht_enable) {
2055 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2056 set_bit(ATH9K_MODE_11NA_HT20,
2057 pCap->wireless_modes);
2058 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2059 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2060 pCap->wireless_modes);
2061 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2062 pCap->wireless_modes);
2063 }
2064 }
2065 }
2066
2067 if (eeval & AR5416_OPFLAGS_11G) {
2068 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2069 if (ah->config.ht_enable) {
2070 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2071 set_bit(ATH9K_MODE_11NG_HT20,
2072 pCap->wireless_modes);
2073 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2074 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2075 pCap->wireless_modes);
2076 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2077 pCap->wireless_modes);
2078 }
2079 }
2080 }
2081
2082 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2083 /*
2084 * For AR9271 we will temporarilly uses the rx chainmax as read from
2085 * the EEPROM.
2086 */
2087 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2088 !(eeval & AR5416_OPFLAGS_11A) &&
2089 !(AR_SREV_9271(ah)))
2090 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2091 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2092 else
2093 /* Use rx_chainmask from EEPROM. */
2094 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2095
2096 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2097 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2098
2099 pCap->low_2ghz_chan = 2312;
2100 pCap->high_2ghz_chan = 2732;
2101
2102 pCap->low_5ghz_chan = 4920;
2103 pCap->high_5ghz_chan = 6100;
2104
2105 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2106 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2107 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2108
2109 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2110 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2111 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2112
2113 if (ah->config.ht_enable)
2114 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2115 else
2116 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2117
2118 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2119 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2120 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2121 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2122
2123 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2124 pCap->total_queues =
2125 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2126 else
2127 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2128
2129 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2130 pCap->keycache_size =
2131 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2132 else
2133 pCap->keycache_size = AR_KEYTABLE_SIZE;
2134
2135 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2136
2137 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2138 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2139 else
2140 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2141
2142 if (AR_SREV_9271(ah))
2143 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2144 else if (AR_SREV_9285_10_OR_LATER(ah))
2145 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2146 else if (AR_SREV_9280_10_OR_LATER(ah))
2147 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2148 else
2149 pCap->num_gpio_pins = AR_NUM_GPIO;
2150
2151 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2152 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2153 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2154 } else {
2155 pCap->rts_aggr_limit = (8 * 1024);
2156 }
2157
2158 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2159
2160 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2161 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2162 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2163 ah->rfkill_gpio =
2164 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2165 ah->rfkill_polarity =
2166 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2167
2168 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2169 }
2170 #endif
2171 if (AR_SREV_9271(ah))
2172 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2173 else
2174 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2175
2176 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2177 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2178 else
2179 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2180
2181 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2182 pCap->reg_cap =
2183 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2184 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2185 AR_EEPROM_EEREGCAP_EN_KK_U2 |
2186 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2187 } else {
2188 pCap->reg_cap =
2189 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2190 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2191 }
2192
2193 /* Advertise midband for AR5416 with FCC midband set in eeprom */
2194 if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2195 AR_SREV_5416(ah))
2196 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2197
2198 pCap->num_antcfg_5ghz =
2199 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2200 pCap->num_antcfg_2ghz =
2201 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2202
2203 if (AR_SREV_9280_10_OR_LATER(ah) &&
2204 ath9k_hw_btcoex_supported(ah)) {
2205 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2206 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2207
2208 if (AR_SREV_9285(ah)) {
2209 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2210 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2211 } else {
2212 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2213 }
2214 } else {
2215 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2216 }
2217
2218 if (AR_SREV_9300_20_OR_LATER(ah)) {
2219 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2220 ATH9K_HW_CAP_FASTCLOCK;
2221 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2222 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2223 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2224 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2225 pCap->txs_len = sizeof(struct ar9003_txs);
2226 } else {
2227 pCap->tx_desc_len = sizeof(struct ath_desc);
2228 if (AR_SREV_9280_20(ah) &&
2229 ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2230 AR5416_EEP_MINOR_VER_16) ||
2231 ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2232 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2233 }
2234
2235 if (AR_SREV_9300_20_OR_LATER(ah))
2236 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2237
2238 return 0;
2239 }
2240
2241 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2242 u32 capability, u32 *result)
2243 {
2244 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2245 switch (type) {
2246 case ATH9K_CAP_CIPHER:
2247 switch (capability) {
2248 case ATH9K_CIPHER_AES_CCM:
2249 case ATH9K_CIPHER_AES_OCB:
2250 case ATH9K_CIPHER_TKIP:
2251 case ATH9K_CIPHER_WEP:
2252 case ATH9K_CIPHER_MIC:
2253 case ATH9K_CIPHER_CLR:
2254 return true;
2255 default:
2256 return false;
2257 }
2258 case ATH9K_CAP_TKIP_MIC:
2259 switch (capability) {
2260 case 0:
2261 return true;
2262 case 1:
2263 return (ah->sta_id1_defaults &
2264 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
2265 false;
2266 }
2267 case ATH9K_CAP_TKIP_SPLIT:
2268 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
2269 false : true;
2270 case ATH9K_CAP_MCAST_KEYSRCH:
2271 switch (capability) {
2272 case 0:
2273 return true;
2274 case 1:
2275 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
2276 return false;
2277 } else {
2278 return (ah->sta_id1_defaults &
2279 AR_STA_ID1_MCAST_KSRCH) ? true :
2280 false;
2281 }
2282 }
2283 return false;
2284 case ATH9K_CAP_TXPOW:
2285 switch (capability) {
2286 case 0:
2287 return 0;
2288 case 1:
2289 *result = regulatory->power_limit;
2290 return 0;
2291 case 2:
2292 *result = regulatory->max_power_level;
2293 return 0;
2294 case 3:
2295 *result = regulatory->tp_scale;
2296 return 0;
2297 }
2298 return false;
2299 case ATH9K_CAP_DS:
2300 return (AR_SREV_9280_20_OR_LATER(ah) &&
2301 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2302 ? false : true;
2303 default:
2304 return false;
2305 }
2306 }
2307 EXPORT_SYMBOL(ath9k_hw_getcapability);
2308
2309 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2310 u32 capability, u32 setting, int *status)
2311 {
2312 switch (type) {
2313 case ATH9K_CAP_TKIP_MIC:
2314 if (setting)
2315 ah->sta_id1_defaults |=
2316 AR_STA_ID1_CRPT_MIC_ENABLE;
2317 else
2318 ah->sta_id1_defaults &=
2319 ~AR_STA_ID1_CRPT_MIC_ENABLE;
2320 return true;
2321 case ATH9K_CAP_MCAST_KEYSRCH:
2322 if (setting)
2323 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
2324 else
2325 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
2326 return true;
2327 default:
2328 return false;
2329 }
2330 }
2331 EXPORT_SYMBOL(ath9k_hw_setcapability);
2332
2333 /****************************/
2334 /* GPIO / RFKILL / Antennae */
2335 /****************************/
2336
2337 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2338 u32 gpio, u32 type)
2339 {
2340 int addr;
2341 u32 gpio_shift, tmp;
2342
2343 if (gpio > 11)
2344 addr = AR_GPIO_OUTPUT_MUX3;
2345 else if (gpio > 5)
2346 addr = AR_GPIO_OUTPUT_MUX2;
2347 else
2348 addr = AR_GPIO_OUTPUT_MUX1;
2349
2350 gpio_shift = (gpio % 6) * 5;
2351
2352 if (AR_SREV_9280_20_OR_LATER(ah)
2353 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2354 REG_RMW(ah, addr, (type << gpio_shift),
2355 (0x1f << gpio_shift));
2356 } else {
2357 tmp = REG_READ(ah, addr);
2358 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2359 tmp &= ~(0x1f << gpio_shift);
2360 tmp |= (type << gpio_shift);
2361 REG_WRITE(ah, addr, tmp);
2362 }
2363 }
2364
2365 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2366 {
2367 u32 gpio_shift;
2368
2369 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2370
2371 gpio_shift = gpio << 1;
2372
2373 REG_RMW(ah,
2374 AR_GPIO_OE_OUT,
2375 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2376 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2377 }
2378 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2379
2380 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2381 {
2382 #define MS_REG_READ(x, y) \
2383 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2384
2385 if (gpio >= ah->caps.num_gpio_pins)
2386 return 0xffffffff;
2387
2388 if (AR_SREV_9300_20_OR_LATER(ah))
2389 return MS_REG_READ(AR9300, gpio) != 0;
2390 else if (AR_SREV_9271(ah))
2391 return MS_REG_READ(AR9271, gpio) != 0;
2392 else if (AR_SREV_9287_10_OR_LATER(ah))
2393 return MS_REG_READ(AR9287, gpio) != 0;
2394 else if (AR_SREV_9285_10_OR_LATER(ah))
2395 return MS_REG_READ(AR9285, gpio) != 0;
2396 else if (AR_SREV_9280_10_OR_LATER(ah))
2397 return MS_REG_READ(AR928X, gpio) != 0;
2398 else
2399 return MS_REG_READ(AR, gpio) != 0;
2400 }
2401 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2402
2403 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2404 u32 ah_signal_type)
2405 {
2406 u32 gpio_shift;
2407
2408 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2409
2410 gpio_shift = 2 * gpio;
2411
2412 REG_RMW(ah,
2413 AR_GPIO_OE_OUT,
2414 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2415 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2416 }
2417 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2418
2419 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2420 {
2421 if (AR_SREV_9271(ah))
2422 val = ~val;
2423
2424 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2425 AR_GPIO_BIT(gpio));
2426 }
2427 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2428
2429 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2430 {
2431 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2432 }
2433 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2434
2435 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2436 {
2437 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2438 }
2439 EXPORT_SYMBOL(ath9k_hw_setantenna);
2440
2441 /*********************/
2442 /* General Operation */
2443 /*********************/
2444
2445 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2446 {
2447 u32 bits = REG_READ(ah, AR_RX_FILTER);
2448 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2449
2450 if (phybits & AR_PHY_ERR_RADAR)
2451 bits |= ATH9K_RX_FILTER_PHYRADAR;
2452 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2453 bits |= ATH9K_RX_FILTER_PHYERR;
2454
2455 return bits;
2456 }
2457 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2458
2459 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2460 {
2461 u32 phybits;
2462
2463 ENABLE_REGWRITE_BUFFER(ah);
2464
2465 REG_WRITE(ah, AR_RX_FILTER, bits);
2466
2467 phybits = 0;
2468 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2469 phybits |= AR_PHY_ERR_RADAR;
2470 if (bits & ATH9K_RX_FILTER_PHYERR)
2471 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2472 REG_WRITE(ah, AR_PHY_ERR, phybits);
2473
2474 if (phybits)
2475 REG_WRITE(ah, AR_RXCFG,
2476 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2477 else
2478 REG_WRITE(ah, AR_RXCFG,
2479 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2480
2481 REGWRITE_BUFFER_FLUSH(ah);
2482 DISABLE_REGWRITE_BUFFER(ah);
2483 }
2484 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2485
2486 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2487 {
2488 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2489 return false;
2490
2491 ath9k_hw_init_pll(ah, NULL);
2492 return true;
2493 }
2494 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2495
2496 bool ath9k_hw_disable(struct ath_hw *ah)
2497 {
2498 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2499 return false;
2500
2501 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2502 return false;
2503
2504 ath9k_hw_init_pll(ah, NULL);
2505 return true;
2506 }
2507 EXPORT_SYMBOL(ath9k_hw_disable);
2508
2509 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2510 {
2511 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2512 struct ath9k_channel *chan = ah->curchan;
2513 struct ieee80211_channel *channel = chan->chan;
2514
2515 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2516
2517 ah->eep_ops->set_txpower(ah, chan,
2518 ath9k_regd_get_ctl(regulatory, chan),
2519 channel->max_antenna_gain * 2,
2520 channel->max_power * 2,
2521 min((u32) MAX_RATE_POWER,
2522 (u32) regulatory->power_limit));
2523 }
2524 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2525
2526 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
2527 {
2528 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
2529 }
2530 EXPORT_SYMBOL(ath9k_hw_setmac);
2531
2532 void ath9k_hw_setopmode(struct ath_hw *ah)
2533 {
2534 ath9k_hw_set_operating_mode(ah, ah->opmode);
2535 }
2536 EXPORT_SYMBOL(ath9k_hw_setopmode);
2537
2538 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2539 {
2540 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2541 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2542 }
2543 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2544
2545 void ath9k_hw_write_associd(struct ath_hw *ah)
2546 {
2547 struct ath_common *common = ath9k_hw_common(ah);
2548
2549 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2550 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2551 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2552 }
2553 EXPORT_SYMBOL(ath9k_hw_write_associd);
2554
2555 #define ATH9K_MAX_TSF_READ 10
2556
2557 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2558 {
2559 u32 tsf_lower, tsf_upper1, tsf_upper2;
2560 int i;
2561
2562 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2563 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2564 tsf_lower = REG_READ(ah, AR_TSF_L32);
2565 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2566 if (tsf_upper2 == tsf_upper1)
2567 break;
2568 tsf_upper1 = tsf_upper2;
2569 }
2570
2571 WARN_ON( i == ATH9K_MAX_TSF_READ );
2572
2573 return (((u64)tsf_upper1 << 32) | tsf_lower);
2574 }
2575 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2576
2577 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2578 {
2579 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2580 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2581 }
2582 EXPORT_SYMBOL(ath9k_hw_settsf64);
2583
2584 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2585 {
2586 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2587 AH_TSF_WRITE_TIMEOUT))
2588 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2589 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2590
2591 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2592 }
2593 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2594
2595 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2596 {
2597 if (setting)
2598 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2599 else
2600 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2601 }
2602 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2603
2604 /*
2605 * Extend 15-bit time stamp from rx descriptor to
2606 * a full 64-bit TSF using the current h/w TSF.
2607 */
2608 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
2609 {
2610 u64 tsf;
2611
2612 tsf = ath9k_hw_gettsf64(ah);
2613 if ((tsf & 0x7fff) < rstamp)
2614 tsf -= 0x8000;
2615 return (tsf & ~0x7fff) | rstamp;
2616 }
2617 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
2618
2619 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2620 {
2621 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2622 u32 macmode;
2623
2624 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2625 macmode = AR_2040_JOINED_RX_CLEAR;
2626 else
2627 macmode = 0;
2628
2629 REG_WRITE(ah, AR_2040_MODE, macmode);
2630 }
2631
2632 /* HW Generic timers configuration */
2633
2634 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2635 {
2636 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2637 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2638 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2639 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2640 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2641 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2642 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2643 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2644 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2645 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2646 AR_NDP2_TIMER_MODE, 0x0002},
2647 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2648 AR_NDP2_TIMER_MODE, 0x0004},
2649 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2650 AR_NDP2_TIMER_MODE, 0x0008},
2651 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2652 AR_NDP2_TIMER_MODE, 0x0010},
2653 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2654 AR_NDP2_TIMER_MODE, 0x0020},
2655 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2656 AR_NDP2_TIMER_MODE, 0x0040},
2657 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2658 AR_NDP2_TIMER_MODE, 0x0080}
2659 };
2660
2661 /* HW generic timer primitives */
2662
2663 /* compute and clear index of rightmost 1 */
2664 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2665 {
2666 u32 b;
2667
2668 b = *mask;
2669 b &= (0-b);
2670 *mask &= ~b;
2671 b *= debruijn32;
2672 b >>= 27;
2673
2674 return timer_table->gen_timer_index[b];
2675 }
2676
2677 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2678 {
2679 return REG_READ(ah, AR_TSF_L32);
2680 }
2681 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2682
2683 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2684 void (*trigger)(void *),
2685 void (*overflow)(void *),
2686 void *arg,
2687 u8 timer_index)
2688 {
2689 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2690 struct ath_gen_timer *timer;
2691
2692 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2693
2694 if (timer == NULL) {
2695 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2696 "Failed to allocate memory"
2697 "for hw timer[%d]\n", timer_index);
2698 return NULL;
2699 }
2700
2701 /* allocate a hardware generic timer slot */
2702 timer_table->timers[timer_index] = timer;
2703 timer->index = timer_index;
2704 timer->trigger = trigger;
2705 timer->overflow = overflow;
2706 timer->arg = arg;
2707
2708 return timer;
2709 }
2710 EXPORT_SYMBOL(ath_gen_timer_alloc);
2711
2712 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2713 struct ath_gen_timer *timer,
2714 u32 timer_next,
2715 u32 timer_period)
2716 {
2717 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2718 u32 tsf;
2719
2720 BUG_ON(!timer_period);
2721
2722 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2723
2724 tsf = ath9k_hw_gettsf32(ah);
2725
2726 ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2727 "curent tsf %x period %x"
2728 "timer_next %x\n", tsf, timer_period, timer_next);
2729
2730 /*
2731 * Pull timer_next forward if the current TSF already passed it
2732 * because of software latency
2733 */
2734 if (timer_next < tsf)
2735 timer_next = tsf + timer_period;
2736
2737 /*
2738 * Program generic timer registers
2739 */
2740 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2741 timer_next);
2742 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2743 timer_period);
2744 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2745 gen_tmr_configuration[timer->index].mode_mask);
2746
2747 /* Enable both trigger and thresh interrupt masks */
2748 REG_SET_BIT(ah, AR_IMR_S5,
2749 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2750 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2751 }
2752 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2753
2754 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2755 {
2756 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2757
2758 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2759 (timer->index >= ATH_MAX_GEN_TIMER)) {
2760 return;
2761 }
2762
2763 /* Clear generic timer enable bits. */
2764 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2765 gen_tmr_configuration[timer->index].mode_mask);
2766
2767 /* Disable both trigger and thresh interrupt masks */
2768 REG_CLR_BIT(ah, AR_IMR_S5,
2769 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2770 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2771
2772 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2773 }
2774 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2775
2776 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2777 {
2778 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2779
2780 /* free the hardware generic timer slot */
2781 timer_table->timers[timer->index] = NULL;
2782 kfree(timer);
2783 }
2784 EXPORT_SYMBOL(ath_gen_timer_free);
2785
2786 /*
2787 * Generic Timer Interrupts handling
2788 */
2789 void ath_gen_timer_isr(struct ath_hw *ah)
2790 {
2791 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2792 struct ath_gen_timer *timer;
2793 struct ath_common *common = ath9k_hw_common(ah);
2794 u32 trigger_mask, thresh_mask, index;
2795
2796 /* get hardware generic timer interrupt status */
2797 trigger_mask = ah->intr_gen_timer_trigger;
2798 thresh_mask = ah->intr_gen_timer_thresh;
2799 trigger_mask &= timer_table->timer_mask.val;
2800 thresh_mask &= timer_table->timer_mask.val;
2801
2802 trigger_mask &= ~thresh_mask;
2803
2804 while (thresh_mask) {
2805 index = rightmost_index(timer_table, &thresh_mask);
2806 timer = timer_table->timers[index];
2807 BUG_ON(!timer);
2808 ath_print(common, ATH_DBG_HWTIMER,
2809 "TSF overflow for Gen timer %d\n", index);
2810 timer->overflow(timer->arg);
2811 }
2812
2813 while (trigger_mask) {
2814 index = rightmost_index(timer_table, &trigger_mask);
2815 timer = timer_table->timers[index];
2816 BUG_ON(!timer);
2817 ath_print(common, ATH_DBG_HWTIMER,
2818 "Gen timer[%d] trigger\n", index);
2819 timer->trigger(timer->arg);
2820 }
2821 }
2822 EXPORT_SYMBOL(ath_gen_timer_isr);
2823
2824 /********/
2825 /* HTC */
2826 /********/
2827
2828 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2829 {
2830 ah->htc_reset_init = true;
2831 }
2832 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2833
2834 static struct {
2835 u32 version;
2836 const char * name;
2837 } ath_mac_bb_names[] = {
2838 /* Devices with external radios */
2839 { AR_SREV_VERSION_5416_PCI, "5416" },
2840 { AR_SREV_VERSION_5416_PCIE, "5418" },
2841 { AR_SREV_VERSION_9100, "9100" },
2842 { AR_SREV_VERSION_9160, "9160" },
2843 /* Single-chip solutions */
2844 { AR_SREV_VERSION_9280, "9280" },
2845 { AR_SREV_VERSION_9285, "9285" },
2846 { AR_SREV_VERSION_9287, "9287" },
2847 { AR_SREV_VERSION_9271, "9271" },
2848 { AR_SREV_VERSION_9300, "9300" },
2849 };
2850
2851 /* For devices with external radios */
2852 static struct {
2853 u16 version;
2854 const char * name;
2855 } ath_rf_names[] = {
2856 { 0, "5133" },
2857 { AR_RAD5133_SREV_MAJOR, "5133" },
2858 { AR_RAD5122_SREV_MAJOR, "5122" },
2859 { AR_RAD2133_SREV_MAJOR, "2133" },
2860 { AR_RAD2122_SREV_MAJOR, "2122" }
2861 };
2862
2863 /*
2864 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2865 */
2866 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2867 {
2868 int i;
2869
2870 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2871 if (ath_mac_bb_names[i].version == mac_bb_version) {
2872 return ath_mac_bb_names[i].name;
2873 }
2874 }
2875
2876 return "????";
2877 }
2878
2879 /*
2880 * Return the RF name. "????" is returned if the RF is unknown.
2881 * Used for devices with external radios.
2882 */
2883 static const char *ath9k_hw_rf_name(u16 rf_version)
2884 {
2885 int i;
2886
2887 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2888 if (ath_rf_names[i].version == rf_version) {
2889 return ath_rf_names[i].name;
2890 }
2891 }
2892
2893 return "????";
2894 }
2895
2896 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2897 {
2898 int used;
2899
2900 /* chipsets >= AR9280 are single-chip */
2901 if (AR_SREV_9280_10_OR_LATER(ah)) {
2902 used = snprintf(hw_name, len,
2903 "Atheros AR%s Rev:%x",
2904 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2905 ah->hw_version.macRev);
2906 }
2907 else {
2908 used = snprintf(hw_name, len,
2909 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2910 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2911 ah->hw_version.macRev,
2912 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2913 AR_RADIO_SREV_MAJOR)),
2914 ah->hw_version.phyRev);
2915 }
2916
2917 hw_name[used] = '\0';
2918 }
2919 EXPORT_SYMBOL(ath9k_hw_name);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree