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m68knommu: Add Coldfire DMA Timer support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / blackfin / mach-common / ints-priority.c
blobf5fd768022eaeb13cab7d7be9dd24b8e86c6d5e7
1 /*
2 * File: arch/blackfin/mach-common/ints-priority.c
3 * Based on:
4 * Author:
5 *
6 * Created: ?
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
40 #ifdef CONFIG_KGDB
41 #include <linux/kgdb.h>
42 #endif
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
45 #include <asm/gpio.h>
46 #include <asm/irq_handler.h>
47
48 #ifdef BF537_FAMILY
49 # define BF537_GENERIC_ERROR_INT_DEMUX
50 #else
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
52 #endif
53
54 /*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67 unsigned long irq_flags = 0x1f;
68
69 /* The number of spurious interrupts */
70 atomic_t num_spurious;
71
72 #ifdef CONFIG_PM
73 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74 #endif
75
76 struct ivgx {
77 /* irq number for request_irq, available in mach-bf5xx/irq.h */
78 unsigned int irqno;
79 /* corresponding bit in the SIC_ISR register */
80 unsigned int isrflag;
81 } ivg_table[NR_PERI_INTS];
82
83 struct ivg_slice {
84 /* position of first irq in ivg_table for given ivg */
85 struct ivgx *ifirst;
86 struct ivgx *istop;
87 } ivg7_13[IVG13 - IVG7 + 1];
88
89
90 /*
91 * Search SIC_IAR and fill tables with the irqvalues
92 * and their positions in the SIC_ISR register.
93 */
94 static void __init search_IAR(void)
95 {
96 unsigned ivg, irq_pos = 0;
97 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
98 int irqn;
99
100 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
101
102 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
103 int iar_shift = (irqn & 7) * 4;
104 if (ivg == (0xf &
105 #ifndef CONFIG_BF52x
106 bfin_read32((unsigned long *)SIC_IAR0 +
107 (irqn >> 3)) >> iar_shift)) {
108 #else
109 bfin_read32((unsigned long *)SIC_IAR0 +
110 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
111 #endif
112 ivg_table[irq_pos].irqno = IVG7 + irqn;
113 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
114 ivg7_13[ivg].istop++;
115 irq_pos++;
116 }
117 }
118 }
119 }
120
121 /*
122 * This is for core internal IRQs
123 */
124
125 static void bfin_ack_noop(unsigned int irq)
126 {
127 /* Dummy function. */
128 }
129
130 static void bfin_core_mask_irq(unsigned int irq)
131 {
132 irq_flags &= ~(1 << irq);
133 if (!irqs_disabled())
134 local_irq_enable();
135 }
136
137 static void bfin_core_unmask_irq(unsigned int irq)
138 {
139 irq_flags |= 1 << irq;
140 /*
141 * If interrupts are enabled, IMASK must contain the same value
142 * as irq_flags. Make sure that invariant holds. If interrupts
143 * are currently disabled we need not do anything; one of the
144 * callers will take care of setting IMASK to the proper value
145 * when reenabling interrupts.
146 * local_irq_enable just does "STI irq_flags", so it's exactly
147 * what we need.
148 */
149 if (!irqs_disabled())
150 local_irq_enable();
151 return;
152 }
153
154 static void bfin_internal_mask_irq(unsigned int irq)
155 {
156 #ifdef CONFIG_BF53x
157 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
158 ~(1 << SIC_SYSIRQ(irq)));
159 #else
160 unsigned mask_bank, mask_bit;
161 mask_bank = SIC_SYSIRQ(irq) / 32;
162 mask_bit = SIC_SYSIRQ(irq) % 32;
163 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
164 ~(1 << mask_bit));
165 #endif
166 SSYNC();
167 }
168
169 static void bfin_internal_unmask_irq(unsigned int irq)
170 {
171 #ifdef CONFIG_BF53x
172 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
173 (1 << SIC_SYSIRQ(irq)));
174 #else
175 unsigned mask_bank, mask_bit;
176 mask_bank = SIC_SYSIRQ(irq) / 32;
177 mask_bit = SIC_SYSIRQ(irq) % 32;
178 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
179 (1 << mask_bit));
180 #endif
181 SSYNC();
182 }
183
184 #ifdef CONFIG_PM
185 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
186 {
187 unsigned bank, bit;
188 unsigned long flags;
189 bank = SIC_SYSIRQ(irq) / 32;
190 bit = SIC_SYSIRQ(irq) % 32;
191
192 local_irq_save(flags);
193
194 if (state)
195 bfin_sic_iwr[bank] |= (1 << bit);
196 else
197 bfin_sic_iwr[bank] &= ~(1 << bit);
198
199 local_irq_restore(flags);
200
201 return 0;
202 }
203 #endif
204
205 static struct irq_chip bfin_core_irqchip = {
206 .ack = bfin_ack_noop,
207 .mask = bfin_core_mask_irq,
208 .unmask = bfin_core_unmask_irq,
209 };
210
211 static struct irq_chip bfin_internal_irqchip = {
212 .ack = bfin_ack_noop,
213 .mask = bfin_internal_mask_irq,
214 .unmask = bfin_internal_unmask_irq,
215 .mask_ack = bfin_internal_mask_irq,
216 .disable = bfin_internal_mask_irq,
217 .enable = bfin_internal_unmask_irq,
218 #ifdef CONFIG_PM
219 .set_wake = bfin_internal_set_wake,
220 #endif
221 };
222
223 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
224 static int error_int_mask;
225
226 static void bfin_generic_error_mask_irq(unsigned int irq)
227 {
228 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
229
230 if (!error_int_mask)
231 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
232 }
233
234 static void bfin_generic_error_unmask_irq(unsigned int irq)
235 {
236 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
237 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
238 }
239
240 static struct irq_chip bfin_generic_error_irqchip = {
241 .ack = bfin_ack_noop,
242 .mask_ack = bfin_generic_error_mask_irq,
243 .mask = bfin_generic_error_mask_irq,
244 .unmask = bfin_generic_error_unmask_irq,
245 };
246
247 static void bfin_demux_error_irq(unsigned int int_err_irq,
248 struct irq_desc *inta_desc)
249 {
250 int irq = 0;
251
252 SSYNC();
253
254 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
255 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
256 irq = IRQ_MAC_ERROR;
257 else
258 #endif
259 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
260 irq = IRQ_SPORT0_ERROR;
261 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
262 irq = IRQ_SPORT1_ERROR;
263 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
264 irq = IRQ_PPI_ERROR;
265 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
266 irq = IRQ_CAN_ERROR;
267 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
268 irq = IRQ_SPI_ERROR;
269 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
270 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
271 irq = IRQ_UART0_ERROR;
272 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
273 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
274 irq = IRQ_UART1_ERROR;
275
276 if (irq) {
277 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
278 struct irq_desc *desc = irq_desc + irq;
279 desc->handle_irq(irq, desc);
280 } else {
281
282 switch (irq) {
283 case IRQ_PPI_ERROR:
284 bfin_write_PPI_STATUS(PPI_ERR_MASK);
285 break;
286 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
287 case IRQ_MAC_ERROR:
288 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
289 break;
290 #endif
291 case IRQ_SPORT0_ERROR:
292 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
293 break;
294
295 case IRQ_SPORT1_ERROR:
296 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
297 break;
298
299 case IRQ_CAN_ERROR:
300 bfin_write_CAN_GIS(CAN_ERR_MASK);
301 break;
302
303 case IRQ_SPI_ERROR:
304 bfin_write_SPI_STAT(SPI_ERR_MASK);
305 break;
306
307 default:
308 break;
309 }
310
311 pr_debug("IRQ %d:"
312 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
313 irq);
314 }
315 } else
316 printk(KERN_ERR
317 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
318 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
319 __func__, __FILE__, __LINE__);
320
321 }
322 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
323
324 #if !defined(CONFIG_BF54x)
325
326 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
327 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
328
329 extern void bfin_gpio_irq_prepare(unsigned gpio);
330
331 static void bfin_gpio_ack_irq(unsigned int irq)
332 {
333 u16 gpionr = irq - IRQ_PF0;
334
335 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
336 set_gpio_data(gpionr, 0);
337 SSYNC();
338 }
339 }
340
341 static void bfin_gpio_mask_ack_irq(unsigned int irq)
342 {
343 u16 gpionr = irq - IRQ_PF0;
344
345 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
346 set_gpio_data(gpionr, 0);
347 SSYNC();
348 }
349
350 set_gpio_maska(gpionr, 0);
351 SSYNC();
352 }
353
354 static void bfin_gpio_mask_irq(unsigned int irq)
355 {
356 set_gpio_maska(irq - IRQ_PF0, 0);
357 SSYNC();
358 }
359
360 static void bfin_gpio_unmask_irq(unsigned int irq)
361 {
362 set_gpio_maska(irq - IRQ_PF0, 1);
363 SSYNC();
364 }
365
366 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
367 {
368 u16 gpionr = irq - IRQ_PF0;
369
370 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
371 bfin_gpio_irq_prepare(gpionr);
372
373 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
374 bfin_gpio_unmask_irq(irq);
375
376 return 0;
377 }
378
379 static void bfin_gpio_irq_shutdown(unsigned int irq)
380 {
381 bfin_gpio_mask_irq(irq);
382 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
383 }
384
385 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
386 {
387 u16 gpionr = irq - IRQ_PF0;
388
389 if (type == IRQ_TYPE_PROBE) {
390 /* only probe unenabled GPIO interrupt lines */
391 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
392 return 0;
393 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
394 }
395
396 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
397 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
398 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
399 bfin_gpio_irq_prepare(gpionr);
400
401 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
402 } else {
403 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
404 return 0;
405 }
406
407 set_gpio_inen(gpionr, 0);
408 set_gpio_dir(gpionr, 0);
409
410 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
411 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
412 set_gpio_both(gpionr, 1);
413 else
414 set_gpio_both(gpionr, 0);
415
416 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
417 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
418 else
419 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
420
421 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
422 set_gpio_edge(gpionr, 1);
423 set_gpio_inen(gpionr, 1);
424 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
425 set_gpio_data(gpionr, 0);
426
427 } else {
428 set_gpio_edge(gpionr, 0);
429 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
430 set_gpio_inen(gpionr, 1);
431 }
432
433 SSYNC();
434
435 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
436 set_irq_handler(irq, handle_edge_irq);
437 else
438 set_irq_handler(irq, handle_level_irq);
439
440 return 0;
441 }
442
443 #ifdef CONFIG_PM
444 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
445 {
446 unsigned gpio = irq_to_gpio(irq);
447
448 if (state)
449 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
450 else
451 gpio_pm_wakeup_free(gpio);
452
453 return 0;
454 }
455 #endif
456
457 static struct irq_chip bfin_gpio_irqchip = {
458 .ack = bfin_gpio_ack_irq,
459 .mask = bfin_gpio_mask_irq,
460 .mask_ack = bfin_gpio_mask_ack_irq,
461 .unmask = bfin_gpio_unmask_irq,
462 .set_type = bfin_gpio_irq_type,
463 .startup = bfin_gpio_irq_startup,
464 .shutdown = bfin_gpio_irq_shutdown,
465 #ifdef CONFIG_PM
466 .set_wake = bfin_gpio_set_wake,
467 #endif
468 };
469
470 static void bfin_demux_gpio_irq(unsigned int inta_irq,
471 struct irq_desc *desc)
472 {
473 unsigned int i, gpio, mask, irq, search = 0;
474
475 switch (inta_irq) {
476 #if defined(CONFIG_BF53x)
477 case IRQ_PROG_INTA:
478 irq = IRQ_PF0;
479 search = 1;
480 break;
481 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
482 case IRQ_MAC_RX:
483 irq = IRQ_PH0;
484 break;
485 # endif
486 #elif defined(CONFIG_BF52x)
487 case IRQ_PORTF_INTA:
488 irq = IRQ_PF0;
489 break;
490 case IRQ_PORTG_INTA:
491 irq = IRQ_PG0;
492 break;
493 case IRQ_PORTH_INTA:
494 irq = IRQ_PH0;
495 break;
496 #elif defined(CONFIG_BF561)
497 case IRQ_PROG0_INTA:
498 irq = IRQ_PF0;
499 break;
500 case IRQ_PROG1_INTA:
501 irq = IRQ_PF16;
502 break;
503 case IRQ_PROG2_INTA:
504 irq = IRQ_PF32;
505 break;
506 #endif
507 default:
508 BUG();
509 return;
510 }
511
512 if (search) {
513 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
514 irq += i;
515
516 mask = get_gpiop_data(i) &
517 (gpio_enabled[gpio_bank(i)] &
518 get_gpiop_maska(i));
519
520 while (mask) {
521 if (mask & 1) {
522 desc = irq_desc + irq;
523 desc->handle_irq(irq, desc);
524 }
525 irq++;
526 mask >>= 1;
527 }
528 }
529 } else {
530 gpio = irq_to_gpio(irq);
531 mask = get_gpiop_data(gpio) &
532 (gpio_enabled[gpio_bank(gpio)] &
533 get_gpiop_maska(gpio));
534
535 do {
536 if (mask & 1) {
537 desc = irq_desc + irq;
538 desc->handle_irq(irq, desc);
539 }
540 irq++;
541 mask >>= 1;
542 } while (mask);
543 }
544
545 }
546
547 #else /* CONFIG_BF54x */
548
549 #define NR_PINT_SYS_IRQS 4
550 #define NR_PINT_BITS 32
551 #define NR_PINTS 160
552 #define IRQ_NOT_AVAIL 0xFF
553
554 #define PINT_2_BANK(x) ((x) >> 5)
555 #define PINT_2_BIT(x) ((x) & 0x1F)
556 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
557
558 static unsigned char irq2pint_lut[NR_PINTS];
559 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
560
561 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
562 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
563
564
565 struct pin_int_t {
566 unsigned int mask_set;
567 unsigned int mask_clear;
568 unsigned int request;
569 unsigned int assign;
570 unsigned int edge_set;
571 unsigned int edge_clear;
572 unsigned int invert_set;
573 unsigned int invert_clear;
574 unsigned int pinstate;
575 unsigned int latch;
576 };
577
578 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
579 (struct pin_int_t *)PINT0_MASK_SET,
580 (struct pin_int_t *)PINT1_MASK_SET,
581 (struct pin_int_t *)PINT2_MASK_SET,
582 (struct pin_int_t *)PINT3_MASK_SET,
583 };
584
585 extern void bfin_gpio_irq_prepare(unsigned gpio);
586
587 inline unsigned short get_irq_base(u8 bank, u8 bmap)
588 {
589
590 u16 irq_base;
591
592 if (bank < 2) { /*PA-PB */
593 irq_base = IRQ_PA0 + bmap * 16;
594 } else { /*PC-PJ */
595 irq_base = IRQ_PC0 + bmap * 16;
596 }
597
598 return irq_base;
599
600 }
601
602 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
603 void init_pint_lut(void)
604 {
605 u16 bank, bit, irq_base, bit_pos;
606 u32 pint_assign;
607 u8 bmap;
608
609 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
610
611 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
612
613 pint_assign = pint[bank]->assign;
614
615 for (bit = 0; bit < NR_PINT_BITS; bit++) {
616
617 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
618
619 irq_base = get_irq_base(bank, bmap);
620
621 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
622 bit_pos = bit + bank * NR_PINT_BITS;
623
624 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
625 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
626
627 }
628
629 }
630
631 }
632
633 static void bfin_gpio_ack_irq(unsigned int irq)
634 {
635 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
636 u32 pintbit = PINT_BIT(pint_val);
637 u8 bank = PINT_2_BANK(pint_val);
638
639 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
640 if (pint[bank]->invert_set & pintbit)
641 pint[bank]->invert_clear = pintbit;
642 else
643 pint[bank]->invert_set = pintbit;
644 }
645 pint[bank]->request = pintbit;
646
647 SSYNC();
648 }
649
650 static void bfin_gpio_mask_ack_irq(unsigned int irq)
651 {
652 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
653 u32 pintbit = PINT_BIT(pint_val);
654 u8 bank = PINT_2_BANK(pint_val);
655
656 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
657 if (pint[bank]->invert_set & pintbit)
658 pint[bank]->invert_clear = pintbit;
659 else
660 pint[bank]->invert_set = pintbit;
661 }
662
663 pint[bank]->request = pintbit;
664 pint[bank]->mask_clear = pintbit;
665 SSYNC();
666 }
667
668 static void bfin_gpio_mask_irq(unsigned int irq)
669 {
670 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
671
672 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
673 SSYNC();
674 }
675
676 static void bfin_gpio_unmask_irq(unsigned int irq)
677 {
678 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
679 u32 pintbit = PINT_BIT(pint_val);
680 u8 bank = PINT_2_BANK(pint_val);
681
682 pint[bank]->request = pintbit;
683 pint[bank]->mask_set = pintbit;
684 SSYNC();
685 }
686
687 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
688 {
689 u16 gpionr = irq_to_gpio(irq);
690 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
691
692 if (pint_val == IRQ_NOT_AVAIL) {
693 printk(KERN_ERR
694 "GPIO IRQ %d :Not in PINT Assign table "
695 "Reconfigure Interrupt to Port Assignemt\n", irq);
696 return -ENODEV;
697 }
698
699 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
700 bfin_gpio_irq_prepare(gpionr);
701
702 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
703 bfin_gpio_unmask_irq(irq);
704
705 return 0;
706 }
707
708 static void bfin_gpio_irq_shutdown(unsigned int irq)
709 {
710 u16 gpionr = irq_to_gpio(irq);
711
712 bfin_gpio_mask_irq(irq);
713 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
714 }
715
716 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
717 {
718
719 u16 gpionr = irq_to_gpio(irq);
720 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
721 u32 pintbit = PINT_BIT(pint_val);
722 u8 bank = PINT_2_BANK(pint_val);
723
724 if (pint_val == IRQ_NOT_AVAIL)
725 return -ENODEV;
726
727 if (type == IRQ_TYPE_PROBE) {
728 /* only probe unenabled GPIO interrupt lines */
729 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
730 return 0;
731 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
732 }
733
734 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
735 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
736 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr)))
737 bfin_gpio_irq_prepare(gpionr);
738
739 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
740 } else {
741 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
742 return 0;
743 }
744
745 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
746 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
747 else
748 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
749
750 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
751 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
752
753 gpio_both_edge_triggered[bank] |= pintbit;
754
755 if (gpio_get_value(gpionr))
756 pint[bank]->invert_set = pintbit;
757 else
758 pint[bank]->invert_clear = pintbit;
759 } else {
760 gpio_both_edge_triggered[bank] &= ~pintbit;
761 }
762
763 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
764 pint[bank]->edge_set = pintbit;
765 set_irq_handler(irq, handle_edge_irq);
766 } else {
767 pint[bank]->edge_clear = pintbit;
768 set_irq_handler(irq, handle_level_irq);
769 }
770
771 SSYNC();
772
773 return 0;
774 }
775
776 #ifdef CONFIG_PM
777 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
778 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
779
780 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
781 {
782 u32 pint_irq;
783 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
784 u32 bank = PINT_2_BANK(pint_val);
785 u32 pintbit = PINT_BIT(pint_val);
786
787 switch (bank) {
788 case 0:
789 pint_irq = IRQ_PINT0;
790 break;
791 case 2:
792 pint_irq = IRQ_PINT2;
793 break;
794 case 3:
795 pint_irq = IRQ_PINT3;
796 break;
797 case 1:
798 pint_irq = IRQ_PINT1;
799 break;
800 default:
801 return -EINVAL;
802 }
803
804 bfin_internal_set_wake(pint_irq, state);
805
806 if (state)
807 pint_wakeup_masks[bank] |= pintbit;
808 else
809 pint_wakeup_masks[bank] &= ~pintbit;
810
811 return 0;
812 }
813
814 u32 bfin_pm_setup(void)
815 {
816 u32 val, i;
817
818 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
819 val = pint[i]->mask_clear;
820 pint_saved_masks[i] = val;
821 if (val ^ pint_wakeup_masks[i]) {
822 pint[i]->mask_clear = val;
823 pint[i]->mask_set = pint_wakeup_masks[i];
824 }
825 }
826
827 return 0;
828 }
829
830 void bfin_pm_restore(void)
831 {
832 u32 i, val;
833
834 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
835 val = pint_saved_masks[i];
836 if (val ^ pint_wakeup_masks[i]) {
837 pint[i]->mask_clear = pint[i]->mask_clear;
838 pint[i]->mask_set = val;
839 }
840 }
841 }
842 #endif
843
844 static struct irq_chip bfin_gpio_irqchip = {
845 .ack = bfin_gpio_ack_irq,
846 .mask = bfin_gpio_mask_irq,
847 .mask_ack = bfin_gpio_mask_ack_irq,
848 .unmask = bfin_gpio_unmask_irq,
849 .set_type = bfin_gpio_irq_type,
850 .startup = bfin_gpio_irq_startup,
851 .shutdown = bfin_gpio_irq_shutdown,
852 #ifdef CONFIG_PM
853 .set_wake = bfin_gpio_set_wake,
854 #endif
855 };
856
857 static void bfin_demux_gpio_irq(unsigned int inta_irq,
858 struct irq_desc *desc)
859 {
860 u8 bank, pint_val;
861 u32 request, irq;
862
863 switch (inta_irq) {
864 case IRQ_PINT0:
865 bank = 0;
866 break;
867 case IRQ_PINT2:
868 bank = 2;
869 break;
870 case IRQ_PINT3:
871 bank = 3;
872 break;
873 case IRQ_PINT1:
874 bank = 1;
875 break;
876 default:
877 return;
878 }
879
880 pint_val = bank * NR_PINT_BITS;
881
882 request = pint[bank]->request;
883
884 while (request) {
885 if (request & 1) {
886 irq = pint2irq_lut[pint_val] + SYS_IRQS;
887 desc = irq_desc + irq;
888 desc->handle_irq(irq, desc);
889 }
890 pint_val++;
891 request >>= 1;
892 }
893
894 }
895 #endif
896
897 void __init init_exception_vectors(void)
898 {
899 SSYNC();
900
901 /* cannot program in software:
902 * evt0 - emulation (jtag)
903 * evt1 - reset
904 */
905 bfin_write_EVT2(evt_nmi);
906 bfin_write_EVT3(trap);
907 bfin_write_EVT5(evt_ivhw);
908 bfin_write_EVT6(evt_timer);
909 bfin_write_EVT7(evt_evt7);
910 bfin_write_EVT8(evt_evt8);
911 bfin_write_EVT9(evt_evt9);
912 bfin_write_EVT10(evt_evt10);
913 bfin_write_EVT11(evt_evt11);
914 bfin_write_EVT12(evt_evt12);
915 bfin_write_EVT13(evt_evt13);
916 bfin_write_EVT14(evt14_softirq);
917 bfin_write_EVT15(evt_system_call);
918 CSYNC();
919 }
920
921 /*
922 * This function should be called during kernel startup to initialize
923 * the BFin IRQ handling routines.
924 */
925 int __init init_arch_irq(void)
926 {
927 int irq;
928 unsigned long ilat = 0;
929 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
930 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
931 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
932 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
933 # ifdef CONFIG_BF54x
934 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
935 # endif
936 #else
937 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
938 #endif
939
940 local_irq_disable();
941
942 #ifdef CONFIG_BF54x
943 # ifdef CONFIG_PINTx_REASSIGN
944 pint[0]->assign = CONFIG_PINT0_ASSIGN;
945 pint[1]->assign = CONFIG_PINT1_ASSIGN;
946 pint[2]->assign = CONFIG_PINT2_ASSIGN;
947 pint[3]->assign = CONFIG_PINT3_ASSIGN;
948 # endif
949 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
950 init_pint_lut();
951 #endif
952
953 for (irq = 0; irq <= SYS_IRQS; irq++) {
954 if (irq <= IRQ_CORETMR)
955 set_irq_chip(irq, &bfin_core_irqchip);
956 else
957 set_irq_chip(irq, &bfin_internal_irqchip);
958
959 switch (irq) {
960 #if defined(CONFIG_BF53x)
961 case IRQ_PROG_INTA:
962 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
963 case IRQ_MAC_RX:
964 # endif
965 #elif defined(CONFIG_BF54x)
966 case IRQ_PINT0:
967 case IRQ_PINT1:
968 case IRQ_PINT2:
969 case IRQ_PINT3:
970 #elif defined(CONFIG_BF52x)
971 case IRQ_PORTF_INTA:
972 case IRQ_PORTG_INTA:
973 case IRQ_PORTH_INTA:
974 #elif defined(CONFIG_BF561)
975 case IRQ_PROG0_INTA:
976 case IRQ_PROG1_INTA:
977 case IRQ_PROG2_INTA:
978 #endif
979 set_irq_chained_handler(irq,
980 bfin_demux_gpio_irq);
981 break;
982 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
983 case IRQ_GENERIC_ERROR:
984 set_irq_handler(irq, bfin_demux_error_irq);
985
986 break;
987 #endif
988 default:
989 set_irq_handler(irq, handle_simple_irq);
990 break;
991 }
992 }
993
994 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
995 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
996 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
997 handle_level_irq);
998 #endif
999
1000 /* if configured as edge, then will be changed to do_edge_IRQ */
1001 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1002 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1003 handle_level_irq);
1004
1005
1006 bfin_write_IMASK(0);
1007 CSYNC();
1008 ilat = bfin_read_ILAT();
1009 CSYNC();
1010 bfin_write_ILAT(ilat);
1011 CSYNC();
1012
1013 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1014 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1015 * local_irq_enable()
1016 */
1017 program_IAR();
1018 /* Therefore it's better to setup IARs before interrupts enabled */
1019 search_IAR();
1020
1021 /* Enable interrupts IVG7-15 */
1022 irq_flags = irq_flags | IMASK_IVG15 |
1023 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1024 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1025
1026 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1027 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1028 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1029 # ifdef CONFIG_BF54x
1030 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1031 # endif
1032 #else
1033 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1034 #endif
1035
1036 return 0;
1037 }
1038
1039 #ifdef CONFIG_DO_IRQ_L1
1040 __attribute__((l1_text))
1041 #endif
1042 void do_irq(int vec, struct pt_regs *fp)
1043 {
1044 if (vec == EVT_IVTMR_P) {
1045 vec = IRQ_CORETMR;
1046 } else {
1047 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1048 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1049 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1050 unsigned long sic_status[3];
1051
1052 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1053 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1054 #ifdef CONFIG_BF54x
1055 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1056 #endif
1057 for (;; ivg++) {
1058 if (ivg >= ivg_stop) {
1059 atomic_inc(&num_spurious);
1060 return;
1061 }
1062 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1063 break;
1064 }
1065 #else
1066 unsigned long sic_status;
1067
1068 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1069
1070 for (;; ivg++) {
1071 if (ivg >= ivg_stop) {
1072 atomic_inc(&num_spurious);
1073 return;
1074 } else if (sic_status & ivg->isrflag)
1075 break;
1076 }
1077 #endif
1078 vec = ivg->irqno;
1079 }
1080 asm_do_IRQ(vec, fp);
1081
1082 #ifdef CONFIG_KGDB
1083 kgdb_process_breakpoint();
1084 #endif
1085 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree