drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2010, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <linux/hrtimer.h>      /* ktime_get_real() */
  60 #include <trace/events/power.h>
  61 #include <linux/sched.h>
  62 #include <linux/notifier.h>
  63 #include <linux/cpu.h>
  64 #include <asm/mwait.h>
  65
  66 #define INTEL_IDLE_VERSION "0.4"
  67 #define PREFIX "intel_idle: "
  68
  69 static struct cpuidle_driver intel_idle_driver = {
  70         .name = "intel_idle",
  71         .owner = THIS_MODULE,
  72 };
  73 /* intel_idle.max_cstate=0 disables driver */
  74 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  75
  76 static unsigned int mwait_substates;
  77
  78 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  79 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  80 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  81
  82 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  83 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
  84
  85 static struct cpuidle_state *cpuidle_state_table;
  86
  87 /*
  88  * Set this flag for states where the HW flushes the TLB for us
  89  * and so we don't need cross-calls to keep it consistent.
  90  * If this flag is set, SW flushes the TLB, so even if the
  91  * HW doesn't do the flushing, this flag is safe to use.
  92  */
  93 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
  94
  95 /*
  96  * States are indexed by the cstate number,
  97  * which is also the index into the MWAIT hint array.
  98  * Thus C0 is a dummy.
  99  */
 100 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
 101         { /* MWAIT C0 */ },
 102         { /* MWAIT C1 */
 103                 .name = "NHM-C1",
 104                 .desc = "MWAIT 0x00",
 105                 .driver_data = (void *) 0x00,
 106                 .flags = CPUIDLE_FLAG_TIME_VALID,
 107                 .exit_latency = 3,
 108                 .target_residency = 6,
 109                 .enter = &intel_idle },
 110         { /* MWAIT C2 */
 111                 .name = "NHM-C3",
 112                 .desc = "MWAIT 0x10",
 113                 .driver_data = (void *) 0x10,
 114                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 115                 .exit_latency = 20,
 116                 .target_residency = 80,
 117                 .enter = &intel_idle },
 118         { /* MWAIT C3 */
 119                 .name = "NHM-C6",
 120                 .desc = "MWAIT 0x20",
 121                 .driver_data = (void *) 0x20,
 122                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 123                 .exit_latency = 200,
 124                 .target_residency = 800,
 125                 .enter = &intel_idle },
 126 };
 127
 128 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
 129         { /* MWAIT C0 */ },
 130         { /* MWAIT C1 */
 131                 .name = "SNB-C1",
 132                 .desc = "MWAIT 0x00",
 133                 .driver_data = (void *) 0x00,
 134                 .flags = CPUIDLE_FLAG_TIME_VALID,
 135                 .exit_latency = 1,
 136                 .target_residency = 1,
 137                 .enter = &intel_idle },
 138         { /* MWAIT C2 */
 139                 .name = "SNB-C3",
 140                 .desc = "MWAIT 0x10",
 141                 .driver_data = (void *) 0x10,
 142                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 143                 .exit_latency = 80,
 144                 .target_residency = 211,
 145                 .enter = &intel_idle },
 146         { /* MWAIT C3 */
 147                 .name = "SNB-C6",
 148                 .desc = "MWAIT 0x20",
 149                 .driver_data = (void *) 0x20,
 150                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 151                 .exit_latency = 104,
 152                 .target_residency = 345,
 153                 .enter = &intel_idle },
 154         { /* MWAIT C4 */
 155                 .name = "SNB-C7",
 156                 .desc = "MWAIT 0x30",
 157                 .driver_data = (void *) 0x30,
 158                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 159                 .exit_latency = 109,
 160                 .target_residency = 345,
 161                 .enter = &intel_idle },
 162 };
 163
 164 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
 165         { /* MWAIT C0 */ },
 166         { /* MWAIT C1 */
 167                 .name = "ATM-C1",
 168                 .desc = "MWAIT 0x00",
 169                 .driver_data = (void *) 0x00,
 170                 .flags = CPUIDLE_FLAG_TIME_VALID,
 171                 .exit_latency = 1,
 172                 .target_residency = 4,
 173                 .enter = &intel_idle },
 174         { /* MWAIT C2 */
 175                 .name = "ATM-C2",
 176                 .desc = "MWAIT 0x10",
 177                 .driver_data = (void *) 0x10,
 178                 .flags = CPUIDLE_FLAG_TIME_VALID,
 179                 .exit_latency = 20,
 180                 .target_residency = 80,
 181                 .enter = &intel_idle },
 182         { /* MWAIT C3 */ },
 183         { /* MWAIT C4 */
 184                 .name = "ATM-C4",
 185                 .desc = "MWAIT 0x30",
 186                 .driver_data = (void *) 0x30,
 187                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 188                 .exit_latency = 100,
 189                 .target_residency = 400,
 190                 .enter = &intel_idle },
 191         { /* MWAIT C5 */ },
 192         { /* MWAIT C6 */
 193                 .name = "ATM-C6",
 194                 .desc = "MWAIT 0x52",
 195                 .driver_data = (void *) 0x52,
 196                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 197                 .exit_latency = 140,
 198                 .target_residency = 560,
 199                 .enter = &intel_idle },
 200 };
 201
 202 /**
 203  * intel_idle
 204  * @dev: cpuidle_device
 205  * @state: cpuidle state
 206  *
 207  */
 208 static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
 209 {
 210         unsigned long ecx = 1; /* break on interrupt flag */
 211         unsigned long eax = (unsigned long)cpuidle_get_statedata(state);
 212         unsigned int cstate;
 213         ktime_t kt_before, kt_after;
 214         s64 usec_delta;
 215         int cpu = smp_processor_id();
 216
 217         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 218
 219         local_irq_disable();
 220
 221         /*
 222          * leave_mm() to avoid costly and often unnecessary wakeups
 223          * for flushing the user TLB's associated with the active mm.
 224          */
 225         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 226                 leave_mm(cpu);
 227
 228         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 229                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 230
 231         kt_before = ktime_get_real();
 232
 233         stop_critical_timings();
 234         trace_power_start(POWER_CSTATE, (eax >> 4) + 1, cpu);
 235         trace_cpu_idle((eax >> 4) + 1, cpu);
 236         if (!need_resched()) {
 237
 238                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 239                 smp_mb();
 240                 if (!need_resched())
 241                         __mwait(eax, ecx);
 242         }
 243
 244         start_critical_timings();
 245
 246         kt_after = ktime_get_real();
 247         usec_delta = ktime_to_us(ktime_sub(kt_after, kt_before));
 248
 249         local_irq_enable();
 250
 251         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 252                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 253
 254         return usec_delta;
 255 }
 256
 257 static void __setup_broadcast_timer(void *arg)
 258 {
 259         unsigned long reason = (unsigned long)arg;
 260         int cpu = smp_processor_id();
 261
 262         reason = reason ?
 263                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 264
 265         clockevents_notify(reason, &cpu);
 266 }
 267
 268 static int __cpuinit setup_broadcast_cpuhp_notify(struct notifier_block *n,
 269                 unsigned long action, void *hcpu)
 270 {
 271         int hotcpu = (unsigned long)hcpu;
 272
 273         switch (action & 0xf) {
 274         case CPU_ONLINE:
 275                 smp_call_function_single(hotcpu, __setup_broadcast_timer,
 276                         (void *)true, 1);
 277                 break;
 278         case CPU_DOWN_PREPARE:
 279                 smp_call_function_single(hotcpu, __setup_broadcast_timer,
 280                         (void *)false, 1);
 281                 break;
 282         }
 283         return NOTIFY_OK;
 284 }
 285
 286 static struct notifier_block __cpuinitdata setup_broadcast_notifier = {
 287         .notifier_call = setup_broadcast_cpuhp_notify,
 288 };
 289
 290 /*
 291  * intel_idle_probe()
 292  */
 293 static int intel_idle_probe(void)
 294 {
 295         unsigned int eax, ebx, ecx;
 296
 297         if (max_cstate == 0) {
 298                 pr_debug(PREFIX "disabled\n");
 299                 return -EPERM;
 300         }
 301
 302         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 303                 return -ENODEV;
 304
 305         if (!boot_cpu_has(X86_FEATURE_MWAIT))
 306                 return -ENODEV;
 307
 308         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 309                 return -ENODEV;
 310
 311         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 312
 313         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 314                 !(ecx & CPUID5_ECX_INTERRUPT_BREAK))
 315                         return -ENODEV;
 316
 317         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 318
 319
 320         if (boot_cpu_data.x86 != 6)     /* family 6 */
 321                 return -ENODEV;
 322
 323         switch (boot_cpu_data.x86_model) {
 324
 325         case 0x1A:      /* Core i7, Xeon 5500 series */
 326         case 0x1E:      /* Core i7 and i5 Processor - Lynnfield Jasper Forest */
 327         case 0x1F:      /* Core i7 and i5 Processor - Nehalem */
 328         case 0x2E:      /* Nehalem-EX Xeon */
 329         case 0x2F:      /* Westmere-EX Xeon */
 330         case 0x25:      /* Westmere */
 331         case 0x2C:      /* Westmere */
 332                 cpuidle_state_table = nehalem_cstates;
 333                 break;
 334
 335         case 0x1C:      /* 28 - Atom Processor */
 336         case 0x26:      /* 38 - Lincroft Atom Processor */
 337                 cpuidle_state_table = atom_cstates;
 338                 break;
 339
 340         case 0x2A:      /* SNB */
 341         case 0x2D:      /* SNB Xeon */
 342                 cpuidle_state_table = snb_cstates;
 343                 break;
 344
 345         default:
 346                 pr_debug(PREFIX "does not run on family %d model %d\n",
 347                         boot_cpu_data.x86, boot_cpu_data.x86_model);
 348                 return -ENODEV;
 349         }
 350
 351         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 352                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 353         else {
 354                 smp_call_function(__setup_broadcast_timer, (void *)true, 1);
 355                 register_cpu_notifier(&setup_broadcast_notifier);
 356         }
 357
 358         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 359                 " model 0x%X\n", boot_cpu_data.x86_model);
 360
 361         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 362                 lapic_timer_reliable_states);
 363         return 0;
 364 }
 365
 366 /*
 367  * intel_idle_cpuidle_devices_uninit()
 368  * unregister, free cpuidle_devices
 369  */
 370 static void intel_idle_cpuidle_devices_uninit(void)
 371 {
 372         int i;
 373         struct cpuidle_device *dev;
 374
 375         for_each_online_cpu(i) {
 376                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 377                 cpuidle_unregister_device(dev);
 378         }
 379
 380         free_percpu(intel_idle_cpuidle_devices);
 381         return;
 382 }
 383 /*
 384  * intel_idle_cpuidle_devices_init()
 385  * allocate, initialize, register cpuidle_devices
 386  */
 387 static int intel_idle_cpuidle_devices_init(void)
 388 {
 389         int i, cstate;
 390         struct cpuidle_device *dev;
 391
 392         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 393         if (intel_idle_cpuidle_devices == NULL)
 394                 return -ENOMEM;
 395
 396         for_each_online_cpu(i) {
 397                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 398
 399                 dev->state_count = 1;
 400
 401                 for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 402                         int num_substates;
 403
 404                         if (cstate > max_cstate) {
 405                                 printk(PREFIX "max_cstate %d reached\n",
 406                                         max_cstate);
 407                                 break;
 408                         }
 409
 410                         /* does the state exist in CPUID.MWAIT? */
 411                         num_substates = (mwait_substates >> ((cstate) * 4))
 412                                                 & MWAIT_SUBSTATE_MASK;
 413                         if (num_substates == 0)
 414                                 continue;
 415                         /* is the state not enabled? */
 416                         if (cpuidle_state_table[cstate].enter == NULL) {
 417                                 /* does the driver not know about the state? */
 418                                 if (*cpuidle_state_table[cstate].name == '\0')
 419                                         pr_debug(PREFIX "unaware of model 0x%x"
 420                                                 " MWAIT %d please"
 421                                                 " contact lenb@kernel.org",
 422                                         boot_cpu_data.x86_model, cstate);
 423                                 continue;
 424                         }
 425
 426                         if ((cstate > 2) &&
 427                                 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 428                                 mark_tsc_unstable("TSC halts in idle"
 429                                         " states deeper than C2");
 430
 431                         dev->states[dev->state_count] = /* structure copy */
 432                                 cpuidle_state_table[cstate];
 433
 434                         dev->state_count += 1;
 435                 }
 436
 437                 dev->cpu = i;
 438                 if (cpuidle_register_device(dev)) {
 439                         pr_debug(PREFIX "cpuidle_register_device %d failed!\n",
 440                                  i);
 441                         intel_idle_cpuidle_devices_uninit();
 442                         return -EIO;
 443                 }
 444         }
 445
 446         return 0;
 447 }
 448
 449
 450 static int __init intel_idle_init(void)
 451 {
 452         int retval;
 453
 454         /* Do not load intel_idle at all for now if idle= is passed */
 455         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 456                 return -ENODEV;
 457
 458         retval = intel_idle_probe();
 459         if (retval)
 460                 return retval;
 461
 462         retval = cpuidle_register_driver(&intel_idle_driver);
 463         if (retval) {
 464                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 465                         cpuidle_get_driver()->name);
 466                 return retval;
 467         }
 468
 469         retval = intel_idle_cpuidle_devices_init();
 470         if (retval) {
 471                 cpuidle_unregister_driver(&intel_idle_driver);
 472                 return retval;
 473         }
 474
 475         return 0;
 476 }
 477
 478 static void __exit intel_idle_exit(void)
 479 {
 480         intel_idle_cpuidle_devices_uninit();
 481         cpuidle_unregister_driver(&intel_idle_driver);
 482
 483         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE) {
 484                 smp_call_function(__setup_broadcast_timer, (void *)false, 1);
 485                 unregister_cpu_notifier(&setup_broadcast_notifier);
 486         }
 487
 488         return;
 489 }
 490
 491 module_init(intel_idle_init);
 492 module_exit(intel_idle_exit);
 493
 494 module_param(max_cstate, int, 0444);
 495
 496 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 497 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 498 MODULE_LICENSE("GPL");