drivers/clocksource/acpi_pm.c

   1 /*
   2  * linux/drivers/clocksource/acpi_pm.c
   3  *
   4  * This file contains the ACPI PM based clocksource.
   5  *
   6  * This code was largely moved from the i386 timer_pm.c file
   7  * which was (C) Dominik Brodowski <linux@brodo.de> 2003
   8  * and contained the following comments:
   9  *
  10  * Driver to use the Power Management Timer (PMTMR) available in some
  11  * southbridges as primary timing source for the Linux kernel.
  12  *
  13  * Based on parts of linux/drivers/acpi/hardware/hwtimer.c, timer_pit.c,
  14  * timer_hpet.c, and on Arjan van de Ven's implementation for 2.4.
  15  *
  16  * This file is licensed under the GPL v2.
  17  */
  18
  19 #include <linux/clocksource.h>
  20 #include <linux/errno.h>
  21 #include <linux/init.h>
  22 #include <linux/pci.h>
  23 #include <asm/io.h>
  24
  25 /* Number of PMTMR ticks expected during calibration run */
  26 #define PMTMR_TICKS_PER_SEC 3579545
  27
  28 /*
  29  * The I/O port the PMTMR resides at.
  30  * The location is detected during setup_arch(),
  31  * in arch/i386/acpi/boot.c
  32  */
  33 u32 pmtmr_ioport __read_mostly;
  34
  35 #define ACPI_PM_MASK CLOCKSOURCE_MASK(24) /* limit it to 24 bits */
  36
  37 static inline u32 read_pmtmr(void)
  38 {
  39         /* mask the output to 24 bits */
  40         return inl(pmtmr_ioport) & ACPI_PM_MASK;
  41 }
  42
  43 static cycle_t acpi_pm_read_verified(void)
  44 {
  45         u32 v1 = 0, v2 = 0, v3 = 0;
  46
  47         /*
  48          * It has been reported that because of various broken
  49          * chipsets (ICH4, PIIX4 and PIIX4E) where the ACPI PM clock
  50          * source is not latched, you must read it multiple
  51          * times to ensure a safe value is read:
  52          */
  53         do {
  54                 v1 = read_pmtmr();
  55                 v2 = read_pmtmr();
  56                 v3 = read_pmtmr();
  57         } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1)
  58                           || (v3 > v1 && v3 < v2)));
  59
  60         return (cycle_t)v2;
  61 }
  62
  63 static cycle_t acpi_pm_read(void)
  64 {
  65         return (cycle_t)read_pmtmr();
  66 }
  67
  68 static struct clocksource clocksource_acpi_pm = {
  69         .name           = "acpi_pm",
  70         .rating         = 200,
  71         .read           = acpi_pm_read,
  72         .mask           = (cycle_t)ACPI_PM_MASK,
  73         .mult           = 0, /*to be caluclated*/
  74         .shift          = 22,
  75         .is_continuous  = 1,
  76 };
  77
  78
  79 #ifdef CONFIG_PCI
  80 static int acpi_pm_good;
  81 static int __init acpi_pm_good_setup(char *__str)
  82 {
  83        acpi_pm_good = 1;
  84        return 1;
  85 }
  86 __setup("acpi_pm_good", acpi_pm_good_setup);
  87
  88 static inline void acpi_pm_need_workaround(void)
  89 {
  90         clocksource_acpi_pm.read = acpi_pm_read_verified;
  91         clocksource_acpi_pm.rating = 110;
  92 }
  93
  94 /*
  95  * PIIX4 Errata:
  96  *
  97  * The power management timer may return improper results when read.
  98  * Although the timer value settles properly after incrementing,
  99  * while incrementing there is a 3 ns window every 69.8 ns where the
 100  * timer value is indeterminate (a 4.2% chance that the data will be
 101  * incorrect when read). As a result, the ACPI free running count up
 102  * timer specification is violated due to erroneous reads.
 103  */
 104 static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
 105 {
 106         u8 rev;
 107
 108         if (acpi_pm_good)
 109                 return;
 110
 111         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
 112         /* the bug has been fixed in PIIX4M */
 113         if (rev < 3) {
 114                 printk(KERN_WARNING "* Found PM-Timer Bug on the chipset."
 115                        " Due to workarounds for a bug,\n"
 116                        "* this clock source is slow. Consider trying"
 117                        " other clock sources\n");
 118
 119                 acpi_pm_need_workaround();
 120         }
 121 }
 122 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
 123                         acpi_pm_check_blacklist);
 124
 125 static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
 126 {
 127         if (acpi_pm_good)
 128                 return;
 129
 130         printk(KERN_WARNING "* The chipset may have PM-Timer Bug. Due to"
 131                " workarounds for a bug,\n"
 132                "* this clock source is slow. If you are sure your timer"
 133                " does not have\n"
 134                "* this bug, please use \"acpi_pm_good\" to disable the"
 135                " workaround\n");
 136
 137         acpi_pm_need_workaround();
 138 }
 139 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
 140                         acpi_pm_check_graylist);
 141 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
 142                         acpi_pm_check_graylist);
 143 #endif
 144
 145 #ifndef CONFIG_X86_64
 146 #include "mach_timer.h"
 147 #define PMTMR_EXPECTED_RATE \
 148   ((CALIBRATE_LATCH * (PMTMR_TICKS_PER_SEC >> 10)) / (CLOCK_TICK_RATE>>10))
 149 /*
 150  * Some boards have the PMTMR running way too fast. We check
 151  * the PMTMR rate against PIT channel 2 to catch these cases.
 152  */
 153 static int verify_pmtmr_rate(void)
 154 {
 155         u32 value1, value2;
 156         unsigned long count, delta;
 157
 158         mach_prepare_counter();
 159         value1 = read_pmtmr();
 160         mach_countup(&count);
 161         value2 = read_pmtmr();
 162         delta = (value2 - value1) & ACPI_PM_MASK;
 163
 164         /* Check that the PMTMR delta is within 5% of what we expect */
 165         if (delta < (PMTMR_EXPECTED_RATE * 19) / 20 ||
 166             delta > (PMTMR_EXPECTED_RATE * 21) / 20) {
 167                 printk(KERN_INFO "PM-Timer running at invalid rate: %lu%% "
 168                         "of normal - aborting.\n",
 169                         100UL * delta / PMTMR_EXPECTED_RATE);
 170                 return -1;
 171         }
 172
 173         return 0;
 174 }
 175 #else
 176 #define verify_pmtmr_rate() (0)
 177 #endif
 178
 179 static int __init init_acpi_pm_clocksource(void)
 180 {
 181         u32 value1, value2;
 182         unsigned int i;
 183
 184         if (!pmtmr_ioport)
 185                 return -ENODEV;
 186
 187         clocksource_acpi_pm.mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC,
 188                                                 clocksource_acpi_pm.shift);
 189
 190         /* "verify" this timing source: */
 191         value1 = read_pmtmr();
 192         for (i = 0; i < 10000; i++) {
 193                 value2 = read_pmtmr();
 194                 if (value2 == value1)
 195                         continue;
 196                 if (value2 > value1)
 197                         goto pm_good;
 198                 if ((value2 < value1) && ((value2) < 0xFFF))
 199                         goto pm_good;
 200                 printk(KERN_INFO "PM-Timer had inconsistent results:"
 201                         " 0x%#x, 0x%#x - aborting.\n", value1, value2);
 202                 return -EINVAL;
 203         }
 204         printk(KERN_INFO "PM-Timer had no reasonable result:"
 205                         " 0x%#x - aborting.\n", value1);
 206         return -ENODEV;
 207
 208 pm_good:
 209         if (verify_pmtmr_rate() != 0)
 210                 return -ENODEV;
 211
 212         return clocksource_register(&clocksource_acpi_pm);
 213 }
 214
 215 module_init(init_acpi_pm_clocksource);