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Staging: brcm80211: s/int8/s8/
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / brcm80211 / include / d11.h
blob3c4304c84549257bb8024ccc81d2c6e2ea5088e3
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef _D11_H
18 #define _D11_H
19
20 #include <typedefs.h>
21 #include <bcmdevs.h>
22 #include <hndsoc.h>
23 #include <sbhndpio.h>
24 #include <sbhnddma.h>
25 #include <proto/802.11.h>
26
27 /* This marks the start of a packed structure section. */
28 #include <packed_section_start.h>
29
30 #ifndef WL_RSSI_ANT_MAX
31 #define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
32 #elif WL_RSSI_ANT_MAX != 4
33 #error "WL_RSSI_ANT_MAX does not match"
34 #endif
35
36 /* cpp contortions to concatenate w/arg prescan */
37 #ifndef PAD
38 #define _PADLINE(line) pad ## line
39 #define _XSTR(line) _PADLINE(line)
40 #define PAD _XSTR(__LINE__)
41 #endif
42
43 #define BCN_TMPL_LEN 512 /* length of the BCN template area */
44
45 /* RX FIFO numbers */
46 #define RX_FIFO 0 /* data and ctl frames */
47 #define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
48
49 /* TX FIFO numbers using WME Access Classes */
50 #define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */
51 #define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */
52 #define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */
53 #define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */
54 #define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
55 #define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
56
57 /* Addr is byte address used by SW; offset is word offset used by uCode */
58
59 /* Per AC TX limit settings */
60 #define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
61 #define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
62
63 /* Legacy TX FIFO numbers */
64 #define TX_DATA_FIFO TX_AC_BE_FIFO
65 #define TX_CTL_FIFO TX_AC_VO_FIFO
66
67 typedef volatile struct {
68 uint32 intstatus;
69 uint32 intmask;
70 } intctrlregs_t;
71
72 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
73 * write: only low 16b-it half can be written
74 */
75 typedef volatile union {
76 uint32 pmqhostdata; /* read only! */
77 struct {
78 uint16 pmqctrlstatus; /* read/write */
79 uint16 PAD;
80 } w;
81 } pmqreg_t;
82
83 /* pio register set 2/4 bytes union for d11 fifo */
84 typedef volatile union {
85 pio2regp_t b2; /* < corerev 8 */
86 pio4regp_t b4; /* >= corerev 8 */
87 } u_pioreg_t;
88
89 /* dma/pio corerev < 11 */
90 typedef volatile struct {
91 dma32regp_t dmaregs[8]; /* 0x200 - 0x2fc */
92 u_pioreg_t pioregs[8]; /* 0x300 */
93 } fifo32_t;
94
95 /* dma/pio corerev >= 11 */
96 typedef volatile struct {
97 dma64regs_t dmaxmt; /* dma tx */
98 pio4regs_t piotx; /* pio tx */
99 dma64regs_t dmarcv; /* dma rx */
100 pio4regs_t piorx; /* pio rx */
101 } fifo64_t;
102
103 /*
104 * Host Interface Registers
105 * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h
106 * - but definitely not complete
107 */
108 typedef volatile struct _d11regs {
109 /* Device Control ("semi-standard host registers") */
110 uint32 PAD[3]; /* 0x0 - 0x8 */
111 uint32 biststatus; /* 0xC */
112 uint32 biststatus2; /* 0x10 */
113 uint32 PAD; /* 0x14 */
114 uint32 gptimer; /* 0x18 *//* for corerev >= 3 */
115 uint32 usectimer; /* 0x1c *//* for corerev >= 26 */
116
117 /* Interrupt Control *//* 0x20 */
118 intctrlregs_t intctrlregs[8];
119
120 uint32 PAD[40]; /* 0x60 - 0xFC */
121
122 /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
123 uint32 intrcvlazy[4]; /* 0x100 - 0x10C */
124
125 uint32 PAD[4]; /* 0x110 - 0x11c */
126
127 uint32 maccontrol; /* 0x120 */
128 uint32 maccommand; /* 0x124 */
129 uint32 macintstatus; /* 0x128 */
130 uint32 macintmask; /* 0x12C */
131
132 /* Transmit Template Access */
133 uint32 tplatewrptr; /* 0x130 */
134 uint32 tplatewrdata; /* 0x134 */
135 uint32 PAD[2]; /* 0x138 - 0x13C */
136
137 /* PMQ registers */
138 pmqreg_t pmqreg; /* 0x140 */
139 uint32 pmqpatl; /* 0x144 */
140 uint32 pmqpath; /* 0x148 */
141 uint32 PAD; /* 0x14C */
142
143 uint32 chnstatus; /* 0x150 */
144 uint32 psmdebug; /* 0x154 *//* for corerev >= 3 */
145 uint32 phydebug; /* 0x158 *//* for corerev >= 3 */
146 uint32 machwcap; /* 0x15C *//* Corerev >= 13 */
147
148 /* Extended Internal Objects */
149 uint32 objaddr; /* 0x160 */
150 uint32 objdata; /* 0x164 */
151 uint32 PAD[2]; /* 0x168 - 0x16c */
152
153 /* New txstatus registers on corerev >= 5 */
154 uint32 frmtxstatus; /* 0x170 */
155 uint32 frmtxstatus2; /* 0x174 */
156 uint32 PAD[2]; /* 0x178 - 0x17c */
157
158 /* New TSF host access on corerev >= 3 */
159
160 uint32 tsf_timerlow; /* 0x180 */
161 uint32 tsf_timerhigh; /* 0x184 */
162 uint32 tsf_cfprep; /* 0x188 */
163 uint32 tsf_cfpstart; /* 0x18c */
164 uint32 tsf_cfpmaxdur32; /* 0x190 */
165 uint32 PAD[3]; /* 0x194 - 0x19c */
166
167 uint32 maccontrol1; /* 0x1a0 */
168 uint32 machwcap1; /* 0x1a4 */
169 uint32 PAD[14]; /* 0x1a8 - 0x1dc */
170
171 /* Clock control and hardware workarounds (corerev >= 13) */
172 uint32 clk_ctl_st; /* 0x1e0 */
173 uint32 hw_war;
174 uint32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are
175 * moved to clk_ctl_st for corerev >= 17
176 */
177 uint32 PAD[5]; /* 0x1ec - 0x1fc */
178
179 /* 0x200-0x37F dma/pio registers */
180 volatile union {
181 fifo32_t f32regs; /* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */
182 fifo64_t f64regs[6]; /* on corerev >= 11 */
183 } fifo;
184
185 /* FIFO diagnostic port access */
186 dma32diag_t dmafifo; /* 0x380 - 0x38C */
187
188 uint32 aggfifocnt; /* 0x390 */
189 uint32 aggfifodata; /* 0x394 */
190 uint32 PAD[16]; /* 0x398 - 0x3d4 */
191 uint16 radioregaddr; /* 0x3d8 */
192 uint16 radioregdata; /* 0x3da */
193
194 /* time delay between the change on rf disable input and radio shutdown corerev 10 */
195 uint32 rfdisabledly; /* 0x3DC */
196
197 /* PHY register access */
198 uint16 phyversion; /* 0x3e0 - 0x0 */
199 uint16 phybbconfig; /* 0x3e2 - 0x1 */
200 uint16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
201 uint16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
202 uint16 phyrxstatus0; /* 0x3e8 - 0x4 */
203 uint16 phyrxstatus1; /* 0x3ea - 0x5 */
204 uint16 phycrsth; /* 0x3ec - 0x6 */
205 uint16 phytxerror; /* 0x3ee - 0x7 */
206 uint16 phychannel; /* 0x3f0 - 0x8 */
207 uint16 PAD[1]; /* 0x3f2 - 0x9 */
208 uint16 phytest; /* 0x3f4 - 0xa */
209 uint16 phy4waddr; /* 0x3f6 - 0xb */
210 uint16 phy4wdatahi; /* 0x3f8 - 0xc */
211 uint16 phy4wdatalo; /* 0x3fa - 0xd */
212 uint16 phyregaddr; /* 0x3fc - 0xe */
213 uint16 phyregdata; /* 0x3fe - 0xf */
214
215 /* IHR *//* 0x400 - 0x7FE */
216
217 /* RXE Block */
218 uint16 PAD[3]; /* 0x400 - 0x406 */
219 uint16 rcv_fifo_ctl; /* 0x406 */
220 uint16 PAD; /* 0x408 - 0x40a */
221 uint16 rcv_frm_cnt; /* 0x40a */
222 uint16 PAD[4]; /* 0x40a - 0x414 */
223 uint16 rssi; /* 0x414 */
224 uint16 PAD[5]; /* 0x414 - 0x420 */
225 uint16 rcm_ctl; /* 0x420 */
226 uint16 rcm_mat_data; /* 0x422 */
227 uint16 rcm_mat_mask; /* 0x424 */
228 uint16 rcm_mat_dly; /* 0x426 */
229 uint16 rcm_cond_mask_l; /* 0x428 */
230 uint16 rcm_cond_mask_h; /* 0x42A */
231 uint16 rcm_cond_dly; /* 0x42C */
232 uint16 PAD[1]; /* 0x42E */
233 uint16 ext_ihr_addr; /* 0x430 */
234 uint16 ext_ihr_data; /* 0x432 */
235 uint16 rxe_phyrs_2; /* 0x434 */
236 uint16 rxe_phyrs_3; /* 0x436 */
237 uint16 phy_mode; /* 0x438 */
238 uint16 rcmta_ctl; /* 0x43a */
239 uint16 rcmta_size; /* 0x43c */
240 uint16 rcmta_addr0; /* 0x43e */
241 uint16 rcmta_addr1; /* 0x440 */
242 uint16 rcmta_addr2; /* 0x442 */
243 uint16 PAD[30]; /* 0x444 - 0x480 */
244
245 /* PSM Block *//* 0x480 - 0x500 */
246
247 uint16 PAD; /* 0x480 */
248 uint16 psm_maccontrol_h; /* 0x482 */
249 uint16 psm_macintstatus_l; /* 0x484 */
250 uint16 psm_macintstatus_h; /* 0x486 */
251 uint16 psm_macintmask_l; /* 0x488 */
252 uint16 psm_macintmask_h; /* 0x48A */
253 uint16 PAD; /* 0x48C */
254 uint16 psm_maccommand; /* 0x48E */
255 uint16 psm_brc; /* 0x490 */
256 uint16 psm_phy_hdr_param; /* 0x492 */
257 uint16 psm_postcard; /* 0x494 */
258 uint16 psm_pcard_loc_l; /* 0x496 */
259 uint16 psm_pcard_loc_h; /* 0x498 */
260 uint16 psm_gpio_in; /* 0x49A */
261 uint16 psm_gpio_out; /* 0x49C */
262 uint16 psm_gpio_oe; /* 0x49E */
263
264 uint16 psm_bred_0; /* 0x4A0 */
265 uint16 psm_bred_1; /* 0x4A2 */
266 uint16 psm_bred_2; /* 0x4A4 */
267 uint16 psm_bred_3; /* 0x4A6 */
268 uint16 psm_brcl_0; /* 0x4A8 */
269 uint16 psm_brcl_1; /* 0x4AA */
270 uint16 psm_brcl_2; /* 0x4AC */
271 uint16 psm_brcl_3; /* 0x4AE */
272 uint16 psm_brpo_0; /* 0x4B0 */
273 uint16 psm_brpo_1; /* 0x4B2 */
274 uint16 psm_brpo_2; /* 0x4B4 */
275 uint16 psm_brpo_3; /* 0x4B6 */
276 uint16 psm_brwk_0; /* 0x4B8 */
277 uint16 psm_brwk_1; /* 0x4BA */
278 uint16 psm_brwk_2; /* 0x4BC */
279 uint16 psm_brwk_3; /* 0x4BE */
280
281 uint16 psm_base_0; /* 0x4C0 */
282 uint16 psm_base_1; /* 0x4C2 */
283 uint16 psm_base_2; /* 0x4C4 */
284 uint16 psm_base_3; /* 0x4C6 */
285 uint16 psm_base_4; /* 0x4C8 */
286 uint16 psm_base_5; /* 0x4CA */
287 uint16 psm_base_6; /* 0x4CC */
288 uint16 psm_pc_reg_0; /* 0x4CE */
289 uint16 psm_pc_reg_1; /* 0x4D0 */
290 uint16 psm_pc_reg_2; /* 0x4D2 */
291 uint16 psm_pc_reg_3; /* 0x4D4 */
292 uint16 PAD[0xD]; /* 0x4D6 - 0x4DE */
293 uint16 psm_corectlsts; /* 0x4f0 *//* Corerev >= 13 */
294 uint16 PAD[0x7]; /* 0x4f2 - 0x4fE */
295
296 /* TXE0 Block *//* 0x500 - 0x580 */
297 uint16 txe_ctl; /* 0x500 */
298 uint16 txe_aux; /* 0x502 */
299 uint16 txe_ts_loc; /* 0x504 */
300 uint16 txe_time_out; /* 0x506 */
301 uint16 txe_wm_0; /* 0x508 */
302 uint16 txe_wm_1; /* 0x50A */
303 uint16 txe_phyctl; /* 0x50C */
304 uint16 txe_status; /* 0x50E */
305 uint16 txe_mmplcp0; /* 0x510 */
306 uint16 txe_mmplcp1; /* 0x512 */
307 uint16 txe_phyctl1; /* 0x514 */
308
309 uint16 PAD[0x05]; /* 0x510 - 0x51E */
310
311 /* Transmit control */
312 uint16 xmtfifodef; /* 0x520 */
313 uint16 xmtfifo_frame_cnt; /* 0x522 *//* Corerev >= 16 */
314 uint16 xmtfifo_byte_cnt; /* 0x524 *//* Corerev >= 16 */
315 uint16 xmtfifo_head; /* 0x526 *//* Corerev >= 16 */
316 uint16 xmtfifo_rd_ptr; /* 0x528 *//* Corerev >= 16 */
317 uint16 xmtfifo_wr_ptr; /* 0x52A *//* Corerev >= 16 */
318 uint16 xmtfifodef1; /* 0x52C *//* Corerev >= 16 */
319
320 uint16 PAD[0x09]; /* 0x52E - 0x53E */
321
322 uint16 xmtfifocmd; /* 0x540 */
323 uint16 xmtfifoflush; /* 0x542 */
324 uint16 xmtfifothresh; /* 0x544 */
325 uint16 xmtfifordy; /* 0x546 */
326 uint16 xmtfifoprirdy; /* 0x548 */
327 uint16 xmtfiforqpri; /* 0x54A */
328 uint16 xmttplatetxptr; /* 0x54C */
329 uint16 PAD; /* 0x54E */
330 uint16 xmttplateptr; /* 0x550 */
331 uint16 smpl_clct_strptr; /* 0x552 *//* Corerev >= 22 */
332 uint16 smpl_clct_stpptr; /* 0x554 *//* Corerev >= 22 */
333 uint16 smpl_clct_curptr; /* 0x556 *//* Corerev >= 22 */
334 uint16 PAD[0x04]; /* 0x558 - 0x55E */
335 uint16 xmttplatedatalo; /* 0x560 */
336 uint16 xmttplatedatahi; /* 0x562 */
337
338 uint16 PAD[2]; /* 0x564 - 0x566 */
339
340 uint16 xmtsel; /* 0x568 */
341 uint16 xmttxcnt; /* 0x56A */
342 uint16 xmttxshmaddr; /* 0x56C */
343
344 uint16 PAD[0x09]; /* 0x56E - 0x57E */
345
346 /* TXE1 Block */
347 uint16 PAD[0x40]; /* 0x580 - 0x5FE */
348
349 /* TSF Block */
350 uint16 PAD[0X02]; /* 0x600 - 0x602 */
351 uint16 tsf_cfpstrt_l; /* 0x604 */
352 uint16 tsf_cfpstrt_h; /* 0x606 */
353 uint16 PAD[0X05]; /* 0x608 - 0x610 */
354 uint16 tsf_cfppretbtt; /* 0x612 */
355 uint16 PAD[0XD]; /* 0x614 - 0x62C */
356 uint16 tsf_clk_frac_l; /* 0x62E */
357 uint16 tsf_clk_frac_h; /* 0x630 */
358 uint16 PAD[0X14]; /* 0x632 - 0x658 */
359 uint16 tsf_random; /* 0x65A */
360 uint16 PAD[0x05]; /* 0x65C - 0x664 */
361 /* GPTimer 2 registers are corerev >= 3 */
362 uint16 tsf_gpt2_stat; /* 0x666 */
363 uint16 tsf_gpt2_ctr_l; /* 0x668 */
364 uint16 tsf_gpt2_ctr_h; /* 0x66A */
365 uint16 tsf_gpt2_val_l; /* 0x66C */
366 uint16 tsf_gpt2_val_h; /* 0x66E */
367 uint16 tsf_gptall_stat; /* 0x670 */
368 uint16 PAD[0x07]; /* 0x672 - 0x67E */
369
370 /* IFS Block */
371 uint16 ifs_sifs_rx_tx_tx; /* 0x680 */
372 uint16 ifs_sifs_nav_tx; /* 0x682 */
373 uint16 ifs_slot; /* 0x684 */
374 uint16 PAD; /* 0x686 */
375 uint16 ifs_ctl; /* 0x688 */
376 uint16 PAD[0x3]; /* 0x68a - 0x68F */
377 uint16 ifsstat; /* 0x690 */
378 uint16 ifsmedbusyctl; /* 0x692 */
379 uint16 iftxdur; /* 0x694 */
380 uint16 PAD[0x3]; /* 0x696 - 0x69b */
381 /* EDCF support in dot11macs with corerevs >= 16 */
382 uint16 ifs_aifsn; /* 0x69c */
383 uint16 ifs_ctl1; /* 0x69e */
384
385 /* New slow clock registers on corerev >= 5 */
386 uint16 scc_ctl; /* 0x6a0 */
387 uint16 scc_timer_l; /* 0x6a2 */
388 uint16 scc_timer_h; /* 0x6a4 */
389 uint16 scc_frac; /* 0x6a6 */
390 uint16 scc_fastpwrup_dly; /* 0x6a8 */
391 uint16 scc_per; /* 0x6aa */
392 uint16 scc_per_frac; /* 0x6ac */
393 uint16 scc_cal_timer_l; /* 0x6ae */
394 uint16 scc_cal_timer_h; /* 0x6b0 */
395 uint16 PAD; /* 0x6b2 */
396
397 uint16 PAD[0x26];
398
399 /* NAV Block */
400 uint16 nav_ctl; /* 0x700 */
401 uint16 navstat; /* 0x702 */
402 uint16 PAD[0x3e]; /* 0x702 - 0x77E */
403
404 /* WEP/PMQ Block *//* 0x780 - 0x7FE */
405 uint16 PAD[0x20]; /* 0x780 - 0x7BE */
406
407 uint16 wepctl; /* 0x7C0 */
408 uint16 wepivloc; /* 0x7C2 */
409 uint16 wepivkey; /* 0x7C4 */
410 uint16 wepwkey; /* 0x7C6 */
411
412 uint16 PAD[4]; /* 0x7C8 - 0x7CE */
413 uint16 pcmctl; /* 0X7D0 */
414 uint16 pcmstat; /* 0X7D2 */
415 uint16 PAD[6]; /* 0x7D4 - 0x7DE */
416
417 uint16 pmqctl; /* 0x7E0 */
418 uint16 pmqstatus; /* 0x7E2 */
419 uint16 pmqpat0; /* 0x7E4 */
420 uint16 pmqpat1; /* 0x7E6 */
421 uint16 pmqpat2; /* 0x7E8 */
422
423 uint16 pmqdat; /* 0x7EA */
424 uint16 pmqdator; /* 0x7EC */
425 uint16 pmqhst; /* 0x7EE */
426 uint16 pmqpath0; /* 0x7F0 */
427 uint16 pmqpath1; /* 0x7F2 */
428 uint16 pmqpath2; /* 0x7F4 */
429 uint16 pmqdath; /* 0x7F6 */
430
431 uint16 PAD[0x04]; /* 0x7F8 - 0x7FE */
432
433 /* SHM *//* 0x800 - 0xEFE */
434 uint16 PAD[0x380]; /* 0x800 - 0xEFE */
435
436 /* SB configuration registers: 0xF00 */
437 sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */
438 } d11regs_t;
439
440 #define PIHR_BASE 0x0400 /* byte address of packed IHR region */
441
442 /* biststatus */
443 #define BT_DONE (1U << 31) /* bist done */
444 #define BT_B2S (1 << 30) /* bist2 ram summary bit */
445
446 /* intstatus and intmask */
447 #define I_PC (1 << 10) /* pci descriptor error */
448 #define I_PD (1 << 11) /* pci data error */
449 #define I_DE (1 << 12) /* descriptor protocol error */
450 #define I_RU (1 << 13) /* receive descriptor underflow */
451 #define I_RO (1 << 14) /* receive fifo overflow */
452 #define I_XU (1 << 15) /* transmit fifo underflow */
453 #define I_RI (1 << 16) /* receive interrupt */
454 #define I_XI (1 << 24) /* transmit interrupt */
455
456 /* interrupt receive lazy */
457 #define IRL_TO_MASK 0x00ffffff /* timeout */
458 #define IRL_FC_MASK 0xff000000 /* frame count */
459 #define IRL_FC_SHIFT 24 /* frame count */
460
461 /* maccontrol register */
462 #define MCTL_GMODE (1U << 31)
463 #define MCTL_DISCARD_PMQ (1 << 30)
464 #define MCTL_WAKE (1 << 26)
465 #define MCTL_HPS (1 << 25)
466 #define MCTL_PROMISC (1 << 24)
467 #define MCTL_KEEPBADFCS (1 << 23)
468 #define MCTL_KEEPCONTROL (1 << 22)
469 #define MCTL_PHYLOCK (1 << 21)
470 #define MCTL_BCNS_PROMISC (1 << 20)
471 #define MCTL_LOCK_RADIO (1 << 19)
472 #define MCTL_AP (1 << 18)
473 #define MCTL_INFRA (1 << 17)
474 #define MCTL_BIGEND (1 << 16)
475 #define MCTL_GPOUT_SEL_MASK (3 << 14)
476 #define MCTL_GPOUT_SEL_SHIFT 14
477 #define MCTL_EN_PSMDBG (1 << 13)
478 #define MCTL_IHR_EN (1 << 10)
479 #define MCTL_SHM_UPPER (1 << 9)
480 #define MCTL_SHM_EN (1 << 8)
481 #define MCTL_PSM_JMP_0 (1 << 2)
482 #define MCTL_PSM_RUN (1 << 1)
483 #define MCTL_EN_MAC (1 << 0)
484
485 /* maccommand register */
486 #define MCMD_BCN0VLD (1 << 0)
487 #define MCMD_BCN1VLD (1 << 1)
488 #define MCMD_DIRFRMQVAL (1 << 2)
489 #define MCMD_CCA (1 << 3)
490 #define MCMD_BG_NOISE (1 << 4)
491 #define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
492 #define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
493
494 /* macintstatus/macintmask */
495 #define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */
496 #define MI_BCNTPL (1 << 1) /* beacon template available */
497 #define MI_TBTT (1 << 2) /* TBTT indication */
498 #define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */
499 #define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */
500 #define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */
501 #define MI_PMQ (1 << 6) /* PMQ entries available */
502 #define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */
503 #define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */
504 #define MI_MACTXERR (1 << 9) /* MAC level Tx error */
505 #define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */
506 #define MI_PHYTXERR (1 << 11) /* PHY Tx error */
507 #define MI_PME (1 << 12) /* Power Management Event */
508 #define MI_GP0 (1 << 13) /* General-purpose timer0 */
509 #define MI_GP1 (1 << 14) /* General-purpose timer1 */
510 #define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */
511 #define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */
512 #define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */
513 #define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */
514 #define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */
515 #define MI_PRQ (1 << 20) /* Probe response queue needs attention */
516 #define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */
517 #define MI_RESERVED3 (1 << 22)
518 #define MI_RESERVED2 (1 << 23)
519 #define MI_RESERVED1 (1 << 25)
520 #define MI_RFDISABLE (1 << 28) /* MAC detected a change on RF Disable input
521 * (corerev >= 10)
522 */
523 #define MI_TFS (1 << 29) /* MAC has completed a TX (corerev >= 5) */
524 #define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */
525 #define MI_TO (1U << 31) /* general purpose timeout (corerev >= 3) */
526
527 /* Mac capabilities registers */
528 /* machwcap */
529 #define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
530
531 /* pmqhost data */
532 #define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */
533 #define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */
534 #define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */
535 #define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */
536 #define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */
537 #define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */
538 #define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */
539 #define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */
540 #define PMQH_OFLO 0x00000004 /* pmq overflow indication */
541 #define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */
542
543 /* phydebug (corerev >= 3) */
544 #define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */
545 #define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */
546 #define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */
547 #define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */
548 #define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */
549 #define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */
550 #define PDBG_RXFRG (1 << 6) /* rx start not asserted */
551 #define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */
552 #define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */
553
554 /* objaddr register */
555 #define OBJADDR_SEL_MASK 0x000F0000
556 #define OBJADDR_UCM_SEL 0x00000000
557 #define OBJADDR_SHM_SEL 0x00010000
558 #define OBJADDR_SCR_SEL 0x00020000
559 #define OBJADDR_IHR_SEL 0x00030000
560 #define OBJADDR_RCMTA_SEL 0x00040000
561 #define OBJADDR_SRCHM_SEL 0x00060000
562 #define OBJADDR_WINC 0x01000000
563 #define OBJADDR_RINC 0x02000000
564 #define OBJADDR_AUTO_INC 0x03000000
565
566 #define WEP_PCMADDR 0x07d4
567 #define WEP_PCMDATA 0x07d6
568
569 /* frmtxstatus */
570 #define TXS_V (1 << 0) /* valid bit */
571 #define TXS_STATUS_MASK 0xffff
572 /* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */
573 #define TXS_COMPAT_MASK 0x3
574 #define TXS_COMPAT_SHIFT 1
575 #define TXS_FID_MASK 0xffff0000
576 #define TXS_FID_SHIFT 16
577
578 /* frmtxstatus2 */
579 #define TXS_SEQ_MASK 0xffff
580 #define TXS_PTX_MASK 0xff0000
581 #define TXS_PTX_SHIFT 16
582 #define TXS_MU_MASK 0x01000000
583 #define TXS_MU_SHIFT 24
584
585 /* clk_ctl_st, corerev >= 17 */
586 #define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
587 #define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
588 #define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
589 #define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
590
591 /* HT Cloclk Ctrl and Clock Avail for 4313 */
592 #define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
593 #define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
594
595 /* d11_pwrctl, corerev16 only */
596 #define D11_PHYPLL_AVAIL_REQ 0x000010000 /* request PHY PLL resource */
597 #define D11_PHYPLL_AVAIL_STS 0x001000000 /* PHY PLL is available */
598
599 /* tsf_cfprep register */
600 #define CFPREP_CBI_MASK 0xffffffc0
601 #define CFPREP_CBI_SHIFT 6
602 #define CFPREP_CFPP 0x00000001
603
604 /* tx fifo sizes for corerev >= 9 */
605 /* tx fifo sizes values are in terms of 256 byte blocks */
606 #define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
607 #define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
608 #define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
609
610 #define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
611 #define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
612 #define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */
613 #define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
614
615 /* phy versions, PhyVersion:Revision field */
616 #define PV_AV_MASK 0xf000 /* analog block version */
617 #define PV_AV_SHIFT 12 /* analog block version bitfield offset */
618 #define PV_PT_MASK 0x0f00 /* phy type */
619 #define PV_PT_SHIFT 8 /* phy type bitfield offset */
620 #define PV_PV_MASK 0x000f /* phy version */
621 #define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
622
623 /* phy types, PhyVersion:PhyType field */
624 #define PHY_TYPE_N 4 /* N-Phy value */
625 #define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
626 #define PHY_TYPE_LCN 8 /* LCN-Phy value */
627 #define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
628 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
629
630 /* analog types, PhyVersion:AnalogType field */
631 #define ANA_11N_013 5
632
633 /* 802.11a PLCP header def */
634 typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
635 BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
636 u8 rlpt[3]; /* rate, length, parity, tail */
637 uint16 service;
638 u8 pad;
639 } BWL_POST_PACKED_STRUCT;
640
641 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
642 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
643 #define D11A_PHY_HDR_GLENGTH(phdr) (((uint32 *)((phdr)->rlpt) >> 5) & 0x0fff)
644 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
645 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
646
647 /* rate encoded per 802.11a-1999 sec 17.3.4.1 */
648 #define D11A_PHY_HDR_SRATE(phdr, rate) \
649 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
650 /* set reserved field to zero */
651 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
652 /* length is number of octets in PSDU */
653 #define D11A_PHY_HDR_SLENGTH(phdr, length) \
654 (*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \
655 (((length) & 0x0fff) << 5))
656 /* set the tail to all zeros */
657 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
658
659 #define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
660 #define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
661
662 #define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
663
664 #define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
665 #define D11A_PHY_PRE_TIME (16)
666 #define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
667
668 /* 802.11b PLCP header def */
669 typedef struct cck_phy_hdr cck_phy_hdr_t;
670 BWL_PRE_PACKED_STRUCT struct cck_phy_hdr {
671 u8 signal;
672 u8 service;
673 uint16 length;
674 uint16 crc;
675 } BWL_POST_PACKED_STRUCT;
676
677 #define D11B_PHY_HDR_LEN 6
678
679 #define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
680
681 #define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
682 #define D11B_PHY_LPRE_TIME (144)
683 #define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
684
685 #define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
686 #define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
687 #define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
688
689 #define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
690 #define D11B_PLCP_SIGNAL_LE (1 << 7)
691
692 #define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
693 #define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
694 #define MIMO_PLCP_AMPDU 0x08 /* ampdu */
695
696 #define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
697 #define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
698 #define WLC_SET_MIMO_PLCP_LEN(plcp, len) \
699 do { \
700 plcp[1] = len & 0xff; \
701 plcp[2] = ((len >> 8) & 0xff); \
702 } while (0);
703
704 #define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
705 #define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
706 #define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
707
708 /* The dot11a PLCP header is 5 bytes. To simplify the software (so that we
709 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
710 * padding added in the ucode.
711 */
712 #define D11_PHY_HDR_LEN 6
713
714 /* TX DMA buffer header */
715 typedef struct d11txh d11txh_t;
716 BWL_PRE_PACKED_STRUCT struct d11txh {
717 uint16 MacTxControlLow; /* 0x0 */
718 uint16 MacTxControlHigh; /* 0x1 */
719 uint16 MacFrameControl; /* 0x2 */
720 uint16 TxFesTimeNormal; /* 0x3 */
721 uint16 PhyTxControlWord; /* 0x4 */
722 uint16 PhyTxControlWord_1; /* 0x5 */
723 uint16 PhyTxControlWord_1_Fbr; /* 0x6 */
724 uint16 PhyTxControlWord_1_Rts; /* 0x7 */
725 uint16 PhyTxControlWord_1_FbrRts; /* 0x8 */
726 uint16 MainRates; /* 0x9 */
727 uint16 XtraFrameTypes; /* 0xa */
728 u8 IV[16]; /* 0x0b - 0x12 */
729 u8 TxFrameRA[6]; /* 0x13 - 0x15 */
730 uint16 TxFesTimeFallback; /* 0x16 */
731 u8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
732 uint16 RTSDurFallback; /* 0x1a */
733 u8 FragPLCPFallback[6]; /* 0x1b - 1d */
734 uint16 FragDurFallback; /* 0x1e */
735 uint16 MModeLen; /* 0x1f */
736 uint16 MModeFbrLen; /* 0x20 */
737 uint16 TstampLow; /* 0x21 */
738 uint16 TstampHigh; /* 0x22 */
739 uint16 ABI_MimoAntSel; /* 0x23 */
740 uint16 PreloadSize; /* 0x24 */
741 uint16 AmpduSeqCtl; /* 0x25 */
742 uint16 TxFrameID; /* 0x26 */
743 uint16 TxStatus; /* 0x27 */
744 uint16 MaxNMpdus; /* 0x28 corerev >=16 */
745 uint16 MaxABytes_MRT; /* 0x29 corerev >=16 */
746 uint16 MaxABytes_FBR; /* 0x2a corerev >=16 */
747 uint16 MinMBytes; /* 0x2b corerev >=16 */
748 u8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
749 struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */
750 uint16 PAD; /* 0x37 */
751 } BWL_POST_PACKED_STRUCT;
752
753 #define D11_TXH_LEN 112 /* bytes */
754
755 /* Frame Types */
756 #define FT_CCK 0
757 #define FT_OFDM 1
758 #define FT_HT 2
759 #define FT_N 3
760
761 /* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
762 #define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
763 #define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
764 #define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
765 #define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
766 #define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
767
768 /* MacTxControlLow */
769 #define TXC_AMIC 0x8000
770 #define TXC_SENDCTS 0x0800
771 #define TXC_AMPDU_MASK 0x0600
772 #define TXC_BW_40 0x0100
773 #define TXC_FREQBAND_5G 0x0080
774 #define TXC_DFCS 0x0040
775 #define TXC_IGNOREPMQ 0x0020
776 #define TXC_HWSEQ 0x0010
777 #define TXC_STARTMSDU 0x0008
778 #define TXC_SENDRTS 0x0004
779 #define TXC_LONGFRAME 0x0002
780 #define TXC_IMMEDACK 0x0001
781
782 /* MacTxControlHigh */
783 #define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
784 #define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
785 #define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type
786 * 1 = SHORT for OFDM/GF for MIMO
787 * 0 = LONG for CCK/MM for MIMO
788 */
789 /* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
790 #define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */
791 #define TXC_SECKEY_MASK 0x0FF0
792 #define TXC_SECKEY_SHIFT 4
793 #define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
794 #define TXC_SECTYPE_MASK 0x0007
795 #define TXC_SECTYPE_SHIFT 0
796
797 /* Null delimiter for Fallback rate */
798 #define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
799
800 /* PhyTxControl for Mimophy */
801 #define PHY_TXC_PWR_MASK 0xFC00
802 #define PHY_TXC_PWR_SHIFT 10
803 #define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
804 #define PHY_TXC_ANT_SHIFT 6
805 #define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
806 #define PHY_TXC_LCNPHY_ANT_LAST 0x0000
807 #define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
808 #define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
809 #define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
810 #define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
811 #define PHY_TXC_SHORT_HDR 0x0010
812
813 #define PHY_TXC_OLD_ANT_0 0x0000
814 #define PHY_TXC_OLD_ANT_1 0x0100
815 #define PHY_TXC_OLD_ANT_LAST 0x0300
816
817 /* PhyTxControl_1 for Mimophy */
818 #define PHY_TXC1_BW_MASK 0x0007
819 #define PHY_TXC1_BW_10MHZ 0
820 #define PHY_TXC1_BW_10MHZ_UP 1
821 #define PHY_TXC1_BW_20MHZ 2
822 #define PHY_TXC1_BW_20MHZ_UP 3
823 #define PHY_TXC1_BW_40MHZ 4
824 #define PHY_TXC1_BW_40MHZ_DUP 5
825 #define PHY_TXC1_MODE_SHIFT 3
826 #define PHY_TXC1_MODE_MASK 0x0038
827 #define PHY_TXC1_MODE_SISO 0
828 #define PHY_TXC1_MODE_CDD 1
829 #define PHY_TXC1_MODE_STBC 2
830 #define PHY_TXC1_MODE_SDM 3
831
832 /* PhyTxControl for HTphy that are different from Mimophy */
833 #define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */
834
835 /* XtraFrameTypes */
836 #define XFTS_RTS_FT_SHIFT 2
837 #define XFTS_FBRRTS_FT_SHIFT 4
838 #define XFTS_CHANNEL_SHIFT 8
839
840 /* Antenna diversity bit in ant_wr_settle */
841 #define PHY_AWS_ANTDIV 0x2000
842
843 /* IFS ctl */
844 #define IFS_USEEDCF (1 << 2)
845
846 /* IFS ctl1 */
847 #define IFS_CTL1_EDCRS (1 << 3)
848 #define IFS_CTL1_EDCRS_20L (1 << 4)
849 #define IFS_CTL1_EDCRS_40 (1 << 5)
850
851 /* ABI_MimoAntSel */
852 #define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
853 #define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
854 #define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
855 #define ABI_MAS_FBR_ANT_PTN_SHIFT 4
856 #define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
857
858 /* tx status packet */
859 typedef struct tx_status tx_status_t;
860 BWL_PRE_PACKED_STRUCT struct tx_status {
861 uint16 framelen;
862 uint16 PAD;
863 uint16 frameid;
864 uint16 status;
865 uint16 lasttxtime;
866 uint16 sequence;
867 uint16 phyerr;
868 uint16 ackphyrxsh;
869 } BWL_POST_PACKED_STRUCT;
870
871 #define TXSTATUS_LEN 16
872
873 /* status field bit definitions */
874 #define TX_STATUS_FRM_RTX_MASK 0xF000
875 #define TX_STATUS_FRM_RTX_SHIFT 12
876 #define TX_STATUS_RTS_RTX_MASK 0x0F00
877 #define TX_STATUS_RTS_RTX_SHIFT 8
878 #define TX_STATUS_MASK 0x00FE
879 #define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
880 #define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
881 #define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
882 #define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
883 #define TX_STATUS_SUPR_SHIFT 2
884 #define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
885 #define TX_STATUS_VALID (1 << 0) /* Tx status valid (corerev >= 5) */
886 #define TX_STATUS_NO_ACK 0
887
888 /* suppress status reason codes */
889 #define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */
890 #define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */
891 #define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */
892 #define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */
893 #define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */
894 #define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */
895 #define TX_STATUS_SUPR_UF (6 << 2) /* underflow */
896
897 /* Unexpected tx status for rate update */
898 #define TX_STATUS_UNEXP(status) \
899 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
900 TX_STATUS_UNEXP_AMPDU(status))
901
902 /* Unexpected tx status for A-MPDU rate update */
903 #define TX_STATUS_UNEXP_AMPDU(status) \
904 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
905 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))
906
907 #define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
908 #define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
909 #define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
910 #define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
911
912 /* RXE (Receive Engine) */
913
914 /* RCM_CTL */
915 #define RCM_INC_MASK_H 0x0080
916 #define RCM_INC_MASK_L 0x0040
917 #define RCM_INC_DATA 0x0020
918 #define RCM_INDEX_MASK 0x001F
919 #define RCM_SIZE 15
920
921 #define RCM_MAC_OFFSET 0 /* current MAC address */
922 #define RCM_BSSID_OFFSET 3 /* current BSSID address */
923 #define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
924 #define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
925 #define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
926
927 #define RCM_WEP_TA0_OFFSET 16
928 #define RCM_WEP_TA1_OFFSET 19
929 #define RCM_WEP_TA2_OFFSET 22
930 #define RCM_WEP_TA3_OFFSET 25
931
932 /* PSM Block */
933
934 /* psm_phy_hdr_param bits */
935 #define MAC_PHY_RESET 1
936 #define MAC_PHY_CLOCK_EN 2
937 #define MAC_PHY_FORCE_CLK 4
938
939 /* WEP Block */
940
941 /* WEP_WKEY */
942 #define WKEY_START (1 << 8)
943 #define WKEY_SEL_MASK 0x1F
944
945 /* WEP data formats */
946
947 /* the number of RCMTA entries */
948 #define RCMTA_SIZE 50
949
950 #define M_ADDR_BMP_BLK (0x37e * 2)
951 #define M_ADDR_BMP_BLK_SZ 12
952
953 #define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
954 #define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
955 #define ADDR_BMP_BSSID (1 << 2) /* BSSID */
956 #define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */
957 #define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */
958 #define ADDR_BMP_RESERVED1 (1 << 5)
959 #define ADDR_BMP_RESERVED2 (1 << 6)
960 #define ADDR_BMP_RESERVED3 (1 << 7)
961 #define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
962 #define ADDR_BMP_BSS_IDX_SHIFT 8
963
964 #define WSEC_MAX_RCMTA_KEYS 54
965
966 /* max keys in M_TKMICKEYS_BLK */
967 #define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
968
969 /* max RXE match registers */
970 #define WSEC_MAX_RXE_KEYS 4
971
972 /* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
973 /* SKL (Security Key Lookup) */
974 #define SKL_ALGO_MASK 0x0007
975 #define SKL_ALGO_SHIFT 0
976 #define SKL_KEYID_MASK 0x0008
977 #define SKL_KEYID_SHIFT 3
978 #define SKL_INDEX_MASK 0x03F0
979 #define SKL_INDEX_SHIFT 4
980 #define SKL_GRP_ALGO_MASK 0x1c00
981 #define SKL_GRP_ALGO_SHIFT 10
982
983 /* additional bits defined for IBSS group key support */
984 #define SKL_IBSS_INDEX_MASK 0x01F0
985 #define SKL_IBSS_INDEX_SHIFT 4
986 #define SKL_IBSS_KEYID1_MASK 0x0600
987 #define SKL_IBSS_KEYID1_SHIFT 9
988 #define SKL_IBSS_KEYID2_MASK 0x1800
989 #define SKL_IBSS_KEYID2_SHIFT 11
990 #define SKL_IBSS_KEYALGO_MASK 0xE000
991 #define SKL_IBSS_KEYALGO_SHIFT 13
992
993 #define WSEC_MODE_OFF 0
994 #define WSEC_MODE_HW 1
995 #define WSEC_MODE_SW 2
996
997 #define WSEC_ALGO_OFF 0
998 #define WSEC_ALGO_WEP1 1
999 #define WSEC_ALGO_TKIP 2
1000 #define WSEC_ALGO_AES 3
1001 #define WSEC_ALGO_WEP128 4
1002 #define WSEC_ALGO_AES_LEGACY 5
1003 #define WSEC_ALGO_NALG 6
1004
1005 #define AES_MODE_NONE 0
1006 #define AES_MODE_CCM 1
1007
1008 /* WEP_CTL (Rev 0) */
1009 #define WECR0_KEYREG_SHIFT 0
1010 #define WECR0_KEYREG_MASK 0x7
1011 #define WECR0_DECRYPT (1 << 3)
1012 #define WECR0_IVINLINE (1 << 4)
1013 #define WECR0_WEPALG_SHIFT 5
1014 #define WECR0_WEPALG_MASK (0x7 << 5)
1015 #define WECR0_WKEYSEL_SHIFT 8
1016 #define WECR0_WKEYSEL_MASK (0x7 << 8)
1017 #define WECR0_WKEYSTART (1 << 11)
1018 #define WECR0_WEPINIT (1 << 14)
1019 #define WECR0_ICVERR (1 << 15)
1020
1021 /* Frame template map byte offsets */
1022 #define T_ACTS_TPL_BASE (0)
1023 #define T_NULL_TPL_BASE (0xc * 2)
1024 #define T_QNULL_TPL_BASE (0x1c * 2)
1025 #define T_RR_TPL_BASE (0x2c * 2)
1026 #define T_BCN0_TPL_BASE (0x34 * 2)
1027 #define T_PRS_TPL_BASE (0x134 * 2)
1028 #define T_BCN1_TPL_BASE (0x234 * 2)
1029 #define T_TX_FIFO_TXRAM_BASE (T_ACTS_TPL_BASE + (TXFIFO_START_BLK * TXFIFO_SIZE_UNIT))
1030
1031 #define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
1032
1033 #define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
1034
1035 /* Shared Mem byte offsets */
1036
1037 /* Location where the ucode expects the corerev */
1038 #define M_MACHW_VER (0x00b * 2)
1039
1040 /* Location where the ucode expects the MAC capabilities */
1041 #define M_MACHW_CAP_L (0x060 * 2)
1042 #define M_MACHW_CAP_H (0x061 * 2)
1043
1044 /* WME shared memory */
1045 #define M_EDCF_STATUS_OFF (0x007 * 2)
1046 #define M_TXF_CUR_INDEX (0x018 * 2)
1047 #define M_EDCF_QINFO (0x120 * 2)
1048
1049 /* PS-mode related parameters */
1050 #define M_DOT11_SLOT (0x008 * 2)
1051 #define M_DOT11_DTIMPERIOD (0x009 * 2)
1052 #define M_NOSLPZNATDTIM (0x026 * 2)
1053
1054 /* Beacon-related parameters */
1055 #define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1056 #define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1057 #define M_BCN_TXTSF_OFFSET (0x00e * 2)
1058 #define M_TIMBPOS_INBEACON (0x00f * 2)
1059 #define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1060 #define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1061 #define M_BCN_PCTLWD (0x02a * 2)
1062 #define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1063
1064 /* MAX Rx Frame len */
1065 #define M_MAXRXFRM_LEN (0x010 * 2)
1066
1067 /* ACK/CTS related params */
1068 #define M_RSP_PCTLWD (0x011 * 2)
1069
1070 /* Hardware Power Control */
1071 #define M_TXPWR_N (0x012 * 2)
1072 #define M_TXPWR_TARGET (0x013 * 2)
1073 #define M_TXPWR_MAX (0x014 * 2)
1074 #define M_TXPWR_CUR (0x019 * 2)
1075
1076 /* Rx-related parameters */
1077 #define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1078
1079 /* WEP Shared mem data */
1080 #define M_SEC_DEFIVLOC (0x01e * 2)
1081 #define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1082 #define M_PHYVER (0x028 * 2)
1083 #define M_PHYTYPE (0x029 * 2)
1084 #define M_SECRXKEYS_PTR (0x02b * 2)
1085 #define M_TKMICKEYS_PTR (0x059 * 2)
1086 #define M_SECKINDXALGO_BLK (0x2ea * 2)
1087 #define M_SECKINDXALGO_BLK_SZ 54
1088 #define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1089 #define M_TKIP_TSC_TTAK (0x18c * 2)
1090 #define D11_MAX_KEY_SIZE 16
1091
1092 #define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1093
1094 /* Probe response related parameters */
1095 #define M_SSIDLEN (0x024 * 2)
1096 #define M_PRB_RESP_FRM_LEN (0x025 * 2)
1097 #define M_PRS_MAXTIME (0x03a * 2)
1098 #define M_SSID (0xb0 * 2)
1099 #define M_CTXPRS_BLK (0xc0 * 2)
1100 #define C_CTX_PCTLWD_POS (0x4 * 2)
1101
1102 /* Delta between OFDM and CCK power in CCK power boost mode */
1103 #define M_OFDM_OFFSET (0x027 * 2)
1104
1105 /* TSSI for last 4 11b/g CCK packets transmitted */
1106 #define M_B_TSSI_0 (0x02c * 2)
1107 #define M_B_TSSI_1 (0x02d * 2)
1108
1109 /* Host flags to turn on ucode options */
1110 #define M_HOST_FLAGS1 (0x02f * 2)
1111 #define M_HOST_FLAGS2 (0x030 * 2)
1112 #define M_HOST_FLAGS3 (0x031 * 2)
1113 #define M_HOST_FLAGS4 (0x03c * 2)
1114 #define M_HOST_FLAGS5 (0x06a * 2)
1115 #define M_HOST_FLAGS_SZ 16
1116
1117 #define M_RADAR_REG (0x033 * 2)
1118
1119 /* TSSI for last 4 11a OFDM packets transmitted */
1120 #define M_A_TSSI_0 (0x034 * 2)
1121 #define M_A_TSSI_1 (0x035 * 2)
1122
1123 /* noise interference measurement */
1124 #define M_NOISE_IF_COUNT (0x034 * 2)
1125 #define M_NOISE_IF_TIMEOUT (0x035 * 2)
1126
1127 #define M_RF_RX_SP_REG1 (0x036 * 2)
1128
1129 /* TSSI for last 4 11g OFDM packets transmitted */
1130 #define M_G_TSSI_0 (0x038 * 2)
1131 #define M_G_TSSI_1 (0x039 * 2)
1132
1133 /* Background noise measure */
1134 #define M_JSSI_0 (0x44 * 2)
1135 #define M_JSSI_1 (0x45 * 2)
1136 #define M_JSSI_AUX (0x46 * 2)
1137
1138 #define M_CUR_2050_RADIOCODE (0x47 * 2)
1139
1140 /* TX fifo sizes */
1141 #define M_FIFOSIZE0 (0x4c * 2)
1142 #define M_FIFOSIZE1 (0x4d * 2)
1143 #define M_FIFOSIZE2 (0x4e * 2)
1144 #define M_FIFOSIZE3 (0x4f * 2)
1145 #define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
1146
1147 /* Current channel number plus upper bits */
1148 #define M_CURCHANNEL (0x50 * 2)
1149 #define D11_CURCHANNEL_5G 0x0100;
1150 #define D11_CURCHANNEL_40 0x0200;
1151 #define D11_CURCHANNEL_MAX 0x00FF;
1152
1153 /* last posted frameid on the bcmc fifo */
1154 #define M_BCMC_FID (0x54 * 2)
1155 #define INVALIDFID 0xffff
1156
1157 /* extended beacon phyctl bytes for 11N */
1158 #define M_BCN_PCTL1WD (0x058 * 2)
1159
1160 /* idle busy ratio to duty_cycle requirement */
1161 #define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1162 #define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1163
1164 /* CW RSSI for LCNPHY */
1165 #define M_LCN_RSSI_0 0x1332
1166 #define M_LCN_RSSI_1 0x1338
1167 #define M_LCN_RSSI_2 0x133e
1168 #define M_LCN_RSSI_3 0x1344
1169
1170 /* SNR for LCNPHY */
1171 #define M_LCN_SNR_A_0 0x1334
1172 #define M_LCN_SNR_B_0 0x1336
1173
1174 #define M_LCN_SNR_A_1 0x133a
1175 #define M_LCN_SNR_B_1 0x133c
1176
1177 #define M_LCN_SNR_A_2 0x1340
1178 #define M_LCN_SNR_B_2 0x1342
1179
1180 #define M_LCN_SNR_A_3 0x1346
1181 #define M_LCN_SNR_B_3 0x1348
1182
1183 #define M_LCN_LAST_RESET (81*2)
1184 #define M_LCN_LAST_LOC (63*2)
1185 #define M_LCNPHY_RESET_STATUS (4902)
1186 #define M_LCNPHY_DSC_TIME (0x98d*2)
1187 #define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1188 #define M_LCNPHY_RESET_CNT (0x98c*2)
1189
1190 /* Rate table offsets */
1191 #define M_RT_DIRMAP_A (0xe0 * 2)
1192 #define M_RT_BBRSMAP_A (0xf0 * 2)
1193 #define M_RT_DIRMAP_B (0x100 * 2)
1194 #define M_RT_BBRSMAP_B (0x110 * 2)
1195
1196 /* Rate table entry offsets */
1197 #define M_RT_PRS_PLCP_POS 10
1198 #define M_RT_PRS_DUR_POS 16
1199 #define M_RT_OFDM_PCTL1_POS 18
1200
1201 #define M_20IN40_IQ (0x380 * 2)
1202
1203 /* SHM locations where ucode stores the current power index */
1204 #define M_CURR_IDX1 (0x384 * 2)
1205 #define M_CURR_IDX2 (0x387 * 2)
1206
1207 #define M_BSCALE_ANT0 (0x5e * 2)
1208 #define M_BSCALE_ANT1 (0x5f * 2)
1209
1210 /* Antenna Diversity Testing */
1211 #define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1212 #define M_ANTSEL_CLKDIV (0x61 * 2)
1213 #define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1214
1215 #define M_MIMO_MAXSYM (0x5d * 2)
1216 #define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1217 #define MIMO_MAXSYM_MAX 0xffff /* 64k */
1218
1219 #define M_WATCHDOG_8TU (0x1e * 2)
1220 #define WATCHDOG_8TU_DEF 5
1221 #define WATCHDOG_8TU_MAX 10
1222
1223 /* Manufacturing Test Variables */
1224 #define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */
1225 #define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */
1226 #define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */
1227 #define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */
1228
1229 /* Index variation in vbat ripple */
1230 #define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1231 #define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1232
1233 /* M_PKTENG_CTRL bit definitions */
1234 #define M_PKTENG_MODE_TX 0x0001
1235 #define M_PKTENG_MODE_TX_RIFS 0x0004
1236 #define M_PKTENG_MODE_TX_CTS 0x0008
1237 #define M_PKTENG_MODE_RX 0x0002
1238 #define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1239 #define M_PKTENG_MODE_MASK 0x0003
1240 #define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */
1241
1242 /* Sample Collect parameters (bitmap and type) */
1243 #define M_SMPL_COL_BMP (0x37d * 2) /* Trigger bitmap for sample collect */
1244 #define M_SMPL_COL_CTL (0x3b2 * 2) /* Sample collect type */
1245
1246 #define ANTSEL_CLKDIV_4MHZ 6
1247 #define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1248 #define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1249 #define MIMO_ANTSEL_WAIT 50 /* 50us wait */
1250 #define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1251
1252 typedef struct shm_acparams shm_acparams_t;
1253 BWL_PRE_PACKED_STRUCT struct shm_acparams {
1254 uint16 txop;
1255 uint16 cwmin;
1256 uint16 cwmax;
1257 uint16 cwcur;
1258 uint16 aifs;
1259 uint16 bslots;
1260 uint16 reggap;
1261 uint16 status;
1262 uint16 rsvd[8];
1263 } BWL_POST_PACKED_STRUCT;
1264 #define M_EDCF_QLEN (16 * 2)
1265
1266 #define WME_STATUS_NEWAC (1 << 8)
1267
1268 /* M_HOST_FLAGS */
1269 #define MHFMAX 5 /* Number of valid hostflag half-word (uint16) */
1270 #define MHF1 0 /* Hostflag 1 index */
1271 #define MHF2 1 /* Hostflag 2 index */
1272 #define MHF3 2 /* Hostflag 3 index */
1273 #define MHF4 3 /* Hostflag 4 index */
1274 #define MHF5 4 /* Hostflag 5 index */
1275
1276 /* Flags in M_HOST_FLAGS */
1277 #define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */
1278 #define MHF1_EDCF 0x0100 /* Enable EDCF access control */
1279 #define MHF1_IQSWAP_WAR 0x0200
1280 #define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */
1281
1282 /* Flags in M_HOST_FLAGS2 */
1283 #define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */
1284 #define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */
1285 #define MHF2_HWPWRCTL 0x0080 /* Enable ucode/hw power control */
1286 #define MHF2_NPHY40MHZ_WAR 0x0800
1287
1288 /* Flags in M_HOST_FLAGS3 */
1289 #define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */
1290 #define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */
1291 #define MHF3_RESERVED1 0x0004
1292 #define MHF3_RESERVED2 0x0008
1293 #define MHF3_NPHY_MLADV_WAR 0x0010
1294
1295 /* Flags in M_HOST_FLAGS4 */
1296 #define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
1297 #define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
1298
1299 /* Flags in M_HOST_FLAGS5 */
1300 #define MHF5_4313_GPIOCTRL 0x0001
1301 #define MHF5_RESERVED1 0x0002
1302 #define MHF5_RESERVED2 0x0004
1303 /* Radio power setting for ucode */
1304 #define M_RADIO_PWR (0x32 * 2)
1305
1306 /* phy noise recorded by ucode right after tx */
1307 #define M_PHY_NOISE (0x037 * 2)
1308 #define PHY_NOISE_MASK 0x00ff
1309
1310 /* Receive Frame Data Header for 802.11b DCF-only frames */
1311 typedef struct d11rxhdr d11rxhdr_t;
1312 BWL_PRE_PACKED_STRUCT struct d11rxhdr {
1313 uint16 RxFrameSize; /* Actual byte length of the frame data received */
1314 uint16 PAD;
1315 uint16 PhyRxStatus_0; /* PhyRxStatus 15:0 */
1316 uint16 PhyRxStatus_1; /* PhyRxStatus 31:16 */
1317 uint16 PhyRxStatus_2; /* PhyRxStatus 47:32 */
1318 uint16 PhyRxStatus_3; /* PhyRxStatus 63:48 */
1319 uint16 PhyRxStatus_4; /* PhyRxStatus 79:64 */
1320 uint16 PhyRxStatus_5; /* PhyRxStatus 95:80 */
1321 uint16 RxStatus1; /* MAC Rx Status */
1322 uint16 RxStatus2; /* extended MAC Rx status */
1323 uint16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
1324 uint16 RxChan; /* gain code, channel radio code, and phy type */
1325 } BWL_POST_PACKED_STRUCT;
1326
1327 #define RXHDR_LEN 24 /* sizeof d11rxhdr_t */
1328 #define FRAMELEN(h) ((h)->RxFrameSize)
1329
1330 typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
1331 BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr {
1332 d11rxhdr_t rxhdr;
1333 uint32 tsf_l; /* TSF_L reading */
1334 s8 rssi; /* computed instanteneous rssi in BMAC */
1335 s8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1336 s8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1337 s8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */
1338 s8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */
1339 } BWL_POST_PACKED_STRUCT;
1340
1341 /* PhyRxStatus_0: */
1342 #define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */
1343 #define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */
1344 #define PRXS0_CLIP_SHIFT 2
1345 #define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
1346 #define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */
1347 #define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
1348 #define PRXS0_SHORTH 0x0080 /* Short Preamble */
1349 #define PRXS0_PLCPFV 0x0100 /* PLCP violation */
1350 #define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */
1351 #define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */
1352 #define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */
1353 #define PRXS0_ANTSEL_SHIFT 0x12
1354
1355 /* subfield PRXS0_FT_MASK */
1356 #define PRXS0_CCK 0x0000
1357 #define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */
1358 #define PRXS0_PREN 0x0002
1359 #define PRXS0_STDN 0x0003
1360
1361 /* subfield PRXS0_ANTSEL_MASK */
1362 #define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1363 #define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1364 #define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1365 #define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1366
1367 /* PhyRxStatus_1: */
1368 #define PRXS1_JSSI_MASK 0x00FF
1369 #define PRXS1_JSSI_SHIFT 0
1370 #define PRXS1_SQ_MASK 0xFF00
1371 #define PRXS1_SQ_SHIFT 8
1372
1373 /* nphy PhyRxStatus_1: */
1374 #define PRXS1_nphy_PWR0_MASK 0x00FF
1375 #define PRXS1_nphy_PWR1_MASK 0xFF00
1376
1377 /* HTPHY Rx Status defines */
1378 /* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
1379 #define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1380 #define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1381 #define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1382
1383 /* htphy PhyRxStatus_1: */
1384 #define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */
1385 #define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */
1386 #define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */
1387
1388 /* htphy PhyRxStatus_2: */
1389 #define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */
1390 #define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */
1391 #define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */
1392
1393 /* htphy PhyRxStatus_3: */
1394 #define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
1395 #define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
1396
1397 /* htphy PhyRxStatus_4: */
1398 #define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
1399 #define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */
1400
1401 /* htphy PhyRxStatus_5: */
1402 #define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */
1403 #define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */
1404
1405 #define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1406 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1407 /* Get Rx power on core 0 */
1408 #define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1409 /* Get Rx power on core 1 */
1410 #define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1411 /* Get Rx power on core 2 */
1412 #define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1413
1414 /* ucode RxStatus1: */
1415 #define RXS_BCNSENT 0x8000
1416 #define RXS_SECKINDX_MASK 0x07e0
1417 #define RXS_SECKINDX_SHIFT 5
1418 #define RXS_DECERR (1 << 4)
1419 #define RXS_DECATMPT (1 << 3)
1420 #define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */
1421 #define RXS_RESPFRAMETX (1 << 1)
1422 #define RXS_FCSERR (1 << 0)
1423
1424 /* ucode RxStatus2: */
1425 #define RXS_AMSDU_MASK 1
1426 #define RXS_AGGTYPE_MASK 0x6
1427 #define RXS_AGGTYPE_SHIFT 1
1428 #define RXS_PHYRXST_VALID (1 << 8)
1429 #define RXS_RXANT_MASK 0x3
1430 #define RXS_RXANT_SHIFT 12
1431
1432 /* RxChan */
1433 #define RXS_CHAN_40 0x1000
1434 #define RXS_CHAN_5G 0x0800
1435 #define RXS_CHAN_ID_MASK 0x07f8
1436 #define RXS_CHAN_ID_SHIFT 3
1437 #define RXS_CHAN_PHYTYPE_MASK 0x0007
1438 #define RXS_CHAN_PHYTYPE_SHIFT 0
1439
1440 /* Index of attenuations used during ucode power control. */
1441 #define M_PWRIND_BLKS (0x184 * 2)
1442 #define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1443 #define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1444 #define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1445 #define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1446 /* M_PWRIND_MAP(core) macro */
1447 #define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
1448
1449 /* PSM SHM variable offsets */
1450 #define M_PSM_SOFT_REGS 0x0
1451 #define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1452 #define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1453 #define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1454 #define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1455
1456 #define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1457 #define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1458 #define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1459 #define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1460 #define M_PRETBTT (0x4b * 2)
1461
1462 #define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */
1463 #define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1464 #define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1465 #define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1466
1467 /* PKTENG Rx Stats Block */
1468 #define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1469
1470 /* ucode debug status codes */
1471 #define DBGST_INACTIVE 0 /* not valid really */
1472 #define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */
1473 #define DBGST_ACTIVE 2 /* "normal" state */
1474 #define DBGST_SUSPENDED 3 /* suspended */
1475 #define DBGST_ASLEEP 4 /* asleep (PS mode) */
1476
1477 /* Scratch Reg defs */
1478 typedef enum {
1479 S_RSV0 = 0,
1480 S_RSV1,
1481 S_RSV2,
1482
1483 /* scratch registers for Dot11-contants */
1484 S_DOT11_CWMIN, /* CW-minimum 0x03 */
1485 S_DOT11_CWMAX, /* CW-maximum 0x04 */
1486 S_DOT11_CWCUR, /* CW-current 0x05 */
1487 S_DOT11_SRC_LMT, /* short retry count limit 0x06 */
1488 S_DOT11_LRC_LMT, /* long retry count limit 0x07 */
1489 S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */
1490
1491 /* Tx-side scratch registers */
1492 S_SEQ_NUM, /* hardware sequence number reg 0x09 */
1493 S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */
1494 S_FRMRETX_CNT, /* frame retx count 0x0B */
1495 S_SSRC, /* Station short retry count 0x0C */
1496 S_SLRC, /* Station long retry count 0x0D */
1497 S_EXP_RSP, /* Expected response frame 0x0E */
1498 S_OLD_BREM, /* Remaining backoff ctr 0x0F */
1499 S_OLD_CWWIN, /* saved-off CW-cur 0x10 */
1500 S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */
1501 S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */
1502
1503 /* Rx-side scratch registers */
1504 S_RXTST, /* Type and subtype in Rxframe 0x13 */
1505
1506 /* Global state register */
1507 S_STREG, /* state storage actual bit maps below 0x14 */
1508
1509 S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */
1510 S_TXPWR_ITER, /* Tx power control: iteration 0x16 */
1511 S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */
1512 S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */
1513
1514 S_KEYINDX, /* 0x19 */
1515 S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */
1516
1517 /* Receive TSF time stored in SCR */
1518 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */
1519 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */
1520 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */
1521 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */
1522 S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */
1523 S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */
1524
1525 /* Scratch pad regs used in microcode as temp storage */
1526 S_TMP0, /* stmp0 0x21 */
1527 S_TMP1, /* stmp1 0x22 */
1528 S_TMP2, /* stmp2 0x23 */
1529 S_TMP3, /* stmp3 0x24 */
1530 S_TMP4, /* stmp4 0x25 */
1531 S_TMP5, /* stmp5 0x26 */
1532 S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */
1533 S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */
1534 S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */
1535 S_RXTP, /* rx frame type 0x2A */
1536 S_STREG2, /* extra state storage 0x2B */
1537 S_STREG3, /* even more extra state storage 0x2C */
1538 S_STREG4, /* ... 0x2D */
1539 S_STREG5, /* remember to initialize it to zero 0x2E */
1540
1541 S_ADJPWR_IDX,
1542 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */
1543 S_REVID4, /* 0x33 */
1544 S_INDX, /* 0x34 */
1545 S_ADDR0, /* 0x35 */
1546 S_ADDR1, /* 0x36 */
1547 S_ADDR2, /* 0x37 */
1548 S_ADDR3, /* 0x38 */
1549 S_ADDR4, /* 0x39 */
1550 S_ADDR5, /* 0x3A */
1551 S_TMP6, /* 0x3B */
1552 S_KEYINDX_BU, /* Backup for Key index 0x3C */
1553 S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */
1554 S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */
1555 S_STREG6, /* 0x3F */
1556 } ePsmScratchPadRegDefinitions;
1557
1558 #define S_BEACON_INDX S_OLD_BREM
1559 #define S_PRS_INDX S_OLD_CWWIN
1560 #define S_PHYTYPE S_SSRC
1561 #define S_PHYVER S_SLRC
1562
1563 /* IHR SLOW_CTRL values */
1564 #define SLOW_CTRL_PDE (1 << 0)
1565 #define SLOW_CTRL_FD (1 << 8)
1566
1567 /* ucode mac statistic counters in shared memory */
1568 typedef struct macstat {
1569 uint16 txallfrm; /* 0x80 */
1570 uint16 txrtsfrm; /* 0x82 */
1571 uint16 txctsfrm; /* 0x84 */
1572 uint16 txackfrm; /* 0x86 */
1573 uint16 txdnlfrm; /* 0x88 */
1574 uint16 txbcnfrm; /* 0x8a */
1575 uint16 txfunfl[8]; /* 0x8c - 0x9b */
1576 uint16 txtplunfl; /* 0x9c */
1577 uint16 txphyerr; /* 0x9e */
1578 uint16 pktengrxducast; /* 0xa0 */
1579 uint16 pktengrxdmcast; /* 0xa2 */
1580 uint16 rxfrmtoolong; /* 0xa4 */
1581 uint16 rxfrmtooshrt; /* 0xa6 */
1582 uint16 rxinvmachdr; /* 0xa8 */
1583 uint16 rxbadfcs; /* 0xaa */
1584 uint16 rxbadplcp; /* 0xac */
1585 uint16 rxcrsglitch; /* 0xae */
1586 uint16 rxstrt; /* 0xb0 */
1587 uint16 rxdfrmucastmbss; /* 0xb2 */
1588 uint16 rxmfrmucastmbss; /* 0xb4 */
1589 uint16 rxcfrmucast; /* 0xb6 */
1590 uint16 rxrtsucast; /* 0xb8 */
1591 uint16 rxctsucast; /* 0xba */
1592 uint16 rxackucast; /* 0xbc */
1593 uint16 rxdfrmocast; /* 0xbe */
1594 uint16 rxmfrmocast; /* 0xc0 */
1595 uint16 rxcfrmocast; /* 0xc2 */
1596 uint16 rxrtsocast; /* 0xc4 */
1597 uint16 rxctsocast; /* 0xc6 */
1598 uint16 rxdfrmmcast; /* 0xc8 */
1599 uint16 rxmfrmmcast; /* 0xca */
1600 uint16 rxcfrmmcast; /* 0xcc */
1601 uint16 rxbeaconmbss; /* 0xce */
1602 uint16 rxdfrmucastobss; /* 0xd0 */
1603 uint16 rxbeaconobss; /* 0xd2 */
1604 uint16 rxrsptmout; /* 0xd4 */
1605 uint16 bcntxcancl; /* 0xd6 */
1606 uint16 PAD;
1607 uint16 rxf0ovfl; /* 0xda */
1608 uint16 rxf1ovfl; /* 0xdc */
1609 uint16 rxf2ovfl; /* 0xde */
1610 uint16 txsfovfl; /* 0xe0 */
1611 uint16 pmqovfl; /* 0xe2 */
1612 uint16 rxcgprqfrm; /* 0xe4 */
1613 uint16 rxcgprsqovfl; /* 0xe6 */
1614 uint16 txcgprsfail; /* 0xe8 */
1615 uint16 txcgprssuc; /* 0xea */
1616 uint16 prs_timeout; /* 0xec */
1617 uint16 rxnack;
1618 uint16 frmscons;
1619 uint16 txnack;
1620 uint16 txglitch_nack;
1621 uint16 txburst; /* 0xf6 # tx bursts */
1622 uint16 bphy_rxcrsglitch; /* bphy rx crs glitch */
1623 uint16 phywatchdog; /* 0xfa # of phy watchdog events */
1624 uint16 PAD;
1625 uint16 bphy_badplcp; /* bphy bad plcp */
1626 } macstat_t;
1627
1628 /* dot11 core-specific control flags */
1629 #define SICF_PCLKE 0x0004 /* PHY clock enable */
1630 #define SICF_PRST 0x0008 /* PHY reset */
1631 #define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
1632 #define SICF_FREF 0x0020 /* PLL FreqRefSelect (corerev >= 5) */
1633 /* NOTE: the following bw bits only apply when the core is attached
1634 * to a NPHY (and corerev >= 11 which it will always be for NPHYs).
1635 */
1636 #define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
1637 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
1638 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
1639 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
1640 #define SICF_GMODE 0x2000 /* gmode enable */
1641
1642 /* dot11 core-specific status flags */
1643 #define SISF_2G_PHY 0x0001 /* 2.4G capable phy (corerev >= 5) */
1644 #define SISF_5G_PHY 0x0002 /* 5G capable phy (corerev >= 5) */
1645 #define SISF_FCLKA 0x0004 /* FastClkAvailable (corerev >= 5) */
1646 #define SISF_DB_PHY 0x0008 /* Dualband phy (corerev >= 11) */
1647
1648 /* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
1649
1650 #define BPHY_REG_OFT_BASE 0x0
1651 /* offsets for indirect access to bphy registers */
1652 #define BPHY_BB_CONFIG 0x01
1653 #define BPHY_ADCBIAS 0x02
1654 #define BPHY_ANACORE 0x03
1655 #define BPHY_PHYCRSTH 0x06
1656 #define BPHY_TEST 0x0a
1657 #define BPHY_PA_TX_TO 0x10
1658 #define BPHY_SYNTH_DC_TO 0x11
1659 #define BPHY_PA_TX_TIME_UP 0x12
1660 #define BPHY_RX_FLTR_TIME_UP 0x13
1661 #define BPHY_TX_POWER_OVERRIDE 0x14
1662 #define BPHY_RF_OVERRIDE 0x15
1663 #define BPHY_RF_TR_LOOKUP1 0x16
1664 #define BPHY_RF_TR_LOOKUP2 0x17
1665 #define BPHY_COEFFS 0x18
1666 #define BPHY_PLL_OUT 0x19
1667 #define BPHY_REFRESH_MAIN 0x1a
1668 #define BPHY_REFRESH_TO0 0x1b
1669 #define BPHY_REFRESH_TO1 0x1c
1670 #define BPHY_RSSI_TRESH 0x20
1671 #define BPHY_IQ_TRESH_HH 0x21
1672 #define BPHY_IQ_TRESH_H 0x22
1673 #define BPHY_IQ_TRESH_L 0x23
1674 #define BPHY_IQ_TRESH_LL 0x24
1675 #define BPHY_GAIN 0x25
1676 #define BPHY_LNA_GAIN_RANGE 0x26
1677 #define BPHY_JSSI 0x27
1678 #define BPHY_TSSI_CTL 0x28
1679 #define BPHY_TSSI 0x29
1680 #define BPHY_TR_LOSS_CTL 0x2a
1681 #define BPHY_LO_LEAKAGE 0x2b
1682 #define BPHY_LO_RSSI_ACC 0x2c
1683 #define BPHY_LO_IQMAG_ACC 0x2d
1684 #define BPHY_TX_DC_OFF1 0x2e
1685 #define BPHY_TX_DC_OFF2 0x2f
1686 #define BPHY_PEAK_CNT_THRESH 0x30
1687 #define BPHY_FREQ_OFFSET 0x31
1688 #define BPHY_DIVERSITY_CTL 0x32
1689 #define BPHY_PEAK_ENERGY_LO 0x33
1690 #define BPHY_PEAK_ENERGY_HI 0x34
1691 #define BPHY_SYNC_CTL 0x35
1692 #define BPHY_TX_PWR_CTRL 0x36
1693 #define BPHY_TX_EST_PWR 0x37
1694 #define BPHY_STEP 0x38
1695 #define BPHY_WARMUP 0x39
1696 #define BPHY_LMS_CFF_READ 0x3a
1697 #define BPHY_LMS_COEFF_I 0x3b
1698 #define BPHY_LMS_COEFF_Q 0x3c
1699 #define BPHY_SIG_POW 0x3d
1700 #define BPHY_RFDC_CANCEL_CTL 0x3e
1701 #define BPHY_HDR_TYPE 0x40
1702 #define BPHY_SFD_TO 0x41
1703 #define BPHY_SFD_CTL 0x42
1704 #define BPHY_DEBUG 0x43
1705 #define BPHY_RX_DELAY_COMP 0x44
1706 #define BPHY_CRS_DROP_TO 0x45
1707 #define BPHY_SHORT_SFD_NZEROS 0x46
1708 #define BPHY_DSSS_COEFF1 0x48
1709 #define BPHY_DSSS_COEFF2 0x49
1710 #define BPHY_CCK_COEFF1 0x4a
1711 #define BPHY_CCK_COEFF2 0x4b
1712 #define BPHY_TR_CORR 0x4c
1713 #define BPHY_ANGLE_SCALE 0x4d
1714 #define BPHY_TX_PWR_BASE_IDX 0x4e
1715 #define BPHY_OPTIONAL_MODES2 0x4f
1716 #define BPHY_CCK_LMS_STEP 0x50
1717 #define BPHY_BYPASS 0x51
1718 #define BPHY_CCK_DELAY_LONG 0x52
1719 #define BPHY_CCK_DELAY_SHORT 0x53
1720 #define BPHY_PPROC_CHAN_DELAY 0x54
1721 #define BPHY_DDFS_ENABLE 0x58
1722 #define BPHY_PHASE_SCALE 0x59
1723 #define BPHY_FREQ_CONTROL 0x5a
1724 #define BPHY_LNA_GAIN_RANGE_10 0x5b
1725 #define BPHY_LNA_GAIN_RANGE_32 0x5c
1726 #define BPHY_OPTIONAL_MODES 0x5d
1727 #define BPHY_RX_STATUS2 0x5e
1728 #define BPHY_RX_STATUS3 0x5f
1729 #define BPHY_DAC_CONTROL 0x60
1730 #define BPHY_ANA11G_FILT_CTRL 0x62
1731 #define BPHY_REFRESH_CTRL 0x64
1732 #define BPHY_RF_OVERRIDE2 0x65
1733 #define BPHY_SPUR_CANCEL_CTRL 0x66
1734 #define BPHY_FINE_DIGIGAIN_CTRL 0x67
1735 #define BPHY_RSSI_LUT 0x88
1736 #define BPHY_RSSI_LUT_END 0xa7
1737 #define BPHY_TSSI_LUT 0xa8
1738 #define BPHY_TSSI_LUT_END 0xc7
1739 #define BPHY_TSSI2PWR_LUT 0x380
1740 #define BPHY_TSSI2PWR_LUT_END 0x39f
1741 #define BPHY_LOCOMP_LUT 0x3a0
1742 #define BPHY_LOCOMP_LUT_END 0x3bf
1743 #define BPHY_TXGAIN_LUT 0x3c0
1744 #define BPHY_TXGAIN_LUT_END 0x3ff
1745
1746 /* Bits in BB_CONFIG: */
1747 #define PHY_BBC_ANT_MASK 0x0180
1748 #define PHY_BBC_ANT_SHIFT 7
1749 #define BB_DARWIN 0x1000
1750 #define BBCFG_RESETCCA 0x4000
1751 #define BBCFG_RESETRX 0x8000
1752
1753 /* Bits in phytest(0x0a): */
1754 #define TST_DDFS 0x2000
1755 #define TST_TXFILT1 0x0800
1756 #define TST_UNSCRAM 0x0400
1757 #define TST_CARR_SUPP 0x0200
1758 #define TST_DC_COMP_LOOP 0x0100
1759 #define TST_LOOPBACK 0x0080
1760 #define TST_TXFILT0 0x0040
1761 #define TST_TXTEST_ENABLE 0x0020
1762 #define TST_TXTEST_RATE 0x0018
1763 #define TST_TXTEST_PHASE 0x0007
1764
1765 /* phytest txTestRate values */
1766 #define TST_TXTEST_RATE_1MBPS 0
1767 #define TST_TXTEST_RATE_2MBPS 1
1768 #define TST_TXTEST_RATE_5_5MBPS 2
1769 #define TST_TXTEST_RATE_11MBPS 3
1770 #define TST_TXTEST_RATE_SHIFT 3
1771
1772 /* This marks the end of a packed structure section. */
1773 #include <packed_section_end.h>
1774
1775 #define SHM_BYT_CNT 0x2 /* IHR location */
1776 #define MAX_BYT_CNT 0x600 /* Maximum frame len */
1777
1778 #endif /* _D11_H */
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