include/asm-s390/system.h

   1 /*
   2  *  include/asm-s390/system.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
   7  *
   8  *  Derived from "include/asm-i386/system.h"
   9  */
  10
  11 #ifndef __ASM_SYSTEM_H
  12 #define __ASM_SYSTEM_H
  13
  14 #include <linux/config.h>
  15 #include <linux/kernel.h>
  16 #include <asm/types.h>
  17 #include <asm/ptrace.h>
  18 #include <asm/setup.h>
  19 #include <asm/processor.h>
  20
  21 #ifdef __KERNEL__
  22
  23 struct task_struct;
  24
  25 extern struct task_struct *__switch_to(void *, void *);
  26
  27 #ifdef __s390x__
  28 #define __FLAG_SHIFT 56
  29 #else /* ! __s390x__ */
  30 #define __FLAG_SHIFT 24
  31 #endif /* ! __s390x__ */
  32
  33 static inline void save_fp_regs(s390_fp_regs *fpregs)
  34 {
  35         asm volatile (
  36                 "   std   0,8(%1)\n"
  37                 "   std   2,24(%1)\n"
  38                 "   std   4,40(%1)\n"
  39                 "   std   6,56(%1)"
  40                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
  41         if (!MACHINE_HAS_IEEE)
  42                 return;
  43         asm volatile(
  44                 "   stfpc 0(%1)\n"
  45                 "   std   1,16(%1)\n"
  46                 "   std   3,32(%1)\n"
  47                 "   std   5,48(%1)\n"
  48                 "   std   7,64(%1)\n"
  49                 "   std   8,72(%1)\n"
  50                 "   std   9,80(%1)\n"
  51                 "   std   10,88(%1)\n"
  52                 "   std   11,96(%1)\n"
  53                 "   std   12,104(%1)\n"
  54                 "   std   13,112(%1)\n"
  55                 "   std   14,120(%1)\n"
  56                 "   std   15,128(%1)\n"
  57                 : "=m" (*fpregs) : "a" (fpregs), "m" (*fpregs) : "memory" );
  58 }
  59
  60 static inline void restore_fp_regs(s390_fp_regs *fpregs)
  61 {
  62         asm volatile (
  63                 "   ld    0,8(%0)\n"
  64                 "   ld    2,24(%0)\n"
  65                 "   ld    4,40(%0)\n"
  66                 "   ld    6,56(%0)"
  67                 : : "a" (fpregs), "m" (*fpregs) );
  68         if (!MACHINE_HAS_IEEE)
  69                 return;
  70         asm volatile(
  71                 "   lfpc  0(%0)\n"
  72                 "   ld    1,16(%0)\n"
  73                 "   ld    3,32(%0)\n"
  74                 "   ld    5,48(%0)\n"
  75                 "   ld    7,64(%0)\n"
  76                 "   ld    8,72(%0)\n"
  77                 "   ld    9,80(%0)\n"
  78                 "   ld    10,88(%0)\n"
  79                 "   ld    11,96(%0)\n"
  80                 "   ld    12,104(%0)\n"
  81                 "   ld    13,112(%0)\n"
  82                 "   ld    14,120(%0)\n"
  83                 "   ld    15,128(%0)\n"
  84                 : : "a" (fpregs), "m" (*fpregs) );
  85 }
  86
  87 static inline void save_access_regs(unsigned int *acrs)
  88 {
  89         asm volatile ("stam 0,15,0(%0)" : : "a" (acrs) : "memory" );
  90 }
  91
  92 static inline void restore_access_regs(unsigned int *acrs)
  93 {
  94         asm volatile ("lam 0,15,0(%0)" : : "a" (acrs) );
  95 }
  96
  97 #define switch_to(prev,next,last) do {                                       \
  98         if (prev == next)                                                    \
  99                 break;                                                       \
 100         save_fp_regs(&prev->thread.fp_regs);                                 \
 101         restore_fp_regs(&next->thread.fp_regs);                              \
 102         save_access_regs(&prev->thread.acrs[0]);                             \
 103         restore_access_regs(&next->thread.acrs[0]);                          \
 104         prev = __switch_to(prev,next);                                       \
 105 } while (0)
 106
 107 /*
 108  * On SMP systems, when the scheduler does migration-cost autodetection,
 109  * it needs a way to flush as much of the CPU's caches as possible.
 110  *
 111  * TODO: fill this in!
 112  */
 113 static inline void sched_cacheflush(void)
 114 {
 115 }
 116
 117 #ifdef CONFIG_VIRT_CPU_ACCOUNTING
 118 extern void account_vtime(struct task_struct *);
 119 extern void account_tick_vtime(struct task_struct *);
 120 extern void account_system_vtime(struct task_struct *);
 121 #else
 122 #define account_vtime(x) do { /* empty */ } while (0)
 123 #endif
 124
 125 #define finish_arch_switch(prev) do {                                        \
 126         set_fs(current->thread.mm_segment);                                  \
 127         account_vtime(prev);                                                 \
 128 } while (0)
 129
 130 #define nop() __asm__ __volatile__ ("nop")
 131
 132 #define xchg(ptr,x) \
 133   ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(void *)(ptr),sizeof(*(ptr))))
 134
 135 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
 136 {
 137         unsigned long addr, old;
 138         int shift;
 139
 140         switch (size) {
 141         case 1:
 142                 addr = (unsigned long) ptr;
 143                 shift = (3 ^ (addr & 3)) << 3;
 144                 addr ^= addr & 3;
 145                 asm volatile(
 146                         "    l   %0,0(%4)\n"
 147                         "0:  lr  0,%0\n"
 148                         "    nr  0,%3\n"
 149                         "    or  0,%2\n"
 150                         "    cs  %0,0,0(%4)\n"
 151                         "    jl  0b\n"
 152                         : "=&d" (old), "=m" (*(int *) addr)
 153                         : "d" (x << shift), "d" (~(255 << shift)), "a" (addr),
 154                           "m" (*(int *) addr) : "memory", "cc", "0" );
 155                 x = old >> shift;
 156                 break;
 157         case 2:
 158                 addr = (unsigned long) ptr;
 159                 shift = (2 ^ (addr & 2)) << 3;
 160                 addr ^= addr & 2;
 161                 asm volatile(
 162                         "    l   %0,0(%4)\n"
 163                         "0:  lr  0,%0\n"
 164                         "    nr  0,%3\n"
 165                         "    or  0,%2\n"
 166                         "    cs  %0,0,0(%4)\n"
 167                         "    jl  0b\n"
 168                         : "=&d" (old), "=m" (*(int *) addr)
 169                         : "d" (x << shift), "d" (~(65535 << shift)), "a" (addr),
 170                           "m" (*(int *) addr) : "memory", "cc", "0" );
 171                 x = old >> shift;
 172                 break;
 173         case 4:
 174                 asm volatile (
 175                         "    l   %0,0(%3)\n"
 176                         "0:  cs  %0,%2,0(%3)\n"
 177                         "    jl  0b\n"
 178                         : "=&d" (old), "=m" (*(int *) ptr)
 179                         : "d" (x), "a" (ptr), "m" (*(int *) ptr)
 180                         : "memory", "cc" );
 181                 x = old;
 182                 break;
 183 #ifdef __s390x__
 184         case 8:
 185                 asm volatile (
 186                         "    lg  %0,0(%3)\n"
 187                         "0:  csg %0,%2,0(%3)\n"
 188                         "    jl  0b\n"
 189                         : "=&d" (old), "=m" (*(long *) ptr)
 190                         : "d" (x), "a" (ptr), "m" (*(long *) ptr)
 191                         : "memory", "cc" );
 192                 x = old;
 193                 break;
 194 #endif /* __s390x__ */
 195         }
 196         return x;
 197 }
 198
 199 /*
 200  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 201  * store NEW in MEM.  Return the initial value in MEM.  Success is
 202  * indicated by comparing RETURN with OLD.
 203  */
 204
 205 #define __HAVE_ARCH_CMPXCHG 1
 206
 207 #define cmpxchg(ptr,o,n)\
 208         ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
 209                                         (unsigned long)(n),sizeof(*(ptr))))
 210
 211 static inline unsigned long
 212 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 213 {
 214         unsigned long addr, prev, tmp;
 215         int shift;
 216
 217         switch (size) {
 218         case 1:
 219                 addr = (unsigned long) ptr;
 220                 shift = (3 ^ (addr & 3)) << 3;
 221                 addr ^= addr & 3;
 222                 asm volatile(
 223                         "    l   %0,0(%4)\n"
 224                         "0:  nr  %0,%5\n"
 225                         "    lr  %1,%0\n"
 226                         "    or  %0,%2\n"
 227                         "    or  %1,%3\n"
 228                         "    cs  %0,%1,0(%4)\n"
 229                         "    jnl 1f\n"
 230                         "    xr  %1,%0\n"
 231                         "    nr  %1,%5\n"
 232                         "    jnz 0b\n"
 233                         "1:"
 234                         : "=&d" (prev), "=&d" (tmp)
 235                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 236                           "d" (~(255 << shift))
 237                         : "memory", "cc" );
 238                 return prev >> shift;
 239         case 2:
 240                 addr = (unsigned long) ptr;
 241                 shift = (2 ^ (addr & 2)) << 3;
 242                 addr ^= addr & 2;
 243                 asm volatile(
 244                         "    l   %0,0(%4)\n"
 245                         "0:  nr  %0,%5\n"
 246                         "    lr  %1,%0\n"
 247                         "    or  %0,%2\n"
 248                         "    or  %1,%3\n"
 249                         "    cs  %0,%1,0(%4)\n"
 250                         "    jnl 1f\n"
 251                         "    xr  %1,%0\n"
 252                         "    nr  %1,%5\n"
 253                         "    jnz 0b\n"
 254                         "1:"
 255                         : "=&d" (prev), "=&d" (tmp)
 256                         : "d" (old << shift), "d" (new << shift), "a" (ptr),
 257                           "d" (~(65535 << shift))
 258                         : "memory", "cc" );
 259                 return prev >> shift;
 260         case 4:
 261                 asm volatile (
 262                         "    cs  %0,%2,0(%3)\n"
 263                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 264                         : "memory", "cc" );
 265                 return prev;
 266 #ifdef __s390x__
 267         case 8:
 268                 asm volatile (
 269                         "    csg %0,%2,0(%3)\n"
 270                         : "=&d" (prev) : "0" (old), "d" (new), "a" (ptr)
 271                         : "memory", "cc" );
 272                 return prev;
 273 #endif /* __s390x__ */
 274         }
 275         return old;
 276 }
 277
 278 /*
 279  * Force strict CPU ordering.
 280  * And yes, this is required on UP too when we're talking
 281  * to devices.
 282  *
 283  * This is very similar to the ppc eieio/sync instruction in that is
 284  * does a checkpoint syncronisation & makes sure that
 285  * all memory ops have completed wrt other CPU's ( see 7-15 POP  DJB ).
 286  */
 287
 288 #define eieio()  __asm__ __volatile__ ( "bcr 15,0" : : : "memory" )
 289 # define SYNC_OTHER_CORES(x)   eieio()
 290 #define mb()    eieio()
 291 #define rmb()   eieio()
 292 #define wmb()   eieio()
 293 #define read_barrier_depends() do { } while(0)
 294 #define smp_mb()       mb()
 295 #define smp_rmb()      rmb()
 296 #define smp_wmb()      wmb()
 297 #define smp_read_barrier_depends()    read_barrier_depends()
 298 #define smp_mb__before_clear_bit()     smp_mb()
 299 #define smp_mb__after_clear_bit()      smp_mb()
 300
 301
 302 #define set_mb(var, value)      do { var = value; mb(); } while (0)
 303 #define set_wmb(var, value)     do { var = value; wmb(); } while (0)
 304
 305 /* interrupt control.. */
 306 #define local_irq_enable() ({ \
 307         unsigned long  __dummy; \
 308         __asm__ __volatile__ ( \
 309                 "stosm 0(%1),0x03" \
 310                 : "=m" (__dummy) : "a" (&__dummy) : "memory" ); \
 311         })
 312
 313 #define local_irq_disable() ({ \
 314         unsigned long __flags; \
 315         __asm__ __volatile__ ( \
 316                 "stnsm 0(%1),0xfc" : "=m" (__flags) : "a" (&__flags) ); \
 317         __flags; \
 318         })
 319
 320 #define local_save_flags(x) \
 321         __asm__ __volatile__("stosm 0(%1),0" : "=m" (x) : "a" (&x), "m" (x) )
 322
 323 #define local_irq_restore(x) \
 324         __asm__ __volatile__("ssm   0(%0)" : : "a" (&x), "m" (x) : "memory")
 325
 326 #define irqs_disabled()                 \
 327 ({                                      \
 328         unsigned long flags;            \
 329         local_save_flags(flags);        \
 330         !((flags >> __FLAG_SHIFT) & 3); \
 331 })
 332
 333 #ifdef __s390x__
 334
 335 #define __ctl_load(array, low, high) ({ \
 336         typedef struct { char _[sizeof(array)]; } addrtype; \
 337         __asm__ __volatile__ ( \
 338                 "   bras  1,0f\n" \
 339                 "   lctlg 0,0,0(%0)\n" \
 340                 "0: ex    %1,0(1)" \
 341                 : : "a" (&array), "a" (((low)<<4)+(high)), \
 342                     "m" (*(addrtype *)(array)) : "1" ); \
 343         })
 344
 345 #define __ctl_store(array, low, high) ({ \
 346         typedef struct { char _[sizeof(array)]; } addrtype; \
 347         __asm__ __volatile__ ( \
 348                 "   bras  1,0f\n" \
 349                 "   stctg 0,0,0(%1)\n" \
 350                 "0: ex    %2,0(1)" \
 351                 : "=m" (*(addrtype *)(array)) \
 352                 : "a" (&array), "a" (((low)<<4)+(high)) : "1" ); \
 353         })
 354
 355 #define __ctl_set_bit(cr, bit) ({ \
 356         __u8 __dummy[24]; \
 357         __asm__ __volatile__ ( \
 358                 "    bras  1,0f\n"       /* skip indirect insns */ \
 359                 "    stctg 0,0,0(%1)\n" \
 360                 "    lctlg 0,0,0(%1)\n" \
 361                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 362                 "    lg    0,0(%1)\n" \
 363                 "    ogr   0,%3\n"       /* set the bit */ \
 364                 "    stg   0,0(%1)\n" \
 365                 "1:  ex    %2,6(1)"      /* execute lctl */ \
 366                 : "=m" (__dummy) \
 367                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 368                   "a" (cr*17), "a" (1L<<(bit)) \
 369                 : "cc", "0", "1" ); \
 370         })
 371
 372 #define __ctl_clear_bit(cr, bit) ({ \
 373         __u8 __dummy[16]; \
 374         __asm__ __volatile__ ( \
 375                 "    bras  1,0f\n"       /* skip indirect insns */ \
 376                 "    stctg 0,0,0(%1)\n" \
 377                 "    lctlg 0,0,0(%1)\n" \
 378                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 379                 "    lg    0,0(%1)\n" \
 380                 "    ngr   0,%3\n"       /* set the bit */ \
 381                 "    stg   0,0(%1)\n" \
 382                 "1:  ex    %2,6(1)"      /* execute lctl */ \
 383                 : "=m" (__dummy) \
 384                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 385                   "a" (cr*17), "a" (~(1L<<(bit))) \
 386                 : "cc", "0", "1" ); \
 387         })
 388
 389 #else /* __s390x__ */
 390
 391 #define __ctl_load(array, low, high) ({ \
 392         typedef struct { char _[sizeof(array)]; } addrtype; \
 393         __asm__ __volatile__ ( \
 394                 "   bras  1,0f\n" \
 395                 "   lctl 0,0,0(%0)\n" \
 396                 "0: ex    %1,0(1)" \
 397                 : : "a" (&array), "a" (((low)<<4)+(high)), \
 398                     "m" (*(addrtype *)(array)) : "1" ); \
 399         })
 400
 401 #define __ctl_store(array, low, high) ({ \
 402         typedef struct { char _[sizeof(array)]; } addrtype; \
 403         __asm__ __volatile__ ( \
 404                 "   bras  1,0f\n" \
 405                 "   stctl 0,0,0(%1)\n" \
 406                 "0: ex    %2,0(1)" \
 407                 : "=m" (*(addrtype *)(array)) \
 408                 : "a" (&array), "a" (((low)<<4)+(high)): "1" ); \
 409         })
 410
 411 #define __ctl_set_bit(cr, bit) ({ \
 412         __u8 __dummy[16]; \
 413         __asm__ __volatile__ ( \
 414                 "    bras  1,0f\n"       /* skip indirect insns */ \
 415                 "    stctl 0,0,0(%1)\n" \
 416                 "    lctl  0,0,0(%1)\n" \
 417                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 418                 "    l     0,0(%1)\n" \
 419                 "    or    0,%3\n"       /* set the bit */ \
 420                 "    st    0,0(%1)\n" \
 421                 "1:  ex    %2,4(1)"      /* execute lctl */ \
 422                 : "=m" (__dummy) \
 423                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 424                   "a" (cr*17), "a" (1<<(bit)) \
 425                 : "cc", "0", "1" ); \
 426         })
 427
 428 #define __ctl_clear_bit(cr, bit) ({ \
 429         __u8 __dummy[16]; \
 430         __asm__ __volatile__ ( \
 431                 "    bras  1,0f\n"       /* skip indirect insns */ \
 432                 "    stctl 0,0,0(%1)\n" \
 433                 "    lctl  0,0,0(%1)\n" \
 434                 "0:  ex    %2,0(1)\n"    /* execute stctl */ \
 435                 "    l     0,0(%1)\n" \
 436                 "    nr    0,%3\n"       /* set the bit */ \
 437                 "    st    0,0(%1)\n" \
 438                 "1:  ex    %2,4(1)"      /* execute lctl */ \
 439                 : "=m" (__dummy) \
 440                 : "a" ((((unsigned long) &__dummy) + 7) & ~7UL), \
 441                   "a" (cr*17), "a" (~(1<<(bit))) \
 442                 : "cc", "0", "1" ); \
 443         })
 444 #endif /* __s390x__ */
 445
 446 /* For spinlocks etc */
 447 #define local_irq_save(x)       ((x) = local_irq_disable())
 448
 449 /*
 450  * Use to set psw mask except for the first byte which
 451  * won't be changed by this function.
 452  */
 453 static inline void
 454 __set_psw_mask(unsigned long mask)
 455 {
 456         local_save_flags(mask);
 457         __load_psw_mask(mask);
 458 }
 459
 460 #define local_mcck_enable()  __set_psw_mask(PSW_KERNEL_BITS)
 461 #define local_mcck_disable() __set_psw_mask(PSW_KERNEL_BITS & ~PSW_MASK_MCHECK)
 462
 463 #ifdef CONFIG_SMP
 464
 465 extern void smp_ctl_set_bit(int cr, int bit);
 466 extern void smp_ctl_clear_bit(int cr, int bit);
 467 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
 468 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
 469
 470 #else
 471
 472 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
 473 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
 474
 475 #endif /* CONFIG_SMP */
 476
 477 extern void (*_machine_restart)(char *command);
 478 extern void (*_machine_halt)(void);
 479 extern void (*_machine_power_off)(void);
 480
 481 #define arch_align_stack(x) (x)
 482
 483 #endif /* __KERNEL__ */
 484
 485 #endif
 486