2 * linux/arch/arm/mach-mmp/mmp2.c
6 * Copyright (C) 2009 Marvell International Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
18 #include <mach/addr-map.h>
19 #include <mach/regs-apbc.h>
20 #include <mach/regs-apmu.h>
21 #include <mach/cputype.h>
22 #include <mach/irqs.h>
24 #include <mach/gpio.h>
25 #include <mach/devices.h>
30 #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
32 #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x9c)
34 static struct mfp_addr_map mmp2_addr_map
[] __initdata
= {
35 MFP_ADDR(PMIC_INT
, 0x2c4),
40 void mmp2_clear_pmic_int(void)
42 unsigned long mfpr_pmic
, data
;
44 mfpr_pmic
= APB_VIRT_BASE
+ 0x1e000 + 0x2c4;
45 data
= __raw_readl(mfpr_pmic
);
46 __raw_writel(data
| (1 << 6), mfpr_pmic
);
47 __raw_writel(data
, mfpr_pmic
);
50 static void __init
mmp2_init_gpio(void)
54 /* enable GPIO clock */
55 __raw_writel(APBC_APBCLK
| APBC_FNCLK
, APBC_MMP2_GPIO
);
57 /* unmask GPIO edge detection for all 6 banks -- APMASKx */
58 for (i
= 0; i
< 6; i
++)
59 __raw_writel(0xffffffff, APMASK(i
));
61 pxa_init_gpio(IRQ_MMP2_GPIO
, 0, 167, NULL
);
64 void __init
mmp2_init_irq(void)
70 /* APB peripheral clocks */
71 static APBC_CLK(uart1
, MMP2_UART1
, 1, 26000000);
72 static APBC_CLK(uart2
, MMP2_UART2
, 1, 26000000);
73 static APBC_CLK(uart3
, MMP2_UART3
, 1, 26000000);
74 static APBC_CLK(uart4
, MMP2_UART4
, 1, 26000000);
75 static APBC_CLK(twsi1
, MMP2_TWSI1
, 0, 26000000);
76 static APBC_CLK(twsi2
, MMP2_TWSI2
, 0, 26000000);
77 static APBC_CLK(twsi3
, MMP2_TWSI3
, 0, 26000000);
78 static APBC_CLK(twsi4
, MMP2_TWSI4
, 0, 26000000);
79 static APBC_CLK(twsi5
, MMP2_TWSI5
, 0, 26000000);
80 static APBC_CLK(twsi6
, MMP2_TWSI6
, 0, 26000000);
81 static APBC_CLK(rtc
, MMP2_RTC
, 0, 32768);
83 static APMU_CLK(nand
, NAND
, 0xbf, 100000000);
85 static struct clk_lookup mmp2_clkregs
[] = {
86 INIT_CLKREG(&clk_uart1
, "pxa2xx-uart.0", NULL
),
87 INIT_CLKREG(&clk_uart2
, "pxa2xx-uart.1", NULL
),
88 INIT_CLKREG(&clk_uart3
, "pxa2xx-uart.2", NULL
),
89 INIT_CLKREG(&clk_uart4
, "pxa2xx-uart.3", NULL
),
90 INIT_CLKREG(&clk_twsi1
, "pxa2xx-i2c.0", NULL
),
91 INIT_CLKREG(&clk_twsi2
, "pxa2xx-i2c.1", NULL
),
92 INIT_CLKREG(&clk_twsi3
, "pxa2xx-i2c.2", NULL
),
93 INIT_CLKREG(&clk_twsi4
, "pxa2xx-i2c.3", NULL
),
94 INIT_CLKREG(&clk_twsi5
, "pxa2xx-i2c.4", NULL
),
95 INIT_CLKREG(&clk_twsi6
, "pxa2xx-i2c.5", NULL
),
96 INIT_CLKREG(&clk_nand
, "pxa3xx-nand", NULL
),
99 static int __init
mmp2_init(void)
102 mfp_init_base(MFPR_VIRT_BASE
);
103 mfp_init_addr(mmp2_addr_map
);
104 clks_register(ARRAY_AND_SIZE(mmp2_clkregs
));
109 postcore_initcall(mmp2_init
);
111 /* on-chip devices */
112 MMP2_DEVICE(uart1
, "pxa2xx-uart", 0, UART1
, 0xd4030000, 0x30, 4, 5);
113 MMP2_DEVICE(uart2
, "pxa2xx-uart", 1, UART2
, 0xd4017000, 0x30, 20, 21);
114 MMP2_DEVICE(uart3
, "pxa2xx-uart", 2, UART3
, 0xd4018000, 0x30, 22, 23);
115 MMP2_DEVICE(uart4
, "pxa2xx-uart", 3, UART4
, 0xd4016000, 0x30, 18, 19);
116 MMP2_DEVICE(twsi1
, "pxa2xx-i2c", 0, TWSI1
, 0xd4011000, 0x70);
117 MMP2_DEVICE(twsi2
, "pxa2xx-i2c", 1, TWSI2
, 0xd4031000, 0x70);
118 MMP2_DEVICE(twsi3
, "pxa2xx-i2c", 2, TWSI3
, 0xd4032000, 0x70);
119 MMP2_DEVICE(twsi4
, "pxa2xx-i2c", 3, TWSI4
, 0xd4033000, 0x70);
120 MMP2_DEVICE(twsi5
, "pxa2xx-i2c", 4, TWSI5
, 0xd4033800, 0x70);
121 MMP2_DEVICE(twsi6
, "pxa2xx-i2c", 5, TWSI6
, 0xd4034000, 0x70);
122 MMP2_DEVICE(nand
, "pxa3xx-nand", -1, NAND
, 0xd4283000, 0x100, 28, 29);