sparc: Allow handling signals when stack is corrupted.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / tegra / tegra_spdif.h
blob2e03db4302798bc54d5fb127eede1445b76f89f6
1 /*
2 * tegra_spdif.h - Definitions for Tegra SPDIF driver
4 * Author: Stephen Warren <swarren@nvidia.com>
5 * Copyright (C) 2011 - NVIDIA, Inc.
7 * Based on code copyright/by:
8 * Copyright (c) 2008-2009, NVIDIA Corporation
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * 02110-1301 USA
26 #ifndef __TEGRA_SPDIF_H__
27 #define __TEGRA_SPDIF_H__
29 #include "tegra_pcm.h"
31 /* Offsets from TEGRA_SPDIF_BASE */
33 #define TEGRA_SPDIF_CTRL 0x0
34 #define TEGRA_SPDIF_STATUS 0x4
35 #define TEGRA_SPDIF_STROBE_CTRL 0x8
36 #define TEGRA_SPDIF_DATA_FIFO_CSR 0x0C
37 #define TEGRA_SPDIF_DATA_OUT 0x40
38 #define TEGRA_SPDIF_DATA_IN 0x80
39 #define TEGRA_SPDIF_CH_STA_RX_A 0x100
40 #define TEGRA_SPDIF_CH_STA_RX_B 0x104
41 #define TEGRA_SPDIF_CH_STA_RX_C 0x108
42 #define TEGRA_SPDIF_CH_STA_RX_D 0x10C
43 #define TEGRA_SPDIF_CH_STA_RX_E 0x110
44 #define TEGRA_SPDIF_CH_STA_RX_F 0x114
45 #define TEGRA_SPDIF_CH_STA_TX_A 0x140
46 #define TEGRA_SPDIF_CH_STA_TX_B 0x144
47 #define TEGRA_SPDIF_CH_STA_TX_C 0x148
48 #define TEGRA_SPDIF_CH_STA_TX_D 0x14C
49 #define TEGRA_SPDIF_CH_STA_TX_E 0x150
50 #define TEGRA_SPDIF_CH_STA_TX_F 0x154
51 #define TEGRA_SPDIF_USR_STA_RX_A 0x180
52 #define TEGRA_SPDIF_USR_DAT_TX_A 0x1C0
54 /* Fields in TEGRA_SPDIF_CTRL */
56 /* Start capturing from 0=right, 1=left channel */
57 #define TEGRA_SPDIF_CTRL_CAP_LC (1 << 30)
59 /* SPDIF receiver(RX) enable */
60 #define TEGRA_SPDIF_CTRL_RX_EN (1 << 29)
62 /* SPDIF Transmitter(TX) enable */
63 #define TEGRA_SPDIF_CTRL_TX_EN (1 << 28)
65 /* Transmit Channel status */
66 #define TEGRA_SPDIF_CTRL_TC_EN (1 << 27)
68 /* Transmit user Data */
69 #define TEGRA_SPDIF_CTRL_TU_EN (1 << 26)
71 /* Interrupt on transmit error */
72 #define TEGRA_SPDIF_CTRL_IE_TXE (1 << 25)
74 /* Interrupt on receive error */
75 #define TEGRA_SPDIF_CTRL_IE_RXE (1 << 24)
77 /* Interrupt on invalid preamble */
78 #define TEGRA_SPDIF_CTRL_IE_P (1 << 23)
80 /* Interrupt on "B" preamble */
81 #define TEGRA_SPDIF_CTRL_IE_B (1 << 22)
83 /* Interrupt when block of channel status received */
84 #define TEGRA_SPDIF_CTRL_IE_C (1 << 21)
86 /* Interrupt when a valid information unit (IU) is received */
87 #define TEGRA_SPDIF_CTRL_IE_U (1 << 20)
89 /* Interrupt when RX user FIFO attention level is reached */
90 #define TEGRA_SPDIF_CTRL_QE_RU (1 << 19)
92 /* Interrupt when TX user FIFO attention level is reached */
93 #define TEGRA_SPDIF_CTRL_QE_TU (1 << 18)
95 /* Interrupt when RX data FIFO attention level is reached */
96 #define TEGRA_SPDIF_CTRL_QE_RX (1 << 17)
98 /* Interrupt when TX data FIFO attention level is reached */
99 #define TEGRA_SPDIF_CTRL_QE_TX (1 << 16)
101 /* Loopback test mode enable */
102 #define TEGRA_SPDIF_CTRL_LBK_EN (1 << 15)
105 * Pack data mode:
106 * 0 = Single data (16 bit needs to be padded to match the
107 * interface data bit size).
108 * 1 = Packeted left/right channel data into a single word.
110 #define TEGRA_SPDIF_CTRL_PACK (1 << 14)
113 * 00 = 16bit data
114 * 01 = 20bit data
115 * 10 = 24bit data
116 * 11 = raw data
118 #define TEGRA_SPDIF_BIT_MODE_16BIT 0
119 #define TEGRA_SPDIF_BIT_MODE_20BIT 1
120 #define TEGRA_SPDIF_BIT_MODE_24BIT 2
121 #define TEGRA_SPDIF_BIT_MODE_RAW 3
123 #define TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT 12
124 #define TEGRA_SPDIF_CTRL_BIT_MODE_MASK (3 << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT)
125 #define TEGRA_SPDIF_CTRL_BIT_MODE_16BIT (TEGRA_SPDIF_BIT_MODE_16BIT << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT)
126 #define TEGRA_SPDIF_CTRL_BIT_MODE_20BIT (TEGRA_SPDIF_BIT_MODE_20BIT << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT)
127 #define TEGRA_SPDIF_CTRL_BIT_MODE_24BIT (TEGRA_SPDIF_BIT_MODE_24BIT << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT)
128 #define TEGRA_SPDIF_CTRL_BIT_MODE_RAW (TEGRA_SPDIF_BIT_MODE_RAW << TEGRA_SPDIF_CTRL_BIT_MODE_SHIFT)
130 /* Fields in TEGRA_SPDIF_STATUS */
133 * Note: IS_P, IS_B, IS_C, and IS_U are sticky bits. Software must
134 * write a 1 to the corresponding bit location to clear the status.
138 * Receiver(RX) shifter is busy receiving data.
139 * This bit is asserted when the receiver first locked onto the
140 * preamble of the data stream after RX_EN is asserted. This bit is
141 * deasserted when either,
142 * (a) the end of a frame is reached after RX_EN is deeasserted, or
143 * (b) the SPDIF data stream becomes inactive.
145 #define TEGRA_SPDIF_STATUS_RX_BSY (1 << 29)
148 * Transmitter(TX) shifter is busy transmitting data.
149 * This bit is asserted when TX_EN is asserted.
150 * This bit is deasserted when the end of a frame is reached after
151 * TX_EN is deasserted.
153 #define TEGRA_SPDIF_STATUS_TX_BSY (1 << 28)
156 * TX is busy shifting out channel status.
157 * This bit is asserted when both TX_EN and TC_EN are asserted and
158 * data from CH_STA_TX_A register is loaded into the internal shifter.
159 * This bit is deasserted when either,
160 * (a) the end of a frame is reached after TX_EN is deasserted, or
161 * (b) CH_STA_TX_F register is loaded into the internal shifter.
163 #define TEGRA_SPDIF_STATUS_TC_BSY (1 << 27)
166 * TX User data FIFO busy.
167 * This bit is asserted when TX_EN and TXU_EN are asserted and
168 * there's data in the TX user FIFO. This bit is deassert when either,
169 * (a) the end of a frame is reached after TX_EN is deasserted, or
170 * (b) there's no data left in the TX user FIFO.
172 #define TEGRA_SPDIF_STATUS_TU_BSY (1 << 26)
174 /* TX FIFO Underrun error status */
175 #define TEGRA_SPDIF_STATUS_TX_ERR (1 << 25)
177 /* RX FIFO Overrun error status */
178 #define TEGRA_SPDIF_STATUS_RX_ERR (1 << 24)
180 /* Preamble status: 0=Preamble OK, 1=bad/missing preamble */
181 #define TEGRA_SPDIF_STATUS_IS_P (1 << 23)
183 /* B-preamble detection status: 0=not detected, 1=B-preamble detected */
184 #define TEGRA_SPDIF_STATUS_IS_B (1 << 22)
187 * RX channel block data receive status:
188 * 0=entire block not recieved yet.
189 * 1=received entire block of channel status,
191 #define TEGRA_SPDIF_STATUS_IS_C (1 << 21)
193 /* RX User Data Valid flag: 1=valid IU detected, 0 = no IU detected. */
194 #define TEGRA_SPDIF_STATUS_IS_U (1 << 20)
197 * RX User FIFO Status:
198 * 1=attention level reached, 0=attention level not reached.
200 #define TEGRA_SPDIF_STATUS_QS_RU (1 << 19)
203 * TX User FIFO Status:
204 * 1=attention level reached, 0=attention level not reached.
206 #define TEGRA_SPDIF_STATUS_QS_TU (1 << 18)
209 * RX Data FIFO Status:
210 * 1=attention level reached, 0=attention level not reached.
212 #define TEGRA_SPDIF_STATUS_QS_RX (1 << 17)
215 * TX Data FIFO Status:
216 * 1=attention level reached, 0=attention level not reached.
218 #define TEGRA_SPDIF_STATUS_QS_TX (1 << 16)
220 /* Fields in TEGRA_SPDIF_STROBE_CTRL */
223 * Indicates the approximate number of detected SPDIFIN clocks within a
224 * bi-phase period.
226 #define TEGRA_SPDIF_STROBE_CTRL_PERIOD_SHIFT 16
227 #define TEGRA_SPDIF_STROBE_CTRL_PERIOD_MASK (0xff << TEGRA_SPDIF_STROBE_CTRL_PERIOD_SHIFT)
229 /* Data strobe mode: 0=Auto-locked 1=Manual locked */
230 #define TEGRA_SPDIF_STROBE_CTRL_STROBE (1 << 15)
233 * Manual data strobe time within the bi-phase clock period (in terms of
234 * the number of over-sampling clocks).
236 #define TEGRA_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT 8
237 #define TEGRA_SPDIF_STROBE_CTRL_DATA_STROBES_MASK (0x1f << TEGRA_SPDIF_STROBE_CTRL_DATA_STROBES_SHIFT)
240 * Manual SPDIFIN bi-phase clock period (in terms of the number of
241 * over-sampling clocks).
243 #define TEGRA_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT 0
244 #define TEGRA_SPDIF_STROBE_CTRL_CLOCK_PERIOD_MASK (0x3f << TEGRA_SPDIF_STROBE_CTRL_CLOCK_PERIOD_SHIFT)
246 /* Fields in SPDIF_DATA_FIFO_CSR */
248 /* Clear Receiver User FIFO (RX USR.FIFO) */
249 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_CLR (1 << 31)
251 #define TEGRA_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT 0
252 #define TEGRA_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS 1
253 #define TEGRA_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS 2
254 #define TEGRA_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS 3
256 /* RU FIFO attention level */
257 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT 29
258 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_MASK \
259 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
260 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU1_WORD_FULL \
261 (TEGRA_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
262 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU2_WORD_FULL \
263 (TEGRA_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
264 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU3_WORD_FULL \
265 (TEGRA_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
266 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_RU4_WORD_FULL \
267 (TEGRA_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RU_ATN_LVL_SHIFT)
269 /* Number of RX USR.FIFO levels with valid data. */
270 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT 24
271 #define TEGRA_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_MASK (0x1f << TEGRA_SPDIF_DATA_FIFO_CSR_RU_FULL_COUNT_SHIFT)
273 /* Clear Transmitter User FIFO (TX USR.FIFO) */
274 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_CLR (1 << 23)
276 /* TU FIFO attention level */
277 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT 21
278 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_MASK \
279 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
280 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU1_WORD_FULL \
281 (TEGRA_SPDIF_FIFO_ATN_LVL_U_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
282 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU2_WORD_FULL \
283 (TEGRA_SPDIF_FIFO_ATN_LVL_U_TWO_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
284 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU3_WORD_FULL \
285 (TEGRA_SPDIF_FIFO_ATN_LVL_U_THREE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
286 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_TU4_WORD_FULL \
287 (TEGRA_SPDIF_FIFO_ATN_LVL_U_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TU_ATN_LVL_SHIFT)
289 /* Number of TX USR.FIFO levels that could be filled. */
290 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT 16
291 #define TEGRA_SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TU_EMPTY_COUNT_SHIFT)
293 /* Clear Receiver Data FIFO (RX DATA.FIFO) */
294 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_CLR (1 << 15)
296 #define TEGRA_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT 0
297 #define TEGRA_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS 1
298 #define TEGRA_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS 2
299 #define TEGRA_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS 3
301 /* RU FIFO attention level */
302 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT 13
303 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_MASK \
304 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
305 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU1_WORD_FULL \
306 (TEGRA_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
307 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU4_WORD_FULL \
308 (TEGRA_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
309 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU8_WORD_FULL \
310 (TEGRA_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
311 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_RU12_WORD_FULL \
312 (TEGRA_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_RX_ATN_LVL_SHIFT)
314 /* Number of RX DATA.FIFO levels with valid data. */
315 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT 8
316 #define TEGRA_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_MASK (0x1f << TEGRA_SPDIF_DATA_FIFO_CSR_RX_FULL_COUNT_SHIFT)
318 /* Clear Transmitter Data FIFO (TX DATA.FIFO) */
319 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_CLR (1 << 7)
321 /* TU FIFO attention level */
322 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT 5
323 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK \
324 (0x3 << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
325 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU1_WORD_FULL \
326 (TEGRA_SPDIF_FIFO_ATN_LVL_D_ONE_SLOT << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
327 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL \
328 (TEGRA_SPDIF_FIFO_ATN_LVL_D_FOUR_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
329 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU8_WORD_FULL \
330 (TEGRA_SPDIF_FIFO_ATN_LVL_D_EIGHT_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
331 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU12_WORD_FULL \
332 (TEGRA_SPDIF_FIFO_ATN_LVL_D_TWELVE_SLOTS << TEGRA_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_SHIFT)
334 /* Number of TX DATA.FIFO levels that could be filled. */
335 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT 0
336 #define TEGRA_SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_MASK (0x1f << SPDIF_DATA_FIFO_CSR_TX_EMPTY_COUNT_SHIFT)
338 /* Fields in TEGRA_SPDIF_DATA_OUT */
341 * This register has 5 different formats:
342 * 16-bit (BIT_MODE=00, PACK=0)
343 * 20-bit (BIT_MODE=01, PACK=0)
344 * 24-bit (BIT_MODE=10, PACK=0)
345 * raw (BIT_MODE=11, PACK=0)
346 * 16-bit packed (BIT_MODE=00, PACK=1)
349 #define TEGRA_SPDIF_DATA_OUT_DATA_16_SHIFT 0
350 #define TEGRA_SPDIF_DATA_OUT_DATA_16_MASK (0xffff << TEGRA_SPDIF_DATA_OUT_DATA_16_SHIFT)
352 #define TEGRA_SPDIF_DATA_OUT_DATA_20_SHIFT 0
353 #define TEGRA_SPDIF_DATA_OUT_DATA_20_MASK (0xfffff << TEGRA_SPDIF_DATA_OUT_DATA_20_SHIFT)
355 #define TEGRA_SPDIF_DATA_OUT_DATA_24_SHIFT 0
356 #define TEGRA_SPDIF_DATA_OUT_DATA_24_MASK (0xffffff << TEGRA_SPDIF_DATA_OUT_DATA_24_SHIFT)
358 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_P (1 << 31)
359 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_C (1 << 30)
360 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_U (1 << 29)
361 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_V (1 << 28)
363 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT 8
364 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_DATA_MASK (0xfffff << TEGRA_SPDIF_DATA_OUT_DATA_RAW_DATA_SHIFT)
366 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT 4
367 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_AUX_MASK (0xf << TEGRA_SPDIF_DATA_OUT_DATA_RAW_AUX_SHIFT)
369 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT 0
370 #define TEGRA_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA_SPDIF_DATA_OUT_DATA_RAW_PREAMBLE_SHIFT)
372 #define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT 16
373 #define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_RIGHT_SHIFT)
375 #define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT 0
376 #define TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA_SPDIF_DATA_OUT_DATA_16_PACKED_LEFT_SHIFT)
378 /* Fields in TEGRA_SPDIF_DATA_IN */
381 * This register has 5 different formats:
382 * 16-bit (BIT_MODE=00, PACK=0)
383 * 20-bit (BIT_MODE=01, PACK=0)
384 * 24-bit (BIT_MODE=10, PACK=0)
385 * raw (BIT_MODE=11, PACK=0)
386 * 16-bit packed (BIT_MODE=00, PACK=1)
388 * Bits 31:24 are common to all modes except 16-bit packed
391 #define TEGRA_SPDIF_DATA_IN_DATA_P (1 << 31)
392 #define TEGRA_SPDIF_DATA_IN_DATA_C (1 << 30)
393 #define TEGRA_SPDIF_DATA_IN_DATA_U (1 << 29)
394 #define TEGRA_SPDIF_DATA_IN_DATA_V (1 << 28)
396 #define TEGRA_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT 24
397 #define TEGRA_SPDIF_DATA_IN_DATA_PREAMBLE_MASK (0xf << TEGRA_SPDIF_DATA_IN_DATA_PREAMBLE_SHIFT)
399 #define TEGRA_SPDIF_DATA_IN_DATA_16_SHIFT 0
400 #define TEGRA_SPDIF_DATA_IN_DATA_16_MASK (0xffff << TEGRA_SPDIF_DATA_IN_DATA_16_SHIFT)
402 #define TEGRA_SPDIF_DATA_IN_DATA_20_SHIFT 0
403 #define TEGRA_SPDIF_DATA_IN_DATA_20_MASK (0xfffff << TEGRA_SPDIF_DATA_IN_DATA_20_SHIFT)
405 #define TEGRA_SPDIF_DATA_IN_DATA_24_SHIFT 0
406 #define TEGRA_SPDIF_DATA_IN_DATA_24_MASK (0xffffff << TEGRA_SPDIF_DATA_IN_DATA_24_SHIFT)
408 #define TEGRA_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT 8
409 #define TEGRA_SPDIF_DATA_IN_DATA_RAW_DATA_MASK (0xfffff << TEGRA_SPDIF_DATA_IN_DATA_RAW_DATA_SHIFT)
411 #define TEGRA_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT 4
412 #define TEGRA_SPDIF_DATA_IN_DATA_RAW_AUX_MASK (0xf << TEGRA_SPDIF_DATA_IN_DATA_RAW_AUX_SHIFT)
414 #define TEGRA_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT 0
415 #define TEGRA_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_MASK (0xf << TEGRA_SPDIF_DATA_IN_DATA_RAW_PREAMBLE_SHIFT)
417 #define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT 16
418 #define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_MASK (0xffff << TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_RIGHT_SHIFT)
420 #define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT 0
421 #define TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_MASK (0xffff << TEGRA_SPDIF_DATA_IN_DATA_16_PACKED_LEFT_SHIFT)
423 /* Fields in TEGRA_SPDIF_CH_STA_RX_A */
424 /* Fields in TEGRA_SPDIF_CH_STA_RX_B */
425 /* Fields in TEGRA_SPDIF_CH_STA_RX_C */
426 /* Fields in TEGRA_SPDIF_CH_STA_RX_D */
427 /* Fields in TEGRA_SPDIF_CH_STA_RX_E */
428 /* Fields in TEGRA_SPDIF_CH_STA_RX_F */
431 * The 6-word receive channel data page buffer holds a block (192 frames) of
432 * channel status information. The order of receive is from LSB to MSB
433 * bit, and from CH_STA_RX_A to CH_STA_RX_F then back to CH_STA_RX_A.
436 /* Fields in TEGRA_SPDIF_CH_STA_TX_A */
437 /* Fields in TEGRA_SPDIF_CH_STA_TX_B */
438 /* Fields in TEGRA_SPDIF_CH_STA_TX_C */
439 /* Fields in TEGRA_SPDIF_CH_STA_TX_D */
440 /* Fields in TEGRA_SPDIF_CH_STA_TX_E */
441 /* Fields in TEGRA_SPDIF_CH_STA_TX_F */
444 * The 6-word transmit channel data page buffer holds a block (192 frames) of
445 * channel status information. The order of transmission is from LSB to MSB
446 * bit, and from CH_STA_TX_A to CH_STA_TX_F then back to CH_STA_TX_A.
449 /* Fields in TEGRA_SPDIF_USR_STA_RX_A */
452 * This 4-word deep FIFO receives user FIFO field information. The order of
453 * receive is from LSB to MSB bit.
456 /* Fields in TEGRA_SPDIF_USR_DAT_TX_A */
459 * This 4-word deep FIFO transmits user FIFO field information. The order of
460 * transmission is from LSB to MSB bit.
463 struct tegra_spdif {
464 struct clk *clk_spdif_out;
465 int clk_refs;
466 struct tegra_pcm_dma_params capture_dma_data;
467 struct tegra_pcm_dma_params playback_dma_data;
468 void __iomem *regs;
469 struct dentry *debug;
470 u32 reg_ctrl;
473 #endif