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Linux 3.0-rc1
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpio / gpio-omap.c
blob6c51191da567e1fba91e774573f08f087e90daee
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
38 u32 suspend_wakeup;
39 u32 saved_wakeup;
40 #endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57 };
58
59 #ifdef CONFIG_ARCH_OMAP3
60 struct omap3_gpio_regs {
61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
71 };
72
73 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
74 #endif
75
76 /*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80 static struct gpio_bank *gpio_bank;
81
82 static int bank_width;
83
84 /* TODO: Analyze removing gpio_bank_count usage from driver code */
85 int gpio_bank_count;
86
87 static inline struct gpio_bank *get_gpio_bank(int gpio)
88 {
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110 }
111
112 static inline int get_gpio_index(int gpio)
113 {
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121 }
122
123 static inline int gpio_valid(int gpio)
124 {
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145 }
146
147 static int check_gpio(int gpio)
148 {
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155 }
156
157 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158 {
159 void __iomem *reg = bank->base;
160 u32 l;
161
162 switch (bank->method) {
163 #ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167 #endif
168 #ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172 #endif
173 #ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177 #endif
178 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182 #endif
183 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187 #endif
188 #if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192 #endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203 }
204
205 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206 {
207 void __iomem *reg = bank->base;
208 u32 l = 0;
209
210 switch (bank->method) {
211 #ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220 #endif
221 #ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230 #endif
231 #ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239 #endif
240 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249 #endif
250 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258 #endif
259 #ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267 #endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg);
273 }
274
275 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
276 {
277 void __iomem *reg;
278
279 if (check_gpio(gpio) < 0)
280 return -EINVAL;
281 reg = bank->base;
282 switch (bank->method) {
283 #ifdef CONFIG_ARCH_OMAP1
284 case METHOD_MPUIO:
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287 #endif
288 #ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292 #endif
293 #ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297 #endif
298 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302 #endif
303 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307 #endif
308 #ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312 #endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318 }
319
320 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321 {
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329 #ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333 #endif
334 #ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338 #endif
339 #ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343 #endif
344 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348 #endif
349 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353 #endif
354 #ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358 #endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364 }
365
366 #define MOD_REG_BIT(reg, bit_mask, set) \
367 do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372 } while(0)
373
374 /**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385 {
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
390 if (!bank->dbck_flag)
391 return;
392
393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
419 clk_enable(bank->dbck);
420 } else {
421 val &= ~l;
422 clk_disable(bank->dbck);
423 }
424 bank->dbck_enable_mask = val;
425
426 __raw_writel(val, reg);
427 }
428
429 #ifdef CONFIG_ARCH_OMAP2PLUS
430 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
432 {
433 void __iomem *base = bank->base;
434 u32 gpio_bit = 1 << gpio;
435 u32 val;
436
437 if (cpu_is_omap44xx()) {
438 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
439 trigger & IRQ_TYPE_LEVEL_LOW);
440 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
441 trigger & IRQ_TYPE_LEVEL_HIGH);
442 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
443 trigger & IRQ_TYPE_EDGE_RISING);
444 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
445 trigger & IRQ_TYPE_EDGE_FALLING);
446 } else {
447 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
448 trigger & IRQ_TYPE_LEVEL_LOW);
449 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
450 trigger & IRQ_TYPE_LEVEL_HIGH);
451 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
452 trigger & IRQ_TYPE_EDGE_RISING);
453 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
454 trigger & IRQ_TYPE_EDGE_FALLING);
455 }
456 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
457 if (cpu_is_omap44xx()) {
458 if (trigger != 0)
459 __raw_writel(1 << gpio, bank->base+
460 OMAP4_GPIO_IRQWAKEN0);
461 else {
462 val = __raw_readl(bank->base +
463 OMAP4_GPIO_IRQWAKEN0);
464 __raw_writel(val & (~(1 << gpio)), bank->base +
465 OMAP4_GPIO_IRQWAKEN0);
466 }
467 } else {
468 /*
469 * GPIO wakeup request can only be generated on edge
470 * transitions
471 */
472 if (trigger & IRQ_TYPE_EDGE_BOTH)
473 __raw_writel(1 << gpio, bank->base
474 + OMAP24XX_GPIO_SETWKUENA);
475 else
476 __raw_writel(1 << gpio, bank->base
477 + OMAP24XX_GPIO_CLEARWKUENA);
478 }
479 }
480 /* This part needs to be executed always for OMAP34xx */
481 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
482 /*
483 * Log the edge gpio and manually trigger the IRQ
484 * after resume if the input level changes
485 * to avoid irq lost during PER RET/OFF mode
486 * Applies for omap2 non-wakeup gpio and all omap3 gpios
487 */
488 if (trigger & IRQ_TYPE_EDGE_BOTH)
489 bank->enabled_non_wakeup_gpios |= gpio_bit;
490 else
491 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
492 }
493
494 if (cpu_is_omap44xx()) {
495 bank->level_mask =
496 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
497 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
498 } else {
499 bank->level_mask =
500 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
501 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
502 }
503 }
504 #endif
505
506 #ifdef CONFIG_ARCH_OMAP1
507 /*
508 * This only applies to chips that can't do both rising and falling edge
509 * detection at once. For all other chips, this function is a noop.
510 */
511 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
512 {
513 void __iomem *reg = bank->base;
514 u32 l = 0;
515
516 switch (bank->method) {
517 case METHOD_MPUIO:
518 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
519 break;
520 #ifdef CONFIG_ARCH_OMAP15XX
521 case METHOD_GPIO_1510:
522 reg += OMAP1510_GPIO_INT_CONTROL;
523 break;
524 #endif
525 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
526 case METHOD_GPIO_7XX:
527 reg += OMAP7XX_GPIO_INT_CONTROL;
528 break;
529 #endif
530 default:
531 return;
532 }
533
534 l = __raw_readl(reg);
535 if ((l >> gpio) & 1)
536 l &= ~(1 << gpio);
537 else
538 l |= 1 << gpio;
539
540 __raw_writel(l, reg);
541 }
542 #endif
543
544 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
545 {
546 void __iomem *reg = bank->base;
547 u32 l = 0;
548
549 switch (bank->method) {
550 #ifdef CONFIG_ARCH_OMAP1
551 case METHOD_MPUIO:
552 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
553 l = __raw_readl(reg);
554 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
555 bank->toggle_mask |= 1 << gpio;
556 if (trigger & IRQ_TYPE_EDGE_RISING)
557 l |= 1 << gpio;
558 else if (trigger & IRQ_TYPE_EDGE_FALLING)
559 l &= ~(1 << gpio);
560 else
561 goto bad;
562 break;
563 #endif
564 #ifdef CONFIG_ARCH_OMAP15XX
565 case METHOD_GPIO_1510:
566 reg += OMAP1510_GPIO_INT_CONTROL;
567 l = __raw_readl(reg);
568 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
569 bank->toggle_mask |= 1 << gpio;
570 if (trigger & IRQ_TYPE_EDGE_RISING)
571 l |= 1 << gpio;
572 else if (trigger & IRQ_TYPE_EDGE_FALLING)
573 l &= ~(1 << gpio);
574 else
575 goto bad;
576 break;
577 #endif
578 #ifdef CONFIG_ARCH_OMAP16XX
579 case METHOD_GPIO_1610:
580 if (gpio & 0x08)
581 reg += OMAP1610_GPIO_EDGE_CTRL2;
582 else
583 reg += OMAP1610_GPIO_EDGE_CTRL1;
584 gpio &= 0x07;
585 l = __raw_readl(reg);
586 l &= ~(3 << (gpio << 1));
587 if (trigger & IRQ_TYPE_EDGE_RISING)
588 l |= 2 << (gpio << 1);
589 if (trigger & IRQ_TYPE_EDGE_FALLING)
590 l |= 1 << (gpio << 1);
591 if (trigger)
592 /* Enable wake-up during idle for dynamic tick */
593 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
594 else
595 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
596 break;
597 #endif
598 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
599 case METHOD_GPIO_7XX:
600 reg += OMAP7XX_GPIO_INT_CONTROL;
601 l = __raw_readl(reg);
602 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
603 bank->toggle_mask |= 1 << gpio;
604 if (trigger & IRQ_TYPE_EDGE_RISING)
605 l |= 1 << gpio;
606 else if (trigger & IRQ_TYPE_EDGE_FALLING)
607 l &= ~(1 << gpio);
608 else
609 goto bad;
610 break;
611 #endif
612 #ifdef CONFIG_ARCH_OMAP2PLUS
613 case METHOD_GPIO_24XX:
614 case METHOD_GPIO_44XX:
615 set_24xx_gpio_triggering(bank, gpio, trigger);
616 return 0;
617 #endif
618 default:
619 goto bad;
620 }
621 __raw_writel(l, reg);
622 return 0;
623 bad:
624 return -EINVAL;
625 }
626
627 static int gpio_irq_type(struct irq_data *d, unsigned type)
628 {
629 struct gpio_bank *bank;
630 unsigned gpio;
631 int retval;
632 unsigned long flags;
633
634 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
635 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
636 else
637 gpio = d->irq - IH_GPIO_BASE;
638
639 if (check_gpio(gpio) < 0)
640 return -EINVAL;
641
642 if (type & ~IRQ_TYPE_SENSE_MASK)
643 return -EINVAL;
644
645 /* OMAP1 allows only only edge triggering */
646 if (!cpu_class_is_omap2()
647 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
648 return -EINVAL;
649
650 bank = irq_data_get_irq_chip_data(d);
651 spin_lock_irqsave(&bank->lock, flags);
652 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
653 spin_unlock_irqrestore(&bank->lock, flags);
654
655 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
656 __irq_set_handler_locked(d->irq, handle_level_irq);
657 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
658 __irq_set_handler_locked(d->irq, handle_edge_irq);
659
660 return retval;
661 }
662
663 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
664 {
665 void __iomem *reg = bank->base;
666
667 switch (bank->method) {
668 #ifdef CONFIG_ARCH_OMAP1
669 case METHOD_MPUIO:
670 /* MPUIO irqstatus is reset by reading the status register,
671 * so do nothing here */
672 return;
673 #endif
674 #ifdef CONFIG_ARCH_OMAP15XX
675 case METHOD_GPIO_1510:
676 reg += OMAP1510_GPIO_INT_STATUS;
677 break;
678 #endif
679 #ifdef CONFIG_ARCH_OMAP16XX
680 case METHOD_GPIO_1610:
681 reg += OMAP1610_GPIO_IRQSTATUS1;
682 break;
683 #endif
684 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
685 case METHOD_GPIO_7XX:
686 reg += OMAP7XX_GPIO_INT_STATUS;
687 break;
688 #endif
689 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
690 case METHOD_GPIO_24XX:
691 reg += OMAP24XX_GPIO_IRQSTATUS1;
692 break;
693 #endif
694 #if defined(CONFIG_ARCH_OMAP4)
695 case METHOD_GPIO_44XX:
696 reg += OMAP4_GPIO_IRQSTATUS0;
697 break;
698 #endif
699 default:
700 WARN_ON(1);
701 return;
702 }
703 __raw_writel(gpio_mask, reg);
704
705 /* Workaround for clearing DSP GPIO interrupts to allow retention */
706 if (cpu_is_omap24xx() || cpu_is_omap34xx())
707 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
708 else if (cpu_is_omap44xx())
709 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
710
711 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
712 __raw_writel(gpio_mask, reg);
713
714 /* Flush posted write for the irq status to avoid spurious interrupts */
715 __raw_readl(reg);
716 }
717 }
718
719 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
720 {
721 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
722 }
723
724 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
725 {
726 void __iomem *reg = bank->base;
727 int inv = 0;
728 u32 l;
729 u32 mask;
730
731 switch (bank->method) {
732 #ifdef CONFIG_ARCH_OMAP1
733 case METHOD_MPUIO:
734 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
735 mask = 0xffff;
736 inv = 1;
737 break;
738 #endif
739 #ifdef CONFIG_ARCH_OMAP15XX
740 case METHOD_GPIO_1510:
741 reg += OMAP1510_GPIO_INT_MASK;
742 mask = 0xffff;
743 inv = 1;
744 break;
745 #endif
746 #ifdef CONFIG_ARCH_OMAP16XX
747 case METHOD_GPIO_1610:
748 reg += OMAP1610_GPIO_IRQENABLE1;
749 mask = 0xffff;
750 break;
751 #endif
752 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
753 case METHOD_GPIO_7XX:
754 reg += OMAP7XX_GPIO_INT_MASK;
755 mask = 0xffffffff;
756 inv = 1;
757 break;
758 #endif
759 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
760 case METHOD_GPIO_24XX:
761 reg += OMAP24XX_GPIO_IRQENABLE1;
762 mask = 0xffffffff;
763 break;
764 #endif
765 #if defined(CONFIG_ARCH_OMAP4)
766 case METHOD_GPIO_44XX:
767 reg += OMAP4_GPIO_IRQSTATUSSET0;
768 mask = 0xffffffff;
769 break;
770 #endif
771 default:
772 WARN_ON(1);
773 return 0;
774 }
775
776 l = __raw_readl(reg);
777 if (inv)
778 l = ~l;
779 l &= mask;
780 return l;
781 }
782
783 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
784 {
785 void __iomem *reg = bank->base;
786 u32 l;
787
788 switch (bank->method) {
789 #ifdef CONFIG_ARCH_OMAP1
790 case METHOD_MPUIO:
791 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
792 l = __raw_readl(reg);
793 if (enable)
794 l &= ~(gpio_mask);
795 else
796 l |= gpio_mask;
797 break;
798 #endif
799 #ifdef CONFIG_ARCH_OMAP15XX
800 case METHOD_GPIO_1510:
801 reg += OMAP1510_GPIO_INT_MASK;
802 l = __raw_readl(reg);
803 if (enable)
804 l &= ~(gpio_mask);
805 else
806 l |= gpio_mask;
807 break;
808 #endif
809 #ifdef CONFIG_ARCH_OMAP16XX
810 case METHOD_GPIO_1610:
811 if (enable)
812 reg += OMAP1610_GPIO_SET_IRQENABLE1;
813 else
814 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
815 l = gpio_mask;
816 break;
817 #endif
818 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
819 case METHOD_GPIO_7XX:
820 reg += OMAP7XX_GPIO_INT_MASK;
821 l = __raw_readl(reg);
822 if (enable)
823 l &= ~(gpio_mask);
824 else
825 l |= gpio_mask;
826 break;
827 #endif
828 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
829 case METHOD_GPIO_24XX:
830 if (enable)
831 reg += OMAP24XX_GPIO_SETIRQENABLE1;
832 else
833 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
834 l = gpio_mask;
835 break;
836 #endif
837 #ifdef CONFIG_ARCH_OMAP4
838 case METHOD_GPIO_44XX:
839 if (enable)
840 reg += OMAP4_GPIO_IRQSTATUSSET0;
841 else
842 reg += OMAP4_GPIO_IRQSTATUSCLR0;
843 l = gpio_mask;
844 break;
845 #endif
846 default:
847 WARN_ON(1);
848 return;
849 }
850 __raw_writel(l, reg);
851 }
852
853 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
854 {
855 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
856 }
857
858 /*
859 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
860 * 1510 does not seem to have a wake-up register. If JTAG is connected
861 * to the target, system will wake up always on GPIO events. While
862 * system is running all registered GPIO interrupts need to have wake-up
863 * enabled. When system is suspended, only selected GPIO interrupts need
864 * to have wake-up enabled.
865 */
866 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
867 {
868 unsigned long uninitialized_var(flags);
869
870 switch (bank->method) {
871 #ifdef CONFIG_ARCH_OMAP16XX
872 case METHOD_MPUIO:
873 case METHOD_GPIO_1610:
874 spin_lock_irqsave(&bank->lock, flags);
875 if (enable)
876 bank->suspend_wakeup |= (1 << gpio);
877 else
878 bank->suspend_wakeup &= ~(1 << gpio);
879 spin_unlock_irqrestore(&bank->lock, flags);
880 return 0;
881 #endif
882 #ifdef CONFIG_ARCH_OMAP2PLUS
883 case METHOD_GPIO_24XX:
884 case METHOD_GPIO_44XX:
885 if (bank->non_wakeup_gpios & (1 << gpio)) {
886 printk(KERN_ERR "Unable to modify wakeup on "
887 "non-wakeup GPIO%d\n",
888 (bank - gpio_bank) * 32 + gpio);
889 return -EINVAL;
890 }
891 spin_lock_irqsave(&bank->lock, flags);
892 if (enable)
893 bank->suspend_wakeup |= (1 << gpio);
894 else
895 bank->suspend_wakeup &= ~(1 << gpio);
896 spin_unlock_irqrestore(&bank->lock, flags);
897 return 0;
898 #endif
899 default:
900 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
901 bank->method);
902 return -EINVAL;
903 }
904 }
905
906 static void _reset_gpio(struct gpio_bank *bank, int gpio)
907 {
908 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
909 _set_gpio_irqenable(bank, gpio, 0);
910 _clear_gpio_irqstatus(bank, gpio);
911 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
912 }
913
914 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
915 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
916 {
917 unsigned int gpio = d->irq - IH_GPIO_BASE;
918 struct gpio_bank *bank;
919 int retval;
920
921 if (check_gpio(gpio) < 0)
922 return -ENODEV;
923 bank = irq_data_get_irq_chip_data(d);
924 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
925
926 return retval;
927 }
928
929 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
930 {
931 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
932 unsigned long flags;
933
934 spin_lock_irqsave(&bank->lock, flags);
935
936 /* Set trigger to none. You need to enable the desired trigger with
937 * request_irq() or set_irq_type().
938 */
939 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
940
941 #ifdef CONFIG_ARCH_OMAP15XX
942 if (bank->method == METHOD_GPIO_1510) {
943 void __iomem *reg;
944
945 /* Claim the pin for MPU */
946 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
947 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
948 }
949 #endif
950 if (!cpu_class_is_omap1()) {
951 if (!bank->mod_usage) {
952 void __iomem *reg = bank->base;
953 u32 ctrl;
954
955 if (cpu_is_omap24xx() || cpu_is_omap34xx())
956 reg += OMAP24XX_GPIO_CTRL;
957 else if (cpu_is_omap44xx())
958 reg += OMAP4_GPIO_CTRL;
959 ctrl = __raw_readl(reg);
960 /* Module is enabled, clocks are not gated */
961 ctrl &= 0xFFFFFFFE;
962 __raw_writel(ctrl, reg);
963 }
964 bank->mod_usage |= 1 << offset;
965 }
966 spin_unlock_irqrestore(&bank->lock, flags);
967
968 return 0;
969 }
970
971 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
972 {
973 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
974 unsigned long flags;
975
976 spin_lock_irqsave(&bank->lock, flags);
977 #ifdef CONFIG_ARCH_OMAP16XX
978 if (bank->method == METHOD_GPIO_1610) {
979 /* Disable wake-up during idle for dynamic tick */
980 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
981 __raw_writel(1 << offset, reg);
982 }
983 #endif
984 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
985 if (bank->method == METHOD_GPIO_24XX) {
986 /* Disable wake-up during idle for dynamic tick */
987 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
988 __raw_writel(1 << offset, reg);
989 }
990 #endif
991 #ifdef CONFIG_ARCH_OMAP4
992 if (bank->method == METHOD_GPIO_44XX) {
993 /* Disable wake-up during idle for dynamic tick */
994 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
995 __raw_writel(1 << offset, reg);
996 }
997 #endif
998 if (!cpu_class_is_omap1()) {
999 bank->mod_usage &= ~(1 << offset);
1000 if (!bank->mod_usage) {
1001 void __iomem *reg = bank->base;
1002 u32 ctrl;
1003
1004 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1005 reg += OMAP24XX_GPIO_CTRL;
1006 else if (cpu_is_omap44xx())
1007 reg += OMAP4_GPIO_CTRL;
1008 ctrl = __raw_readl(reg);
1009 /* Module is disabled, clocks are gated */
1010 ctrl |= 1;
1011 __raw_writel(ctrl, reg);
1012 }
1013 }
1014 _reset_gpio(bank, bank->chip.base + offset);
1015 spin_unlock_irqrestore(&bank->lock, flags);
1016 }
1017
1018 /*
1019 * We need to unmask the GPIO bank interrupt as soon as possible to
1020 * avoid missing GPIO interrupts for other lines in the bank.
1021 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1022 * in the bank to avoid missing nested interrupts for a GPIO line.
1023 * If we wait to unmask individual GPIO lines in the bank after the
1024 * line's interrupt handler has been run, we may miss some nested
1025 * interrupts.
1026 */
1027 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1028 {
1029 void __iomem *isr_reg = NULL;
1030 u32 isr;
1031 unsigned int gpio_irq, gpio_index;
1032 struct gpio_bank *bank;
1033 u32 retrigger = 0;
1034 int unmasked = 0;
1035 struct irq_chip *chip = irq_desc_get_chip(desc);
1036
1037 chained_irq_enter(chip, desc);
1038
1039 bank = irq_get_handler_data(irq);
1040 #ifdef CONFIG_ARCH_OMAP1
1041 if (bank->method == METHOD_MPUIO)
1042 isr_reg = bank->base +
1043 OMAP_MPUIO_GPIO_INT / bank->stride;
1044 #endif
1045 #ifdef CONFIG_ARCH_OMAP15XX
1046 if (bank->method == METHOD_GPIO_1510)
1047 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1048 #endif
1049 #if defined(CONFIG_ARCH_OMAP16XX)
1050 if (bank->method == METHOD_GPIO_1610)
1051 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1052 #endif
1053 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1054 if (bank->method == METHOD_GPIO_7XX)
1055 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1056 #endif
1057 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1058 if (bank->method == METHOD_GPIO_24XX)
1059 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1060 #endif
1061 #if defined(CONFIG_ARCH_OMAP4)
1062 if (bank->method == METHOD_GPIO_44XX)
1063 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1064 #endif
1065
1066 if (WARN_ON(!isr_reg))
1067 goto exit;
1068
1069 while(1) {
1070 u32 isr_saved, level_mask = 0;
1071 u32 enabled;
1072
1073 enabled = _get_gpio_irqbank_mask(bank);
1074 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1075
1076 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1077 isr &= 0x0000ffff;
1078
1079 if (cpu_class_is_omap2()) {
1080 level_mask = bank->level_mask & enabled;
1081 }
1082
1083 /* clear edge sensitive interrupts before handler(s) are
1084 called so that we don't miss any interrupt occurred while
1085 executing them */
1086 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1087 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1088 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1089
1090 /* if there is only edge sensitive GPIO pin interrupts
1091 configured, we could unmask GPIO bank interrupt immediately */
1092 if (!level_mask && !unmasked) {
1093 unmasked = 1;
1094 chained_irq_exit(chip, desc);
1095 }
1096
1097 isr |= retrigger;
1098 retrigger = 0;
1099 if (!isr)
1100 break;
1101
1102 gpio_irq = bank->virtual_irq_start;
1103 for (; isr != 0; isr >>= 1, gpio_irq++) {
1104 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1105
1106 if (!(isr & 1))
1107 continue;
1108
1109 #ifdef CONFIG_ARCH_OMAP1
1110 /*
1111 * Some chips can't respond to both rising and falling
1112 * at the same time. If this irq was requested with
1113 * both flags, we need to flip the ICR data for the IRQ
1114 * to respond to the IRQ for the opposite direction.
1115 * This will be indicated in the bank toggle_mask.
1116 */
1117 if (bank->toggle_mask & (1 << gpio_index))
1118 _toggle_gpio_edge_triggering(bank, gpio_index);
1119 #endif
1120
1121 generic_handle_irq(gpio_irq);
1122 }
1123 }
1124 /* if bank has any level sensitive GPIO pin interrupt
1125 configured, we must unmask the bank interrupt only after
1126 handler(s) are executed in order to avoid spurious bank
1127 interrupt */
1128 exit:
1129 if (!unmasked)
1130 chained_irq_exit(chip, desc);
1131 }
1132
1133 static void gpio_irq_shutdown(struct irq_data *d)
1134 {
1135 unsigned int gpio = d->irq - IH_GPIO_BASE;
1136 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1137
1138 _reset_gpio(bank, gpio);
1139 }
1140
1141 static void gpio_ack_irq(struct irq_data *d)
1142 {
1143 unsigned int gpio = d->irq - IH_GPIO_BASE;
1144 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1145
1146 _clear_gpio_irqstatus(bank, gpio);
1147 }
1148
1149 static void gpio_mask_irq(struct irq_data *d)
1150 {
1151 unsigned int gpio = d->irq - IH_GPIO_BASE;
1152 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1153
1154 _set_gpio_irqenable(bank, gpio, 0);
1155 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1156 }
1157
1158 static void gpio_unmask_irq(struct irq_data *d)
1159 {
1160 unsigned int gpio = d->irq - IH_GPIO_BASE;
1161 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1162 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1163 u32 trigger = irqd_get_trigger_type(d);
1164
1165 if (trigger)
1166 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1167
1168 /* For level-triggered GPIOs, the clearing must be done after
1169 * the HW source is cleared, thus after the handler has run */
1170 if (bank->level_mask & irq_mask) {
1171 _set_gpio_irqenable(bank, gpio, 0);
1172 _clear_gpio_irqstatus(bank, gpio);
1173 }
1174
1175 _set_gpio_irqenable(bank, gpio, 1);
1176 }
1177
1178 static struct irq_chip gpio_irq_chip = {
1179 .name = "GPIO",
1180 .irq_shutdown = gpio_irq_shutdown,
1181 .irq_ack = gpio_ack_irq,
1182 .irq_mask = gpio_mask_irq,
1183 .irq_unmask = gpio_unmask_irq,
1184 .irq_set_type = gpio_irq_type,
1185 .irq_set_wake = gpio_wake_enable,
1186 };
1187
1188 /*---------------------------------------------------------------------*/
1189
1190 #ifdef CONFIG_ARCH_OMAP1
1191
1192 /* MPUIO uses the always-on 32k clock */
1193
1194 static void mpuio_ack_irq(struct irq_data *d)
1195 {
1196 /* The ISR is reset automatically, so do nothing here. */
1197 }
1198
1199 static void mpuio_mask_irq(struct irq_data *d)
1200 {
1201 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1202 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1203
1204 _set_gpio_irqenable(bank, gpio, 0);
1205 }
1206
1207 static void mpuio_unmask_irq(struct irq_data *d)
1208 {
1209 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1210 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1211
1212 _set_gpio_irqenable(bank, gpio, 1);
1213 }
1214
1215 static struct irq_chip mpuio_irq_chip = {
1216 .name = "MPUIO",
1217 .irq_ack = mpuio_ack_irq,
1218 .irq_mask = mpuio_mask_irq,
1219 .irq_unmask = mpuio_unmask_irq,
1220 .irq_set_type = gpio_irq_type,
1221 #ifdef CONFIG_ARCH_OMAP16XX
1222 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1223 .irq_set_wake = gpio_wake_enable,
1224 #endif
1225 };
1226
1227
1228 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1229
1230
1231 #ifdef CONFIG_ARCH_OMAP16XX
1232
1233 #include <linux/platform_device.h>
1234
1235 static int omap_mpuio_suspend_noirq(struct device *dev)
1236 {
1237 struct platform_device *pdev = to_platform_device(dev);
1238 struct gpio_bank *bank = platform_get_drvdata(pdev);
1239 void __iomem *mask_reg = bank->base +
1240 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1241 unsigned long flags;
1242
1243 spin_lock_irqsave(&bank->lock, flags);
1244 bank->saved_wakeup = __raw_readl(mask_reg);
1245 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1246 spin_unlock_irqrestore(&bank->lock, flags);
1247
1248 return 0;
1249 }
1250
1251 static int omap_mpuio_resume_noirq(struct device *dev)
1252 {
1253 struct platform_device *pdev = to_platform_device(dev);
1254 struct gpio_bank *bank = platform_get_drvdata(pdev);
1255 void __iomem *mask_reg = bank->base +
1256 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1257 unsigned long flags;
1258
1259 spin_lock_irqsave(&bank->lock, flags);
1260 __raw_writel(bank->saved_wakeup, mask_reg);
1261 spin_unlock_irqrestore(&bank->lock, flags);
1262
1263 return 0;
1264 }
1265
1266 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1267 .suspend_noirq = omap_mpuio_suspend_noirq,
1268 .resume_noirq = omap_mpuio_resume_noirq,
1269 };
1270
1271 /* use platform_driver for this. */
1272 static struct platform_driver omap_mpuio_driver = {
1273 .driver = {
1274 .name = "mpuio",
1275 .pm = &omap_mpuio_dev_pm_ops,
1276 },
1277 };
1278
1279 static struct platform_device omap_mpuio_device = {
1280 .name = "mpuio",
1281 .id = -1,
1282 .dev = {
1283 .driver = &omap_mpuio_driver.driver,
1284 }
1285 /* could list the /proc/iomem resources */
1286 };
1287
1288 static inline void mpuio_init(void)
1289 {
1290 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1291 platform_set_drvdata(&omap_mpuio_device, bank);
1292
1293 if (platform_driver_register(&omap_mpuio_driver) == 0)
1294 (void) platform_device_register(&omap_mpuio_device);
1295 }
1296
1297 #else
1298 static inline void mpuio_init(void) {}
1299 #endif /* 16xx */
1300
1301 #else
1302
1303 extern struct irq_chip mpuio_irq_chip;
1304
1305 #define bank_is_mpuio(bank) 0
1306 static inline void mpuio_init(void) {}
1307
1308 #endif
1309
1310 /*---------------------------------------------------------------------*/
1311
1312 /* REVISIT these are stupid implementations! replace by ones that
1313 * don't switch on METHOD_* and which mostly avoid spinlocks
1314 */
1315
1316 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1317 {
1318 struct gpio_bank *bank;
1319 unsigned long flags;
1320
1321 bank = container_of(chip, struct gpio_bank, chip);
1322 spin_lock_irqsave(&bank->lock, flags);
1323 _set_gpio_direction(bank, offset, 1);
1324 spin_unlock_irqrestore(&bank->lock, flags);
1325 return 0;
1326 }
1327
1328 static int gpio_is_input(struct gpio_bank *bank, int mask)
1329 {
1330 void __iomem *reg = bank->base;
1331
1332 switch (bank->method) {
1333 case METHOD_MPUIO:
1334 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1335 break;
1336 case METHOD_GPIO_1510:
1337 reg += OMAP1510_GPIO_DIR_CONTROL;
1338 break;
1339 case METHOD_GPIO_1610:
1340 reg += OMAP1610_GPIO_DIRECTION;
1341 break;
1342 case METHOD_GPIO_7XX:
1343 reg += OMAP7XX_GPIO_DIR_CONTROL;
1344 break;
1345 case METHOD_GPIO_24XX:
1346 reg += OMAP24XX_GPIO_OE;
1347 break;
1348 case METHOD_GPIO_44XX:
1349 reg += OMAP4_GPIO_OE;
1350 break;
1351 default:
1352 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1353 return -EINVAL;
1354 }
1355 return __raw_readl(reg) & mask;
1356 }
1357
1358 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1359 {
1360 struct gpio_bank *bank;
1361 void __iomem *reg;
1362 int gpio;
1363 u32 mask;
1364
1365 gpio = chip->base + offset;
1366 bank = get_gpio_bank(gpio);
1367 reg = bank->base;
1368 mask = 1 << get_gpio_index(gpio);
1369
1370 if (gpio_is_input(bank, mask))
1371 return _get_gpio_datain(bank, gpio);
1372 else
1373 return _get_gpio_dataout(bank, gpio);
1374 }
1375
1376 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1377 {
1378 struct gpio_bank *bank;
1379 unsigned long flags;
1380
1381 bank = container_of(chip, struct gpio_bank, chip);
1382 spin_lock_irqsave(&bank->lock, flags);
1383 _set_gpio_dataout(bank, offset, value);
1384 _set_gpio_direction(bank, offset, 0);
1385 spin_unlock_irqrestore(&bank->lock, flags);
1386 return 0;
1387 }
1388
1389 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1390 unsigned debounce)
1391 {
1392 struct gpio_bank *bank;
1393 unsigned long flags;
1394
1395 bank = container_of(chip, struct gpio_bank, chip);
1396
1397 if (!bank->dbck) {
1398 bank->dbck = clk_get(bank->dev, "dbclk");
1399 if (IS_ERR(bank->dbck))
1400 dev_err(bank->dev, "Could not get gpio dbck\n");
1401 }
1402
1403 spin_lock_irqsave(&bank->lock, flags);
1404 _set_gpio_debounce(bank, offset, debounce);
1405 spin_unlock_irqrestore(&bank->lock, flags);
1406
1407 return 0;
1408 }
1409
1410 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1411 {
1412 struct gpio_bank *bank;
1413 unsigned long flags;
1414
1415 bank = container_of(chip, struct gpio_bank, chip);
1416 spin_lock_irqsave(&bank->lock, flags);
1417 _set_gpio_dataout(bank, offset, value);
1418 spin_unlock_irqrestore(&bank->lock, flags);
1419 }
1420
1421 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1422 {
1423 struct gpio_bank *bank;
1424
1425 bank = container_of(chip, struct gpio_bank, chip);
1426 return bank->virtual_irq_start + offset;
1427 }
1428
1429 /*---------------------------------------------------------------------*/
1430
1431 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1432 {
1433 u32 rev;
1434
1435 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1436 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1437 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1438 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1439 else if (cpu_is_omap44xx())
1440 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1441 else
1442 return;
1443
1444 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1445 (rev >> 4) & 0x0f, rev & 0x0f);
1446 }
1447
1448 /* This lock class tells lockdep that GPIO irqs are in a different
1449 * category than their parents, so it won't report false recursion.
1450 */
1451 static struct lock_class_key gpio_lock_class;
1452
1453 static inline int init_gpio_info(struct platform_device *pdev)
1454 {
1455 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1456 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1457 GFP_KERNEL);
1458 if (!gpio_bank) {
1459 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1460 return -ENOMEM;
1461 }
1462 return 0;
1463 }
1464
1465 /* TODO: Cleanup cpu_is_* checks */
1466 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1467 {
1468 if (cpu_class_is_omap2()) {
1469 if (cpu_is_omap44xx()) {
1470 __raw_writel(0xffffffff, bank->base +
1471 OMAP4_GPIO_IRQSTATUSCLR0);
1472 __raw_writel(0x00000000, bank->base +
1473 OMAP4_GPIO_DEBOUNCENABLE);
1474 /* Initialize interface clk ungated, module enabled */
1475 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1476 } else if (cpu_is_omap34xx()) {
1477 __raw_writel(0x00000000, bank->base +
1478 OMAP24XX_GPIO_IRQENABLE1);
1479 __raw_writel(0xffffffff, bank->base +
1480 OMAP24XX_GPIO_IRQSTATUS1);
1481 __raw_writel(0x00000000, bank->base +
1482 OMAP24XX_GPIO_DEBOUNCE_EN);
1483
1484 /* Initialize interface clk ungated, module enabled */
1485 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1486 } else if (cpu_is_omap24xx()) {
1487 static const u32 non_wakeup_gpios[] = {
1488 0xe203ffc0, 0x08700040
1489 };
1490 if (id < ARRAY_SIZE(non_wakeup_gpios))
1491 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1492 }
1493 } else if (cpu_class_is_omap1()) {
1494 if (bank_is_mpuio(bank))
1495 __raw_writew(0xffff, bank->base +
1496 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1497 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1498 __raw_writew(0xffff, bank->base
1499 + OMAP1510_GPIO_INT_MASK);
1500 __raw_writew(0x0000, bank->base
1501 + OMAP1510_GPIO_INT_STATUS);
1502 }
1503 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1504 __raw_writew(0x0000, bank->base
1505 + OMAP1610_GPIO_IRQENABLE1);
1506 __raw_writew(0xffff, bank->base
1507 + OMAP1610_GPIO_IRQSTATUS1);
1508 __raw_writew(0x0014, bank->base
1509 + OMAP1610_GPIO_SYSCONFIG);
1510
1511 /*
1512 * Enable system clock for GPIO module.
1513 * The CAM_CLK_CTRL *is* really the right place.
1514 */
1515 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1516 ULPD_CAM_CLK_CTRL);
1517 }
1518 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1519 __raw_writel(0xffffffff, bank->base
1520 + OMAP7XX_GPIO_INT_MASK);
1521 __raw_writel(0x00000000, bank->base
1522 + OMAP7XX_GPIO_INT_STATUS);
1523 }
1524 }
1525 }
1526
1527 static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1528 {
1529 int j;
1530 static int gpio;
1531
1532 bank->mod_usage = 0;
1533 /*
1534 * REVISIT eventually switch from OMAP-specific gpio structs
1535 * over to the generic ones
1536 */
1537 bank->chip.request = omap_gpio_request;
1538 bank->chip.free = omap_gpio_free;
1539 bank->chip.direction_input = gpio_input;
1540 bank->chip.get = gpio_get;
1541 bank->chip.direction_output = gpio_output;
1542 bank->chip.set_debounce = gpio_debounce;
1543 bank->chip.set = gpio_set;
1544 bank->chip.to_irq = gpio_2irq;
1545 if (bank_is_mpuio(bank)) {
1546 bank->chip.label = "mpuio";
1547 #ifdef CONFIG_ARCH_OMAP16XX
1548 bank->chip.dev = &omap_mpuio_device.dev;
1549 #endif
1550 bank->chip.base = OMAP_MPUIO(0);
1551 } else {
1552 bank->chip.label = "gpio";
1553 bank->chip.base = gpio;
1554 gpio += bank_width;
1555 }
1556 bank->chip.ngpio = bank_width;
1557
1558 gpiochip_add(&bank->chip);
1559
1560 for (j = bank->virtual_irq_start;
1561 j < bank->virtual_irq_start + bank_width; j++) {
1562 irq_set_lockdep_class(j, &gpio_lock_class);
1563 irq_set_chip_data(j, bank);
1564 if (bank_is_mpuio(bank))
1565 irq_set_chip(j, &mpuio_irq_chip);
1566 else
1567 irq_set_chip(j, &gpio_irq_chip);
1568 irq_set_handler(j, handle_simple_irq);
1569 set_irq_flags(j, IRQF_VALID);
1570 }
1571 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1572 irq_set_handler_data(bank->irq, bank);
1573 }
1574
1575 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1576 {
1577 static int gpio_init_done;
1578 struct omap_gpio_platform_data *pdata;
1579 struct resource *res;
1580 int id;
1581 struct gpio_bank *bank;
1582
1583 if (!pdev->dev.platform_data)
1584 return -EINVAL;
1585
1586 pdata = pdev->dev.platform_data;
1587
1588 if (!gpio_init_done) {
1589 int ret;
1590
1591 ret = init_gpio_info(pdev);
1592 if (ret)
1593 return ret;
1594 }
1595
1596 id = pdev->id;
1597 bank = &gpio_bank[id];
1598
1599 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1600 if (unlikely(!res)) {
1601 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1602 return -ENODEV;
1603 }
1604
1605 bank->irq = res->start;
1606 bank->virtual_irq_start = pdata->virtual_irq_start;
1607 bank->method = pdata->bank_type;
1608 bank->dev = &pdev->dev;
1609 bank->dbck_flag = pdata->dbck_flag;
1610 bank->stride = pdata->bank_stride;
1611 bank_width = pdata->bank_width;
1612
1613 spin_lock_init(&bank->lock);
1614
1615 /* Static mapping, never released */
1616 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1617 if (unlikely(!res)) {
1618 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1619 return -ENODEV;
1620 }
1621
1622 bank->base = ioremap(res->start, resource_size(res));
1623 if (!bank->base) {
1624 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1625 return -ENOMEM;
1626 }
1627
1628 pm_runtime_enable(bank->dev);
1629 pm_runtime_get_sync(bank->dev);
1630
1631 omap_gpio_mod_init(bank, id);
1632 omap_gpio_chip_init(bank);
1633 omap_gpio_show_rev(bank);
1634
1635 if (!gpio_init_done)
1636 gpio_init_done = 1;
1637
1638 return 0;
1639 }
1640
1641 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1642 static int omap_gpio_suspend(void)
1643 {
1644 int i;
1645
1646 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1647 return 0;
1648
1649 for (i = 0; i < gpio_bank_count; i++) {
1650 struct gpio_bank *bank = &gpio_bank[i];
1651 void __iomem *wake_status;
1652 void __iomem *wake_clear;
1653 void __iomem *wake_set;
1654 unsigned long flags;
1655
1656 switch (bank->method) {
1657 #ifdef CONFIG_ARCH_OMAP16XX
1658 case METHOD_GPIO_1610:
1659 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1660 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1661 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1662 break;
1663 #endif
1664 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1665 case METHOD_GPIO_24XX:
1666 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1667 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1668 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1669 break;
1670 #endif
1671 #ifdef CONFIG_ARCH_OMAP4
1672 case METHOD_GPIO_44XX:
1673 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1674 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1675 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1676 break;
1677 #endif
1678 default:
1679 continue;
1680 }
1681
1682 spin_lock_irqsave(&bank->lock, flags);
1683 bank->saved_wakeup = __raw_readl(wake_status);
1684 __raw_writel(0xffffffff, wake_clear);
1685 __raw_writel(bank->suspend_wakeup, wake_set);
1686 spin_unlock_irqrestore(&bank->lock, flags);
1687 }
1688
1689 return 0;
1690 }
1691
1692 static void omap_gpio_resume(void)
1693 {
1694 int i;
1695
1696 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1697 return;
1698
1699 for (i = 0; i < gpio_bank_count; i++) {
1700 struct gpio_bank *bank = &gpio_bank[i];
1701 void __iomem *wake_clear;
1702 void __iomem *wake_set;
1703 unsigned long flags;
1704
1705 switch (bank->method) {
1706 #ifdef CONFIG_ARCH_OMAP16XX
1707 case METHOD_GPIO_1610:
1708 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1709 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1710 break;
1711 #endif
1712 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1713 case METHOD_GPIO_24XX:
1714 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1715 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1716 break;
1717 #endif
1718 #ifdef CONFIG_ARCH_OMAP4
1719 case METHOD_GPIO_44XX:
1720 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1721 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1722 break;
1723 #endif
1724 default:
1725 continue;
1726 }
1727
1728 spin_lock_irqsave(&bank->lock, flags);
1729 __raw_writel(0xffffffff, wake_clear);
1730 __raw_writel(bank->saved_wakeup, wake_set);
1731 spin_unlock_irqrestore(&bank->lock, flags);
1732 }
1733 }
1734
1735 static struct syscore_ops omap_gpio_syscore_ops = {
1736 .suspend = omap_gpio_suspend,
1737 .resume = omap_gpio_resume,
1738 };
1739
1740 #endif
1741
1742 #ifdef CONFIG_ARCH_OMAP2PLUS
1743
1744 static int workaround_enabled;
1745
1746 void omap2_gpio_prepare_for_idle(int off_mode)
1747 {
1748 int i, c = 0;
1749 int min = 0;
1750
1751 if (cpu_is_omap34xx())
1752 min = 1;
1753
1754 for (i = min; i < gpio_bank_count; i++) {
1755 struct gpio_bank *bank = &gpio_bank[i];
1756 u32 l1 = 0, l2 = 0;
1757 int j;
1758
1759 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1760 clk_disable(bank->dbck);
1761
1762 if (!off_mode)
1763 continue;
1764
1765 /* If going to OFF, remove triggering for all
1766 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1767 * generated. See OMAP2420 Errata item 1.101. */
1768 if (!(bank->enabled_non_wakeup_gpios))
1769 continue;
1770
1771 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1772 bank->saved_datain = __raw_readl(bank->base +
1773 OMAP24XX_GPIO_DATAIN);
1774 l1 = __raw_readl(bank->base +
1775 OMAP24XX_GPIO_FALLINGDETECT);
1776 l2 = __raw_readl(bank->base +
1777 OMAP24XX_GPIO_RISINGDETECT);
1778 }
1779
1780 if (cpu_is_omap44xx()) {
1781 bank->saved_datain = __raw_readl(bank->base +
1782 OMAP4_GPIO_DATAIN);
1783 l1 = __raw_readl(bank->base +
1784 OMAP4_GPIO_FALLINGDETECT);
1785 l2 = __raw_readl(bank->base +
1786 OMAP4_GPIO_RISINGDETECT);
1787 }
1788
1789 bank->saved_fallingdetect = l1;
1790 bank->saved_risingdetect = l2;
1791 l1 &= ~bank->enabled_non_wakeup_gpios;
1792 l2 &= ~bank->enabled_non_wakeup_gpios;
1793
1794 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1795 __raw_writel(l1, bank->base +
1796 OMAP24XX_GPIO_FALLINGDETECT);
1797 __raw_writel(l2, bank->base +
1798 OMAP24XX_GPIO_RISINGDETECT);
1799 }
1800
1801 if (cpu_is_omap44xx()) {
1802 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1803 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1804 }
1805
1806 c++;
1807 }
1808 if (!c) {
1809 workaround_enabled = 0;
1810 return;
1811 }
1812 workaround_enabled = 1;
1813 }
1814
1815 void omap2_gpio_resume_after_idle(void)
1816 {
1817 int i;
1818 int min = 0;
1819
1820 if (cpu_is_omap34xx())
1821 min = 1;
1822 for (i = min; i < gpio_bank_count; i++) {
1823 struct gpio_bank *bank = &gpio_bank[i];
1824 u32 l = 0, gen, gen0, gen1;
1825 int j;
1826
1827 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1828 clk_enable(bank->dbck);
1829
1830 if (!workaround_enabled)
1831 continue;
1832
1833 if (!(bank->enabled_non_wakeup_gpios))
1834 continue;
1835
1836 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1837 __raw_writel(bank->saved_fallingdetect,
1838 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1839 __raw_writel(bank->saved_risingdetect,
1840 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1841 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1842 }
1843
1844 if (cpu_is_omap44xx()) {
1845 __raw_writel(bank->saved_fallingdetect,
1846 bank->base + OMAP4_GPIO_FALLINGDETECT);
1847 __raw_writel(bank->saved_risingdetect,
1848 bank->base + OMAP4_GPIO_RISINGDETECT);
1849 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1850 }
1851
1852 /* Check if any of the non-wakeup interrupt GPIOs have changed
1853 * state. If so, generate an IRQ by software. This is
1854 * horribly racy, but it's the best we can do to work around
1855 * this silicon bug. */
1856 l ^= bank->saved_datain;
1857 l &= bank->enabled_non_wakeup_gpios;
1858
1859 /*
1860 * No need to generate IRQs for the rising edge for gpio IRQs
1861 * configured with falling edge only; and vice versa.
1862 */
1863 gen0 = l & bank->saved_fallingdetect;
1864 gen0 &= bank->saved_datain;
1865
1866 gen1 = l & bank->saved_risingdetect;
1867 gen1 &= ~(bank->saved_datain);
1868
1869 /* FIXME: Consider GPIO IRQs with level detections properly! */
1870 gen = l & (~(bank->saved_fallingdetect) &
1871 ~(bank->saved_risingdetect));
1872 /* Consider all GPIO IRQs needed to be updated */
1873 gen |= gen0 | gen1;
1874
1875 if (gen) {
1876 u32 old0, old1;
1877
1878 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1879 old0 = __raw_readl(bank->base +
1880 OMAP24XX_GPIO_LEVELDETECT0);
1881 old1 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT1);
1883 __raw_writel(old0 | gen, bank->base +
1884 OMAP24XX_GPIO_LEVELDETECT0);
1885 __raw_writel(old1 | gen, bank->base +
1886 OMAP24XX_GPIO_LEVELDETECT1);
1887 __raw_writel(old0, bank->base +
1888 OMAP24XX_GPIO_LEVELDETECT0);
1889 __raw_writel(old1, bank->base +
1890 OMAP24XX_GPIO_LEVELDETECT1);
1891 }
1892
1893 if (cpu_is_omap44xx()) {
1894 old0 = __raw_readl(bank->base +
1895 OMAP4_GPIO_LEVELDETECT0);
1896 old1 = __raw_readl(bank->base +
1897 OMAP4_GPIO_LEVELDETECT1);
1898 __raw_writel(old0 | l, bank->base +
1899 OMAP4_GPIO_LEVELDETECT0);
1900 __raw_writel(old1 | l, bank->base +
1901 OMAP4_GPIO_LEVELDETECT1);
1902 __raw_writel(old0, bank->base +
1903 OMAP4_GPIO_LEVELDETECT0);
1904 __raw_writel(old1, bank->base +
1905 OMAP4_GPIO_LEVELDETECT1);
1906 }
1907 }
1908 }
1909
1910 }
1911
1912 #endif
1913
1914 #ifdef CONFIG_ARCH_OMAP3
1915 /* save the registers of bank 2-6 */
1916 void omap_gpio_save_context(void)
1917 {
1918 int i;
1919
1920 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1921 for (i = 1; i < gpio_bank_count; i++) {
1922 struct gpio_bank *bank = &gpio_bank[i];
1923 gpio_context[i].irqenable1 =
1924 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1925 gpio_context[i].irqenable2 =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1927 gpio_context[i].wake_en =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1929 gpio_context[i].ctrl =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1931 gpio_context[i].oe =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1933 gpio_context[i].leveldetect0 =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1935 gpio_context[i].leveldetect1 =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1937 gpio_context[i].risingdetect =
1938 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1939 gpio_context[i].fallingdetect =
1940 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1941 gpio_context[i].dataout =
1942 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1943 }
1944 }
1945
1946 /* restore the required registers of bank 2-6 */
1947 void omap_gpio_restore_context(void)
1948 {
1949 int i;
1950
1951 for (i = 1; i < gpio_bank_count; i++) {
1952 struct gpio_bank *bank = &gpio_bank[i];
1953 __raw_writel(gpio_context[i].irqenable1,
1954 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1955 __raw_writel(gpio_context[i].irqenable2,
1956 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1957 __raw_writel(gpio_context[i].wake_en,
1958 bank->base + OMAP24XX_GPIO_WAKE_EN);
1959 __raw_writel(gpio_context[i].ctrl,
1960 bank->base + OMAP24XX_GPIO_CTRL);
1961 __raw_writel(gpio_context[i].oe,
1962 bank->base + OMAP24XX_GPIO_OE);
1963 __raw_writel(gpio_context[i].leveldetect0,
1964 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1965 __raw_writel(gpio_context[i].leveldetect1,
1966 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1967 __raw_writel(gpio_context[i].risingdetect,
1968 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1969 __raw_writel(gpio_context[i].fallingdetect,
1970 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1971 __raw_writel(gpio_context[i].dataout,
1972 bank->base + OMAP24XX_GPIO_DATAOUT);
1973 }
1974 }
1975 #endif
1976
1977 static struct platform_driver omap_gpio_driver = {
1978 .probe = omap_gpio_probe,
1979 .driver = {
1980 .name = "omap_gpio",
1981 },
1982 };
1983
1984 /*
1985 * gpio driver register needs to be done before
1986 * machine_init functions access gpio APIs.
1987 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1988 */
1989 static int __init omap_gpio_drv_reg(void)
1990 {
1991 return platform_driver_register(&omap_gpio_driver);
1992 }
1993 postcore_initcall(omap_gpio_drv_reg);
1994
1995 static int __init omap_gpio_sysinit(void)
1996 {
1997 mpuio_init();
1998
1999 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2000 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2001 register_syscore_ops(&omap_gpio_syscore_ops);
2002 #endif
2003
2004 return 0;
2005 }
2006
2007 arch_initcall(omap_gpio_sysinit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree