drivers/i2c/busses/i2c-i801.c

   1 /*
   2     i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
   3               monitoring
   4     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   5     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   6     <mdsxyz123@yahoo.com>
   7     Copyright (C) 2007, 2008   Jean Delvare <khali@linux-fr.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   Tolapai               0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46
  47   Features supported by this driver:
  48   Software PEC                     no
  49   Hardware PEC                     yes
  50   Block buffer                     yes
  51   Block process call transaction   no
  52   I2C block read transaction       yes  (doesn't use the block buffer)
  53
  54   See the file Documentation/i2c/busses/i2c-i801 for details.
  55 */
  56
  57 /* Note: we assume there can only be one I801, with one SMBus interface */
  58
  59 #include <linux/module.h>
  60 #include <linux/pci.h>
  61 #include <linux/kernel.h>
  62 #include <linux/stddef.h>
  63 #include <linux/delay.h>
  64 #include <linux/ioport.h>
  65 #include <linux/init.h>
  66 #include <linux/i2c.h>
  67 #include <linux/acpi.h>
  68 #include <asm/io.h>
  69
  70 /* I801 SMBus address offsets */
  71 #define SMBHSTSTS       (0 + i801_smba)
  72 #define SMBHSTCNT       (2 + i801_smba)
  73 #define SMBHSTCMD       (3 + i801_smba)
  74 #define SMBHSTADD       (4 + i801_smba)
  75 #define SMBHSTDAT0      (5 + i801_smba)
  76 #define SMBHSTDAT1      (6 + i801_smba)
  77 #define SMBBLKDAT       (7 + i801_smba)
  78 #define SMBPEC          (8 + i801_smba)         /* ICH3 and later */
  79 #define SMBAUXSTS       (12 + i801_smba)        /* ICH4 and later */
  80 #define SMBAUXCTL       (13 + i801_smba)        /* ICH4 and later */
  81
  82 /* PCI Address Constants */
  83 #define SMBBAR          4
  84 #define SMBHSTCFG       0x040
  85
  86 /* Host configuration bits for SMBHSTCFG */
  87 #define SMBHSTCFG_HST_EN        1
  88 #define SMBHSTCFG_SMB_SMI_EN    2
  89 #define SMBHSTCFG_I2C_EN        4
  90
  91 /* Auxillary control register bits, ICH4+ only */
  92 #define SMBAUXCTL_CRC           1
  93 #define SMBAUXCTL_E32B          2
  94
  95 /* kill bit for SMBHSTCNT */
  96 #define SMBHSTCNT_KILL          2
  97
  98 /* Other settings */
  99 #define MAX_TIMEOUT             100
 100 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 101
 102 /* I801 command constants */
 103 #define I801_QUICK              0x00
 104 #define I801_BYTE               0x04
 105 #define I801_BYTE_DATA          0x08
 106 #define I801_WORD_DATA          0x0C
 107 #define I801_PROC_CALL          0x10    /* unimplemented */
 108 #define I801_BLOCK_DATA         0x14
 109 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 110 #define I801_BLOCK_LAST         0x34
 111 #define I801_I2C_BLOCK_LAST     0x38    /* ICH5 and later */
 112 #define I801_START              0x40
 113 #define I801_PEC_EN             0x80    /* ICH3 and later */
 114
 115 /* I801 Hosts Status register bits */
 116 #define SMBHSTSTS_BYTE_DONE     0x80
 117 #define SMBHSTSTS_INUSE_STS     0x40
 118 #define SMBHSTSTS_SMBALERT_STS  0x20
 119 #define SMBHSTSTS_FAILED        0x10
 120 #define SMBHSTSTS_BUS_ERR       0x08
 121 #define SMBHSTSTS_DEV_ERR       0x04
 122 #define SMBHSTSTS_INTR          0x02
 123 #define SMBHSTSTS_HOST_BUSY     0x01
 124
 125 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 126                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 127                                  SMBHSTSTS_INTR)
 128
 129 static unsigned long i801_smba;
 130 static unsigned char i801_original_hstcfg;
 131 static struct pci_driver i801_driver;
 132 static struct pci_dev *I801_dev;
 133
 134 #define FEATURE_SMBUS_PEC       (1 << 0)
 135 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 136 #define FEATURE_BLOCK_PROC      (1 << 2)
 137 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 138 static unsigned int i801_features;
 139
 140 /* Make sure the SMBus host is ready to start transmitting.
 141    Return 0 if it is, -EBUSY if it is not. */
 142 static int i801_check_pre(void)
 143 {
 144         int status;
 145
 146         status = inb_p(SMBHSTSTS);
 147         if (status & SMBHSTSTS_HOST_BUSY) {
 148                 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
 149                 return -EBUSY;
 150         }
 151
 152         status &= STATUS_FLAGS;
 153         if (status) {
 154                 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
 155                         status);
 156                 outb_p(status, SMBHSTSTS);
 157                 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
 158                 if (status) {
 159                         dev_err(&I801_dev->dev,
 160                                 "Failed clearing status flags (%02x)\n",
 161                                 status);
 162                         return -EBUSY;
 163                 }
 164         }
 165
 166         return 0;
 167 }
 168
 169 /* Convert the status register to an error code, and clear it. */
 170 static int i801_check_post(int status, int timeout)
 171 {
 172         int result = 0;
 173
 174         /* If the SMBus is still busy, we give up */
 175         if (timeout) {
 176                 dev_err(&I801_dev->dev, "Transaction timeout\n");
 177                 /* try to stop the current command */
 178                 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
 179                 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
 180                 msleep(1);
 181                 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
 182
 183                 /* Check if it worked */
 184                 status = inb_p(SMBHSTSTS);
 185                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 186                     !(status & SMBHSTSTS_FAILED))
 187                         dev_err(&I801_dev->dev,
 188                                 "Failed terminating the transaction\n");
 189                 outb_p(STATUS_FLAGS, SMBHSTSTS);
 190                 return -ETIMEDOUT;
 191         }
 192
 193         if (status & SMBHSTSTS_FAILED) {
 194                 result = -EIO;
 195                 dev_err(&I801_dev->dev, "Transaction failed\n");
 196         }
 197         if (status & SMBHSTSTS_DEV_ERR) {
 198                 result = -ENXIO;
 199                 dev_dbg(&I801_dev->dev, "No response\n");
 200         }
 201         if (status & SMBHSTSTS_BUS_ERR) {
 202                 result = -EAGAIN;
 203                 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
 204         }
 205
 206         if (result) {
 207                 /* Clear error flags */
 208                 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
 209                 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
 210                 if (status) {
 211                         dev_warn(&I801_dev->dev, "Failed clearing status "
 212                                  "flags at end of transaction (%02x)\n",
 213                                  status);
 214                 }
 215         }
 216
 217         return result;
 218 }
 219
 220 static int i801_transaction(int xact)
 221 {
 222         int status;
 223         int result;
 224         int timeout = 0;
 225
 226         result = i801_check_pre();
 227         if (result < 0)
 228                 return result;
 229
 230         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 231          * INTREN, SMBSCMD are passed in xact */
 232         outb_p(xact | I801_START, SMBHSTCNT);
 233
 234         /* We will always wait for a fraction of a second! */
 235         do {
 236                 msleep(1);
 237                 status = inb_p(SMBHSTSTS);
 238         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
 239
 240         result = i801_check_post(status, timeout >= MAX_TIMEOUT);
 241         if (result < 0)
 242                 return result;
 243
 244         outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
 245         return 0;
 246 }
 247
 248 /* wait for INTR bit as advised by Intel */
 249 static void i801_wait_hwpec(void)
 250 {
 251         int timeout = 0;
 252         int status;
 253
 254         do {
 255                 msleep(1);
 256                 status = inb_p(SMBHSTSTS);
 257         } while ((!(status & SMBHSTSTS_INTR))
 258                  && (timeout++ < MAX_TIMEOUT));
 259
 260         if (timeout >= MAX_TIMEOUT) {
 261                 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
 262         }
 263         outb_p(status, SMBHSTSTS);
 264 }
 265
 266 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
 267                                            char read_write, int hwpec)
 268 {
 269         int i, len;
 270         int status;
 271
 272         inb_p(SMBHSTCNT); /* reset the data buffer index */
 273
 274         /* Use 32-byte buffer to process this transaction */
 275         if (read_write == I2C_SMBUS_WRITE) {
 276                 len = data->block[0];
 277                 outb_p(len, SMBHSTDAT0);
 278                 for (i = 0; i < len; i++)
 279                         outb_p(data->block[i+1], SMBBLKDAT);
 280         }
 281
 282         status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
 283                                   I801_PEC_EN * hwpec);
 284         if (status)
 285                 return status;
 286
 287         if (read_write == I2C_SMBUS_READ) {
 288                 len = inb_p(SMBHSTDAT0);
 289                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 290                         return -EPROTO;
 291
 292                 data->block[0] = len;
 293                 for (i = 0; i < len; i++)
 294                         data->block[i + 1] = inb_p(SMBBLKDAT);
 295         }
 296         return 0;
 297 }
 298
 299 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
 300                                                char read_write, int command,
 301                                                int hwpec)
 302 {
 303         int i, len;
 304         int smbcmd;
 305         int status;
 306         int result;
 307         int timeout;
 308
 309         result = i801_check_pre();
 310         if (result < 0)
 311                 return result;
 312
 313         len = data->block[0];
 314
 315         if (read_write == I2C_SMBUS_WRITE) {
 316                 outb_p(len, SMBHSTDAT0);
 317                 outb_p(data->block[1], SMBBLKDAT);
 318         }
 319
 320         for (i = 1; i <= len; i++) {
 321                 if (i == len && read_write == I2C_SMBUS_READ) {
 322                         if (command == I2C_SMBUS_I2C_BLOCK_DATA)
 323                                 smbcmd = I801_I2C_BLOCK_LAST;
 324                         else
 325                                 smbcmd = I801_BLOCK_LAST;
 326                 } else {
 327                         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 328                          && read_write == I2C_SMBUS_READ)
 329                                 smbcmd = I801_I2C_BLOCK_DATA;
 330                         else
 331                                 smbcmd = I801_BLOCK_DATA;
 332                 }
 333                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
 334
 335                 if (i == 1)
 336                         outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
 337
 338                 /* We will always wait for a fraction of a second! */
 339                 timeout = 0;
 340                 do {
 341                         msleep(1);
 342                         status = inb_p(SMBHSTSTS);
 343                 }
 344                 while ((!(status & SMBHSTSTS_BYTE_DONE))
 345                        && (timeout++ < MAX_TIMEOUT));
 346
 347                 result = i801_check_post(status, timeout >= MAX_TIMEOUT);
 348                 if (result < 0)
 349                         return result;
 350
 351                 if (i == 1 && read_write == I2C_SMBUS_READ
 352                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 353                         len = inb_p(SMBHSTDAT0);
 354                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 355                                 dev_err(&I801_dev->dev,
 356                                         "Illegal SMBus block read size %d\n",
 357                                         len);
 358                                 /* Recover */
 359                                 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
 360                                         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
 361                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
 362                                 return -EPROTO;
 363                         }
 364                         data->block[0] = len;
 365                 }
 366
 367                 /* Retrieve/store value in SMBBLKDAT */
 368                 if (read_write == I2C_SMBUS_READ)
 369                         data->block[i] = inb_p(SMBBLKDAT);
 370                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 371                         outb_p(data->block[i+1], SMBBLKDAT);
 372
 373                 /* signals SMBBLKDAT ready */
 374                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int i801_set_block_buffer_mode(void)
 381 {
 382         outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
 383         if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
 384                 return -EIO;
 385         return 0;
 386 }
 387
 388 /* Block transaction function */
 389 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
 390                                   int command, int hwpec)
 391 {
 392         int result = 0;
 393         unsigned char hostc;
 394
 395         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 396                 if (read_write == I2C_SMBUS_WRITE) {
 397                         /* set I2C_EN bit in configuration register */
 398                         pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
 399                         pci_write_config_byte(I801_dev, SMBHSTCFG,
 400                                               hostc | SMBHSTCFG_I2C_EN);
 401                 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
 402                         dev_err(&I801_dev->dev,
 403                                 "I2C block read is unsupported!\n");
 404                         return -EOPNOTSUPP;
 405                 }
 406         }
 407
 408         if (read_write == I2C_SMBUS_WRITE
 409          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 410                 if (data->block[0] < 1)
 411                         data->block[0] = 1;
 412                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 413                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 414         } else {
 415                 data->block[0] = 32;    /* max for SMBus block reads */
 416         }
 417
 418         if ((i801_features & FEATURE_BLOCK_BUFFER)
 419          && !(command == I2C_SMBUS_I2C_BLOCK_DATA
 420               && read_write == I2C_SMBUS_READ)
 421          && i801_set_block_buffer_mode() == 0)
 422                 result = i801_block_transaction_by_block(data, read_write,
 423                                                          hwpec);
 424         else
 425                 result = i801_block_transaction_byte_by_byte(data, read_write,
 426                                                              command, hwpec);
 427
 428         if (result == 0 && hwpec)
 429                 i801_wait_hwpec();
 430
 431         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 432          && read_write == I2C_SMBUS_WRITE) {
 433                 /* restore saved configuration register value */
 434                 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
 435         }
 436         return result;
 437 }
 438
 439 /* Return negative errno on error. */
 440 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
 441                        unsigned short flags, char read_write, u8 command,
 442                        int size, union i2c_smbus_data * data)
 443 {
 444         int hwpec;
 445         int block = 0;
 446         int ret, xact = 0;
 447
 448         hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 449                 && size != I2C_SMBUS_QUICK
 450                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 451
 452         switch (size) {
 453         case I2C_SMBUS_QUICK:
 454                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 455                        SMBHSTADD);
 456                 xact = I801_QUICK;
 457                 break;
 458         case I2C_SMBUS_BYTE:
 459                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 460                        SMBHSTADD);
 461                 if (read_write == I2C_SMBUS_WRITE)
 462                         outb_p(command, SMBHSTCMD);
 463                 xact = I801_BYTE;
 464                 break;
 465         case I2C_SMBUS_BYTE_DATA:
 466                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 467                        SMBHSTADD);
 468                 outb_p(command, SMBHSTCMD);
 469                 if (read_write == I2C_SMBUS_WRITE)
 470                         outb_p(data->byte, SMBHSTDAT0);
 471                 xact = I801_BYTE_DATA;
 472                 break;
 473         case I2C_SMBUS_WORD_DATA:
 474                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 475                        SMBHSTADD);
 476                 outb_p(command, SMBHSTCMD);
 477                 if (read_write == I2C_SMBUS_WRITE) {
 478                         outb_p(data->word & 0xff, SMBHSTDAT0);
 479                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 480                 }
 481                 xact = I801_WORD_DATA;
 482                 break;
 483         case I2C_SMBUS_BLOCK_DATA:
 484                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 485                        SMBHSTADD);
 486                 outb_p(command, SMBHSTCMD);
 487                 block = 1;
 488                 break;
 489         case I2C_SMBUS_I2C_BLOCK_DATA:
 490                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 491                  * bit should be cleared here, even when reading */
 492                 outb_p((addr & 0x7f) << 1, SMBHSTADD);
 493                 if (read_write == I2C_SMBUS_READ) {
 494                         /* NB: page 240 of ICH5 datasheet also shows
 495                          * that DATA1 is the cmd field when reading */
 496                         outb_p(command, SMBHSTDAT1);
 497                 } else
 498                         outb_p(command, SMBHSTCMD);
 499                 block = 1;
 500                 break;
 501         default:
 502                 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
 503                 return -EOPNOTSUPP;
 504         }
 505
 506         if (hwpec)      /* enable/disable hardware PEC */
 507                 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
 508         else
 509                 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
 510
 511         if(block)
 512                 ret = i801_block_transaction(data, read_write, size, hwpec);
 513         else
 514                 ret = i801_transaction(xact | ENABLE_INT9);
 515
 516         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 517            time, so we forcibly disable it after every transaction. Turn off
 518            E32B for the same reason. */
 519         if (hwpec || block)
 520                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 521                        SMBAUXCTL);
 522
 523         if(block)
 524                 return ret;
 525         if(ret)
 526                 return ret;
 527         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 528                 return 0;
 529
 530         switch (xact & 0x7f) {
 531         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 532         case I801_BYTE_DATA:
 533                 data->byte = inb_p(SMBHSTDAT0);
 534                 break;
 535         case I801_WORD_DATA:
 536                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 537                 break;
 538         }
 539         return 0;
 540 }
 541
 542
 543 static u32 i801_func(struct i2c_adapter *adapter)
 544 {
 545         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 546                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 547                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 548                ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 549                ((i801_features & FEATURE_I2C_BLOCK_READ) ?
 550                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 551 }
 552
 553 static const struct i2c_algorithm smbus_algorithm = {
 554         .smbus_xfer     = i801_access,
 555         .functionality  = i801_func,
 556 };
 557
 558 static struct i2c_adapter i801_adapter = {
 559         .owner          = THIS_MODULE,
 560         .id             = I2C_HW_SMBUS_I801,
 561         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 562         .algo           = &smbus_algorithm,
 563 };
 564
 565 static struct pci_device_id i801_ids[] = {
 566         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 567         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 568         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 569         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 570         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 571         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 572         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 573         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 574         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 575         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 576         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 577         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 578         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
 579         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 580         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 581         { 0, }
 582 };
 583
 584 MODULE_DEVICE_TABLE (pci, i801_ids);
 585
 586 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
 587 {
 588         unsigned char temp;
 589         int err;
 590
 591         I801_dev = dev;
 592         i801_features = 0;
 593         switch (dev->device) {
 594         case PCI_DEVICE_ID_INTEL_82801EB_3:
 595         case PCI_DEVICE_ID_INTEL_ESB_4:
 596         case PCI_DEVICE_ID_INTEL_ICH6_16:
 597         case PCI_DEVICE_ID_INTEL_ICH7_17:
 598         case PCI_DEVICE_ID_INTEL_ESB2_17:
 599         case PCI_DEVICE_ID_INTEL_ICH8_5:
 600         case PCI_DEVICE_ID_INTEL_ICH9_6:
 601         case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
 602         case PCI_DEVICE_ID_INTEL_ICH10_4:
 603         case PCI_DEVICE_ID_INTEL_ICH10_5:
 604                 i801_features |= FEATURE_I2C_BLOCK_READ;
 605                 /* fall through */
 606         case PCI_DEVICE_ID_INTEL_82801DB_3:
 607                 i801_features |= FEATURE_SMBUS_PEC;
 608                 i801_features |= FEATURE_BLOCK_BUFFER;
 609                 break;
 610         }
 611
 612         err = pci_enable_device(dev);
 613         if (err) {
 614                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 615                         err);
 616                 goto exit;
 617         }
 618
 619         /* Determine the address of the SMBus area */
 620         i801_smba = pci_resource_start(dev, SMBBAR);
 621         if (!i801_smba) {
 622                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 623                         "upgrade BIOS\n");
 624                 err = -ENODEV;
 625                 goto exit;
 626         }
 627
 628         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 629         if (err)
 630                 goto exit;
 631
 632         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 633         if (err) {
 634                 dev_err(&dev->dev, "Failed to request SMBus region "
 635                         "0x%lx-0x%Lx\n", i801_smba,
 636                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 637                 goto exit;
 638         }
 639
 640         pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
 641         i801_original_hstcfg = temp;
 642         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 643         if (!(temp & SMBHSTCFG_HST_EN)) {
 644                 dev_info(&dev->dev, "Enabling SMBus device\n");
 645                 temp |= SMBHSTCFG_HST_EN;
 646         }
 647         pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
 648
 649         if (temp & SMBHSTCFG_SMB_SMI_EN)
 650                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 651         else
 652                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 653
 654         /* Clear special mode bits */
 655         if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 656                 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
 657                        SMBAUXCTL);
 658
 659         /* set up the sysfs linkage to our parent device */
 660         i801_adapter.dev.parent = &dev->dev;
 661
 662         snprintf(i801_adapter.name, sizeof(i801_adapter.name),
 663                 "SMBus I801 adapter at %04lx", i801_smba);
 664         err = i2c_add_adapter(&i801_adapter);
 665         if (err) {
 666                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 667                 goto exit_release;
 668         }
 669         return 0;
 670
 671 exit_release:
 672         pci_release_region(dev, SMBBAR);
 673 exit:
 674         return err;
 675 }
 676
 677 static void __devexit i801_remove(struct pci_dev *dev)
 678 {
 679         i2c_del_adapter(&i801_adapter);
 680         pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
 681         pci_release_region(dev, SMBBAR);
 682         /*
 683          * do not call pci_disable_device(dev) since it can cause hard hangs on
 684          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 685          */
 686 }
 687
 688 #ifdef CONFIG_PM
 689 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 690 {
 691         pci_save_state(dev);
 692         pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
 693         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 694         return 0;
 695 }
 696
 697 static int i801_resume(struct pci_dev *dev)
 698 {
 699         pci_set_power_state(dev, PCI_D0);
 700         pci_restore_state(dev);
 701         return pci_enable_device(dev);
 702 }
 703 #else
 704 #define i801_suspend NULL
 705 #define i801_resume NULL
 706 #endif
 707
 708 static struct pci_driver i801_driver = {
 709         .name           = "i801_smbus",
 710         .id_table       = i801_ids,
 711         .probe          = i801_probe,
 712         .remove         = __devexit_p(i801_remove),
 713         .suspend        = i801_suspend,
 714         .resume         = i801_resume,
 715 };
 716
 717 static int __init i2c_i801_init(void)
 718 {
 719         return pci_register_driver(&i801_driver);
 720 }
 721
 722 static void __exit i2c_i801_exit(void)
 723 {
 724         pci_unregister_driver(&i801_driver);
 725 }
 726
 727 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 728               "Jean Delvare <khali@linux-fr.org>");
 729 MODULE_DESCRIPTION("I801 SMBus driver");
 730 MODULE_LICENSE("GPL");
 731
 732 module_init(i2c_i801_init);
 733 module_exit(i2c_i801_exit);