2 * Copyright © 2009 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 #include <linux/i2c.h>
19 #include <linux/pm_runtime.h>
24 #include "psb_intel_drv.h"
25 #include "psb_intel_reg.h"
26 #include "psb_intel_display.h"
27 #include "psb_powermgmt.h"
29 struct psb_intel_range_t
{
34 struct psb_intel_range_t dot
, m
, p1
;
44 #define MRST_LIMIT_LVDS_100L 0
45 #define MRST_LIMIT_LVDS_83 1
46 #define MRST_LIMIT_LVDS_100 2
48 #define MRST_DOT_MIN 19750
49 #define MRST_DOT_MAX 120000
50 #define MRST_M_MIN_100L 20
51 #define MRST_M_MIN_100 10
52 #define MRST_M_MIN_83 12
53 #define MRST_M_MAX_100L 34
54 #define MRST_M_MAX_100 17
55 #define MRST_M_MAX_83 20
57 #define MRST_P1_MAX_0 7
58 #define MRST_P1_MAX_1 8
60 static const struct mrst_limit_t mrst_limits
[] = {
61 { /* MRST_LIMIT_LVDS_100L */
62 .dot
= {.min
= MRST_DOT_MIN
, .max
= MRST_DOT_MAX
},
63 .m
= {.min
= MRST_M_MIN_100L
, .max
= MRST_M_MAX_100L
},
64 .p1
= {.min
= MRST_P1_MIN
, .max
= MRST_P1_MAX_1
},
66 { /* MRST_LIMIT_LVDS_83L */
67 .dot
= {.min
= MRST_DOT_MIN
, .max
= MRST_DOT_MAX
},
68 .m
= {.min
= MRST_M_MIN_83
, .max
= MRST_M_MAX_83
},
69 .p1
= {.min
= MRST_P1_MIN
, .max
= MRST_P1_MAX_0
},
71 { /* MRST_LIMIT_LVDS_100 */
72 .dot
= {.min
= MRST_DOT_MIN
, .max
= MRST_DOT_MAX
},
73 .m
= {.min
= MRST_M_MIN_100
, .max
= MRST_M_MAX_100
},
74 .p1
= {.min
= MRST_P1_MIN
, .max
= MRST_P1_MAX_1
},
79 static const u32 mrst_m_converts
[] = {
80 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
81 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
82 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
85 static const struct mrst_limit_t
*mrst_limit(struct drm_crtc
*crtc
)
87 const struct mrst_limit_t
*limit
= NULL
;
88 struct drm_device
*dev
= crtc
->dev
;
89 DRM_DRIVER_PRIVATE_T
*dev_priv
= dev
->dev_private
;
91 if (psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)
92 || psb_intel_pipe_has_type(crtc
, INTEL_OUTPUT_MIPI
)) {
93 switch (dev_priv
->core_freq
) {
95 limit
= &mrst_limits
[MRST_LIMIT_LVDS_100L
];
98 limit
= &mrst_limits
[MRST_LIMIT_LVDS_83
];
101 limit
= &mrst_limits
[MRST_LIMIT_LVDS_100
];
106 PSB_DEBUG_ENTRY("mrst_limit Wrong display type.\n");
112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
113 static void mrst_clock(int refclk
, struct mrst_clock_t
*clock
)
115 clock
->dot
= (refclk
* clock
->m
) / (14 * clock
->p1
);
118 void mrstPrintPll(char *prefix
, struct mrst_clock_t
*clock
)
120 PSB_DEBUG_ENTRY("%s: dotclock = %d, m = %d, p1 = %d.\n",
121 prefix
, clock
->dot
, clock
->m
, clock
->p1
);
125 * Returns a set of divisors for the desired target clock with the given refclk,
126 * or FALSE. Divisor values are the actual divisors for
129 mrstFindBestPLL(struct drm_crtc
*crtc
, int target
, int refclk
,
130 struct mrst_clock_t
*best_clock
)
132 struct mrst_clock_t clock
;
133 const struct mrst_limit_t
*limit
= mrst_limit(crtc
);
136 memset(best_clock
, 0, sizeof(*best_clock
));
138 for (clock
.m
= limit
->m
.min
; clock
.m
<= limit
->m
.max
; clock
.m
++) {
139 for (clock
.p1
= limit
->p1
.min
; clock
.p1
<= limit
->p1
.max
;
143 mrst_clock(refclk
, &clock
);
145 this_err
= abs(clock
.dot
- target
);
146 if (this_err
< err
) {
152 DRM_DEBUG("mrstFindBestPLL err = %d.\n", err
);
154 return err
!= target
;
158 * Sets the power management mode of the pipe and plane.
160 * This code should probably grow support for turning the cursor off and back
161 * on appropriately at the same time as we're turning the pipe off/on.
163 static void mrst_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
165 struct drm_device
*dev
= crtc
->dev
;
166 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
167 int pipe
= psb_intel_crtc
->pipe
;
168 int dpll_reg
= (pipe
== 0) ? MRST_DPLL_A
: DPLL_B
;
169 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
170 int dspbase_reg
= (pipe
== 0) ? MRST_DSPABASE
: DSPBBASE
;
171 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
175 PSB_DEBUG_ENTRY("mode = %d, pipe = %d\n", mode
, pipe
);
177 if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
178 OSPM_UHB_FORCE_POWER_ON
))
181 /* XXX: When our outputs are all unaware of DPMS modes other than off
182 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
185 case DRM_MODE_DPMS_ON
:
186 case DRM_MODE_DPMS_STANDBY
:
187 case DRM_MODE_DPMS_SUSPEND
:
188 /* Enable the DPLL */
189 temp
= REG_READ(dpll_reg
);
190 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
191 REG_WRITE(dpll_reg
, temp
);
193 /* Wait for the clocks to stabilize. */
195 REG_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
197 /* Wait for the clocks to stabilize. */
199 REG_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
201 /* Wait for the clocks to stabilize. */
204 /* Enable the pipe */
205 temp
= REG_READ(pipeconf_reg
);
206 if ((temp
& PIPEACONF_ENABLE
) == 0)
207 REG_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
208 /* Enable the plane */
209 temp
= REG_READ(dspcntr_reg
);
210 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
211 REG_WRITE(dspcntr_reg
,
212 temp
| DISPLAY_PLANE_ENABLE
);
213 /* Flush the plane changes */
214 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
217 psb_intel_crtc_load_lut(crtc
);
219 /* Give the overlay scaler a chance to enable
220 if it's on this pipe */
221 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
223 case DRM_MODE_DPMS_OFF
:
224 /* Give the overlay scaler a chance to disable
225 * if it's on this pipe */
226 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
228 /* Disable the VGA plane that we never use */
229 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
230 /* Disable display plane */
231 temp
= REG_READ(dspcntr_reg
);
232 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
233 REG_WRITE(dspcntr_reg
,
234 temp
& ~DISPLAY_PLANE_ENABLE
);
235 /* Flush the plane changes */
236 REG_WRITE(dspbase_reg
, REG_READ(dspbase_reg
));
237 REG_READ(dspbase_reg
);
240 /* Next, disable display pipes */
241 temp
= REG_READ(pipeconf_reg
);
242 if ((temp
& PIPEACONF_ENABLE
) != 0) {
243 REG_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
244 REG_READ(pipeconf_reg
);
246 /* Wait for for the pipe disable to take effect. */
247 psb_intel_wait_for_vblank(dev
);
249 temp
= REG_READ(dpll_reg
);
250 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
251 REG_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
255 /* Wait for the clocks to turn off. */
260 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
262 /*Set FIFO Watermarks*/
263 REG_WRITE(DSPARB
, 0x3FFF);
264 REG_WRITE(DSPFW1
, 0x3F88080A);
265 REG_WRITE(DSPFW2
, 0x0b060808);
266 REG_WRITE(DSPFW3
, 0x0);
267 REG_WRITE(DSPFW4
, 0x08030404);
268 REG_WRITE(DSPFW5
, 0x04040404);
269 REG_WRITE(DSPFW6
, 0x78);
270 REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000);
271 /* Must write Bit 14 of the Chicken Bit Register */
273 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
277 * Return the pipe currently connected to the panel fitter,
278 * or -1 if the panel fitter is not present or not in use
280 static int mrst_panel_fitter_pipe(struct drm_device
*dev
)
284 pfit_control
= REG_READ(PFIT_CONTROL
);
286 /* See if the panel fitter is in use */
287 if ((pfit_control
& PFIT_ENABLE
) == 0)
289 return (pfit_control
>> 29) & 3;
292 static int mrst_crtc_mode_set(struct drm_crtc
*crtc
,
293 struct drm_display_mode
*mode
,
294 struct drm_display_mode
*adjusted_mode
,
296 struct drm_framebuffer
*old_fb
)
298 struct drm_device
*dev
= crtc
->dev
;
299 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
300 DRM_DRIVER_PRIVATE_T
*dev_priv
= dev
->dev_private
;
301 int pipe
= psb_intel_crtc
->pipe
;
302 int fp_reg
= (pipe
== 0) ? MRST_FPA0
: FPB0
;
303 int dpll_reg
= (pipe
== 0) ? MRST_DPLL_A
: DPLL_B
;
304 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
305 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
306 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
307 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
308 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
309 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
310 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
311 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
312 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
314 struct mrst_clock_t clock
;
315 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
316 bool ok
, is_sdvo
= false;
317 bool is_crt
= false, is_lvds
= false, is_tv
= false;
318 bool is_mipi
= false;
319 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
320 struct psb_intel_output
*psb_intel_output
= NULL
;
321 uint64_t scalingType
= DRM_MODE_SCALE_FULLSCREEN
;
322 struct drm_encoder
*encoder
;
324 PSB_DEBUG_ENTRY("pipe = 0x%x\n", pipe
);
326 if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
327 OSPM_UHB_FORCE_POWER_ON
))
330 memcpy(&psb_intel_crtc
->saved_mode
,
332 sizeof(struct drm_display_mode
));
333 memcpy(&psb_intel_crtc
->saved_adjusted_mode
,
335 sizeof(struct drm_display_mode
));
337 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
339 if (encoder
->crtc
!= crtc
)
342 psb_intel_output
= enc_to_psb_intel_output(encoder
);
343 switch (psb_intel_output
->type
) {
344 case INTEL_OUTPUT_LVDS
:
347 case INTEL_OUTPUT_SDVO
:
350 case INTEL_OUTPUT_TVOUT
:
353 case INTEL_OUTPUT_ANALOG
:
356 case INTEL_OUTPUT_MIPI
:
362 /* Disable the VGA plane that we never use */
363 REG_WRITE(VGACNTRL
, VGA_DISP_DISABLE
);
365 /* Disable the panel fitter if it was on our pipe */
366 if (mrst_panel_fitter_pipe(dev
) == pipe
)
367 REG_WRITE(PFIT_CONTROL
, 0);
369 REG_WRITE(pipesrc_reg
,
370 ((mode
->crtc_hdisplay
- 1) << 16) |
371 (mode
->crtc_vdisplay
- 1));
373 if (psb_intel_output
)
374 drm_connector_property_get_value(&psb_intel_output
->base
,
375 dev
->mode_config
.scaling_mode_property
, &scalingType
);
377 if (scalingType
== DRM_MODE_SCALE_NO_SCALE
) {
378 /* Moorestown doesn't have register support for centering so
379 * we need to mess with the h/vblank and h/vsync start and
380 * ends to get centering */
381 int offsetX
= 0, offsetY
= 0;
383 offsetX
= (adjusted_mode
->crtc_hdisplay
-
384 mode
->crtc_hdisplay
) / 2;
385 offsetY
= (adjusted_mode
->crtc_vdisplay
-
386 mode
->crtc_vdisplay
) / 2;
388 REG_WRITE(htot_reg
, (mode
->crtc_hdisplay
- 1) |
389 ((adjusted_mode
->crtc_htotal
- 1) << 16));
390 REG_WRITE(vtot_reg
, (mode
->crtc_vdisplay
- 1) |
391 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
392 REG_WRITE(hblank_reg
,
393 (adjusted_mode
->crtc_hblank_start
- offsetX
- 1) |
394 ((adjusted_mode
->crtc_hblank_end
- offsetX
- 1) << 16));
396 (adjusted_mode
->crtc_hsync_start
- offsetX
- 1) |
397 ((adjusted_mode
->crtc_hsync_end
- offsetX
- 1) << 16));
398 REG_WRITE(vblank_reg
,
399 (adjusted_mode
->crtc_vblank_start
- offsetY
- 1) |
400 ((adjusted_mode
->crtc_vblank_end
- offsetY
- 1) << 16));
402 (adjusted_mode
->crtc_vsync_start
- offsetY
- 1) |
403 ((adjusted_mode
->crtc_vsync_end
- offsetY
- 1) << 16));
405 REG_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
406 ((adjusted_mode
->crtc_htotal
- 1) << 16));
407 REG_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
408 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
409 REG_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
410 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
411 REG_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
412 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
413 REG_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
414 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
415 REG_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
416 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
419 /* Flush the plane changes */
421 struct drm_crtc_helper_funcs
*crtc_funcs
=
422 crtc
->helper_private
;
423 crtc_funcs
->mode_set_base(crtc
, x
, y
, old_fb
);
427 pipeconf
= REG_READ(pipeconf_reg
);
429 /* Set up the display plane register */
430 dspcntr
= REG_READ(dspcntr_reg
);
431 dspcntr
|= DISPPLANE_GAMMA_ENABLE
;
434 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
436 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
438 dev_priv
->dspcntr
= dspcntr
|= DISPLAY_PLANE_ENABLE
;
439 dev_priv
->pipeconf
= pipeconf
|= PIPEACONF_ENABLE
;
442 goto mrst_crtc_mode_set_exit
;
444 refclk
= dev_priv
->core_freq
* 1000;
446 dpll
= 0; /*BIT16 = 0 for 100MHz reference */
448 ok
= mrstFindBestPLL(crtc
, adjusted_mode
->clock
, refclk
, &clock
);
452 "mrstFindBestPLL fail in mrst_crtc_mode_set.\n");
454 PSB_DEBUG_ENTRY("mrst_crtc_mode_set pixel clock = %d,"
455 "m = %x, p1 = %x.\n", clock
.dot
, clock
.m
,
459 fp
= mrst_m_converts
[(clock
.m
- MRST_M_MIN
)] << 8;
461 dpll
|= DPLL_VGA_MODE_DIS
;
464 dpll
|= DPLL_VCO_ENABLE
;
467 dpll
|= DPLLA_MODE_LVDS
;
469 dpll
|= DPLLB_MODE_DAC_SERIAL
;
472 int sdvo_pixel_multiply
=
473 adjusted_mode
->clock
/ mode
->clock
;
475 dpll
|= DPLL_DVO_HIGH_SPEED
;
477 (sdvo_pixel_multiply
-
478 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
482 /* compute bitmask from p1 value */
483 dpll
|= (1 << (clock
.p1
- 2)) << 17;
485 dpll
|= DPLL_VCO_ENABLE
;
487 mrstPrintPll("chosen", &clock
);
489 if (dpll
& DPLL_VCO_ENABLE
) {
490 REG_WRITE(fp_reg
, fp
);
491 REG_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
493 /* Check the DPLLA lock bit PIPEACONF[29] */
497 REG_WRITE(fp_reg
, fp
);
498 REG_WRITE(dpll_reg
, dpll
);
500 /* Wait for the clocks to stabilize. */
503 /* write it again -- the BIOS does, after all */
504 REG_WRITE(dpll_reg
, dpll
);
506 /* Wait for the clocks to stabilize. */
509 REG_WRITE(pipeconf_reg
, pipeconf
);
510 REG_READ(pipeconf_reg
);
511 psb_intel_wait_for_vblank(dev
);
513 REG_WRITE(dspcntr_reg
, dspcntr
);
514 psb_intel_wait_for_vblank(dev
);
516 mrst_crtc_mode_set_exit
:
517 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
521 static bool mrst_crtc_mode_fixup(struct drm_crtc
*crtc
,
522 struct drm_display_mode
*mode
,
523 struct drm_display_mode
*adjusted_mode
)
528 int mrst_pipe_set_base(struct drm_crtc
*crtc
,
529 int x
, int y
, struct drm_framebuffer
*old_fb
)
531 struct drm_device
*dev
= crtc
->dev
;
532 /* struct drm_i915_master_private *master_priv; */
533 struct psb_intel_crtc
*psb_intel_crtc
= to_psb_intel_crtc(crtc
);
534 struct psb_framebuffer
*psbfb
= to_psb_fb(crtc
->fb
);
535 struct psb_intel_mode_device
*mode_dev
= psb_intel_crtc
->mode_dev
;
536 int pipe
= psb_intel_crtc
->pipe
;
537 unsigned long Start
, Offset
;
538 /* FIXME: check if we need this surely MRST is pipe 0 only */
539 int dspbase
= (pipe
== 0 ? DSPALINOFF
: DSPBBASE
);
540 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
541 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
542 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
546 PSB_DEBUG_ENTRY("\n");
550 DRM_DEBUG("No FB bound\n");
554 if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND
,
555 OSPM_UHB_FORCE_POWER_ON
))
558 Start
= mode_dev
->bo_offset(dev
, psbfb
);
559 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
561 REG_WRITE(dspstride
, crtc
->fb
->pitch
);
563 dspcntr
= REG_READ(dspcntr_reg
);
564 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
566 switch (crtc
->fb
->bits_per_pixel
) {
568 dspcntr
|= DISPPLANE_8BPP
;
571 if (crtc
->fb
->depth
== 15)
572 dspcntr
|= DISPPLANE_15_16BPP
;
574 dspcntr
|= DISPPLANE_16BPP
;
578 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
581 DRM_ERROR("Unknown color depth\n");
583 goto pipe_set_base_exit
;
585 REG_WRITE(dspcntr_reg
, dspcntr
);
587 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
588 if (0 /* FIXMEAC - check what PSB needs */) {
589 REG_WRITE(dspbase
, Offset
);
591 REG_WRITE(dspsurf
, Start
);
594 REG_WRITE(dspbase
, Start
+ Offset
);
599 ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND
);
603 static void mrst_crtc_prepare(struct drm_crtc
*crtc
)
605 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
606 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
609 static void mrst_crtc_commit(struct drm_crtc
*crtc
)
611 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
612 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
615 const struct drm_crtc_helper_funcs mrst_helper_funcs
= {
616 .dpms
= mrst_crtc_dpms
,
617 .mode_fixup
= mrst_crtc_mode_fixup
,
618 .mode_set
= mrst_crtc_mode_set
,
619 .mode_set_base
= mrst_pipe_set_base
,
620 .prepare
= mrst_crtc_prepare
,
621 .commit
= mrst_crtc_commit
,