2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
,
39 struct intel_ring_buffer
*pipelined
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
);
48 static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
50 bool map_and_fenceable
);
51 static void i915_gem_clear_fence_reg(struct drm_i915_gem_object
*obj
);
52 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
53 struct drm_i915_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file
);
56 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
);
58 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
67 dev_priv
->mm
.object_count
++;
68 dev_priv
->mm
.object_memory
+= size
;
71 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
74 dev_priv
->mm
.object_count
--;
75 dev_priv
->mm
.object_memory
-= size
;
79 i915_gem_check_is_wedged(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 struct completion
*x
= &dev_priv
->error_completion
;
86 if (!atomic_read(&dev_priv
->mm
.wedged
))
89 ret
= wait_for_completion_interruptible(x
);
93 /* Success, we reset the GPU! */
94 if (!atomic_read(&dev_priv
->mm
.wedged
))
97 /* GPU is hung, bump the completion count to account for
98 * the token we just consumed so that we never hit zero and
99 * end up waiting upon a subsequent completion event that
102 spin_lock_irqsave(&x
->wait
.lock
, flags
);
104 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
108 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
113 ret
= i915_gem_check_is_wedged(dev
);
117 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
121 if (atomic_read(&dev_priv
->mm
.wedged
)) {
122 mutex_unlock(&dev
->struct_mutex
);
126 WARN_ON(i915_verify_lists(dev
));
131 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
133 return obj
->gtt_space
&& !obj
->active
&& obj
->pin_count
== 0;
136 void i915_gem_do_init(struct drm_device
*dev
,
138 unsigned long mappable_end
,
141 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
143 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
146 dev_priv
->mm
.gtt_total
= end
- start
;
147 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
148 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
152 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
153 struct drm_file
*file
)
155 struct drm_i915_gem_init
*args
= data
;
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 mutex_lock(&dev
->struct_mutex
);
162 i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
163 mutex_unlock(&dev
->struct_mutex
);
169 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
170 struct drm_file
*file
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct drm_i915_gem_get_aperture
*args
= data
;
174 struct drm_i915_gem_object
*obj
;
177 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
181 mutex_lock(&dev
->struct_mutex
);
182 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
183 pinned
+= obj
->gtt_space
->size
;
184 mutex_unlock(&dev
->struct_mutex
);
186 args
->aper_size
= dev_priv
->mm
.gtt_total
;
187 args
->aper_available_size
= args
->aper_size
-pinned
;
193 * Creates a new mm object and returns a handle to it.
196 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
197 struct drm_file
*file
)
199 struct drm_i915_gem_create
*args
= data
;
200 struct drm_i915_gem_object
*obj
;
204 args
->size
= roundup(args
->size
, PAGE_SIZE
);
206 /* Allocate the new object */
207 obj
= i915_gem_alloc_object(dev
, args
->size
);
211 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
213 drm_gem_object_release(&obj
->base
);
214 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
219 /* drop reference from allocate - handle holds it now */
220 drm_gem_object_unreference(&obj
->base
);
221 trace_i915_gem_object_create(obj
);
223 args
->handle
= handle
;
227 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
229 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
231 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
232 obj
->tiling_mode
!= I915_TILING_NONE
;
236 slow_shmem_copy(struct page
*dst_page
,
238 struct page
*src_page
,
242 char *dst_vaddr
, *src_vaddr
;
244 dst_vaddr
= kmap(dst_page
);
245 src_vaddr
= kmap(src_page
);
247 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
254 slow_shmem_bit17_copy(struct page
*gpu_page
,
256 struct page
*cpu_page
,
261 char *gpu_vaddr
, *cpu_vaddr
;
263 /* Use the unswizzled path if this page isn't affected. */
264 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
266 return slow_shmem_copy(cpu_page
, cpu_offset
,
267 gpu_page
, gpu_offset
, length
);
269 return slow_shmem_copy(gpu_page
, gpu_offset
,
270 cpu_page
, cpu_offset
, length
);
273 gpu_vaddr
= kmap(gpu_page
);
274 cpu_vaddr
= kmap(cpu_page
);
276 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
277 * XORing with the other bits (A9 for Y, A9 and A10 for X)
280 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
281 int this_length
= min(cacheline_end
- gpu_offset
, length
);
282 int swizzled_gpu_offset
= gpu_offset
^ 64;
285 memcpy(cpu_vaddr
+ cpu_offset
,
286 gpu_vaddr
+ swizzled_gpu_offset
,
289 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
290 cpu_vaddr
+ cpu_offset
,
293 cpu_offset
+= this_length
;
294 gpu_offset
+= this_length
;
295 length
-= this_length
;
303 * This is the fast shmem pread path, which attempts to copy_from_user directly
304 * from the backing pages of the object to the user's address space. On a
305 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
308 i915_gem_shmem_pread_fast(struct drm_device
*dev
,
309 struct drm_i915_gem_object
*obj
,
310 struct drm_i915_gem_pread
*args
,
311 struct drm_file
*file
)
313 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
316 char __user
*user_data
;
317 int page_offset
, page_length
;
319 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
322 offset
= args
->offset
;
329 /* Operation in this page
331 * page_offset = offset within page
332 * page_length = bytes to copy for this page
334 page_offset
= offset
& (PAGE_SIZE
-1);
335 page_length
= remain
;
336 if ((page_offset
+ remain
) > PAGE_SIZE
)
337 page_length
= PAGE_SIZE
- page_offset
;
339 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
340 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
342 return PTR_ERR(page
);
344 vaddr
= kmap_atomic(page
);
345 ret
= __copy_to_user_inatomic(user_data
,
348 kunmap_atomic(vaddr
);
350 mark_page_accessed(page
);
351 page_cache_release(page
);
355 remain
-= page_length
;
356 user_data
+= page_length
;
357 offset
+= page_length
;
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
370 i915_gem_shmem_pread_slow(struct drm_device
*dev
,
371 struct drm_i915_gem_object
*obj
,
372 struct drm_i915_gem_pread
*args
,
373 struct drm_file
*file
)
375 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
376 struct mm_struct
*mm
= current
->mm
;
377 struct page
**user_pages
;
379 loff_t offset
, pinned_pages
, i
;
380 loff_t first_data_page
, last_data_page
, num_pages
;
381 int shmem_page_offset
;
382 int data_page_index
, data_page_offset
;
385 uint64_t data_ptr
= args
->data_ptr
;
386 int do_bit17_swizzling
;
390 /* Pin the user pages containing the data. We can't fault while
391 * holding the struct mutex, yet we want to hold it while
392 * dereferencing the user data.
394 first_data_page
= data_ptr
/ PAGE_SIZE
;
395 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
396 num_pages
= last_data_page
- first_data_page
+ 1;
398 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
399 if (user_pages
== NULL
)
402 mutex_unlock(&dev
->struct_mutex
);
403 down_read(&mm
->mmap_sem
);
404 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
405 num_pages
, 1, 0, user_pages
, NULL
);
406 up_read(&mm
->mmap_sem
);
407 mutex_lock(&dev
->struct_mutex
);
408 if (pinned_pages
< num_pages
) {
413 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
419 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
421 offset
= args
->offset
;
426 /* Operation in this page
428 * shmem_page_offset = offset within page in shmem file
429 * data_page_index = page number in get_user_pages return
430 * data_page_offset = offset with data_page_index page.
431 * page_length = bytes to copy for this page
433 shmem_page_offset
= offset
& ~PAGE_MASK
;
434 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
435 data_page_offset
= data_ptr
& ~PAGE_MASK
;
437 page_length
= remain
;
438 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
439 page_length
= PAGE_SIZE
- shmem_page_offset
;
440 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
441 page_length
= PAGE_SIZE
- data_page_offset
;
443 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
444 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
446 return PTR_ERR(page
);
448 if (do_bit17_swizzling
) {
449 slow_shmem_bit17_copy(page
,
451 user_pages
[data_page_index
],
456 slow_shmem_copy(user_pages
[data_page_index
],
463 mark_page_accessed(page
);
464 page_cache_release(page
);
466 remain
-= page_length
;
467 data_ptr
+= page_length
;
468 offset
+= page_length
;
472 for (i
= 0; i
< pinned_pages
; i
++) {
473 SetPageDirty(user_pages
[i
]);
474 mark_page_accessed(user_pages
[i
]);
475 page_cache_release(user_pages
[i
]);
477 drm_free_large(user_pages
);
483 * Reads data from the object referenced by handle.
485 * On error, the contents of *data are undefined.
488 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
489 struct drm_file
*file
)
491 struct drm_i915_gem_pread
*args
= data
;
492 struct drm_i915_gem_object
*obj
;
498 if (!access_ok(VERIFY_WRITE
,
499 (char __user
*)(uintptr_t)args
->data_ptr
,
503 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
508 ret
= i915_mutex_lock_interruptible(dev
);
512 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
518 /* Bounds check source. */
519 if (args
->offset
> obj
->base
.size
||
520 args
->size
> obj
->base
.size
- args
->offset
) {
525 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
532 if (!i915_gem_object_needs_bit17_swizzle(obj
))
533 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file
);
535 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file
);
538 drm_gem_object_unreference(&obj
->base
);
540 mutex_unlock(&dev
->struct_mutex
);
544 /* This is the fast write path which cannot handle
545 * page faults in the source data
549 fast_user_write(struct io_mapping
*mapping
,
550 loff_t page_base
, int page_offset
,
551 char __user
*user_data
,
555 unsigned long unwritten
;
557 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
558 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
560 io_mapping_unmap_atomic(vaddr_atomic
);
564 /* Here's the write path which can sleep for
569 slow_kernel_write(struct io_mapping
*mapping
,
570 loff_t gtt_base
, int gtt_offset
,
571 struct page
*user_page
, int user_offset
,
574 char __iomem
*dst_vaddr
;
577 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
578 src_vaddr
= kmap(user_page
);
580 memcpy_toio(dst_vaddr
+ gtt_offset
,
581 src_vaddr
+ user_offset
,
585 io_mapping_unmap(dst_vaddr
);
589 * This is the fast pwrite path, where we copy the data directly from the
590 * user into the GTT, uncached.
593 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
594 struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
600 loff_t offset
, page_base
;
601 char __user
*user_data
;
602 int page_offset
, page_length
;
604 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
607 offset
= obj
->gtt_offset
+ args
->offset
;
610 /* Operation in this page
612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
616 page_base
= (offset
& ~(PAGE_SIZE
-1));
617 page_offset
= offset
& (PAGE_SIZE
-1);
618 page_length
= remain
;
619 if ((page_offset
+ remain
) > PAGE_SIZE
)
620 page_length
= PAGE_SIZE
- page_offset
;
622 /* If we get a fault while copying data, then (presumably) our
623 * source page isn't available. Return the error and we'll
624 * retry in the slow path.
626 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
627 page_offset
, user_data
, page_length
))
631 remain
-= page_length
;
632 user_data
+= page_length
;
633 offset
+= page_length
;
640 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
641 * the memory and maps it using kmap_atomic for copying.
643 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
644 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
647 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
,
648 struct drm_i915_gem_object
*obj
,
649 struct drm_i915_gem_pwrite
*args
,
650 struct drm_file
*file
)
652 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
654 loff_t gtt_page_base
, offset
;
655 loff_t first_data_page
, last_data_page
, num_pages
;
656 loff_t pinned_pages
, i
;
657 struct page
**user_pages
;
658 struct mm_struct
*mm
= current
->mm
;
659 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
661 uint64_t data_ptr
= args
->data_ptr
;
665 /* Pin the user pages containing the data. We can't fault while
666 * holding the struct mutex, and all of the pwrite implementations
667 * want to hold it while dereferencing the user data.
669 first_data_page
= data_ptr
/ PAGE_SIZE
;
670 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
671 num_pages
= last_data_page
- first_data_page
+ 1;
673 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
674 if (user_pages
== NULL
)
677 mutex_unlock(&dev
->struct_mutex
);
678 down_read(&mm
->mmap_sem
);
679 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
680 num_pages
, 0, 0, user_pages
, NULL
);
681 up_read(&mm
->mmap_sem
);
682 mutex_lock(&dev
->struct_mutex
);
683 if (pinned_pages
< num_pages
) {
685 goto out_unpin_pages
;
688 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
690 goto out_unpin_pages
;
692 offset
= obj
->gtt_offset
+ args
->offset
;
695 /* Operation in this page
697 * gtt_page_base = page offset within aperture
698 * gtt_page_offset = offset within page in aperture
699 * data_page_index = page number in get_user_pages return
700 * data_page_offset = offset with data_page_index page.
701 * page_length = bytes to copy for this page
703 gtt_page_base
= offset
& PAGE_MASK
;
704 gtt_page_offset
= offset
& ~PAGE_MASK
;
705 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
706 data_page_offset
= data_ptr
& ~PAGE_MASK
;
708 page_length
= remain
;
709 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
710 page_length
= PAGE_SIZE
- gtt_page_offset
;
711 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
712 page_length
= PAGE_SIZE
- data_page_offset
;
714 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
715 gtt_page_base
, gtt_page_offset
,
716 user_pages
[data_page_index
],
720 remain
-= page_length
;
721 offset
+= page_length
;
722 data_ptr
+= page_length
;
726 for (i
= 0; i
< pinned_pages
; i
++)
727 page_cache_release(user_pages
[i
]);
728 drm_free_large(user_pages
);
734 * This is the fast shmem pwrite path, which attempts to directly
735 * copy_from_user into the kmapped pages backing the object.
738 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
,
739 struct drm_i915_gem_object
*obj
,
740 struct drm_i915_gem_pwrite
*args
,
741 struct drm_file
*file
)
743 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
746 char __user
*user_data
;
747 int page_offset
, page_length
;
749 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
752 offset
= args
->offset
;
760 /* Operation in this page
762 * page_offset = offset within page
763 * page_length = bytes to copy for this page
765 page_offset
= offset
& (PAGE_SIZE
-1);
766 page_length
= remain
;
767 if ((page_offset
+ remain
) > PAGE_SIZE
)
768 page_length
= PAGE_SIZE
- page_offset
;
770 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
771 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
773 return PTR_ERR(page
);
775 vaddr
= kmap_atomic(page
, KM_USER0
);
776 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
779 kunmap_atomic(vaddr
, KM_USER0
);
781 set_page_dirty(page
);
782 mark_page_accessed(page
);
783 page_cache_release(page
);
785 /* If we get a fault while copying data, then (presumably) our
786 * source page isn't available. Return the error and we'll
787 * retry in the slow path.
792 remain
-= page_length
;
793 user_data
+= page_length
;
794 offset
+= page_length
;
801 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
802 * the memory and maps it using kmap_atomic for copying.
804 * This avoids taking mmap_sem for faulting on the user's address while the
805 * struct_mutex is held.
808 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
,
809 struct drm_i915_gem_object
*obj
,
810 struct drm_i915_gem_pwrite
*args
,
811 struct drm_file
*file
)
813 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
814 struct mm_struct
*mm
= current
->mm
;
815 struct page
**user_pages
;
817 loff_t offset
, pinned_pages
, i
;
818 loff_t first_data_page
, last_data_page
, num_pages
;
819 int shmem_page_offset
;
820 int data_page_index
, data_page_offset
;
823 uint64_t data_ptr
= args
->data_ptr
;
824 int do_bit17_swizzling
;
828 /* Pin the user pages containing the data. We can't fault while
829 * holding the struct mutex, and all of the pwrite implementations
830 * want to hold it while dereferencing the user data.
832 first_data_page
= data_ptr
/ PAGE_SIZE
;
833 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
834 num_pages
= last_data_page
- first_data_page
+ 1;
836 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
837 if (user_pages
== NULL
)
840 mutex_unlock(&dev
->struct_mutex
);
841 down_read(&mm
->mmap_sem
);
842 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
843 num_pages
, 0, 0, user_pages
, NULL
);
844 up_read(&mm
->mmap_sem
);
845 mutex_lock(&dev
->struct_mutex
);
846 if (pinned_pages
< num_pages
) {
851 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
855 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
857 offset
= args
->offset
;
863 /* Operation in this page
865 * shmem_page_offset = offset within page in shmem file
866 * data_page_index = page number in get_user_pages return
867 * data_page_offset = offset with data_page_index page.
868 * page_length = bytes to copy for this page
870 shmem_page_offset
= offset
& ~PAGE_MASK
;
871 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
872 data_page_offset
= data_ptr
& ~PAGE_MASK
;
874 page_length
= remain
;
875 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
876 page_length
= PAGE_SIZE
- shmem_page_offset
;
877 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
878 page_length
= PAGE_SIZE
- data_page_offset
;
880 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
881 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
887 if (do_bit17_swizzling
) {
888 slow_shmem_bit17_copy(page
,
890 user_pages
[data_page_index
],
895 slow_shmem_copy(page
,
897 user_pages
[data_page_index
],
902 set_page_dirty(page
);
903 mark_page_accessed(page
);
904 page_cache_release(page
);
906 remain
-= page_length
;
907 data_ptr
+= page_length
;
908 offset
+= page_length
;
912 for (i
= 0; i
< pinned_pages
; i
++)
913 page_cache_release(user_pages
[i
]);
914 drm_free_large(user_pages
);
920 * Writes data to the object referenced by handle.
922 * On error, the contents of the buffer that were to be modified are undefined.
925 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
926 struct drm_file
*file
)
928 struct drm_i915_gem_pwrite
*args
= data
;
929 struct drm_i915_gem_object
*obj
;
935 if (!access_ok(VERIFY_READ
,
936 (char __user
*)(uintptr_t)args
->data_ptr
,
940 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
945 ret
= i915_mutex_lock_interruptible(dev
);
949 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
955 /* Bounds check destination. */
956 if (args
->offset
> obj
->base
.size
||
957 args
->size
> obj
->base
.size
- args
->offset
) {
962 /* We can only do the GTT pwrite on untiled buffers, as otherwise
963 * it would end up going through the fenced access, and we'll get
964 * different detiling behavior between reading and writing.
965 * pread/pwrite currently are reading and writing from the CPU
966 * perspective, requiring manual detiling by the client.
969 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
970 else if (obj
->tiling_mode
== I915_TILING_NONE
&&
972 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
973 ret
= i915_gem_object_pin(obj
, 0, true);
977 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
981 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
983 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
986 i915_gem_object_unpin(obj
);
988 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
993 if (!i915_gem_object_needs_bit17_swizzle(obj
))
994 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
996 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1000 drm_gem_object_unreference(&obj
->base
);
1002 mutex_unlock(&dev
->struct_mutex
);
1007 * Called when user space prepares to use an object with the CPU, either
1008 * through the mmap ioctl's mapping or a GTT mapping.
1011 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1012 struct drm_file
*file
)
1014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1015 struct drm_i915_gem_set_domain
*args
= data
;
1016 struct drm_i915_gem_object
*obj
;
1017 uint32_t read_domains
= args
->read_domains
;
1018 uint32_t write_domain
= args
->write_domain
;
1021 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1024 /* Only handle setting domains to types used by the CPU. */
1025 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1028 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1031 /* Having something in the write domain implies it's in the read
1032 * domain, and only that read domain. Enforce that in the request.
1034 if (write_domain
!= 0 && read_domains
!= write_domain
)
1037 ret
= i915_mutex_lock_interruptible(dev
);
1041 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1047 intel_mark_busy(dev
, obj
);
1049 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1050 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1052 /* Update the LRU on the fence for the CPU access that's
1055 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1056 struct drm_i915_fence_reg
*reg
=
1057 &dev_priv
->fence_regs
[obj
->fence_reg
];
1058 list_move_tail(®
->lru_list
,
1059 &dev_priv
->mm
.fence_list
);
1062 /* Silently promote "you're not bound, there was nothing to do"
1063 * to success, since the client was just asking us to
1064 * make sure everything was done.
1069 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1072 /* Maintain LRU order of "inactive" objects */
1073 if (ret
== 0 && i915_gem_object_is_inactive(obj
))
1074 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1076 drm_gem_object_unreference(&obj
->base
);
1078 mutex_unlock(&dev
->struct_mutex
);
1083 * Called when user space has done writes to this buffer
1086 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1087 struct drm_file
*file
)
1089 struct drm_i915_gem_sw_finish
*args
= data
;
1090 struct drm_i915_gem_object
*obj
;
1093 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1096 ret
= i915_mutex_lock_interruptible(dev
);
1100 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1106 /* Pinned buffers may be scanout, so flush the cache */
1108 i915_gem_object_flush_cpu_write_domain(obj
);
1110 drm_gem_object_unreference(&obj
->base
);
1112 mutex_unlock(&dev
->struct_mutex
);
1117 * Maps the contents of an object, returning the address it is mapped
1120 * While the mapping holds a reference on the contents of the object, it doesn't
1121 * imply a ref on the object itself.
1124 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1125 struct drm_file
*file
)
1127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1128 struct drm_i915_gem_mmap
*args
= data
;
1129 struct drm_gem_object
*obj
;
1133 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1136 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1140 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1141 drm_gem_object_unreference_unlocked(obj
);
1145 offset
= args
->offset
;
1147 down_write(¤t
->mm
->mmap_sem
);
1148 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1149 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1151 up_write(¤t
->mm
->mmap_sem
);
1152 drm_gem_object_unreference_unlocked(obj
);
1153 if (IS_ERR((void *)addr
))
1156 args
->addr_ptr
= (uint64_t) addr
;
1162 * i915_gem_fault - fault a page into the GTT
1163 * vma: VMA in question
1166 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1167 * from userspace. The fault handler takes care of binding the object to
1168 * the GTT (if needed), allocating and programming a fence register (again,
1169 * only if needed based on whether the old reg is still valid or the object
1170 * is tiled) and inserting a new PTE into the faulting process.
1172 * Note that the faulting process may involve evicting existing objects
1173 * from the GTT and/or fence registers to make room. So performance may
1174 * suffer if the GTT working set is large or there are few fence registers
1177 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1179 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1180 struct drm_device
*dev
= obj
->base
.dev
;
1181 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1182 pgoff_t page_offset
;
1185 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1187 /* We don't use vmf->pgoff since that has the fake offset */
1188 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1191 /* Now bind it into the GTT if needed */
1192 mutex_lock(&dev
->struct_mutex
);
1194 if (!obj
->map_and_fenceable
) {
1195 ret
= i915_gem_object_unbind(obj
);
1199 if (!obj
->gtt_space
) {
1200 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1205 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1209 /* Need a new fence register? */
1210 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
1211 ret
= i915_gem_object_get_fence_reg(obj
, true);
1216 if (i915_gem_object_is_inactive(obj
))
1217 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1219 obj
->fault_mappable
= true;
1221 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1224 /* Finally, remap it using the new GTT offset */
1225 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1227 mutex_unlock(&dev
->struct_mutex
);
1234 return VM_FAULT_NOPAGE
;
1236 return VM_FAULT_OOM
;
1238 return VM_FAULT_SIGBUS
;
1243 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1244 * @obj: obj in question
1246 * GEM memory mapping works by handing back to userspace a fake mmap offset
1247 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1248 * up the object based on the offset and sets up the various memory mapping
1251 * This routine allocates and attaches a fake offset for @obj.
1254 i915_gem_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1256 struct drm_device
*dev
= obj
->base
.dev
;
1257 struct drm_gem_mm
*mm
= dev
->mm_private
;
1258 struct drm_map_list
*list
;
1259 struct drm_local_map
*map
;
1262 /* Set the object up for mmap'ing */
1263 list
= &obj
->base
.map_list
;
1264 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1269 map
->type
= _DRM_GEM
;
1270 map
->size
= obj
->base
.size
;
1273 /* Get a DRM GEM mmap offset allocated... */
1274 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1275 obj
->base
.size
/ PAGE_SIZE
,
1277 if (!list
->file_offset_node
) {
1278 DRM_ERROR("failed to allocate offset for bo %d\n",
1284 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1285 obj
->base
.size
/ PAGE_SIZE
,
1287 if (!list
->file_offset_node
) {
1292 list
->hash
.key
= list
->file_offset_node
->start
;
1293 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1295 DRM_ERROR("failed to add to map hash\n");
1302 drm_mm_put_block(list
->file_offset_node
);
1311 * i915_gem_release_mmap - remove physical page mappings
1312 * @obj: obj in question
1314 * Preserve the reservation of the mmapping with the DRM core code, but
1315 * relinquish ownership of the pages back to the system.
1317 * It is vital that we remove the page mapping if we have mapped a tiled
1318 * object through the GTT and then lose the fence register due to
1319 * resource pressure. Similarly if the object has been moved out of the
1320 * aperture, than pages mapped into userspace must be revoked. Removing the
1321 * mapping will then trigger a page fault on the next user access, allowing
1322 * fixup by i915_gem_fault().
1325 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1327 if (!obj
->fault_mappable
)
1330 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1331 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1334 obj
->fault_mappable
= false;
1338 i915_gem_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1340 struct drm_device
*dev
= obj
->base
.dev
;
1341 struct drm_gem_mm
*mm
= dev
->mm_private
;
1342 struct drm_map_list
*list
= &obj
->base
.map_list
;
1344 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1345 drm_mm_put_block(list
->file_offset_node
);
1351 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj
)
1353 struct drm_device
*dev
= obj
->base
.dev
;
1356 if (INTEL_INFO(dev
)->gen
>= 4 ||
1357 obj
->tiling_mode
== I915_TILING_NONE
)
1358 return obj
->base
.size
;
1360 /* Previous chips need a power-of-two fence region when tiling */
1361 if (INTEL_INFO(dev
)->gen
== 3)
1366 while (size
< obj
->base
.size
)
1373 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1374 * @obj: object to check
1376 * Return the required GTT alignment for an object, taking into account
1377 * potential fence register mapping.
1380 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj
)
1382 struct drm_device
*dev
= obj
->base
.dev
;
1385 * Minimum alignment is 4k (GTT page size), but might be greater
1386 * if a fence register is needed for the object.
1388 if (INTEL_INFO(dev
)->gen
>= 4 ||
1389 obj
->tiling_mode
== I915_TILING_NONE
)
1393 * Previous chips need to be aligned to the size of the smallest
1394 * fence register that can contain the object.
1396 return i915_gem_get_gtt_size(obj
);
1400 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1402 * @obj: object to check
1404 * Return the required GTT alignment for an object, only taking into account
1405 * unfenced tiled surface requirements.
1408 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj
)
1410 struct drm_device
*dev
= obj
->base
.dev
;
1414 * Minimum alignment is 4k (GTT page size) for sane hw.
1416 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1417 obj
->tiling_mode
== I915_TILING_NONE
)
1421 * Older chips need unfenced tiled buffers to be aligned to the left
1422 * edge of an even tile row (where tile rows are counted as if the bo is
1423 * placed in a fenced gtt region).
1426 (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
1431 return tile_height
* obj
->stride
* 2;
1435 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1437 * @data: GTT mapping ioctl data
1438 * @file: GEM object info
1440 * Simply returns the fake offset to userspace so it can mmap it.
1441 * The mmap call will end up in drm_gem_mmap(), which will set things
1442 * up so we can get faults in the handler above.
1444 * The fault handler will take care of binding the object into the GTT
1445 * (since it may have been evicted to make room for something), allocating
1446 * a fence register, and mapping the appropriate aperture address into
1450 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1451 struct drm_file
*file
)
1453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1454 struct drm_i915_gem_mmap_gtt
*args
= data
;
1455 struct drm_i915_gem_object
*obj
;
1458 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1461 ret
= i915_mutex_lock_interruptible(dev
);
1465 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1471 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1476 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1477 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1482 if (!obj
->base
.map_list
.map
) {
1483 ret
= i915_gem_create_mmap_offset(obj
);
1488 args
->offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1491 drm_gem_object_unreference(&obj
->base
);
1493 mutex_unlock(&dev
->struct_mutex
);
1498 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1502 struct address_space
*mapping
;
1503 struct inode
*inode
;
1506 /* Get the list of pages out of our struct file. They'll be pinned
1507 * at this point until we release them.
1509 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1510 BUG_ON(obj
->pages
!= NULL
);
1511 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1512 if (obj
->pages
== NULL
)
1515 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1516 mapping
= inode
->i_mapping
;
1517 for (i
= 0; i
< page_count
; i
++) {
1518 page
= read_cache_page_gfp(mapping
, i
,
1526 obj
->pages
[i
] = page
;
1529 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1530 i915_gem_object_do_bit_17_swizzle(obj
);
1536 page_cache_release(obj
->pages
[i
]);
1538 drm_free_large(obj
->pages
);
1540 return PTR_ERR(page
);
1544 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1546 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1549 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1551 if (obj
->tiling_mode
!= I915_TILING_NONE
)
1552 i915_gem_object_save_bit_17_swizzle(obj
);
1554 if (obj
->madv
== I915_MADV_DONTNEED
)
1557 for (i
= 0; i
< page_count
; i
++) {
1559 set_page_dirty(obj
->pages
[i
]);
1561 if (obj
->madv
== I915_MADV_WILLNEED
)
1562 mark_page_accessed(obj
->pages
[i
]);
1564 page_cache_release(obj
->pages
[i
]);
1568 drm_free_large(obj
->pages
);
1573 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1574 struct intel_ring_buffer
*ring
)
1576 struct drm_device
*dev
= obj
->base
.dev
;
1577 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1578 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1580 BUG_ON(ring
== NULL
);
1583 /* Add a reference if we're newly entering the active list. */
1585 drm_gem_object_reference(&obj
->base
);
1589 /* Move from whatever list we were on to the tail of execution. */
1590 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1591 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1593 obj
->last_rendering_seqno
= seqno
;
1594 if (obj
->fenced_gpu_access
) {
1595 struct drm_i915_fence_reg
*reg
;
1597 BUG_ON(obj
->fence_reg
== I915_FENCE_REG_NONE
);
1599 obj
->last_fenced_seqno
= seqno
;
1600 obj
->last_fenced_ring
= ring
;
1602 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1603 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
1608 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1610 list_del_init(&obj
->ring_list
);
1611 obj
->last_rendering_seqno
= 0;
1612 obj
->last_fenced_seqno
= 0;
1616 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1618 struct drm_device
*dev
= obj
->base
.dev
;
1619 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1621 BUG_ON(!obj
->active
);
1622 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1624 i915_gem_object_move_off_active(obj
);
1628 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1630 struct drm_device
*dev
= obj
->base
.dev
;
1631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1633 if (obj
->pin_count
!= 0)
1634 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.pinned_list
);
1636 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1638 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1639 BUG_ON(!obj
->active
);
1642 i915_gem_object_move_off_active(obj
);
1643 obj
->fenced_gpu_access
= false;
1644 obj
->last_fenced_ring
= NULL
;
1647 drm_gem_object_unreference(&obj
->base
);
1649 WARN_ON(i915_verify_lists(dev
));
1652 /* Immediately discard the backing storage */
1654 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1656 struct inode
*inode
;
1658 /* Our goal here is to return as much of the memory as
1659 * is possible back to the system as we are called from OOM.
1660 * To do this we must instruct the shmfs to drop all of its
1661 * backing pages, *now*. Here we mirror the actions taken
1662 * when by shmem_delete_inode() to release the backing store.
1664 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1665 truncate_inode_pages(inode
->i_mapping
, 0);
1666 if (inode
->i_op
->truncate_range
)
1667 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1669 obj
->madv
= __I915_MADV_PURGED
;
1673 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1675 return obj
->madv
== I915_MADV_DONTNEED
;
1679 i915_gem_process_flushing_list(struct drm_device
*dev
,
1680 uint32_t flush_domains
,
1681 struct intel_ring_buffer
*ring
)
1683 struct drm_i915_gem_object
*obj
, *next
;
1685 list_for_each_entry_safe(obj
, next
,
1686 &ring
->gpu_write_list
,
1688 if (obj
->base
.write_domain
& flush_domains
) {
1689 uint32_t old_write_domain
= obj
->base
.write_domain
;
1691 obj
->base
.write_domain
= 0;
1692 list_del_init(&obj
->gpu_write_list
);
1693 i915_gem_object_move_to_active(obj
, ring
);
1695 trace_i915_gem_object_change_domain(obj
,
1696 obj
->base
.read_domains
,
1703 i915_add_request(struct drm_device
*dev
,
1704 struct drm_file
*file
,
1705 struct drm_i915_gem_request
*request
,
1706 struct intel_ring_buffer
*ring
)
1708 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1709 struct drm_i915_file_private
*file_priv
= NULL
;
1714 BUG_ON(request
== NULL
);
1717 file_priv
= file
->driver_priv
;
1719 ret
= ring
->add_request(ring
, &seqno
);
1723 ring
->outstanding_lazy_request
= false;
1725 request
->seqno
= seqno
;
1726 request
->ring
= ring
;
1727 request
->emitted_jiffies
= jiffies
;
1728 was_empty
= list_empty(&ring
->request_list
);
1729 list_add_tail(&request
->list
, &ring
->request_list
);
1732 spin_lock(&file_priv
->mm
.lock
);
1733 request
->file_priv
= file_priv
;
1734 list_add_tail(&request
->client_list
,
1735 &file_priv
->mm
.request_list
);
1736 spin_unlock(&file_priv
->mm
.lock
);
1739 if (!dev_priv
->mm
.suspended
) {
1740 mod_timer(&dev_priv
->hangcheck_timer
,
1741 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1743 queue_delayed_work(dev_priv
->wq
,
1744 &dev_priv
->mm
.retire_work
, HZ
);
1750 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1752 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1757 spin_lock(&file_priv
->mm
.lock
);
1758 list_del(&request
->client_list
);
1759 request
->file_priv
= NULL
;
1760 spin_unlock(&file_priv
->mm
.lock
);
1763 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1764 struct intel_ring_buffer
*ring
)
1766 while (!list_empty(&ring
->request_list
)) {
1767 struct drm_i915_gem_request
*request
;
1769 request
= list_first_entry(&ring
->request_list
,
1770 struct drm_i915_gem_request
,
1773 list_del(&request
->list
);
1774 i915_gem_request_remove_from_client(request
);
1778 while (!list_empty(&ring
->active_list
)) {
1779 struct drm_i915_gem_object
*obj
;
1781 obj
= list_first_entry(&ring
->active_list
,
1782 struct drm_i915_gem_object
,
1785 obj
->base
.write_domain
= 0;
1786 list_del_init(&obj
->gpu_write_list
);
1787 i915_gem_object_move_to_inactive(obj
);
1791 static void i915_gem_reset_fences(struct drm_device
*dev
)
1793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1796 for (i
= 0; i
< 16; i
++) {
1797 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1799 i915_gem_clear_fence_reg(reg
->obj
);
1803 void i915_gem_reset(struct drm_device
*dev
)
1805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1806 struct drm_i915_gem_object
*obj
;
1808 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1809 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1810 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1812 /* Remove anything from the flushing lists. The GPU cache is likely
1813 * to be lost on reset along with the data, so simply move the
1814 * lost bo to the inactive list.
1816 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1817 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1818 struct drm_i915_gem_object
,
1821 obj
->base
.write_domain
= 0;
1822 list_del_init(&obj
->gpu_write_list
);
1823 i915_gem_object_move_to_inactive(obj
);
1826 /* Move everything out of the GPU domains to ensure we do any
1827 * necessary invalidation upon reuse.
1829 list_for_each_entry(obj
,
1830 &dev_priv
->mm
.inactive_list
,
1833 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1836 /* The fence registers are invalidated so clear them out */
1837 i915_gem_reset_fences(dev
);
1841 * This function clears the request list as sequence numbers are passed.
1844 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1845 struct intel_ring_buffer
*ring
)
1847 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1850 if (!ring
->status_page
.page_addr
||
1851 list_empty(&ring
->request_list
))
1854 WARN_ON(i915_verify_lists(dev
));
1856 seqno
= ring
->get_seqno(ring
);
1857 while (!list_empty(&ring
->request_list
)) {
1858 struct drm_i915_gem_request
*request
;
1860 request
= list_first_entry(&ring
->request_list
,
1861 struct drm_i915_gem_request
,
1864 if (!i915_seqno_passed(seqno
, request
->seqno
))
1867 trace_i915_gem_request_retire(dev
, request
->seqno
);
1869 list_del(&request
->list
);
1870 i915_gem_request_remove_from_client(request
);
1874 /* Move any buffers on the active list that are no longer referenced
1875 * by the ringbuffer to the flushing/inactive lists as appropriate.
1877 while (!list_empty(&ring
->active_list
)) {
1878 struct drm_i915_gem_object
*obj
;
1880 obj
= list_first_entry(&ring
->active_list
,
1881 struct drm_i915_gem_object
,
1884 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1887 if (obj
->base
.write_domain
!= 0)
1888 i915_gem_object_move_to_flushing(obj
);
1890 i915_gem_object_move_to_inactive(obj
);
1893 if (unlikely (dev_priv
->trace_irq_seqno
&&
1894 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1895 ring
->user_irq_put(ring
);
1896 dev_priv
->trace_irq_seqno
= 0;
1899 WARN_ON(i915_verify_lists(dev
));
1903 i915_gem_retire_requests(struct drm_device
*dev
)
1905 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1907 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1908 struct drm_i915_gem_object
*obj
, *next
;
1910 /* We must be careful that during unbind() we do not
1911 * accidentally infinitely recurse into retire requests.
1913 * retire -> free -> unbind -> wait -> retire_ring
1915 list_for_each_entry_safe(obj
, next
,
1916 &dev_priv
->mm
.deferred_free_list
,
1918 i915_gem_free_object_tail(obj
);
1921 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1922 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1923 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
1927 i915_gem_retire_work_handler(struct work_struct
*work
)
1929 drm_i915_private_t
*dev_priv
;
1930 struct drm_device
*dev
;
1932 dev_priv
= container_of(work
, drm_i915_private_t
,
1933 mm
.retire_work
.work
);
1934 dev
= dev_priv
->dev
;
1936 /* Come back later if the device is busy... */
1937 if (!mutex_trylock(&dev
->struct_mutex
)) {
1938 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1942 i915_gem_retire_requests(dev
);
1944 if (!dev_priv
->mm
.suspended
&&
1945 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1946 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
1947 !list_empty(&dev_priv
->blt_ring
.request_list
)))
1948 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1949 mutex_unlock(&dev
->struct_mutex
);
1953 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1954 bool interruptible
, struct intel_ring_buffer
*ring
)
1956 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1962 if (atomic_read(&dev_priv
->mm
.wedged
))
1965 if (seqno
== ring
->outstanding_lazy_request
) {
1966 struct drm_i915_gem_request
*request
;
1968 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1969 if (request
== NULL
)
1972 ret
= i915_add_request(dev
, NULL
, request
, ring
);
1978 seqno
= request
->seqno
;
1981 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
1982 if (HAS_PCH_SPLIT(dev
))
1983 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1985 ier
= I915_READ(IER
);
1987 DRM_ERROR("something (likely vbetool) disabled "
1988 "interrupts, re-enabling\n");
1989 i915_driver_irq_preinstall(dev
);
1990 i915_driver_irq_postinstall(dev
);
1993 trace_i915_gem_request_wait_begin(dev
, seqno
);
1995 ring
->waiting_seqno
= seqno
;
1996 ring
->user_irq_get(ring
);
1998 ret
= wait_event_interruptible(ring
->irq_queue
,
1999 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2000 || atomic_read(&dev_priv
->mm
.wedged
));
2002 wait_event(ring
->irq_queue
,
2003 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2004 || atomic_read(&dev_priv
->mm
.wedged
));
2006 ring
->user_irq_put(ring
);
2007 ring
->waiting_seqno
= 0;
2009 trace_i915_gem_request_wait_end(dev
, seqno
);
2011 if (atomic_read(&dev_priv
->mm
.wedged
))
2014 if (ret
&& ret
!= -ERESTARTSYS
)
2015 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2016 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2017 dev_priv
->next_seqno
);
2019 /* Directly dispatch request retiring. While we have the work queue
2020 * to handle this, the waiter on a request often wants an associated
2021 * buffer to have made it to the inactive list, and we would need
2022 * a separate wait queue to handle that.
2025 i915_gem_retire_requests_ring(dev
, ring
);
2031 * Waits for a sequence number to be signaled, and cleans up the
2032 * request and object lists appropriately for that event.
2035 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2036 struct intel_ring_buffer
*ring
)
2038 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2042 * Ensures that all rendering to the object has completed and the object is
2043 * safe to unbind from the GTT or access from the CPU.
2046 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
2049 struct drm_device
*dev
= obj
->base
.dev
;
2052 /* This function only exists to support waiting for existing rendering,
2053 * not for emitting required flushes.
2055 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2057 /* If there is rendering queued on the buffer being evicted, wait for
2061 ret
= i915_do_wait_request(dev
,
2062 obj
->last_rendering_seqno
,
2073 * Unbinds an object from the GTT aperture.
2076 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2080 if (obj
->gtt_space
== NULL
)
2083 if (obj
->pin_count
!= 0) {
2084 DRM_ERROR("Attempting to unbind pinned buffer\n");
2088 /* blow away mappings if mapped through GTT */
2089 i915_gem_release_mmap(obj
);
2091 /* Move the object to the CPU domain to ensure that
2092 * any possible CPU writes while it's not in the GTT
2093 * are flushed when we go to remap it. This will
2094 * also ensure that all pending GPU writes are finished
2097 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2098 if (ret
== -ERESTARTSYS
)
2100 /* Continue on if we fail due to EIO, the GPU is hung so we
2101 * should be safe and we need to cleanup or else we might
2102 * cause memory corruption through use-after-free.
2105 i915_gem_clflush_object(obj
);
2106 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2109 /* release the fence reg _after_ flushing */
2110 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
)
2111 i915_gem_clear_fence_reg(obj
);
2113 i915_gem_gtt_unbind_object(obj
);
2114 i915_gem_object_put_pages_gtt(obj
);
2116 list_del_init(&obj
->gtt_list
);
2117 list_del_init(&obj
->mm_list
);
2118 /* Avoid an unnecessary call to unbind on rebind. */
2119 obj
->map_and_fenceable
= true;
2121 drm_mm_put_block(obj
->gtt_space
);
2122 obj
->gtt_space
= NULL
;
2123 obj
->gtt_offset
= 0;
2125 if (i915_gem_object_is_purgeable(obj
))
2126 i915_gem_object_truncate(obj
);
2128 trace_i915_gem_object_unbind(obj
);
2134 i915_gem_flush_ring(struct drm_device
*dev
,
2135 struct intel_ring_buffer
*ring
,
2136 uint32_t invalidate_domains
,
2137 uint32_t flush_domains
)
2139 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2140 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2143 static int i915_ring_idle(struct drm_device
*dev
,
2144 struct intel_ring_buffer
*ring
)
2146 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2149 i915_gem_flush_ring(dev
, ring
,
2150 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2151 return i915_wait_request(dev
,
2152 i915_gem_next_request_seqno(dev
, ring
),
2157 i915_gpu_idle(struct drm_device
*dev
)
2159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2163 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2164 list_empty(&dev_priv
->mm
.active_list
));
2168 /* Flush everything onto the inactive list. */
2169 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2173 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2177 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2184 static int sandybridge_write_fence_reg(struct drm_i915_gem_object
*obj
,
2185 struct intel_ring_buffer
*pipelined
)
2187 struct drm_device
*dev
= obj
->base
.dev
;
2188 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2189 u32 size
= obj
->gtt_space
->size
;
2190 int regnum
= obj
->fence_reg
;
2193 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2195 val
|= obj
->gtt_offset
& 0xfffff000;
2196 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2197 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2199 if (obj
->tiling_mode
== I915_TILING_Y
)
2200 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2201 val
|= I965_FENCE_REG_VALID
;
2204 int ret
= intel_ring_begin(pipelined
, 6);
2208 intel_ring_emit(pipelined
, MI_NOOP
);
2209 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2210 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8);
2211 intel_ring_emit(pipelined
, (u32
)val
);
2212 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8 + 4);
2213 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2214 intel_ring_advance(pipelined
);
2216 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ regnum
* 8, val
);
2221 static int i965_write_fence_reg(struct drm_i915_gem_object
*obj
,
2222 struct intel_ring_buffer
*pipelined
)
2224 struct drm_device
*dev
= obj
->base
.dev
;
2225 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2226 u32 size
= obj
->gtt_space
->size
;
2227 int regnum
= obj
->fence_reg
;
2230 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2232 val
|= obj
->gtt_offset
& 0xfffff000;
2233 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2234 if (obj
->tiling_mode
== I915_TILING_Y
)
2235 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2236 val
|= I965_FENCE_REG_VALID
;
2239 int ret
= intel_ring_begin(pipelined
, 6);
2243 intel_ring_emit(pipelined
, MI_NOOP
);
2244 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2245 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8);
2246 intel_ring_emit(pipelined
, (u32
)val
);
2247 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8 + 4);
2248 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2249 intel_ring_advance(pipelined
);
2251 I915_WRITE64(FENCE_REG_965_0
+ regnum
* 8, val
);
2256 static int i915_write_fence_reg(struct drm_i915_gem_object
*obj
,
2257 struct intel_ring_buffer
*pipelined
)
2259 struct drm_device
*dev
= obj
->base
.dev
;
2260 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2261 u32 size
= obj
->gtt_space
->size
;
2262 u32 fence_reg
, val
, pitch_val
;
2265 if (WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2266 (size
& -size
) != size
||
2267 (obj
->gtt_offset
& (size
- 1)),
2268 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2269 obj
->gtt_offset
, obj
->map_and_fenceable
, size
))
2272 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2277 /* Note: pitch better be a power of two tile widths */
2278 pitch_val
= obj
->stride
/ tile_width
;
2279 pitch_val
= ffs(pitch_val
) - 1;
2281 val
= obj
->gtt_offset
;
2282 if (obj
->tiling_mode
== I915_TILING_Y
)
2283 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2284 val
|= I915_FENCE_SIZE_BITS(size
);
2285 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2286 val
|= I830_FENCE_REG_VALID
;
2288 fence_reg
= obj
->fence_reg
;
2290 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2292 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2295 int ret
= intel_ring_begin(pipelined
, 4);
2299 intel_ring_emit(pipelined
, MI_NOOP
);
2300 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2301 intel_ring_emit(pipelined
, fence_reg
);
2302 intel_ring_emit(pipelined
, val
);
2303 intel_ring_advance(pipelined
);
2305 I915_WRITE(fence_reg
, val
);
2310 static int i830_write_fence_reg(struct drm_i915_gem_object
*obj
,
2311 struct intel_ring_buffer
*pipelined
)
2313 struct drm_device
*dev
= obj
->base
.dev
;
2314 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2315 u32 size
= obj
->gtt_space
->size
;
2316 int regnum
= obj
->fence_reg
;
2320 if (WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2321 (size
& -size
) != size
||
2322 (obj
->gtt_offset
& (size
- 1)),
2323 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2324 obj
->gtt_offset
, size
))
2327 pitch_val
= obj
->stride
/ 128;
2328 pitch_val
= ffs(pitch_val
) - 1;
2330 val
= obj
->gtt_offset
;
2331 if (obj
->tiling_mode
== I915_TILING_Y
)
2332 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2333 val
|= I830_FENCE_SIZE_BITS(size
);
2334 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2335 val
|= I830_FENCE_REG_VALID
;
2338 int ret
= intel_ring_begin(pipelined
, 4);
2342 intel_ring_emit(pipelined
, MI_NOOP
);
2343 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2344 intel_ring_emit(pipelined
, FENCE_REG_830_0
+ regnum
*4);
2345 intel_ring_emit(pipelined
, val
);
2346 intel_ring_advance(pipelined
);
2348 I915_WRITE(FENCE_REG_830_0
+ regnum
* 4, val
);
2353 static int i915_find_fence_reg(struct drm_device
*dev
,
2356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2357 struct drm_i915_fence_reg
*reg
;
2358 struct drm_i915_gem_object
*obj
= NULL
;
2361 /* First try to find a free reg */
2363 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2364 reg
= &dev_priv
->fence_regs
[i
];
2368 if (!reg
->obj
->pin_count
)
2375 /* None available, try to steal one or wait for a user to finish */
2376 avail
= I915_FENCE_REG_NONE
;
2377 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2384 avail
= obj
->fence_reg
;
2388 BUG_ON(avail
== I915_FENCE_REG_NONE
);
2390 /* We only have a reference on obj from the active list. put_fence_reg
2391 * might drop that one, causing a use-after-free in it. So hold a
2392 * private reference to obj like the other callers of put_fence_reg
2393 * (set_tiling ioctl) do. */
2394 drm_gem_object_reference(&obj
->base
);
2395 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2396 drm_gem_object_unreference(&obj
->base
);
2404 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2405 * @obj: object to map through a fence reg
2407 * When mapping objects through the GTT, userspace wants to be able to write
2408 * to them without having to worry about swizzling if the object is tiled.
2410 * This function walks the fence regs looking for a free one for @obj,
2411 * stealing one if it can't find any.
2413 * It then sets up the reg based on the object's properties: address, pitch
2414 * and tiling format.
2417 i915_gem_object_get_fence_reg(struct drm_i915_gem_object
*obj
,
2420 struct drm_device
*dev
= obj
->base
.dev
;
2421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2422 struct drm_i915_fence_reg
*reg
= NULL
;
2423 struct intel_ring_buffer
*pipelined
= NULL
;
2426 /* Just update our place in the LRU if our fence is getting used. */
2427 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2428 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2429 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2433 switch (obj
->tiling_mode
) {
2434 case I915_TILING_NONE
:
2435 WARN(1, "allocating a fence for non-tiled object?\n");
2440 WARN((obj
->stride
& (512 - 1)),
2441 "object 0x%08x is X tiled but has non-512B pitch\n",
2447 WARN((obj
->stride
& (128 - 1)),
2448 "object 0x%08x is Y tiled but has non-128B pitch\n",
2453 ret
= i915_find_fence_reg(dev
, interruptible
);
2457 obj
->fence_reg
= ret
;
2458 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2459 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2463 switch (INTEL_INFO(dev
)->gen
) {
2465 ret
= sandybridge_write_fence_reg(obj
, pipelined
);
2469 ret
= i965_write_fence_reg(obj
, pipelined
);
2472 ret
= i915_write_fence_reg(obj
, pipelined
);
2475 ret
= i830_write_fence_reg(obj
, pipelined
);
2479 trace_i915_gem_object_get_fence(obj
,
2486 * i915_gem_clear_fence_reg - clear out fence register info
2487 * @obj: object to clear
2489 * Zeroes out the fence register itself and clears out the associated
2490 * data structures in dev_priv and obj.
2493 i915_gem_clear_fence_reg(struct drm_i915_gem_object
*obj
)
2495 struct drm_device
*dev
= obj
->base
.dev
;
2496 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2497 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2500 switch (INTEL_INFO(dev
)->gen
) {
2502 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2503 (obj
->fence_reg
* 8), 0);
2507 I915_WRITE64(FENCE_REG_965_0
+ (obj
->fence_reg
* 8), 0);
2510 if (obj
->fence_reg
>= 8)
2511 fence_reg
= FENCE_REG_945_8
+ (obj
->fence_reg
- 8) * 4;
2514 fence_reg
= FENCE_REG_830_0
+ obj
->fence_reg
* 4;
2516 I915_WRITE(fence_reg
, 0);
2521 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2522 list_del_init(®
->lru_list
);
2526 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2527 * to the buffer to finish, and then resets the fence register.
2528 * @obj: tiled object holding a fence register.
2529 * @bool: whether the wait upon the fence is interruptible
2531 * Zeroes out the fence register itself and clears out the associated
2532 * data structures in dev_priv and obj.
2535 i915_gem_object_put_fence_reg(struct drm_i915_gem_object
*obj
,
2538 struct drm_device
*dev
= obj
->base
.dev
;
2541 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2544 /* If we've changed tiling, GTT-mappings of the object
2545 * need to re-fault to ensure that the correct fence register
2546 * setup is in place.
2548 i915_gem_release_mmap(obj
);
2550 /* On the i915, GPU access to tiled buffers is via a fence,
2551 * therefore we must wait for any outstanding access to complete
2552 * before clearing the fence.
2554 if (obj
->fenced_gpu_access
) {
2555 ret
= i915_gem_object_flush_gpu_write_domain(obj
, NULL
);
2559 obj
->fenced_gpu_access
= false;
2562 if (obj
->last_fenced_seqno
) {
2563 ret
= i915_do_wait_request(dev
,
2564 obj
->last_fenced_seqno
,
2566 obj
->last_fenced_ring
);
2570 obj
->last_fenced_seqno
= false;
2573 i915_gem_object_flush_gtt_write_domain(obj
);
2574 i915_gem_clear_fence_reg(obj
);
2580 * Finds free space in the GTT aperture and binds the object there.
2583 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2585 bool map_and_fenceable
)
2587 struct drm_device
*dev
= obj
->base
.dev
;
2588 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2589 struct drm_mm_node
*free_space
;
2590 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2591 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2592 bool mappable
, fenceable
;
2595 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2596 DRM_ERROR("Attempting to bind a purgeable object\n");
2600 fence_size
= i915_gem_get_gtt_size(obj
);
2601 fence_alignment
= i915_gem_get_gtt_alignment(obj
);
2602 unfenced_alignment
= i915_gem_get_unfenced_gtt_alignment(obj
);
2605 alignment
= map_and_fenceable
? fence_alignment
:
2607 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2608 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2612 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2614 /* If the object is bigger than the entire aperture, reject it early
2615 * before evicting everything in a vain attempt to find space.
2617 if (obj
->base
.size
>
2618 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2619 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2624 if (map_and_fenceable
)
2626 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2628 dev_priv
->mm
.gtt_mappable_end
,
2631 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2632 size
, alignment
, 0);
2634 if (free_space
!= NULL
) {
2635 if (map_and_fenceable
)
2637 drm_mm_get_block_range_generic(free_space
,
2639 dev_priv
->mm
.gtt_mappable_end
,
2643 drm_mm_get_block(free_space
, size
, alignment
);
2645 if (obj
->gtt_space
== NULL
) {
2646 /* If the gtt is empty and we're still having trouble
2647 * fitting our object in, we're out of memory.
2649 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2657 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2659 drm_mm_put_block(obj
->gtt_space
);
2660 obj
->gtt_space
= NULL
;
2662 if (ret
== -ENOMEM
) {
2663 /* first try to clear up some space from the GTT */
2664 ret
= i915_gem_evict_something(dev
, size
,
2668 /* now try to shrink everyone else */
2683 ret
= i915_gem_gtt_bind_object(obj
);
2685 i915_gem_object_put_pages_gtt(obj
);
2686 drm_mm_put_block(obj
->gtt_space
);
2687 obj
->gtt_space
= NULL
;
2689 ret
= i915_gem_evict_something(dev
, size
,
2690 alignment
, map_and_fenceable
);
2697 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2698 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2700 /* Assert that the object is not currently in any GPU domain. As it
2701 * wasn't in the GTT, there shouldn't be any way it could have been in
2704 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2705 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2707 obj
->gtt_offset
= obj
->gtt_space
->start
;
2710 obj
->gtt_space
->size
== fence_size
&&
2711 (obj
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2714 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2716 obj
->map_and_fenceable
= mappable
&& fenceable
;
2718 trace_i915_gem_object_bind(obj
, obj
->gtt_offset
, map_and_fenceable
);
2723 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2725 /* If we don't have a page list set up, then we're not pinned
2726 * to GPU, and we can ignore the cache flush because it'll happen
2727 * again at bind time.
2729 if (obj
->pages
== NULL
)
2732 trace_i915_gem_object_clflush(obj
);
2734 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2737 /** Flushes any GPU write domain for the object if it's dirty. */
2739 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
,
2740 struct intel_ring_buffer
*pipelined
)
2742 struct drm_device
*dev
= obj
->base
.dev
;
2744 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2747 /* Queue the GPU write cache flushing we need. */
2748 i915_gem_flush_ring(dev
, obj
->ring
, 0, obj
->base
.write_domain
);
2749 BUG_ON(obj
->base
.write_domain
);
2751 if (pipelined
&& pipelined
== obj
->ring
)
2754 return i915_gem_object_wait_rendering(obj
, true);
2757 /** Flushes the GTT write domain for the object if it's dirty. */
2759 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2761 uint32_t old_write_domain
;
2763 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2766 /* No actual flushing is required for the GTT write domain. Writes
2767 * to it immediately go to main memory as far as we know, so there's
2768 * no chipset flush. It also doesn't land in render cache.
2770 i915_gem_release_mmap(obj
);
2772 old_write_domain
= obj
->base
.write_domain
;
2773 obj
->base
.write_domain
= 0;
2775 trace_i915_gem_object_change_domain(obj
,
2776 obj
->base
.read_domains
,
2780 /** Flushes the CPU write domain for the object if it's dirty. */
2782 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2784 uint32_t old_write_domain
;
2786 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2789 i915_gem_clflush_object(obj
);
2790 intel_gtt_chipset_flush();
2791 old_write_domain
= obj
->base
.write_domain
;
2792 obj
->base
.write_domain
= 0;
2794 trace_i915_gem_object_change_domain(obj
,
2795 obj
->base
.read_domains
,
2800 * Moves a single object to the GTT read, and possibly write domain.
2802 * This function returns when the move is complete, including waiting on
2806 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2808 uint32_t old_write_domain
, old_read_domains
;
2811 /* Not valid to be called on unbound objects. */
2812 if (obj
->gtt_space
== NULL
)
2815 ret
= i915_gem_object_flush_gpu_write_domain(obj
, NULL
);
2819 i915_gem_object_flush_cpu_write_domain(obj
);
2822 ret
= i915_gem_object_wait_rendering(obj
, true);
2827 old_write_domain
= obj
->base
.write_domain
;
2828 old_read_domains
= obj
->base
.read_domains
;
2830 /* It should now be out of any other write domains, and we can update
2831 * the domain values for our changes.
2833 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2834 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2836 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2837 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2841 trace_i915_gem_object_change_domain(obj
,
2849 * Prepare buffer for display plane. Use uninterruptible for possible flush
2850 * wait, as in modesetting process we're not supposed to be interrupted.
2853 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object
*obj
,
2854 struct intel_ring_buffer
*pipelined
)
2856 uint32_t old_read_domains
;
2859 /* Not valid to be called on unbound objects. */
2860 if (obj
->gtt_space
== NULL
)
2863 ret
= i915_gem_object_flush_gpu_write_domain(obj
, pipelined
);
2867 /* Currently, we are always called from an non-interruptible context. */
2869 ret
= i915_gem_object_wait_rendering(obj
, false);
2874 i915_gem_object_flush_cpu_write_domain(obj
);
2876 old_read_domains
= obj
->base
.read_domains
;
2877 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2879 trace_i915_gem_object_change_domain(obj
,
2881 obj
->base
.write_domain
);
2887 i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
2893 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
)
2894 i915_gem_flush_ring(obj
->base
.dev
, obj
->ring
,
2895 0, obj
->base
.write_domain
);
2897 return i915_gem_object_wait_rendering(obj
, interruptible
);
2901 * Moves a single object to the CPU read, and possibly write domain.
2903 * This function returns when the move is complete, including waiting on
2907 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
2909 uint32_t old_write_domain
, old_read_domains
;
2912 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2916 i915_gem_object_flush_gtt_write_domain(obj
);
2918 /* If we have a partially-valid cache of the object in the CPU,
2919 * finish invalidating it and free the per-page flags.
2921 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2924 ret
= i915_gem_object_wait_rendering(obj
, true);
2929 old_write_domain
= obj
->base
.write_domain
;
2930 old_read_domains
= obj
->base
.read_domains
;
2932 /* Flush the CPU cache if it's still invalid. */
2933 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2934 i915_gem_clflush_object(obj
);
2936 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
2939 /* It should now be out of any other write domains, and we can update
2940 * the domain values for our changes.
2942 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2944 /* If we're writing through the CPU, then the GPU read domains will
2945 * need to be invalidated at next use.
2948 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2949 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2952 trace_i915_gem_object_change_domain(obj
,
2960 * Moves the object from a partially CPU read to a full one.
2962 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
2963 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
2966 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
)
2968 if (!obj
->page_cpu_valid
)
2971 /* If we're partially in the CPU read domain, finish moving it in.
2973 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) {
2976 for (i
= 0; i
<= (obj
->base
.size
- 1) / PAGE_SIZE
; i
++) {
2977 if (obj
->page_cpu_valid
[i
])
2979 drm_clflush_pages(obj
->pages
+ i
, 1);
2983 /* Free the page_cpu_valid mappings which are now stale, whether
2984 * or not we've got I915_GEM_DOMAIN_CPU.
2986 kfree(obj
->page_cpu_valid
);
2987 obj
->page_cpu_valid
= NULL
;
2991 * Set the CPU read domain on a range of the object.
2993 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
2994 * not entirely valid. The page_cpu_valid member of the object flags which
2995 * pages have been flushed, and will be respected by
2996 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
2997 * of the whole object.
2999 * This function returns when the move is complete, including waiting on
3003 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
3004 uint64_t offset
, uint64_t size
)
3006 uint32_t old_read_domains
;
3009 if (offset
== 0 && size
== obj
->base
.size
)
3010 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3012 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3015 i915_gem_object_flush_gtt_write_domain(obj
);
3017 /* If we're already fully in the CPU read domain, we're done. */
3018 if (obj
->page_cpu_valid
== NULL
&&
3019 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3022 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3023 * newly adding I915_GEM_DOMAIN_CPU
3025 if (obj
->page_cpu_valid
== NULL
) {
3026 obj
->page_cpu_valid
= kzalloc(obj
->base
.size
/ PAGE_SIZE
,
3028 if (obj
->page_cpu_valid
== NULL
)
3030 } else if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3031 memset(obj
->page_cpu_valid
, 0, obj
->base
.size
/ PAGE_SIZE
);
3033 /* Flush the cache on any pages that are still invalid from the CPU's
3036 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3038 if (obj
->page_cpu_valid
[i
])
3041 drm_clflush_pages(obj
->pages
+ i
, 1);
3043 obj
->page_cpu_valid
[i
] = 1;
3046 /* It should now be out of any other write domains, and we can update
3047 * the domain values for our changes.
3049 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3051 old_read_domains
= obj
->base
.read_domains
;
3052 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3054 trace_i915_gem_object_change_domain(obj
,
3056 obj
->base
.write_domain
);
3061 /* Throttle our rendering by waiting until the ring has completed our requests
3062 * emitted over 20 msec ago.
3064 * Note that if we were to use the current jiffies each time around the loop,
3065 * we wouldn't escape the function with any frames outstanding if the time to
3066 * render a frame was over 20ms.
3068 * This should get us reasonable parallelism between CPU and GPU but also
3069 * relatively low latency when blocking on a particular request to finish.
3072 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3075 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3076 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3077 struct drm_i915_gem_request
*request
;
3078 struct intel_ring_buffer
*ring
= NULL
;
3082 spin_lock(&file_priv
->mm
.lock
);
3083 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3084 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3087 ring
= request
->ring
;
3088 seqno
= request
->seqno
;
3090 spin_unlock(&file_priv
->mm
.lock
);
3096 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3097 /* And wait for the seqno passing without holding any locks and
3098 * causing extra latency for others. This is safe as the irq
3099 * generation is designed to be run atomically and so is
3102 ring
->user_irq_get(ring
);
3103 ret
= wait_event_interruptible(ring
->irq_queue
,
3104 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3105 || atomic_read(&dev_priv
->mm
.wedged
));
3106 ring
->user_irq_put(ring
);
3108 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3113 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3119 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3121 bool map_and_fenceable
)
3123 struct drm_device
*dev
= obj
->base
.dev
;
3124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3127 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3128 WARN_ON(i915_verify_lists(dev
));
3130 if (obj
->gtt_space
!= NULL
) {
3131 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3132 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3133 WARN(obj
->pin_count
,
3134 "bo is already pinned with incorrect alignment:"
3135 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3136 " obj->map_and_fenceable=%d\n",
3137 obj
->gtt_offset
, alignment
,
3139 obj
->map_and_fenceable
);
3140 ret
= i915_gem_object_unbind(obj
);
3146 if (obj
->gtt_space
== NULL
) {
3147 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3153 if (obj
->pin_count
++ == 0) {
3155 list_move_tail(&obj
->mm_list
,
3156 &dev_priv
->mm
.pinned_list
);
3158 obj
->pin_mappable
|= map_and_fenceable
;
3160 WARN_ON(i915_verify_lists(dev
));
3165 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3167 struct drm_device
*dev
= obj
->base
.dev
;
3168 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3170 WARN_ON(i915_verify_lists(dev
));
3171 BUG_ON(obj
->pin_count
== 0);
3172 BUG_ON(obj
->gtt_space
== NULL
);
3174 if (--obj
->pin_count
== 0) {
3176 list_move_tail(&obj
->mm_list
,
3177 &dev_priv
->mm
.inactive_list
);
3178 obj
->pin_mappable
= false;
3180 WARN_ON(i915_verify_lists(dev
));
3184 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3185 struct drm_file
*file
)
3187 struct drm_i915_gem_pin
*args
= data
;
3188 struct drm_i915_gem_object
*obj
;
3191 ret
= i915_mutex_lock_interruptible(dev
);
3195 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3201 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3202 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3207 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3208 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3214 obj
->user_pin_count
++;
3215 obj
->pin_filp
= file
;
3216 if (obj
->user_pin_count
== 1) {
3217 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3222 /* XXX - flush the CPU caches for pinned objects
3223 * as the X server doesn't manage domains yet
3225 i915_gem_object_flush_cpu_write_domain(obj
);
3226 args
->offset
= obj
->gtt_offset
;
3228 drm_gem_object_unreference(&obj
->base
);
3230 mutex_unlock(&dev
->struct_mutex
);
3235 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3236 struct drm_file
*file
)
3238 struct drm_i915_gem_pin
*args
= data
;
3239 struct drm_i915_gem_object
*obj
;
3242 ret
= i915_mutex_lock_interruptible(dev
);
3246 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3252 if (obj
->pin_filp
!= file
) {
3253 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3258 obj
->user_pin_count
--;
3259 if (obj
->user_pin_count
== 0) {
3260 obj
->pin_filp
= NULL
;
3261 i915_gem_object_unpin(obj
);
3265 drm_gem_object_unreference(&obj
->base
);
3267 mutex_unlock(&dev
->struct_mutex
);
3272 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3273 struct drm_file
*file
)
3275 struct drm_i915_gem_busy
*args
= data
;
3276 struct drm_i915_gem_object
*obj
;
3279 ret
= i915_mutex_lock_interruptible(dev
);
3283 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3289 /* Count all active objects as busy, even if they are currently not used
3290 * by the gpu. Users of this interface expect objects to eventually
3291 * become non-busy without any further actions, therefore emit any
3292 * necessary flushes here.
3294 args
->busy
= obj
->active
;
3296 /* Unconditionally flush objects, even when the gpu still uses this
3297 * object. Userspace calling this function indicates that it wants to
3298 * use this buffer rather sooner than later, so issuing the required
3299 * flush earlier is beneficial.
3301 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
)
3302 i915_gem_flush_ring(dev
, obj
->ring
,
3303 0, obj
->base
.write_domain
);
3305 /* Update the active list for the hardware's current position.
3306 * Otherwise this only updates on a delayed timer or when irqs
3307 * are actually unmasked, and our working set ends up being
3308 * larger than required.
3310 i915_gem_retire_requests_ring(dev
, obj
->ring
);
3312 args
->busy
= obj
->active
;
3315 drm_gem_object_unreference(&obj
->base
);
3317 mutex_unlock(&dev
->struct_mutex
);
3322 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3323 struct drm_file
*file_priv
)
3325 return i915_gem_ring_throttle(dev
, file_priv
);
3329 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3330 struct drm_file
*file_priv
)
3332 struct drm_i915_gem_madvise
*args
= data
;
3333 struct drm_i915_gem_object
*obj
;
3336 switch (args
->madv
) {
3337 case I915_MADV_DONTNEED
:
3338 case I915_MADV_WILLNEED
:
3344 ret
= i915_mutex_lock_interruptible(dev
);
3348 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3354 if (obj
->pin_count
) {
3359 if (obj
->madv
!= __I915_MADV_PURGED
)
3360 obj
->madv
= args
->madv
;
3362 /* if the object is no longer bound, discard its backing storage */
3363 if (i915_gem_object_is_purgeable(obj
) &&
3364 obj
->gtt_space
== NULL
)
3365 i915_gem_object_truncate(obj
);
3367 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3370 drm_gem_object_unreference(&obj
->base
);
3372 mutex_unlock(&dev
->struct_mutex
);
3376 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3380 struct drm_i915_gem_object
*obj
;
3382 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3386 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3391 i915_gem_info_add_obj(dev_priv
, size
);
3393 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3394 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3396 obj
->agp_type
= AGP_USER_MEMORY
;
3397 obj
->base
.driver_private
= NULL
;
3398 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3399 INIT_LIST_HEAD(&obj
->mm_list
);
3400 INIT_LIST_HEAD(&obj
->gtt_list
);
3401 INIT_LIST_HEAD(&obj
->ring_list
);
3402 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3403 obj
->madv
= I915_MADV_WILLNEED
;
3404 /* Avoid an unnecessary call to unbind on the first bind. */
3405 obj
->map_and_fenceable
= true;
3410 int i915_gem_init_object(struct drm_gem_object
*obj
)
3417 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
)
3419 struct drm_device
*dev
= obj
->base
.dev
;
3420 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3423 ret
= i915_gem_object_unbind(obj
);
3424 if (ret
== -ERESTARTSYS
) {
3425 list_move(&obj
->mm_list
,
3426 &dev_priv
->mm
.deferred_free_list
);
3430 if (obj
->base
.map_list
.map
)
3431 i915_gem_free_mmap_offset(obj
);
3433 drm_gem_object_release(&obj
->base
);
3434 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3436 kfree(obj
->page_cpu_valid
);
3441 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3443 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3444 struct drm_device
*dev
= obj
->base
.dev
;
3446 trace_i915_gem_object_destroy(obj
);
3448 while (obj
->pin_count
> 0)
3449 i915_gem_object_unpin(obj
);
3452 i915_gem_detach_phys_object(dev
, obj
);
3454 i915_gem_free_object_tail(obj
);
3458 i915_gem_idle(struct drm_device
*dev
)
3460 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3463 mutex_lock(&dev
->struct_mutex
);
3465 if (dev_priv
->mm
.suspended
) {
3466 mutex_unlock(&dev
->struct_mutex
);
3470 ret
= i915_gpu_idle(dev
);
3472 mutex_unlock(&dev
->struct_mutex
);
3476 /* Under UMS, be paranoid and evict. */
3477 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3478 ret
= i915_gem_evict_inactive(dev
, false);
3480 mutex_unlock(&dev
->struct_mutex
);
3485 i915_gem_reset_fences(dev
);
3487 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3488 * We need to replace this with a semaphore, or something.
3489 * And not confound mm.suspended!
3491 dev_priv
->mm
.suspended
= 1;
3492 del_timer_sync(&dev_priv
->hangcheck_timer
);
3494 i915_kernel_lost_context(dev
);
3495 i915_gem_cleanup_ringbuffer(dev
);
3497 mutex_unlock(&dev
->struct_mutex
);
3499 /* Cancel the retire work handler, which should be idle now. */
3500 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3506 i915_gem_init_ringbuffer(struct drm_device
*dev
)
3508 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3511 ret
= intel_init_render_ring_buffer(dev
);
3516 ret
= intel_init_bsd_ring_buffer(dev
);
3518 goto cleanup_render_ring
;
3522 ret
= intel_init_blt_ring_buffer(dev
);
3524 goto cleanup_bsd_ring
;
3527 dev_priv
->next_seqno
= 1;
3532 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
3533 cleanup_render_ring
:
3534 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
3539 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3541 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3543 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
3544 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
3545 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
3549 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3550 struct drm_file
*file_priv
)
3552 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3555 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3558 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3559 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3560 atomic_set(&dev_priv
->mm
.wedged
, 0);
3563 mutex_lock(&dev
->struct_mutex
);
3564 dev_priv
->mm
.suspended
= 0;
3566 ret
= i915_gem_init_ringbuffer(dev
);
3568 mutex_unlock(&dev
->struct_mutex
);
3572 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3573 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
3574 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
3575 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
3576 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3577 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3578 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
3579 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
3580 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
3581 mutex_unlock(&dev
->struct_mutex
);
3583 ret
= drm_irq_install(dev
);
3585 goto cleanup_ringbuffer
;
3590 mutex_lock(&dev
->struct_mutex
);
3591 i915_gem_cleanup_ringbuffer(dev
);
3592 dev_priv
->mm
.suspended
= 1;
3593 mutex_unlock(&dev
->struct_mutex
);
3599 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3600 struct drm_file
*file_priv
)
3602 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3605 drm_irq_uninstall(dev
);
3606 return i915_gem_idle(dev
);
3610 i915_gem_lastclose(struct drm_device
*dev
)
3614 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3617 ret
= i915_gem_idle(dev
);
3619 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3623 init_ring_lists(struct intel_ring_buffer
*ring
)
3625 INIT_LIST_HEAD(&ring
->active_list
);
3626 INIT_LIST_HEAD(&ring
->request_list
);
3627 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3631 i915_gem_load(struct drm_device
*dev
)
3634 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3636 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3637 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3638 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3639 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
3640 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3641 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
3642 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3643 init_ring_lists(&dev_priv
->render_ring
);
3644 init_ring_lists(&dev_priv
->bsd_ring
);
3645 init_ring_lists(&dev_priv
->blt_ring
);
3646 for (i
= 0; i
< 16; i
++)
3647 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3648 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3649 i915_gem_retire_work_handler
);
3650 init_completion(&dev_priv
->error_completion
);
3652 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3654 u32 tmp
= I915_READ(MI_ARB_STATE
);
3655 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3656 /* arb state is a masked write, so set bit + bit in mask */
3657 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3658 I915_WRITE(MI_ARB_STATE
, tmp
);
3662 /* Old X drivers will take 0-2 for front, back, depth buffers */
3663 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3664 dev_priv
->fence_reg_start
= 3;
3666 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3667 dev_priv
->num_fence_regs
= 16;
3669 dev_priv
->num_fence_regs
= 8;
3671 /* Initialize fence registers to zero */
3672 switch (INTEL_INFO(dev
)->gen
) {
3674 for (i
= 0; i
< 16; i
++)
3675 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
3679 for (i
= 0; i
< 16; i
++)
3680 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
3683 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3684 for (i
= 0; i
< 8; i
++)
3685 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
3687 for (i
= 0; i
< 8; i
++)
3688 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
3691 i915_gem_detect_bit_6_swizzle(dev
);
3692 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3694 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3695 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3696 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3700 * Create a physically contiguous memory object for this object
3701 * e.g. for cursor + overlay regs
3703 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3704 int id
, int size
, int align
)
3706 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3707 struct drm_i915_gem_phys_object
*phys_obj
;
3710 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3713 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3719 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3720 if (!phys_obj
->handle
) {
3725 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3728 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3736 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3738 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3739 struct drm_i915_gem_phys_object
*phys_obj
;
3741 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3744 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3745 if (phys_obj
->cur_obj
) {
3746 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3750 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3752 drm_pci_free(dev
, phys_obj
->handle
);
3754 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3757 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3761 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3762 i915_gem_free_phys_object(dev
, i
);
3765 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3766 struct drm_i915_gem_object
*obj
)
3768 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3775 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3777 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3778 for (i
= 0; i
< page_count
; i
++) {
3779 struct page
*page
= read_cache_page_gfp(mapping
, i
,
3780 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3781 if (!IS_ERR(page
)) {
3782 char *dst
= kmap_atomic(page
);
3783 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3786 drm_clflush_pages(&page
, 1);
3788 set_page_dirty(page
);
3789 mark_page_accessed(page
);
3790 page_cache_release(page
);
3793 intel_gtt_chipset_flush();
3795 obj
->phys_obj
->cur_obj
= NULL
;
3796 obj
->phys_obj
= NULL
;
3800 i915_gem_attach_phys_object(struct drm_device
*dev
,
3801 struct drm_i915_gem_object
*obj
,
3805 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3806 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3811 if (id
> I915_MAX_PHYS_OBJECT
)
3814 if (obj
->phys_obj
) {
3815 if (obj
->phys_obj
->id
== id
)
3817 i915_gem_detach_phys_object(dev
, obj
);
3820 /* create a new object */
3821 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3822 ret
= i915_gem_init_phys_object(dev
, id
,
3823 obj
->base
.size
, align
);
3825 DRM_ERROR("failed to init phys object %d size: %zu\n",
3826 id
, obj
->base
.size
);
3831 /* bind to the object */
3832 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3833 obj
->phys_obj
->cur_obj
= obj
;
3835 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3837 for (i
= 0; i
< page_count
; i
++) {
3841 page
= read_cache_page_gfp(mapping
, i
,
3842 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3844 return PTR_ERR(page
);
3846 src
= kmap_atomic(page
);
3847 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3848 memcpy(dst
, src
, PAGE_SIZE
);
3851 mark_page_accessed(page
);
3852 page_cache_release(page
);
3859 i915_gem_phys_pwrite(struct drm_device
*dev
,
3860 struct drm_i915_gem_object
*obj
,
3861 struct drm_i915_gem_pwrite
*args
,
3862 struct drm_file
*file_priv
)
3864 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
3865 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
3867 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
3868 unsigned long unwritten
;
3870 /* The physical object once assigned is fixed for the lifetime
3871 * of the obj, so we can safely drop the lock and continue
3874 mutex_unlock(&dev
->struct_mutex
);
3875 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
3876 mutex_lock(&dev
->struct_mutex
);
3881 intel_gtt_chipset_flush();
3885 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
3887 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3889 /* Clean up our request list when the client is going away, so that
3890 * later retire_requests won't dereference our soon-to-be-gone
3893 spin_lock(&file_priv
->mm
.lock
);
3894 while (!list_empty(&file_priv
->mm
.request_list
)) {
3895 struct drm_i915_gem_request
*request
;
3897 request
= list_first_entry(&file_priv
->mm
.request_list
,
3898 struct drm_i915_gem_request
,
3900 list_del(&request
->client_list
);
3901 request
->file_priv
= NULL
;
3903 spin_unlock(&file_priv
->mm
.lock
);
3907 i915_gpu_is_active(struct drm_device
*dev
)
3909 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3912 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
3913 list_empty(&dev_priv
->mm
.active_list
);
3915 return !lists_empty
;
3919 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
3923 struct drm_i915_private
*dev_priv
=
3924 container_of(shrinker
,
3925 struct drm_i915_private
,
3926 mm
.inactive_shrinker
);
3927 struct drm_device
*dev
= dev_priv
->dev
;
3928 struct drm_i915_gem_object
*obj
, *next
;
3931 if (!mutex_trylock(&dev
->struct_mutex
))
3934 /* "fast-path" to count number of available objects */
3935 if (nr_to_scan
== 0) {
3937 list_for_each_entry(obj
,
3938 &dev_priv
->mm
.inactive_list
,
3941 mutex_unlock(&dev
->struct_mutex
);
3942 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
3946 /* first scan for clean buffers */
3947 i915_gem_retire_requests(dev
);
3949 list_for_each_entry_safe(obj
, next
,
3950 &dev_priv
->mm
.inactive_list
,
3952 if (i915_gem_object_is_purgeable(obj
)) {
3953 if (i915_gem_object_unbind(obj
) == 0 &&
3959 /* second pass, evict/count anything still on the inactive list */
3961 list_for_each_entry_safe(obj
, next
,
3962 &dev_priv
->mm
.inactive_list
,
3965 i915_gem_object_unbind(obj
) == 0)
3971 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
3973 * We are desperate for pages, so as a last resort, wait
3974 * for the GPU to finish and discard whatever we can.
3975 * This has a dramatic impact to reduce the number of
3976 * OOM-killer events whilst running the GPU aggressively.
3978 if (i915_gpu_idle(dev
) == 0)
3981 mutex_unlock(&dev
->struct_mutex
);
3982 return cnt
/ 100 * sysctl_vfs_cache_pressure
;