2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
138 unsigned long long addr
;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
145 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
146 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
148 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring
->cycle_state
);
152 ring
->deq_seg
= ring
->deq_seg
->next
;
153 ring
->dequeue
= ring
->deq_seg
->trbs
;
154 next
= ring
->dequeue
;
156 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
157 if (ring
== xhci
->event_ring
)
158 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
159 else if (ring
== xhci
->cmd_ring
)
160 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
162 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
182 union xhci_trb
*next
;
183 unsigned long long addr
;
185 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
186 next
= ++(ring
->enqueue
);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
194 if (ring
!= xhci
->event_ring
) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci
)) {
200 next
->link
.control
&= ~TRB_CHAIN
;
201 next
->link
.control
|= chain
;
203 /* Give this link TRB to the hardware */
205 if (next
->link
.control
& TRB_CYCLE
)
206 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
208 next
->link
.control
|= (u32
) TRB_CYCLE
;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
212 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
214 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring
->cycle_state
);
219 ring
->enq_seg
= ring
->enq_seg
->next
;
220 ring
->enqueue
= ring
->enq_seg
->trbs
;
221 next
= ring
->enqueue
;
223 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
224 if (ring
== xhci
->event_ring
)
225 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
226 else if (ring
== xhci
->cmd_ring
)
227 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
229 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
239 unsigned int num_trbs
)
242 union xhci_trb
*enq
= ring
->enqueue
;
243 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
245 /* Check if ring is empty */
246 if (enq
== ring
->dequeue
)
248 /* Make sure there's an extra empty TRB available */
249 for (i
= 0; i
<= num_trbs
; ++i
) {
250 if (enq
== ring
->dequeue
)
253 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
254 enq_seg
= enq_seg
->next
;
261 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
266 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
267 xhci
->event_ring
->dequeue
);
268 if (deq
== 0 && !in_interrupt())
269 xhci_warn(xhci
, "WARN something wrong with SW event ring "
271 /* Update HC event ring dequeue pointer */
272 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
273 temp
&= ERST_PTR_MASK
;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
278 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
280 &xhci
->ir_set
->erst_dequeue
);
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
288 xhci_dbg(xhci
, "// Ding dong!\n");
289 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
290 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
295 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
296 unsigned int slot_id
,
297 unsigned int ep_index
)
299 struct xhci_virt_ep
*ep
;
300 unsigned int ep_state
;
302 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
304 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
305 ep_state
= ep
->ep_state
;
306 /* Don't ring the doorbell for this endpoint if there are pending
307 * cancellations because the we don't want to interrupt processing.
309 if (!ep
->cancels_pending
&& !(ep_state
& SET_DEQ_PENDING
)
310 && !(ep_state
& EP_HALTED
)) {
311 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
312 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
313 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
314 * isn't time-critical and we shouldn't make the CPU wait for
317 xhci_readl(xhci
, db_addr
);
322 * Find the segment that trb is in. Start searching in start_seg.
323 * If we must move past a segment that has a link TRB with a toggle cycle state
324 * bit set, then we will toggle the value pointed at by cycle_state.
326 static struct xhci_segment
*find_trb_seg(
327 struct xhci_segment
*start_seg
,
328 union xhci_trb
*trb
, int *cycle_state
)
330 struct xhci_segment
*cur_seg
= start_seg
;
331 struct xhci_generic_trb
*generic_trb
;
333 while (cur_seg
->trbs
> trb
||
334 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
335 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
336 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
337 (generic_trb
->field
[3] & LINK_TOGGLE
))
338 *cycle_state
= ~(*cycle_state
) & 0x1;
339 cur_seg
= cur_seg
->next
;
340 if (cur_seg
== start_seg
)
341 /* Looped over the entire list. Oops! */
348 * Move the xHC's endpoint ring dequeue pointer past cur_td.
349 * Record the new state of the xHC's endpoint ring dequeue segment,
350 * dequeue pointer, and new consumer cycle state in state.
351 * Update our internal representation of the ring's dequeue pointer.
353 * We do this in three jumps:
354 * - First we update our new ring state to be the same as when the xHC stopped.
355 * - Then we traverse the ring to find the segment that contains
356 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
357 * any link TRBs with the toggle cycle bit set.
358 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
359 * if we've moved it past a link TRB with the toggle cycle bit set.
361 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
362 unsigned int slot_id
, unsigned int ep_index
,
363 struct xhci_td
*cur_td
, struct xhci_dequeue_state
*state
)
365 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
366 struct xhci_ring
*ep_ring
= dev
->eps
[ep_index
].ring
;
367 struct xhci_generic_trb
*trb
;
368 struct xhci_ep_ctx
*ep_ctx
;
371 state
->new_cycle_state
= 0;
372 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
373 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
374 dev
->eps
[ep_index
].stopped_trb
,
375 &state
->new_cycle_state
);
376 if (!state
->new_deq_seg
)
378 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
379 xhci_dbg(xhci
, "Finding endpoint context\n");
380 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
381 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
383 state
->new_deq_ptr
= cur_td
->last_trb
;
384 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
385 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
387 &state
->new_cycle_state
);
388 if (!state
->new_deq_seg
)
391 trb
= &state
->new_deq_ptr
->generic
;
392 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
393 (trb
->field
[3] & LINK_TOGGLE
))
394 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
395 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
397 /* Don't update the ring cycle state for the producer (us). */
398 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
400 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
401 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
402 (unsigned long long) addr
);
403 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
404 ep_ring
->dequeue
= state
->new_deq_ptr
;
405 ep_ring
->deq_seg
= state
->new_deq_seg
;
408 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
409 struct xhci_td
*cur_td
)
411 struct xhci_segment
*cur_seg
;
412 union xhci_trb
*cur_trb
;
414 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
416 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
417 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
418 TRB_TYPE(TRB_LINK
)) {
419 /* Unchain any chained Link TRBs, but
420 * leave the pointers intact.
422 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
423 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
424 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
425 "in seg %p (0x%llx dma)\n",
427 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
429 (unsigned long long)cur_seg
->dma
);
431 cur_trb
->generic
.field
[0] = 0;
432 cur_trb
->generic
.field
[1] = 0;
433 cur_trb
->generic
.field
[2] = 0;
434 /* Preserve only the cycle bit of this TRB */
435 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
436 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
437 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
438 "in seg %p (0x%llx dma)\n",
440 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
442 (unsigned long long)cur_seg
->dma
);
444 if (cur_trb
== cur_td
->last_trb
)
449 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
450 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
451 union xhci_trb
*deq_ptr
, u32 cycle_state
);
453 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
454 unsigned int slot_id
, unsigned int ep_index
,
455 struct xhci_dequeue_state
*deq_state
)
457 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
459 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
460 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
461 deq_state
->new_deq_seg
,
462 (unsigned long long)deq_state
->new_deq_seg
->dma
,
463 deq_state
->new_deq_ptr
,
464 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
465 deq_state
->new_cycle_state
);
466 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
467 deq_state
->new_deq_seg
,
468 deq_state
->new_deq_ptr
,
469 (u32
) deq_state
->new_cycle_state
);
470 /* Stop the TD queueing code from ringing the doorbell until
471 * this command completes. The HC won't set the dequeue pointer
472 * if the ring is running, and ringing the doorbell starts the
475 ep
->ep_state
|= SET_DEQ_PENDING
;
479 * When we get a command completion for a Stop Endpoint Command, we need to
480 * unlink any cancelled TDs from the ring. There are two ways to do that:
482 * 1. If the HW was in the middle of processing the TD that needs to be
483 * cancelled, then we must move the ring's dequeue pointer past the last TRB
484 * in the TD with a Set Dequeue Pointer Command.
485 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
486 * bit cleared) so that the HW will skip over them.
488 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
491 unsigned int slot_id
;
492 unsigned int ep_index
;
493 struct xhci_ring
*ep_ring
;
494 struct xhci_virt_ep
*ep
;
495 struct list_head
*entry
;
496 struct xhci_td
*cur_td
= 0;
497 struct xhci_td
*last_unlinked_td
;
499 struct xhci_dequeue_state deq_state
;
500 #ifdef CONFIG_USB_HCD_STAT
501 ktime_t stop_time
= ktime_get();
504 memset(&deq_state
, 0, sizeof(deq_state
));
505 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
506 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
507 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
510 if (list_empty(&ep
->cancelled_td_list
))
513 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
514 * We have the xHCI lock, so nothing can modify this list until we drop
515 * it. We're also in the event handler, so we can't get re-interrupted
516 * if another Stop Endpoint command completes
518 list_for_each(entry
, &ep
->cancelled_td_list
) {
519 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
520 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
522 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
524 * If we stopped on the TD we need to cancel, then we have to
525 * move the xHC endpoint ring dequeue pointer past this TD.
527 if (cur_td
== ep
->stopped_td
)
528 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
531 td_to_noop(xhci
, ep_ring
, cur_td
);
533 * The event handler won't see a completion for this TD anymore,
534 * so remove it from the endpoint ring's TD list. Keep it in
535 * the cancelled TD list for URB completion later.
537 list_del(&cur_td
->td_list
);
538 ep
->cancels_pending
--;
540 last_unlinked_td
= cur_td
;
542 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
543 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
544 xhci_queue_new_dequeue_state(xhci
,
545 slot_id
, ep_index
, &deq_state
);
546 xhci_ring_cmd_db(xhci
);
548 /* Otherwise just ring the doorbell to restart the ring */
549 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
553 * Drop the lock and complete the URBs in the cancelled TD list.
554 * New TDs to be cancelled might be added to the end of the list before
555 * we can complete all the URBs for the TDs we already unlinked.
556 * So stop when we've completed the URB for the last TD we unlinked.
559 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
560 struct xhci_td
, cancelled_td_list
);
561 list_del(&cur_td
->cancelled_td_list
);
563 /* Clean up the cancelled URB */
564 #ifdef CONFIG_USB_HCD_STAT
565 hcd_stat_update(xhci
->tp_stat
, cur_td
->urb
->actual_length
,
566 ktime_sub(stop_time
, cur_td
->start_time
));
568 cur_td
->urb
->hcpriv
= NULL
;
569 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), cur_td
->urb
);
571 xhci_dbg(xhci
, "Giveback cancelled URB %p\n", cur_td
->urb
);
572 spin_unlock(&xhci
->lock
);
573 /* Doesn't matter what we pass for status, since the core will
574 * just overwrite it (because the URB has been unlinked).
576 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), cur_td
->urb
, 0);
579 spin_lock(&xhci
->lock
);
580 } while (cur_td
!= last_unlinked_td
);
582 /* Return to the event handler with xhci->lock re-acquired */
586 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
587 * we need to clear the set deq pending flag in the endpoint ring state, so that
588 * the TD queueing code can ring the doorbell again. We also need to ring the
589 * endpoint doorbell to restart the ring, but only if there aren't more
590 * cancellations pending.
592 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
593 struct xhci_event_cmd
*event
,
596 unsigned int slot_id
;
597 unsigned int ep_index
;
598 struct xhci_ring
*ep_ring
;
599 struct xhci_virt_device
*dev
;
600 struct xhci_ep_ctx
*ep_ctx
;
601 struct xhci_slot_ctx
*slot_ctx
;
603 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
604 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
605 dev
= xhci
->devs
[slot_id
];
606 ep_ring
= dev
->eps
[ep_index
].ring
;
607 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
608 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
610 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
611 unsigned int ep_state
;
612 unsigned int slot_state
;
614 switch (GET_COMP_CODE(event
->status
)) {
616 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
617 "of stream ID configuration\n");
620 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
621 "to incorrect slot or ep state.\n");
622 ep_state
= ep_ctx
->ep_info
;
623 ep_state
&= EP_STATE_MASK
;
624 slot_state
= slot_ctx
->dev_state
;
625 slot_state
= GET_SLOT_STATE(slot_state
);
626 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
627 slot_state
, ep_state
);
630 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
631 "slot %u was not enabled.\n", slot_id
);
634 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
635 "completion code of %u.\n",
636 GET_COMP_CODE(event
->status
));
639 /* OK what do we do now? The endpoint state is hosed, and we
640 * should never get to this point if the synchronization between
641 * queueing, and endpoint state are correct. This might happen
642 * if the device gets disconnected after we've finished
643 * cancelling URBs, which might not be an error...
646 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
650 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
651 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
654 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
655 struct xhci_event_cmd
*event
,
659 unsigned int ep_index
;
660 struct xhci_ring
*ep_ring
;
662 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
663 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
664 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
665 /* This command will only fail if the endpoint wasn't halted,
668 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
669 (unsigned int) GET_COMP_CODE(event
->status
));
671 /* HW with the reset endpoint quirk needs to have a configure endpoint
672 * command complete before the endpoint can be used. Queue that here
673 * because the HW can't handle two commands being queued in a row.
675 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
676 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
677 xhci_queue_configure_endpoint(xhci
,
678 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
680 xhci_ring_cmd_db(xhci
);
682 /* Clear our internal halted state and restart the ring */
683 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
684 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
688 /* Check to see if a command in the device's command queue matches this one.
689 * Signal the completion or free the command, and return 1. Return 0 if the
690 * completed command isn't at the head of the command list.
692 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
693 struct xhci_virt_device
*virt_dev
,
694 struct xhci_event_cmd
*event
)
696 struct xhci_command
*command
;
698 if (list_empty(&virt_dev
->cmd_list
))
701 command
= list_entry(virt_dev
->cmd_list
.next
,
702 struct xhci_command
, cmd_list
);
703 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
707 GET_COMP_CODE(event
->status
);
708 list_del(&command
->cmd_list
);
709 if (command
->completion
)
710 complete(command
->completion
);
712 xhci_free_command(xhci
, command
);
716 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
717 struct xhci_event_cmd
*event
)
719 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
721 dma_addr_t cmd_dequeue_dma
;
722 struct xhci_input_control_ctx
*ctrl_ctx
;
723 struct xhci_virt_device
*virt_dev
;
724 unsigned int ep_index
;
725 struct xhci_ring
*ep_ring
;
726 unsigned int ep_state
;
728 cmd_dma
= event
->cmd_trb
;
729 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
730 xhci
->cmd_ring
->dequeue
);
731 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
732 if (cmd_dequeue_dma
== 0) {
733 xhci
->error_bitmask
|= 1 << 4;
736 /* Does the DMA address match our internal dequeue pointer address? */
737 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
738 xhci
->error_bitmask
|= 1 << 5;
741 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
742 case TRB_TYPE(TRB_ENABLE_SLOT
):
743 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
744 xhci
->slot_id
= slot_id
;
747 complete(&xhci
->addr_dev
);
749 case TRB_TYPE(TRB_DISABLE_SLOT
):
750 if (xhci
->devs
[slot_id
])
751 xhci_free_virt_device(xhci
, slot_id
);
753 case TRB_TYPE(TRB_CONFIG_EP
):
754 virt_dev
= xhci
->devs
[slot_id
];
755 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
758 * Configure endpoint commands can come from the USB core
759 * configuration or alt setting changes, or because the HW
760 * needed an extra configure endpoint command after a reset
761 * endpoint command. In the latter case, the xHCI driver is
762 * not waiting on the configure endpoint command.
764 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
766 /* Input ctx add_flags are the endpoint index plus one */
767 ep_index
= xhci_last_valid_endpoint(ctrl_ctx
->add_flags
) - 1;
768 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
770 /* This must have been an initial configure endpoint */
771 xhci
->devs
[slot_id
]->cmd_status
=
772 GET_COMP_CODE(event
->status
);
773 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
776 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
777 xhci_dbg(xhci
, "Completed config ep cmd - last ep index = %d, "
778 "state = %d\n", ep_index
, ep_state
);
779 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
780 ep_state
& EP_HALTED
) {
781 /* Clear our internal halted state and restart ring */
782 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
784 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
786 xhci
->devs
[slot_id
]->cmd_status
=
787 GET_COMP_CODE(event
->status
);
788 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
791 case TRB_TYPE(TRB_EVAL_CONTEXT
):
792 virt_dev
= xhci
->devs
[slot_id
];
793 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
795 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
796 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
798 case TRB_TYPE(TRB_ADDR_DEV
):
799 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
800 complete(&xhci
->addr_dev
);
802 case TRB_TYPE(TRB_STOP_RING
):
803 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
805 case TRB_TYPE(TRB_SET_DEQ
):
806 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
808 case TRB_TYPE(TRB_CMD_NOOP
):
809 ++xhci
->noops_handled
;
811 case TRB_TYPE(TRB_RESET_EP
):
812 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
815 /* Skip over unknown commands on the event ring */
816 xhci
->error_bitmask
|= 1 << 6;
819 inc_deq(xhci
, xhci
->cmd_ring
, false);
822 static void handle_port_status(struct xhci_hcd
*xhci
,
823 union xhci_trb
*event
)
827 /* Port status change events always have a successful completion code */
828 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
829 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
830 xhci
->error_bitmask
|= 1 << 8;
832 /* FIXME: core doesn't care about all port link state changes yet */
833 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
834 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
836 /* Update event ring dequeue pointer before dropping the lock */
837 inc_deq(xhci
, xhci
->event_ring
, true);
838 xhci_set_hc_event_deq(xhci
);
840 spin_unlock(&xhci
->lock
);
841 /* Pass this up to the core */
842 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
843 spin_lock(&xhci
->lock
);
847 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
848 * at end_trb, which may be in another segment. If the suspect DMA address is a
849 * TRB in this TD, this function returns that TRB's segment. Otherwise it
852 static struct xhci_segment
*trb_in_td(
853 struct xhci_segment
*start_seg
,
854 union xhci_trb
*start_trb
,
855 union xhci_trb
*end_trb
,
856 dma_addr_t suspect_dma
)
858 dma_addr_t start_dma
;
859 dma_addr_t end_seg_dma
;
860 dma_addr_t end_trb_dma
;
861 struct xhci_segment
*cur_seg
;
863 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
869 /* We may get an event for a Link TRB in the middle of a TD */
870 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
871 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
872 /* If the end TRB isn't in this segment, this is set to 0 */
873 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
875 if (end_trb_dma
> 0) {
876 /* The end TRB is in this segment, so suspect should be here */
877 if (start_dma
<= end_trb_dma
) {
878 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
881 /* Case for one segment with
882 * a TD wrapped around to the top
884 if ((suspect_dma
>= start_dma
&&
885 suspect_dma
<= end_seg_dma
) ||
886 (suspect_dma
>= cur_seg
->dma
&&
887 suspect_dma
<= end_trb_dma
))
892 /* Might still be somewhere in this segment */
893 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
896 cur_seg
= cur_seg
->next
;
897 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
898 } while (cur_seg
!= start_seg
);
904 * If this function returns an error condition, it means it got a Transfer
905 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
906 * At this point, the host controller is probably hosed and should be reset.
908 static int handle_tx_event(struct xhci_hcd
*xhci
,
909 struct xhci_transfer_event
*event
)
911 struct xhci_virt_device
*xdev
;
912 struct xhci_virt_ep
*ep
;
913 struct xhci_ring
*ep_ring
;
914 unsigned int slot_id
;
916 struct xhci_td
*td
= 0;
917 dma_addr_t event_dma
;
918 struct xhci_segment
*event_seg
;
919 union xhci_trb
*event_trb
;
921 int status
= -EINPROGRESS
;
922 struct xhci_ep_ctx
*ep_ctx
;
925 xhci_dbg(xhci
, "In %s\n", __func__
);
926 slot_id
= TRB_TO_SLOT_ID(event
->flags
);
927 xdev
= xhci
->devs
[slot_id
];
929 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
933 /* Endpoint ID is 1 based, our index is zero based */
934 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
935 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
936 ep
= &xdev
->eps
[ep_index
];
938 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
939 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
940 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
944 event_dma
= event
->buffer
;
945 /* This TRB should be in the TD at the head of this ring's TD list */
946 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
947 if (list_empty(&ep_ring
->td_list
)) {
948 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
949 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
950 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
951 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
952 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
956 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
957 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
959 /* Is this a TRB in the currently executing TD? */
960 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
961 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
962 td
->last_trb
, event_dma
);
963 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
965 /* HC is busted, give up! */
966 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
969 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
970 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
971 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
972 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
973 lower_32_bits(event
->buffer
));
974 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
975 upper_32_bits(event
->buffer
));
976 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
977 (unsigned int) event
->transfer_len
);
978 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
979 (unsigned int) event
->flags
);
981 /* Look for common error cases */
982 trb_comp_code
= GET_COMP_CODE(event
->transfer_len
);
983 switch (trb_comp_code
) {
984 /* Skip codes that require special handling depending on
991 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
993 case COMP_STOP_INVAL
:
994 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
997 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
998 ep
->ep_state
|= EP_HALTED
;
1002 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1006 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
1010 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
1011 status
= -EOVERFLOW
;
1014 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
1018 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
1022 /* Now update the urb's actual_length and give back to the core */
1023 /* Was this a control transfer? */
1024 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
1025 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1026 switch (trb_comp_code
) {
1028 if (event_trb
== ep_ring
->dequeue
) {
1029 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
1030 status
= -ESHUTDOWN
;
1031 } else if (event_trb
!= td
->last_trb
) {
1032 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
1033 status
= -ESHUTDOWN
;
1035 xhci_dbg(xhci
, "Successful control transfer!\n");
1040 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1041 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1042 status
= -EREMOTEIO
;
1047 /* The 0.96 spec says a babbling control endpoint
1048 * is not halted. The 0.96 spec says it is. Some HW
1049 * claims to be 0.95 compliant, but it halts the control
1050 * endpoint anyway. Check if a babble halted the
1053 if (ep_ctx
->ep_info
!= EP_STATE_HALTED
)
1055 /* else fall through */
1057 /* Did we transfer part of the data (middle) phase? */
1058 if (event_trb
!= ep_ring
->dequeue
&&
1059 event_trb
!= td
->last_trb
)
1060 td
->urb
->actual_length
=
1061 td
->urb
->transfer_buffer_length
1062 - TRB_LEN(event
->transfer_len
);
1064 td
->urb
->actual_length
= 0;
1066 ep
->stopped_td
= td
;
1067 ep
->stopped_trb
= event_trb
;
1068 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1069 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1070 xhci_ring_cmd_db(xhci
);
1073 /* Others already handled above */
1077 * Did we transfer any data, despite the errors that might have
1078 * happened? I.e. did we get past the setup stage?
1080 if (event_trb
!= ep_ring
->dequeue
) {
1081 /* The event was for the status stage */
1082 if (event_trb
== td
->last_trb
) {
1083 if (td
->urb
->actual_length
!= 0) {
1084 /* Don't overwrite a previously set error code */
1085 if ((status
== -EINPROGRESS
||
1087 (td
->urb
->transfer_flags
1088 & URB_SHORT_NOT_OK
))
1089 /* Did we already see a short data stage? */
1090 status
= -EREMOTEIO
;
1092 td
->urb
->actual_length
=
1093 td
->urb
->transfer_buffer_length
;
1096 /* Maybe the event was for the data stage? */
1097 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1098 /* We didn't stop on a link TRB in the middle */
1099 td
->urb
->actual_length
=
1100 td
->urb
->transfer_buffer_length
-
1101 TRB_LEN(event
->transfer_len
);
1102 xhci_dbg(xhci
, "Waiting for status stage event\n");
1109 switch (trb_comp_code
) {
1111 /* Double check that the HW transferred everything. */
1112 if (event_trb
!= td
->last_trb
) {
1113 xhci_warn(xhci
, "WARN Successful completion "
1115 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1116 status
= -EREMOTEIO
;
1120 if (usb_endpoint_xfer_bulk(&td
->urb
->ep
->desc
))
1121 xhci_dbg(xhci
, "Successful bulk "
1124 xhci_dbg(xhci
, "Successful interrupt "
1130 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1131 status
= -EREMOTEIO
;
1136 /* Others already handled above */
1139 dev_dbg(&td
->urb
->dev
->dev
,
1140 "ep %#x - asked for %d bytes, "
1141 "%d bytes untransferred\n",
1142 td
->urb
->ep
->desc
.bEndpointAddress
,
1143 td
->urb
->transfer_buffer_length
,
1144 TRB_LEN(event
->transfer_len
));
1145 /* Fast path - was this the last TRB in the TD for this URB? */
1146 if (event_trb
== td
->last_trb
) {
1147 if (TRB_LEN(event
->transfer_len
) != 0) {
1148 td
->urb
->actual_length
=
1149 td
->urb
->transfer_buffer_length
-
1150 TRB_LEN(event
->transfer_len
);
1151 if (td
->urb
->transfer_buffer_length
<
1152 td
->urb
->actual_length
) {
1153 xhci_warn(xhci
, "HC gave bad length "
1154 "of %d bytes left\n",
1155 TRB_LEN(event
->transfer_len
));
1156 td
->urb
->actual_length
= 0;
1157 if (td
->urb
->transfer_flags
&
1159 status
= -EREMOTEIO
;
1163 /* Don't overwrite a previously set error code */
1164 if (status
== -EINPROGRESS
) {
1165 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1166 status
= -EREMOTEIO
;
1171 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1172 /* Ignore a short packet completion if the
1173 * untransferred length was zero.
1175 if (status
== -EREMOTEIO
)
1179 /* Slow path - walk the list, starting from the dequeue
1180 * pointer, to get the actual length transferred.
1182 union xhci_trb
*cur_trb
;
1183 struct xhci_segment
*cur_seg
;
1185 td
->urb
->actual_length
= 0;
1186 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1187 cur_trb
!= event_trb
;
1188 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1189 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
1190 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
1191 td
->urb
->actual_length
+=
1192 TRB_LEN(cur_trb
->generic
.field
[2]);
1194 /* If the ring didn't stop on a Link or No-op TRB, add
1195 * in the actual bytes transferred from the Normal TRB
1197 if (trb_comp_code
!= COMP_STOP_INVAL
)
1198 td
->urb
->actual_length
+=
1199 TRB_LEN(cur_trb
->generic
.field
[2]) -
1200 TRB_LEN(event
->transfer_len
);
1203 if (trb_comp_code
== COMP_STOP_INVAL
||
1204 trb_comp_code
== COMP_STOP
) {
1205 /* The Endpoint Stop Command completion will take care of any
1206 * stopped TDs. A stopped TD may be restarted, so don't update
1207 * the ring dequeue pointer or take this TD off any lists yet.
1209 ep
->stopped_td
= td
;
1210 ep
->stopped_trb
= event_trb
;
1212 if (trb_comp_code
== COMP_STALL
||
1213 trb_comp_code
== COMP_BABBLE
) {
1214 /* The transfer is completed from the driver's
1215 * perspective, but we need to issue a set dequeue
1216 * command for this stalled endpoint to move the dequeue
1217 * pointer past the TD. We can't do that here because
1218 * the halt condition must be cleared first.
1220 ep
->stopped_td
= td
;
1221 ep
->stopped_trb
= event_trb
;
1223 /* Update ring dequeue pointer */
1224 while (ep_ring
->dequeue
!= td
->last_trb
)
1225 inc_deq(xhci
, ep_ring
, false);
1226 inc_deq(xhci
, ep_ring
, false);
1230 /* Clean up the endpoint's TD list */
1232 /* Do one last check of the actual transfer length.
1233 * If the host controller said we transferred more data than
1234 * the buffer length, urb->actual_length will be a very big
1235 * number (since it's unsigned). Play it safe and say we didn't
1236 * transfer anything.
1238 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1239 xhci_warn(xhci
, "URB transfer length is wrong, "
1240 "xHC issue? req. len = %u, "
1242 urb
->transfer_buffer_length
,
1243 urb
->actual_length
);
1244 urb
->actual_length
= 0;
1245 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1246 status
= -EREMOTEIO
;
1250 list_del(&td
->td_list
);
1251 /* Was this TD slated to be cancelled but completed anyway? */
1252 if (!list_empty(&td
->cancelled_td_list
)) {
1253 list_del(&td
->cancelled_td_list
);
1254 ep
->cancels_pending
--;
1256 /* Leave the TD around for the reset endpoint function to use
1257 * (but only if it's not a control endpoint, since we already
1258 * queued the Set TR dequeue pointer command for stalled
1259 * control endpoints).
1261 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
1262 (trb_comp_code
!= COMP_STALL
&&
1263 trb_comp_code
!= COMP_BABBLE
)) {
1269 inc_deq(xhci
, xhci
->event_ring
, true);
1270 xhci_set_hc_event_deq(xhci
);
1272 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1274 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1275 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1276 urb
, urb
->actual_length
, status
);
1277 spin_unlock(&xhci
->lock
);
1278 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1279 spin_lock(&xhci
->lock
);
1285 * This function handles all OS-owned events on the event ring. It may drop
1286 * xhci->lock between event processing (e.g. to pass up port status changes).
1288 void xhci_handle_event(struct xhci_hcd
*xhci
)
1290 union xhci_trb
*event
;
1291 int update_ptrs
= 1;
1294 xhci_dbg(xhci
, "In %s\n", __func__
);
1295 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1296 xhci
->error_bitmask
|= 1 << 1;
1300 event
= xhci
->event_ring
->dequeue
;
1301 /* Does the HC or OS own the TRB? */
1302 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1303 xhci
->event_ring
->cycle_state
) {
1304 xhci
->error_bitmask
|= 1 << 2;
1307 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1309 /* FIXME: Handle more event types. */
1310 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1311 case TRB_TYPE(TRB_COMPLETION
):
1312 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1313 handle_cmd_completion(xhci
, &event
->event_cmd
);
1314 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1316 case TRB_TYPE(TRB_PORT_STATUS
):
1317 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1318 handle_port_status(xhci
, event
);
1319 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1322 case TRB_TYPE(TRB_TRANSFER
):
1323 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1324 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1325 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1327 xhci
->error_bitmask
|= 1 << 9;
1332 xhci
->error_bitmask
|= 1 << 3;
1336 /* Update SW and HC event ring dequeue pointer */
1337 inc_deq(xhci
, xhci
->event_ring
, true);
1338 xhci_set_hc_event_deq(xhci
);
1340 /* Are there more items on the event ring? */
1341 xhci_handle_event(xhci
);
1344 /**** Endpoint Ring Operations ****/
1347 * Generic function for queueing a TRB on a ring.
1348 * The caller must have checked to make sure there's room on the ring.
1350 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1352 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1354 struct xhci_generic_trb
*trb
;
1356 trb
= &ring
->enqueue
->generic
;
1357 trb
->field
[0] = field1
;
1358 trb
->field
[1] = field2
;
1359 trb
->field
[2] = field3
;
1360 trb
->field
[3] = field4
;
1361 inc_enq(xhci
, ring
, consumer
);
1365 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1366 * FIXME allocate segments if the ring is full.
1368 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1369 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1371 /* Make sure the endpoint has been added to xHC schedule */
1372 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1374 case EP_STATE_DISABLED
:
1376 * USB core changed config/interfaces without notifying us,
1377 * or hardware is reporting the wrong state.
1379 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1381 case EP_STATE_ERROR
:
1382 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
1383 /* FIXME event handling code for error needs to clear it */
1384 /* XXX not sure if this should be -ENOENT or not */
1386 case EP_STATE_HALTED
:
1387 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
1388 case EP_STATE_STOPPED
:
1389 case EP_STATE_RUNNING
:
1392 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1394 * FIXME issue Configure Endpoint command to try to get the HC
1395 * back into a known state.
1399 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1400 /* FIXME allocate more room */
1401 xhci_err(xhci
, "ERROR no room on ep ring\n");
1407 static int prepare_transfer(struct xhci_hcd
*xhci
,
1408 struct xhci_virt_device
*xdev
,
1409 unsigned int ep_index
,
1410 unsigned int num_trbs
,
1412 struct xhci_td
**td
,
1416 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1417 ret
= prepare_ring(xhci
, xdev
->eps
[ep_index
].ring
,
1418 ep_ctx
->ep_info
& EP_STATE_MASK
,
1419 num_trbs
, mem_flags
);
1422 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1425 INIT_LIST_HEAD(&(*td
)->td_list
);
1426 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1428 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1429 if (unlikely(ret
)) {
1435 urb
->hcpriv
= (void *) (*td
);
1436 /* Add this TD to the tail of the endpoint ring's TD list */
1437 list_add_tail(&(*td
)->td_list
, &xdev
->eps
[ep_index
].ring
->td_list
);
1438 (*td
)->start_seg
= xdev
->eps
[ep_index
].ring
->enq_seg
;
1439 (*td
)->first_trb
= xdev
->eps
[ep_index
].ring
->enqueue
;
1444 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1446 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1447 struct scatterlist
*sg
;
1450 num_sgs
= urb
->num_sgs
;
1451 temp
= urb
->transfer_buffer_length
;
1453 xhci_dbg(xhci
, "count sg list trbs: \n");
1455 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1456 unsigned int previous_total_trbs
= num_trbs
;
1457 unsigned int len
= sg_dma_len(sg
);
1459 /* Scatter gather list entries may cross 64KB boundaries */
1460 running_total
= TRB_MAX_BUFF_SIZE
-
1461 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1462 if (running_total
!= 0)
1465 /* How many more 64KB chunks to transfer, how many more TRBs? */
1466 while (running_total
< sg_dma_len(sg
)) {
1468 running_total
+= TRB_MAX_BUFF_SIZE
;
1470 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1471 i
, (unsigned long long)sg_dma_address(sg
),
1472 len
, len
, num_trbs
- previous_total_trbs
);
1474 len
= min_t(int, len
, temp
);
1479 xhci_dbg(xhci
, "\n");
1480 if (!in_interrupt())
1481 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1482 urb
->ep
->desc
.bEndpointAddress
,
1483 urb
->transfer_buffer_length
,
1488 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1491 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1492 "TRBs, %d left\n", __func__
,
1493 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1494 if (running_total
!= urb
->transfer_buffer_length
)
1495 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1496 "queued %#x (%d), asked for %#x (%d)\n",
1498 urb
->ep
->desc
.bEndpointAddress
,
1499 running_total
, running_total
,
1500 urb
->transfer_buffer_length
,
1501 urb
->transfer_buffer_length
);
1504 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1505 unsigned int ep_index
, int start_cycle
,
1506 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1509 * Pass all the TRBs to the hardware at once and make sure this write
1513 start_trb
->field
[3] |= start_cycle
;
1514 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1518 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
1519 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
1520 * (comprised of sg list entries) can take several service intervals to
1523 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1524 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1526 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
1527 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
1531 xhci_interval
= EP_INTERVAL_TO_UFRAMES(ep_ctx
->ep_info
);
1532 ep_interval
= urb
->interval
;
1533 /* Convert to microframes */
1534 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1535 urb
->dev
->speed
== USB_SPEED_FULL
)
1537 /* FIXME change this to a warning and a suggestion to use the new API
1538 * to set the polling interval (once the API is added).
1540 if (xhci_interval
!= ep_interval
) {
1541 if (!printk_ratelimit())
1542 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
1543 " (%d microframe%s) than xHCI "
1544 "(%d microframe%s)\n",
1546 ep_interval
== 1 ? "" : "s",
1548 xhci_interval
== 1 ? "" : "s");
1549 urb
->interval
= xhci_interval
;
1550 /* Convert back to frames for LS/FS devices */
1551 if (urb
->dev
->speed
== USB_SPEED_LOW
||
1552 urb
->dev
->speed
== USB_SPEED_FULL
)
1555 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
1558 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1559 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1561 struct xhci_ring
*ep_ring
;
1562 unsigned int num_trbs
;
1564 struct scatterlist
*sg
;
1566 int trb_buff_len
, this_sg_len
, running_total
;
1570 struct xhci_generic_trb
*start_trb
;
1573 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1574 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1575 num_sgs
= urb
->num_sgs
;
1577 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1578 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1579 if (trb_buff_len
< 0)
1580 return trb_buff_len
;
1582 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1583 * until we've finished creating all the other TRBs. The ring's cycle
1584 * state may change as we enqueue the other TRBs, so save it too.
1586 start_trb
= &ep_ring
->enqueue
->generic
;
1587 start_cycle
= ep_ring
->cycle_state
;
1591 * How much data is in the first TRB?
1593 * There are three forces at work for TRB buffer pointers and lengths:
1594 * 1. We don't want to walk off the end of this sg-list entry buffer.
1595 * 2. The transfer length that the driver requested may be smaller than
1596 * the amount of memory allocated for this scatter-gather list.
1597 * 3. TRBs buffers can't cross 64KB boundaries.
1600 addr
= (u64
) sg_dma_address(sg
);
1601 this_sg_len
= sg_dma_len(sg
);
1602 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1603 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1604 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1605 if (trb_buff_len
> urb
->transfer_buffer_length
)
1606 trb_buff_len
= urb
->transfer_buffer_length
;
1607 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1611 /* Queue the first TRB, even if it's zero-length */
1614 u32 length_field
= 0;
1616 /* Don't change the cycle bit of the first TRB until later */
1620 field
|= ep_ring
->cycle_state
;
1622 /* Chain all the TRBs together; clear the chain bit in the last
1623 * TRB to indicate it's the last TRB in the chain.
1628 /* FIXME - add check for ZERO_PACKET flag before this */
1629 td
->last_trb
= ep_ring
->enqueue
;
1632 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1633 "64KB boundary at %#x, end dma = %#x\n",
1634 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1635 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1636 (unsigned int) addr
+ trb_buff_len
);
1637 if (TRB_MAX_BUFF_SIZE
-
1638 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1639 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1640 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1641 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1642 (unsigned int) addr
+ trb_buff_len
);
1644 length_field
= TRB_LEN(trb_buff_len
) |
1645 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1647 queue_trb(xhci
, ep_ring
, false,
1648 lower_32_bits(addr
),
1649 upper_32_bits(addr
),
1651 /* We always want to know if the TRB was short,
1652 * or we won't get an event when it completes.
1653 * (Unless we use event data TRBs, which are a
1654 * waste of space and HC resources.)
1656 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1658 running_total
+= trb_buff_len
;
1660 /* Calculate length for next transfer --
1661 * Are we done queueing all the TRBs for this sg entry?
1663 this_sg_len
-= trb_buff_len
;
1664 if (this_sg_len
== 0) {
1669 addr
= (u64
) sg_dma_address(sg
);
1670 this_sg_len
= sg_dma_len(sg
);
1672 addr
+= trb_buff_len
;
1675 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1676 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1677 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1678 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1680 urb
->transfer_buffer_length
- running_total
;
1681 } while (running_total
< urb
->transfer_buffer_length
);
1683 check_trb_math(urb
, num_trbs
, running_total
);
1684 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1688 /* This is very similar to what ehci-q.c qtd_fill() does */
1689 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1690 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1692 struct xhci_ring
*ep_ring
;
1695 struct xhci_generic_trb
*start_trb
;
1698 u32 field
, length_field
;
1700 int running_total
, trb_buff_len
, ret
;
1704 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1706 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1709 /* How much data is (potentially) left before the 64KB boundary? */
1710 running_total
= TRB_MAX_BUFF_SIZE
-
1711 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1713 /* If there's some data on this 64KB chunk, or we have to send a
1714 * zero-length transfer, we need at least one TRB
1716 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1718 /* How many more 64KB chunks to transfer, how many more TRBs? */
1719 while (running_total
< urb
->transfer_buffer_length
) {
1721 running_total
+= TRB_MAX_BUFF_SIZE
;
1723 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1725 if (!in_interrupt())
1726 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1727 urb
->ep
->desc
.bEndpointAddress
,
1728 urb
->transfer_buffer_length
,
1729 urb
->transfer_buffer_length
,
1730 (unsigned long long)urb
->transfer_dma
,
1733 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1734 num_trbs
, urb
, &td
, mem_flags
);
1739 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1740 * until we've finished creating all the other TRBs. The ring's cycle
1741 * state may change as we enqueue the other TRBs, so save it too.
1743 start_trb
= &ep_ring
->enqueue
->generic
;
1744 start_cycle
= ep_ring
->cycle_state
;
1747 /* How much data is in the first TRB? */
1748 addr
= (u64
) urb
->transfer_dma
;
1749 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1750 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1751 if (urb
->transfer_buffer_length
< trb_buff_len
)
1752 trb_buff_len
= urb
->transfer_buffer_length
;
1756 /* Queue the first TRB, even if it's zero-length */
1760 /* Don't change the cycle bit of the first TRB until later */
1764 field
|= ep_ring
->cycle_state
;
1766 /* Chain all the TRBs together; clear the chain bit in the last
1767 * TRB to indicate it's the last TRB in the chain.
1772 /* FIXME - add check for ZERO_PACKET flag before this */
1773 td
->last_trb
= ep_ring
->enqueue
;
1776 length_field
= TRB_LEN(trb_buff_len
) |
1777 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1779 queue_trb(xhci
, ep_ring
, false,
1780 lower_32_bits(addr
),
1781 upper_32_bits(addr
),
1783 /* We always want to know if the TRB was short,
1784 * or we won't get an event when it completes.
1785 * (Unless we use event data TRBs, which are a
1786 * waste of space and HC resources.)
1788 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1790 running_total
+= trb_buff_len
;
1792 /* Calculate length for next transfer */
1793 addr
+= trb_buff_len
;
1794 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
1795 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
1796 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
1797 } while (running_total
< urb
->transfer_buffer_length
);
1799 check_trb_math(urb
, num_trbs
, running_total
);
1800 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1804 /* Caller must have locked xhci->lock */
1805 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1806 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1808 struct xhci_ring
*ep_ring
;
1811 struct usb_ctrlrequest
*setup
;
1812 struct xhci_generic_trb
*start_trb
;
1814 u32 field
, length_field
;
1817 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1820 * Need to copy setup packet into setup TRB, so we can't use the setup
1823 if (!urb
->setup_packet
)
1826 if (!in_interrupt())
1827 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
1829 /* 1 TRB for setup, 1 for status */
1832 * Don't need to check if we need additional event data and normal TRBs,
1833 * since data in control transfers will never get bigger than 16MB
1834 * XXX: can we get a buffer that crosses 64KB boundaries?
1836 if (urb
->transfer_buffer_length
> 0)
1838 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
1839 urb
, &td
, mem_flags
);
1844 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1845 * until we've finished creating all the other TRBs. The ring's cycle
1846 * state may change as we enqueue the other TRBs, so save it too.
1848 start_trb
= &ep_ring
->enqueue
->generic
;
1849 start_cycle
= ep_ring
->cycle_state
;
1851 /* Queue setup TRB - see section 6.4.1.2.1 */
1852 /* FIXME better way to translate setup_packet into two u32 fields? */
1853 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
1854 queue_trb(xhci
, ep_ring
, false,
1855 /* FIXME endianness is probably going to bite my ass here. */
1856 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
1857 setup
->wIndex
| setup
->wLength
<< 16,
1858 TRB_LEN(8) | TRB_INTR_TARGET(0),
1859 /* Immediate data in pointer */
1860 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
1862 /* If there's data, queue data TRBs */
1864 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
1865 TD_REMAINDER(urb
->transfer_buffer_length
) |
1867 if (urb
->transfer_buffer_length
> 0) {
1868 if (setup
->bRequestType
& USB_DIR_IN
)
1869 field
|= TRB_DIR_IN
;
1870 queue_trb(xhci
, ep_ring
, false,
1871 lower_32_bits(urb
->transfer_dma
),
1872 upper_32_bits(urb
->transfer_dma
),
1874 /* Event on short tx */
1875 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
1878 /* Save the DMA address of the last TRB in the TD */
1879 td
->last_trb
= ep_ring
->enqueue
;
1881 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1882 /* If the device sent data, the status stage is an OUT transfer */
1883 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
1887 queue_trb(xhci
, ep_ring
, false,
1891 /* Event on completion */
1892 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
1894 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1898 /**** Command Ring Operations ****/
1900 /* Generic function for queueing a command TRB on the command ring.
1901 * Check to make sure there's room on the command ring for one command TRB.
1902 * Also check that there's room reserved for commands that must not fail.
1903 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
1904 * then only check for the number of reserved spots.
1905 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
1906 * because the command event handler may want to resubmit a failed command.
1908 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
1909 u32 field3
, u32 field4
, bool command_must_succeed
)
1911 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
1912 if (!command_must_succeed
)
1915 if (!room_on_ring(xhci
, xhci
->cmd_ring
, reserved_trbs
)) {
1916 if (!in_interrupt())
1917 xhci_err(xhci
, "ERR: No room for command on command ring\n");
1918 if (command_must_succeed
)
1919 xhci_err(xhci
, "ERR: Reserved TRB counting for "
1920 "unfailable commands failed.\n");
1923 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
1924 field4
| xhci
->cmd_ring
->cycle_state
);
1928 /* Queue a no-op command on the command ring */
1929 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
1931 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
), false);
1935 * Place a no-op command on the command ring to test the command and
1938 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
1940 if (queue_cmd_noop(xhci
) < 0)
1942 xhci
->noops_submitted
++;
1943 return xhci_ring_cmd_db
;
1946 /* Queue a slot enable or disable request on the command ring */
1947 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
1949 return queue_command(xhci
, 0, 0, 0,
1950 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
1953 /* Queue an address device command TRB */
1954 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1957 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1958 upper_32_bits(in_ctx_ptr
), 0,
1959 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
1963 /* Queue a configure endpoint command TRB */
1964 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1965 u32 slot_id
, bool command_must_succeed
)
1967 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1968 upper_32_bits(in_ctx_ptr
), 0,
1969 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
1970 command_must_succeed
);
1973 /* Queue an evaluate context command TRB */
1974 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1977 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1978 upper_32_bits(in_ctx_ptr
), 0,
1979 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
1983 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1984 unsigned int ep_index
)
1986 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1987 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1988 u32 type
= TRB_TYPE(TRB_STOP_RING
);
1990 return queue_command(xhci
, 0, 0, 0,
1991 trb_slot_id
| trb_ep_index
| type
, false);
1994 /* Set Transfer Ring Dequeue Pointer command.
1995 * This should not be used for endpoints that have streams enabled.
1997 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
1998 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
1999 union xhci_trb
*deq_ptr
, u32 cycle_state
)
2002 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2003 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2004 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
2006 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
2008 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
2009 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
2013 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
2014 upper_32_bits(addr
), 0,
2015 trb_slot_id
| trb_ep_index
| type
, false);
2018 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
2019 unsigned int ep_index
)
2021 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
2022 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
2023 u32 type
= TRB_TYPE(TRB_RESET_EP
);
2025 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,