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bnx2: Fix netpoll crash.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / bnx2.c
blob1d2db7b5d5534c45672441fa9b78bc9ddffadd1c
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004-2009 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
30 #include <asm/io.h>
31 #include <asm/irq.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
34 #include <asm/page.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
40 #define BCM_VLAN 1
41 #endif
42 #include <net/ip.h>
43 #include <net/tcp.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/firmware.h>
50 #include <linux/log2.h>
51 #include <linux/list.h>
52
53 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
54 #define BCM_CNIC 1
55 #include "cnic_if.h"
56 #endif
57 #include "bnx2.h"
58 #include "bnx2_fw.h"
59
60 #define DRV_MODULE_NAME "bnx2"
61 #define PFX DRV_MODULE_NAME ": "
62 #define DRV_MODULE_VERSION "2.0.3"
63 #define DRV_MODULE_RELDATE "Dec 03, 2009"
64 #define FW_MIPS_FILE_06 "bnx2/bnx2-mips-06-5.0.0.j3.fw"
65 #define FW_RV2P_FILE_06 "bnx2/bnx2-rv2p-06-5.0.0.j3.fw"
66 #define FW_MIPS_FILE_09 "bnx2/bnx2-mips-09-5.0.0.j3.fw"
67 #define FW_RV2P_FILE_09_Ax "bnx2/bnx2-rv2p-09ax-5.0.0.j3.fw"
68 #define FW_RV2P_FILE_09 "bnx2/bnx2-rv2p-09-5.0.0.j3.fw"
69
70 #define RUN_AT(x) (jiffies + (x))
71
72 /* Time in jiffies before concluding the transmitter is hung. */
73 #define TX_TIMEOUT (5*HZ)
74
75 static char version[] __devinitdata =
76 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
77
78 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
79 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
80 MODULE_LICENSE("GPL");
81 MODULE_VERSION(DRV_MODULE_VERSION);
82 MODULE_FIRMWARE(FW_MIPS_FILE_06);
83 MODULE_FIRMWARE(FW_RV2P_FILE_06);
84 MODULE_FIRMWARE(FW_MIPS_FILE_09);
85 MODULE_FIRMWARE(FW_RV2P_FILE_09);
86 MODULE_FIRMWARE(FW_RV2P_FILE_09_Ax);
87
88 static int disable_msi = 0;
89
90 module_param(disable_msi, int, 0);
91 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
92
93 typedef enum {
94 BCM5706 = 0,
95 NC370T,
96 NC370I,
97 BCM5706S,
98 NC370F,
99 BCM5708,
100 BCM5708S,
101 BCM5709,
102 BCM5709S,
103 BCM5716,
104 BCM5716S,
105 } board_t;
106
107 /* indexed by board_t, above */
108 static struct {
109 char *name;
110 } board_info[] __devinitdata = {
111 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
112 { "HP NC370T Multifunction Gigabit Server Adapter" },
113 { "HP NC370i Multifunction Gigabit Server Adapter" },
114 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
115 { "HP NC370F Multifunction Gigabit Server Adapter" },
116 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
117 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
118 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
119 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
120 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
121 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
122 };
123
124 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
126 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
128 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
131 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
133 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
134 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
135 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
137 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
139 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
141 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
143 { PCI_VENDOR_ID_BROADCOM, 0x163b,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
145 { PCI_VENDOR_ID_BROADCOM, 0x163c,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
147 { 0, }
148 };
149
150 static const struct flash_spec flash_table[] =
151 {
152 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
153 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
154 /* Slow EEPROM */
155 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
156 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
157 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
158 "EEPROM - slow"},
159 /* Expansion entry 0001 */
160 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
162 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
163 "Entry 0001"},
164 /* Saifun SA25F010 (non-buffered flash) */
165 /* strap, cfg1, & write1 need updates */
166 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
168 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
169 "Non-buffered flash (128kB)"},
170 /* Saifun SA25F020 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
175 "Non-buffered flash (256kB)"},
176 /* Expansion entry 0100 */
177 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
180 "Entry 0100"},
181 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
182 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
184 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
185 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
186 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
187 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
189 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
190 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
191 /* Saifun SA25F005 (non-buffered flash) */
192 /* strap, cfg1, & write1 need updates */
193 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
194 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
196 "Non-buffered flash (64kB)"},
197 /* Fast EEPROM */
198 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
199 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
200 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
201 "EEPROM - fast"},
202 /* Expansion entry 1001 */
203 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
204 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
205 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 "Entry 1001"},
207 /* Expansion entry 1010 */
208 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
209 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
210 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 "Entry 1010"},
212 /* ATMEL AT45DB011B (buffered flash) */
213 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
214 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
215 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
216 "Buffered flash (128kB)"},
217 /* Expansion entry 1100 */
218 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
219 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
220 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
221 "Entry 1100"},
222 /* Expansion entry 1101 */
223 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
224 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
225 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
226 "Entry 1101"},
227 /* Ateml Expansion entry 1110 */
228 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
229 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
230 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
231 "Entry 1110 (Atmel)"},
232 /* ATMEL AT45DB021B (buffered flash) */
233 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
234 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
235 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
236 "Buffered flash (256kB)"},
237 };
238
239 static const struct flash_spec flash_5709 = {
240 .flags = BNX2_NV_BUFFERED,
241 .page_bits = BCM5709_FLASH_PAGE_BITS,
242 .page_size = BCM5709_FLASH_PAGE_SIZE,
243 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
244 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
245 .name = "5709 Buffered flash (256kB)",
246 };
247
248 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
249
250 static void bnx2_init_napi(struct bnx2 *bp);
251
252 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
253 {
254 u32 diff;
255
256 smp_mb();
257
258 /* The ring uses 256 indices for 255 entries, one of them
259 * needs to be skipped.
260 */
261 diff = txr->tx_prod - txr->tx_cons;
262 if (unlikely(diff >= TX_DESC_CNT)) {
263 diff &= 0xffff;
264 if (diff == TX_DESC_CNT)
265 diff = MAX_TX_DESC_CNT;
266 }
267 return (bp->tx_ring_size - diff);
268 }
269
270 static u32
271 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
272 {
273 u32 val;
274
275 spin_lock_bh(&bp->indirect_lock);
276 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
277 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
278 spin_unlock_bh(&bp->indirect_lock);
279 return val;
280 }
281
282 static void
283 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
284 {
285 spin_lock_bh(&bp->indirect_lock);
286 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
287 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
288 spin_unlock_bh(&bp->indirect_lock);
289 }
290
291 static void
292 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
293 {
294 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
295 }
296
297 static u32
298 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
299 {
300 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
301 }
302
303 static void
304 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
305 {
306 offset += cid_addr;
307 spin_lock_bh(&bp->indirect_lock);
308 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
309 int i;
310
311 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
312 REG_WR(bp, BNX2_CTX_CTX_CTRL,
313 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
314 for (i = 0; i < 5; i++) {
315 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
316 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
317 break;
318 udelay(5);
319 }
320 } else {
321 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
322 REG_WR(bp, BNX2_CTX_DATA, val);
323 }
324 spin_unlock_bh(&bp->indirect_lock);
325 }
326
327 #ifdef BCM_CNIC
328 static int
329 bnx2_drv_ctl(struct net_device *dev, struct drv_ctl_info *info)
330 {
331 struct bnx2 *bp = netdev_priv(dev);
332 struct drv_ctl_io *io = &info->data.io;
333
334 switch (info->cmd) {
335 case DRV_CTL_IO_WR_CMD:
336 bnx2_reg_wr_ind(bp, io->offset, io->data);
337 break;
338 case DRV_CTL_IO_RD_CMD:
339 io->data = bnx2_reg_rd_ind(bp, io->offset);
340 break;
341 case DRV_CTL_CTX_WR_CMD:
342 bnx2_ctx_wr(bp, io->cid_addr, io->offset, io->data);
343 break;
344 default:
345 return -EINVAL;
346 }
347 return 0;
348 }
349
350 static void bnx2_setup_cnic_irq_info(struct bnx2 *bp)
351 {
352 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
353 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
354 int sb_id;
355
356 if (bp->flags & BNX2_FLAG_USING_MSIX) {
357 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
358 bnapi->cnic_present = 0;
359 sb_id = bp->irq_nvecs;
360 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
361 } else {
362 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
363 bnapi->cnic_tag = bnapi->last_status_idx;
364 bnapi->cnic_present = 1;
365 sb_id = 0;
366 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
367 }
368
369 cp->irq_arr[0].vector = bp->irq_tbl[sb_id].vector;
370 cp->irq_arr[0].status_blk = (void *)
371 ((unsigned long) bnapi->status_blk.msi +
372 (BNX2_SBLK_MSIX_ALIGN_SIZE * sb_id));
373 cp->irq_arr[0].status_blk_num = sb_id;
374 cp->num_irq = 1;
375 }
376
377 static int bnx2_register_cnic(struct net_device *dev, struct cnic_ops *ops,
378 void *data)
379 {
380 struct bnx2 *bp = netdev_priv(dev);
381 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
382
383 if (ops == NULL)
384 return -EINVAL;
385
386 if (cp->drv_state & CNIC_DRV_STATE_REGD)
387 return -EBUSY;
388
389 bp->cnic_data = data;
390 rcu_assign_pointer(bp->cnic_ops, ops);
391
392 cp->num_irq = 0;
393 cp->drv_state = CNIC_DRV_STATE_REGD;
394
395 bnx2_setup_cnic_irq_info(bp);
396
397 return 0;
398 }
399
400 static int bnx2_unregister_cnic(struct net_device *dev)
401 {
402 struct bnx2 *bp = netdev_priv(dev);
403 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
404 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
405
406 mutex_lock(&bp->cnic_lock);
407 cp->drv_state = 0;
408 bnapi->cnic_present = 0;
409 rcu_assign_pointer(bp->cnic_ops, NULL);
410 mutex_unlock(&bp->cnic_lock);
411 synchronize_rcu();
412 return 0;
413 }
414
415 struct cnic_eth_dev *bnx2_cnic_probe(struct net_device *dev)
416 {
417 struct bnx2 *bp = netdev_priv(dev);
418 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
419
420 cp->drv_owner = THIS_MODULE;
421 cp->chip_id = bp->chip_id;
422 cp->pdev = bp->pdev;
423 cp->io_base = bp->regview;
424 cp->drv_ctl = bnx2_drv_ctl;
425 cp->drv_register_cnic = bnx2_register_cnic;
426 cp->drv_unregister_cnic = bnx2_unregister_cnic;
427
428 return cp;
429 }
430 EXPORT_SYMBOL(bnx2_cnic_probe);
431
432 static void
433 bnx2_cnic_stop(struct bnx2 *bp)
434 {
435 struct cnic_ops *c_ops;
436 struct cnic_ctl_info info;
437
438 mutex_lock(&bp->cnic_lock);
439 c_ops = bp->cnic_ops;
440 if (c_ops) {
441 info.cmd = CNIC_CTL_STOP_CMD;
442 c_ops->cnic_ctl(bp->cnic_data, &info);
443 }
444 mutex_unlock(&bp->cnic_lock);
445 }
446
447 static void
448 bnx2_cnic_start(struct bnx2 *bp)
449 {
450 struct cnic_ops *c_ops;
451 struct cnic_ctl_info info;
452
453 mutex_lock(&bp->cnic_lock);
454 c_ops = bp->cnic_ops;
455 if (c_ops) {
456 if (!(bp->flags & BNX2_FLAG_USING_MSIX)) {
457 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
458
459 bnapi->cnic_tag = bnapi->last_status_idx;
460 }
461 info.cmd = CNIC_CTL_START_CMD;
462 c_ops->cnic_ctl(bp->cnic_data, &info);
463 }
464 mutex_unlock(&bp->cnic_lock);
465 }
466
467 #else
468
469 static void
470 bnx2_cnic_stop(struct bnx2 *bp)
471 {
472 }
473
474 static void
475 bnx2_cnic_start(struct bnx2 *bp)
476 {
477 }
478
479 #endif
480
481 static int
482 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
483 {
484 u32 val1;
485 int i, ret;
486
487 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
488 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
489 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
490
491 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
492 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
493
494 udelay(40);
495 }
496
497 val1 = (bp->phy_addr << 21) | (reg << 16) |
498 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
499 BNX2_EMAC_MDIO_COMM_START_BUSY;
500 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
501
502 for (i = 0; i < 50; i++) {
503 udelay(10);
504
505 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
506 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
507 udelay(5);
508
509 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
510 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
511
512 break;
513 }
514 }
515
516 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
517 *val = 0x0;
518 ret = -EBUSY;
519 }
520 else {
521 *val = val1;
522 ret = 0;
523 }
524
525 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
526 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
527 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
528
529 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
530 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
531
532 udelay(40);
533 }
534
535 return ret;
536 }
537
538 static int
539 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
540 {
541 u32 val1;
542 int i, ret;
543
544 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
545 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
546 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
547
548 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
549 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
550
551 udelay(40);
552 }
553
554 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
555 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
556 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
557 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
558
559 for (i = 0; i < 50; i++) {
560 udelay(10);
561
562 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
563 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
564 udelay(5);
565 break;
566 }
567 }
568
569 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
570 ret = -EBUSY;
571 else
572 ret = 0;
573
574 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
575 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
576 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
577
578 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
579 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
580
581 udelay(40);
582 }
583
584 return ret;
585 }
586
587 static void
588 bnx2_disable_int(struct bnx2 *bp)
589 {
590 int i;
591 struct bnx2_napi *bnapi;
592
593 for (i = 0; i < bp->irq_nvecs; i++) {
594 bnapi = &bp->bnx2_napi[i];
595 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
596 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
597 }
598 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
599 }
600
601 static void
602 bnx2_enable_int(struct bnx2 *bp)
603 {
604 int i;
605 struct bnx2_napi *bnapi;
606
607 for (i = 0; i < bp->irq_nvecs; i++) {
608 bnapi = &bp->bnx2_napi[i];
609
610 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
611 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
612 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
613 bnapi->last_status_idx);
614
615 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
616 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
617 bnapi->last_status_idx);
618 }
619 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
620 }
621
622 static void
623 bnx2_disable_int_sync(struct bnx2 *bp)
624 {
625 int i;
626
627 atomic_inc(&bp->intr_sem);
628 if (!netif_running(bp->dev))
629 return;
630
631 bnx2_disable_int(bp);
632 for (i = 0; i < bp->irq_nvecs; i++)
633 synchronize_irq(bp->irq_tbl[i].vector);
634 }
635
636 static void
637 bnx2_napi_disable(struct bnx2 *bp)
638 {
639 int i;
640
641 for (i = 0; i < bp->irq_nvecs; i++)
642 napi_disable(&bp->bnx2_napi[i].napi);
643 }
644
645 static void
646 bnx2_napi_enable(struct bnx2 *bp)
647 {
648 int i;
649
650 for (i = 0; i < bp->irq_nvecs; i++)
651 napi_enable(&bp->bnx2_napi[i].napi);
652 }
653
654 static void
655 bnx2_netif_stop(struct bnx2 *bp)
656 {
657 bnx2_cnic_stop(bp);
658 if (netif_running(bp->dev)) {
659 int i;
660
661 bnx2_napi_disable(bp);
662 netif_tx_disable(bp->dev);
663 /* prevent tx timeout */
664 for (i = 0; i < bp->dev->num_tx_queues; i++) {
665 struct netdev_queue *txq;
666
667 txq = netdev_get_tx_queue(bp->dev, i);
668 txq->trans_start = jiffies;
669 }
670 }
671 bnx2_disable_int_sync(bp);
672 }
673
674 static void
675 bnx2_netif_start(struct bnx2 *bp)
676 {
677 if (atomic_dec_and_test(&bp->intr_sem)) {
678 if (netif_running(bp->dev)) {
679 netif_tx_wake_all_queues(bp->dev);
680 bnx2_napi_enable(bp);
681 bnx2_enable_int(bp);
682 bnx2_cnic_start(bp);
683 }
684 }
685 }
686
687 static void
688 bnx2_free_tx_mem(struct bnx2 *bp)
689 {
690 int i;
691
692 for (i = 0; i < bp->num_tx_rings; i++) {
693 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
694 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
695
696 if (txr->tx_desc_ring) {
697 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
698 txr->tx_desc_ring,
699 txr->tx_desc_mapping);
700 txr->tx_desc_ring = NULL;
701 }
702 kfree(txr->tx_buf_ring);
703 txr->tx_buf_ring = NULL;
704 }
705 }
706
707 static void
708 bnx2_free_rx_mem(struct bnx2 *bp)
709 {
710 int i;
711
712 for (i = 0; i < bp->num_rx_rings; i++) {
713 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
714 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
715 int j;
716
717 for (j = 0; j < bp->rx_max_ring; j++) {
718 if (rxr->rx_desc_ring[j])
719 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
720 rxr->rx_desc_ring[j],
721 rxr->rx_desc_mapping[j]);
722 rxr->rx_desc_ring[j] = NULL;
723 }
724 vfree(rxr->rx_buf_ring);
725 rxr->rx_buf_ring = NULL;
726
727 for (j = 0; j < bp->rx_max_pg_ring; j++) {
728 if (rxr->rx_pg_desc_ring[j])
729 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
730 rxr->rx_pg_desc_ring[j],
731 rxr->rx_pg_desc_mapping[j]);
732 rxr->rx_pg_desc_ring[j] = NULL;
733 }
734 vfree(rxr->rx_pg_ring);
735 rxr->rx_pg_ring = NULL;
736 }
737 }
738
739 static int
740 bnx2_alloc_tx_mem(struct bnx2 *bp)
741 {
742 int i;
743
744 for (i = 0; i < bp->num_tx_rings; i++) {
745 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
746 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
747
748 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
749 if (txr->tx_buf_ring == NULL)
750 return -ENOMEM;
751
752 txr->tx_desc_ring =
753 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
754 &txr->tx_desc_mapping);
755 if (txr->tx_desc_ring == NULL)
756 return -ENOMEM;
757 }
758 return 0;
759 }
760
761 static int
762 bnx2_alloc_rx_mem(struct bnx2 *bp)
763 {
764 int i;
765
766 for (i = 0; i < bp->num_rx_rings; i++) {
767 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
768 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
769 int j;
770
771 rxr->rx_buf_ring =
772 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
773 if (rxr->rx_buf_ring == NULL)
774 return -ENOMEM;
775
776 memset(rxr->rx_buf_ring, 0,
777 SW_RXBD_RING_SIZE * bp->rx_max_ring);
778
779 for (j = 0; j < bp->rx_max_ring; j++) {
780 rxr->rx_desc_ring[j] =
781 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
782 &rxr->rx_desc_mapping[j]);
783 if (rxr->rx_desc_ring[j] == NULL)
784 return -ENOMEM;
785
786 }
787
788 if (bp->rx_pg_ring_size) {
789 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
790 bp->rx_max_pg_ring);
791 if (rxr->rx_pg_ring == NULL)
792 return -ENOMEM;
793
794 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
795 bp->rx_max_pg_ring);
796 }
797
798 for (j = 0; j < bp->rx_max_pg_ring; j++) {
799 rxr->rx_pg_desc_ring[j] =
800 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
801 &rxr->rx_pg_desc_mapping[j]);
802 if (rxr->rx_pg_desc_ring[j] == NULL)
803 return -ENOMEM;
804
805 }
806 }
807 return 0;
808 }
809
810 static void
811 bnx2_free_mem(struct bnx2 *bp)
812 {
813 int i;
814 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
815
816 bnx2_free_tx_mem(bp);
817 bnx2_free_rx_mem(bp);
818
819 for (i = 0; i < bp->ctx_pages; i++) {
820 if (bp->ctx_blk[i]) {
821 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
822 bp->ctx_blk[i],
823 bp->ctx_blk_mapping[i]);
824 bp->ctx_blk[i] = NULL;
825 }
826 }
827 if (bnapi->status_blk.msi) {
828 pci_free_consistent(bp->pdev, bp->status_stats_size,
829 bnapi->status_blk.msi,
830 bp->status_blk_mapping);
831 bnapi->status_blk.msi = NULL;
832 bp->stats_blk = NULL;
833 }
834 }
835
836 static int
837 bnx2_alloc_mem(struct bnx2 *bp)
838 {
839 int i, status_blk_size, err;
840 struct bnx2_napi *bnapi;
841 void *status_blk;
842
843 /* Combine status and statistics blocks into one allocation. */
844 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
845 if (bp->flags & BNX2_FLAG_MSIX_CAP)
846 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
847 BNX2_SBLK_MSIX_ALIGN_SIZE);
848 bp->status_stats_size = status_blk_size +
849 sizeof(struct statistics_block);
850
851 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
852 &bp->status_blk_mapping);
853 if (status_blk == NULL)
854 goto alloc_mem_err;
855
856 memset(status_blk, 0, bp->status_stats_size);
857
858 bnapi = &bp->bnx2_napi[0];
859 bnapi->status_blk.msi = status_blk;
860 bnapi->hw_tx_cons_ptr =
861 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
862 bnapi->hw_rx_cons_ptr =
863 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
864 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
865 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
866 struct status_block_msix *sblk;
867
868 bnapi = &bp->bnx2_napi[i];
869
870 sblk = (void *) (status_blk +
871 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
872 bnapi->status_blk.msix = sblk;
873 bnapi->hw_tx_cons_ptr =
874 &sblk->status_tx_quick_consumer_index;
875 bnapi->hw_rx_cons_ptr =
876 &sblk->status_rx_quick_consumer_index;
877 bnapi->int_num = i << 24;
878 }
879 }
880
881 bp->stats_blk = status_blk + status_blk_size;
882
883 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
884
885 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
886 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
887 if (bp->ctx_pages == 0)
888 bp->ctx_pages = 1;
889 for (i = 0; i < bp->ctx_pages; i++) {
890 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
891 BCM_PAGE_SIZE,
892 &bp->ctx_blk_mapping[i]);
893 if (bp->ctx_blk[i] == NULL)
894 goto alloc_mem_err;
895 }
896 }
897
898 err = bnx2_alloc_rx_mem(bp);
899 if (err)
900 goto alloc_mem_err;
901
902 err = bnx2_alloc_tx_mem(bp);
903 if (err)
904 goto alloc_mem_err;
905
906 return 0;
907
908 alloc_mem_err:
909 bnx2_free_mem(bp);
910 return -ENOMEM;
911 }
912
913 static void
914 bnx2_report_fw_link(struct bnx2 *bp)
915 {
916 u32 fw_link_status = 0;
917
918 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
919 return;
920
921 if (bp->link_up) {
922 u32 bmsr;
923
924 switch (bp->line_speed) {
925 case SPEED_10:
926 if (bp->duplex == DUPLEX_HALF)
927 fw_link_status = BNX2_LINK_STATUS_10HALF;
928 else
929 fw_link_status = BNX2_LINK_STATUS_10FULL;
930 break;
931 case SPEED_100:
932 if (bp->duplex == DUPLEX_HALF)
933 fw_link_status = BNX2_LINK_STATUS_100HALF;
934 else
935 fw_link_status = BNX2_LINK_STATUS_100FULL;
936 break;
937 case SPEED_1000:
938 if (bp->duplex == DUPLEX_HALF)
939 fw_link_status = BNX2_LINK_STATUS_1000HALF;
940 else
941 fw_link_status = BNX2_LINK_STATUS_1000FULL;
942 break;
943 case SPEED_2500:
944 if (bp->duplex == DUPLEX_HALF)
945 fw_link_status = BNX2_LINK_STATUS_2500HALF;
946 else
947 fw_link_status = BNX2_LINK_STATUS_2500FULL;
948 break;
949 }
950
951 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
952
953 if (bp->autoneg) {
954 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
955
956 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
957 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
958
959 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
960 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
961 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
962 else
963 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
964 }
965 }
966 else
967 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
968
969 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
970 }
971
972 static char *
973 bnx2_xceiver_str(struct bnx2 *bp)
974 {
975 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
976 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
977 "Copper"));
978 }
979
980 static void
981 bnx2_report_link(struct bnx2 *bp)
982 {
983 if (bp->link_up) {
984 netif_carrier_on(bp->dev);
985 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
986 bnx2_xceiver_str(bp));
987
988 printk("%d Mbps ", bp->line_speed);
989
990 if (bp->duplex == DUPLEX_FULL)
991 printk("full duplex");
992 else
993 printk("half duplex");
994
995 if (bp->flow_ctrl) {
996 if (bp->flow_ctrl & FLOW_CTRL_RX) {
997 printk(", receive ");
998 if (bp->flow_ctrl & FLOW_CTRL_TX)
999 printk("& transmit ");
1000 }
1001 else {
1002 printk(", transmit ");
1003 }
1004 printk("flow control ON");
1005 }
1006 printk("\n");
1007 }
1008 else {
1009 netif_carrier_off(bp->dev);
1010 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
1011 bnx2_xceiver_str(bp));
1012 }
1013
1014 bnx2_report_fw_link(bp);
1015 }
1016
1017 static void
1018 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
1019 {
1020 u32 local_adv, remote_adv;
1021
1022 bp->flow_ctrl = 0;
1023 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1024 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1025
1026 if (bp->duplex == DUPLEX_FULL) {
1027 bp->flow_ctrl = bp->req_flow_ctrl;
1028 }
1029 return;
1030 }
1031
1032 if (bp->duplex != DUPLEX_FULL) {
1033 return;
1034 }
1035
1036 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1037 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
1038 u32 val;
1039
1040 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1041 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
1042 bp->flow_ctrl |= FLOW_CTRL_TX;
1043 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
1044 bp->flow_ctrl |= FLOW_CTRL_RX;
1045 return;
1046 }
1047
1048 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1049 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1050
1051 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1052 u32 new_local_adv = 0;
1053 u32 new_remote_adv = 0;
1054
1055 if (local_adv & ADVERTISE_1000XPAUSE)
1056 new_local_adv |= ADVERTISE_PAUSE_CAP;
1057 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1058 new_local_adv |= ADVERTISE_PAUSE_ASYM;
1059 if (remote_adv & ADVERTISE_1000XPAUSE)
1060 new_remote_adv |= ADVERTISE_PAUSE_CAP;
1061 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
1062 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
1063
1064 local_adv = new_local_adv;
1065 remote_adv = new_remote_adv;
1066 }
1067
1068 /* See Table 28B-3 of 802.3ab-1999 spec. */
1069 if (local_adv & ADVERTISE_PAUSE_CAP) {
1070 if(local_adv & ADVERTISE_PAUSE_ASYM) {
1071 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1072 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1073 }
1074 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
1075 bp->flow_ctrl = FLOW_CTRL_RX;
1076 }
1077 }
1078 else {
1079 if (remote_adv & ADVERTISE_PAUSE_CAP) {
1080 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
1081 }
1082 }
1083 }
1084 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1085 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
1086 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
1087
1088 bp->flow_ctrl = FLOW_CTRL_TX;
1089 }
1090 }
1091 }
1092
1093 static int
1094 bnx2_5709s_linkup(struct bnx2 *bp)
1095 {
1096 u32 val, speed;
1097
1098 bp->link_up = 1;
1099
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
1101 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
1102 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1103
1104 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
1105 bp->line_speed = bp->req_line_speed;
1106 bp->duplex = bp->req_duplex;
1107 return 0;
1108 }
1109 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
1110 switch (speed) {
1111 case MII_BNX2_GP_TOP_AN_SPEED_10:
1112 bp->line_speed = SPEED_10;
1113 break;
1114 case MII_BNX2_GP_TOP_AN_SPEED_100:
1115 bp->line_speed = SPEED_100;
1116 break;
1117 case MII_BNX2_GP_TOP_AN_SPEED_1G:
1118 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
1119 bp->line_speed = SPEED_1000;
1120 break;
1121 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
1122 bp->line_speed = SPEED_2500;
1123 break;
1124 }
1125 if (val & MII_BNX2_GP_TOP_AN_FD)
1126 bp->duplex = DUPLEX_FULL;
1127 else
1128 bp->duplex = DUPLEX_HALF;
1129 return 0;
1130 }
1131
1132 static int
1133 bnx2_5708s_linkup(struct bnx2 *bp)
1134 {
1135 u32 val;
1136
1137 bp->link_up = 1;
1138 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
1139 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
1140 case BCM5708S_1000X_STAT1_SPEED_10:
1141 bp->line_speed = SPEED_10;
1142 break;
1143 case BCM5708S_1000X_STAT1_SPEED_100:
1144 bp->line_speed = SPEED_100;
1145 break;
1146 case BCM5708S_1000X_STAT1_SPEED_1G:
1147 bp->line_speed = SPEED_1000;
1148 break;
1149 case BCM5708S_1000X_STAT1_SPEED_2G5:
1150 bp->line_speed = SPEED_2500;
1151 break;
1152 }
1153 if (val & BCM5708S_1000X_STAT1_FD)
1154 bp->duplex = DUPLEX_FULL;
1155 else
1156 bp->duplex = DUPLEX_HALF;
1157
1158 return 0;
1159 }
1160
1161 static int
1162 bnx2_5706s_linkup(struct bnx2 *bp)
1163 {
1164 u32 bmcr, local_adv, remote_adv, common;
1165
1166 bp->link_up = 1;
1167 bp->line_speed = SPEED_1000;
1168
1169 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1170 if (bmcr & BMCR_FULLDPLX) {
1171 bp->duplex = DUPLEX_FULL;
1172 }
1173 else {
1174 bp->duplex = DUPLEX_HALF;
1175 }
1176
1177 if (!(bmcr & BMCR_ANENABLE)) {
1178 return 0;
1179 }
1180
1181 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1182 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1183
1184 common = local_adv & remote_adv;
1185 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1186
1187 if (common & ADVERTISE_1000XFULL) {
1188 bp->duplex = DUPLEX_FULL;
1189 }
1190 else {
1191 bp->duplex = DUPLEX_HALF;
1192 }
1193 }
1194
1195 return 0;
1196 }
1197
1198 static int
1199 bnx2_copper_linkup(struct bnx2 *bp)
1200 {
1201 u32 bmcr;
1202
1203 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1204 if (bmcr & BMCR_ANENABLE) {
1205 u32 local_adv, remote_adv, common;
1206
1207 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1208 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1209
1210 common = local_adv & (remote_adv >> 2);
1211 if (common & ADVERTISE_1000FULL) {
1212 bp->line_speed = SPEED_1000;
1213 bp->duplex = DUPLEX_FULL;
1214 }
1215 else if (common & ADVERTISE_1000HALF) {
1216 bp->line_speed = SPEED_1000;
1217 bp->duplex = DUPLEX_HALF;
1218 }
1219 else {
1220 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1221 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1222
1223 common = local_adv & remote_adv;
1224 if (common & ADVERTISE_100FULL) {
1225 bp->line_speed = SPEED_100;
1226 bp->duplex = DUPLEX_FULL;
1227 }
1228 else if (common & ADVERTISE_100HALF) {
1229 bp->line_speed = SPEED_100;
1230 bp->duplex = DUPLEX_HALF;
1231 }
1232 else if (common & ADVERTISE_10FULL) {
1233 bp->line_speed = SPEED_10;
1234 bp->duplex = DUPLEX_FULL;
1235 }
1236 else if (common & ADVERTISE_10HALF) {
1237 bp->line_speed = SPEED_10;
1238 bp->duplex = DUPLEX_HALF;
1239 }
1240 else {
1241 bp->line_speed = 0;
1242 bp->link_up = 0;
1243 }
1244 }
1245 }
1246 else {
1247 if (bmcr & BMCR_SPEED100) {
1248 bp->line_speed = SPEED_100;
1249 }
1250 else {
1251 bp->line_speed = SPEED_10;
1252 }
1253 if (bmcr & BMCR_FULLDPLX) {
1254 bp->duplex = DUPLEX_FULL;
1255 }
1256 else {
1257 bp->duplex = DUPLEX_HALF;
1258 }
1259 }
1260
1261 return 0;
1262 }
1263
1264 static void
1265 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1266 {
1267 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1268
1269 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1270 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1271 val |= 0x02 << 8;
1272
1273 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1274 u32 lo_water, hi_water;
1275
1276 if (bp->flow_ctrl & FLOW_CTRL_TX)
1277 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1278 else
1279 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1280 if (lo_water >= bp->rx_ring_size)
1281 lo_water = 0;
1282
1283 hi_water = bp->rx_ring_size / 4;
1284
1285 if (hi_water <= lo_water)
1286 lo_water = 0;
1287
1288 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1289 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1290
1291 if (hi_water > 0xf)
1292 hi_water = 0xf;
1293 else if (hi_water == 0)
1294 lo_water = 0;
1295 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1296 }
1297 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1298 }
1299
1300 static void
1301 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1302 {
1303 int i;
1304 u32 cid;
1305
1306 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1307 if (i == 1)
1308 cid = RX_RSS_CID;
1309 bnx2_init_rx_context(bp, cid);
1310 }
1311 }
1312
1313 static void
1314 bnx2_set_mac_link(struct bnx2 *bp)
1315 {
1316 u32 val;
1317
1318 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1319 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1320 (bp->duplex == DUPLEX_HALF)) {
1321 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1322 }
1323
1324 /* Configure the EMAC mode register. */
1325 val = REG_RD(bp, BNX2_EMAC_MODE);
1326
1327 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1328 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1329 BNX2_EMAC_MODE_25G_MODE);
1330
1331 if (bp->link_up) {
1332 switch (bp->line_speed) {
1333 case SPEED_10:
1334 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1335 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1336 break;
1337 }
1338 /* fall through */
1339 case SPEED_100:
1340 val |= BNX2_EMAC_MODE_PORT_MII;
1341 break;
1342 case SPEED_2500:
1343 val |= BNX2_EMAC_MODE_25G_MODE;
1344 /* fall through */
1345 case SPEED_1000:
1346 val |= BNX2_EMAC_MODE_PORT_GMII;
1347 break;
1348 }
1349 }
1350 else {
1351 val |= BNX2_EMAC_MODE_PORT_GMII;
1352 }
1353
1354 /* Set the MAC to operate in the appropriate duplex mode. */
1355 if (bp->duplex == DUPLEX_HALF)
1356 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1357 REG_WR(bp, BNX2_EMAC_MODE, val);
1358
1359 /* Enable/disable rx PAUSE. */
1360 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1361
1362 if (bp->flow_ctrl & FLOW_CTRL_RX)
1363 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1364 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1365
1366 /* Enable/disable tx PAUSE. */
1367 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1368 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1369
1370 if (bp->flow_ctrl & FLOW_CTRL_TX)
1371 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1372 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1373
1374 /* Acknowledge the interrupt. */
1375 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1376
1377 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1378 bnx2_init_all_rx_contexts(bp);
1379 }
1380
1381 static void
1382 bnx2_enable_bmsr1(struct bnx2 *bp)
1383 {
1384 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1385 (CHIP_NUM(bp) == CHIP_NUM_5709))
1386 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1387 MII_BNX2_BLK_ADDR_GP_STATUS);
1388 }
1389
1390 static void
1391 bnx2_disable_bmsr1(struct bnx2 *bp)
1392 {
1393 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1394 (CHIP_NUM(bp) == CHIP_NUM_5709))
1395 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1396 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1397 }
1398
1399 static int
1400 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1401 {
1402 u32 up1;
1403 int ret = 1;
1404
1405 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1406 return 0;
1407
1408 if (bp->autoneg & AUTONEG_SPEED)
1409 bp->advertising |= ADVERTISED_2500baseX_Full;
1410
1411 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1412 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1413
1414 bnx2_read_phy(bp, bp->mii_up1, &up1);
1415 if (!(up1 & BCM5708S_UP1_2G5)) {
1416 up1 |= BCM5708S_UP1_2G5;
1417 bnx2_write_phy(bp, bp->mii_up1, up1);
1418 ret = 0;
1419 }
1420
1421 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1422 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1423 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1424
1425 return ret;
1426 }
1427
1428 static int
1429 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1430 {
1431 u32 up1;
1432 int ret = 0;
1433
1434 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1435 return 0;
1436
1437 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1438 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1439
1440 bnx2_read_phy(bp, bp->mii_up1, &up1);
1441 if (up1 & BCM5708S_UP1_2G5) {
1442 up1 &= ~BCM5708S_UP1_2G5;
1443 bnx2_write_phy(bp, bp->mii_up1, up1);
1444 ret = 1;
1445 }
1446
1447 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1448 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1449 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1450
1451 return ret;
1452 }
1453
1454 static void
1455 bnx2_enable_forced_2g5(struct bnx2 *bp)
1456 {
1457 u32 bmcr;
1458
1459 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1460 return;
1461
1462 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1463 u32 val;
1464
1465 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1466 MII_BNX2_BLK_ADDR_SERDES_DIG);
1467 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1468 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1469 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1470 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1471
1472 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1473 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1474 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1475
1476 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1477 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1478 bmcr |= BCM5708S_BMCR_FORCE_2500;
1479 } else {
1480 return;
1481 }
1482
1483 if (bp->autoneg & AUTONEG_SPEED) {
1484 bmcr &= ~BMCR_ANENABLE;
1485 if (bp->req_duplex == DUPLEX_FULL)
1486 bmcr |= BMCR_FULLDPLX;
1487 }
1488 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1489 }
1490
1491 static void
1492 bnx2_disable_forced_2g5(struct bnx2 *bp)
1493 {
1494 u32 bmcr;
1495
1496 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1497 return;
1498
1499 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1500 u32 val;
1501
1502 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1503 MII_BNX2_BLK_ADDR_SERDES_DIG);
1504 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1505 val &= ~MII_BNX2_SD_MISC1_FORCE;
1506 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1507
1508 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1509 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1510 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1511
1512 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1513 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1514 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1515 } else {
1516 return;
1517 }
1518
1519 if (bp->autoneg & AUTONEG_SPEED)
1520 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1521 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1522 }
1523
1524 static void
1525 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1526 {
1527 u32 val;
1528
1529 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1530 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1531 if (start)
1532 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1533 else
1534 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1535 }
1536
1537 static int
1538 bnx2_set_link(struct bnx2 *bp)
1539 {
1540 u32 bmsr;
1541 u8 link_up;
1542
1543 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1544 bp->link_up = 1;
1545 return 0;
1546 }
1547
1548 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1549 return 0;
1550
1551 link_up = bp->link_up;
1552
1553 bnx2_enable_bmsr1(bp);
1554 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1555 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1556 bnx2_disable_bmsr1(bp);
1557
1558 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1559 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1560 u32 val, an_dbg;
1561
1562 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1563 bnx2_5706s_force_link_dn(bp, 0);
1564 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1565 }
1566 val = REG_RD(bp, BNX2_EMAC_STATUS);
1567
1568 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1569 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1570 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1571
1572 if ((val & BNX2_EMAC_STATUS_LINK) &&
1573 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1574 bmsr |= BMSR_LSTATUS;
1575 else
1576 bmsr &= ~BMSR_LSTATUS;
1577 }
1578
1579 if (bmsr & BMSR_LSTATUS) {
1580 bp->link_up = 1;
1581
1582 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1583 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1584 bnx2_5706s_linkup(bp);
1585 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1586 bnx2_5708s_linkup(bp);
1587 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1588 bnx2_5709s_linkup(bp);
1589 }
1590 else {
1591 bnx2_copper_linkup(bp);
1592 }
1593 bnx2_resolve_flow_ctrl(bp);
1594 }
1595 else {
1596 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1597 (bp->autoneg & AUTONEG_SPEED))
1598 bnx2_disable_forced_2g5(bp);
1599
1600 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1601 u32 bmcr;
1602
1603 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1604 bmcr |= BMCR_ANENABLE;
1605 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1606
1607 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1608 }
1609 bp->link_up = 0;
1610 }
1611
1612 if (bp->link_up != link_up) {
1613 bnx2_report_link(bp);
1614 }
1615
1616 bnx2_set_mac_link(bp);
1617
1618 return 0;
1619 }
1620
1621 static int
1622 bnx2_reset_phy(struct bnx2 *bp)
1623 {
1624 int i;
1625 u32 reg;
1626
1627 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1628
1629 #define PHY_RESET_MAX_WAIT 100
1630 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1631 udelay(10);
1632
1633 bnx2_read_phy(bp, bp->mii_bmcr, &reg);
1634 if (!(reg & BMCR_RESET)) {
1635 udelay(20);
1636 break;
1637 }
1638 }
1639 if (i == PHY_RESET_MAX_WAIT) {
1640 return -EBUSY;
1641 }
1642 return 0;
1643 }
1644
1645 static u32
1646 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1647 {
1648 u32 adv = 0;
1649
1650 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1651 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1652
1653 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1654 adv = ADVERTISE_1000XPAUSE;
1655 }
1656 else {
1657 adv = ADVERTISE_PAUSE_CAP;
1658 }
1659 }
1660 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1661 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1662 adv = ADVERTISE_1000XPSE_ASYM;
1663 }
1664 else {
1665 adv = ADVERTISE_PAUSE_ASYM;
1666 }
1667 }
1668 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1669 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1670 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1671 }
1672 else {
1673 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1674 }
1675 }
1676 return adv;
1677 }
1678
1679 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1680
1681 static int
1682 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1683 __releases(&bp->phy_lock)
1684 __acquires(&bp->phy_lock)
1685 {
1686 u32 speed_arg = 0, pause_adv;
1687
1688 pause_adv = bnx2_phy_get_pause_adv(bp);
1689
1690 if (bp->autoneg & AUTONEG_SPEED) {
1691 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1692 if (bp->advertising & ADVERTISED_10baseT_Half)
1693 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1694 if (bp->advertising & ADVERTISED_10baseT_Full)
1695 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1696 if (bp->advertising & ADVERTISED_100baseT_Half)
1697 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1698 if (bp->advertising & ADVERTISED_100baseT_Full)
1699 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1700 if (bp->advertising & ADVERTISED_1000baseT_Full)
1701 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1702 if (bp->advertising & ADVERTISED_2500baseX_Full)
1703 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1704 } else {
1705 if (bp->req_line_speed == SPEED_2500)
1706 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1707 else if (bp->req_line_speed == SPEED_1000)
1708 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1709 else if (bp->req_line_speed == SPEED_100) {
1710 if (bp->req_duplex == DUPLEX_FULL)
1711 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1712 else
1713 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1714 } else if (bp->req_line_speed == SPEED_10) {
1715 if (bp->req_duplex == DUPLEX_FULL)
1716 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1717 else
1718 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1719 }
1720 }
1721
1722 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1723 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1724 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1725 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1726
1727 if (port == PORT_TP)
1728 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1729 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1730
1731 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1732
1733 spin_unlock_bh(&bp->phy_lock);
1734 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1735 spin_lock_bh(&bp->phy_lock);
1736
1737 return 0;
1738 }
1739
1740 static int
1741 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1742 __releases(&bp->phy_lock)
1743 __acquires(&bp->phy_lock)
1744 {
1745 u32 adv, bmcr;
1746 u32 new_adv = 0;
1747
1748 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1749 return (bnx2_setup_remote_phy(bp, port));
1750
1751 if (!(bp->autoneg & AUTONEG_SPEED)) {
1752 u32 new_bmcr;
1753 int force_link_down = 0;
1754
1755 if (bp->req_line_speed == SPEED_2500) {
1756 if (!bnx2_test_and_enable_2g5(bp))
1757 force_link_down = 1;
1758 } else if (bp->req_line_speed == SPEED_1000) {
1759 if (bnx2_test_and_disable_2g5(bp))
1760 force_link_down = 1;
1761 }
1762 bnx2_read_phy(bp, bp->mii_adv, &adv);
1763 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1764
1765 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1766 new_bmcr = bmcr & ~BMCR_ANENABLE;
1767 new_bmcr |= BMCR_SPEED1000;
1768
1769 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1770 if (bp->req_line_speed == SPEED_2500)
1771 bnx2_enable_forced_2g5(bp);
1772 else if (bp->req_line_speed == SPEED_1000) {
1773 bnx2_disable_forced_2g5(bp);
1774 new_bmcr &= ~0x2000;
1775 }
1776
1777 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1778 if (bp->req_line_speed == SPEED_2500)
1779 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1780 else
1781 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1782 }
1783
1784 if (bp->req_duplex == DUPLEX_FULL) {
1785 adv |= ADVERTISE_1000XFULL;
1786 new_bmcr |= BMCR_FULLDPLX;
1787 }
1788 else {
1789 adv |= ADVERTISE_1000XHALF;
1790 new_bmcr &= ~BMCR_FULLDPLX;
1791 }
1792 if ((new_bmcr != bmcr) || (force_link_down)) {
1793 /* Force a link down visible on the other side */
1794 if (bp->link_up) {
1795 bnx2_write_phy(bp, bp->mii_adv, adv &
1796 ~(ADVERTISE_1000XFULL |
1797 ADVERTISE_1000XHALF));
1798 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1799 BMCR_ANRESTART | BMCR_ANENABLE);
1800
1801 bp->link_up = 0;
1802 netif_carrier_off(bp->dev);
1803 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1804 bnx2_report_link(bp);
1805 }
1806 bnx2_write_phy(bp, bp->mii_adv, adv);
1807 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1808 } else {
1809 bnx2_resolve_flow_ctrl(bp);
1810 bnx2_set_mac_link(bp);
1811 }
1812 return 0;
1813 }
1814
1815 bnx2_test_and_enable_2g5(bp);
1816
1817 if (bp->advertising & ADVERTISED_1000baseT_Full)
1818 new_adv |= ADVERTISE_1000XFULL;
1819
1820 new_adv |= bnx2_phy_get_pause_adv(bp);
1821
1822 bnx2_read_phy(bp, bp->mii_adv, &adv);
1823 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1824
1825 bp->serdes_an_pending = 0;
1826 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1827 /* Force a link down visible on the other side */
1828 if (bp->link_up) {
1829 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1830 spin_unlock_bh(&bp->phy_lock);
1831 msleep(20);
1832 spin_lock_bh(&bp->phy_lock);
1833 }
1834
1835 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1836 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1837 BMCR_ANENABLE);
1838 /* Speed up link-up time when the link partner
1839 * does not autonegotiate which is very common
1840 * in blade servers. Some blade servers use
1841 * IPMI for kerboard input and it's important
1842 * to minimize link disruptions. Autoneg. involves
1843 * exchanging base pages plus 3 next pages and
1844 * normally completes in about 120 msec.
1845 */
1846 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1847 bp->serdes_an_pending = 1;
1848 mod_timer(&bp->timer, jiffies + bp->current_interval);
1849 } else {
1850 bnx2_resolve_flow_ctrl(bp);
1851 bnx2_set_mac_link(bp);
1852 }
1853
1854 return 0;
1855 }
1856
1857 #define ETHTOOL_ALL_FIBRE_SPEED \
1858 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1859 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1860 (ADVERTISED_1000baseT_Full)
1861
1862 #define ETHTOOL_ALL_COPPER_SPEED \
1863 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1864 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1865 ADVERTISED_1000baseT_Full)
1866
1867 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1868 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1869
1870 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1871
1872 static void
1873 bnx2_set_default_remote_link(struct bnx2 *bp)
1874 {
1875 u32 link;
1876
1877 if (bp->phy_port == PORT_TP)
1878 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1879 else
1880 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1881
1882 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1883 bp->req_line_speed = 0;
1884 bp->autoneg |= AUTONEG_SPEED;
1885 bp->advertising = ADVERTISED_Autoneg;
1886 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1887 bp->advertising |= ADVERTISED_10baseT_Half;
1888 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1889 bp->advertising |= ADVERTISED_10baseT_Full;
1890 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1891 bp->advertising |= ADVERTISED_100baseT_Half;
1892 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1893 bp->advertising |= ADVERTISED_100baseT_Full;
1894 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1895 bp->advertising |= ADVERTISED_1000baseT_Full;
1896 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1897 bp->advertising |= ADVERTISED_2500baseX_Full;
1898 } else {
1899 bp->autoneg = 0;
1900 bp->advertising = 0;
1901 bp->req_duplex = DUPLEX_FULL;
1902 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1903 bp->req_line_speed = SPEED_10;
1904 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1905 bp->req_duplex = DUPLEX_HALF;
1906 }
1907 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1908 bp->req_line_speed = SPEED_100;
1909 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1910 bp->req_duplex = DUPLEX_HALF;
1911 }
1912 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1913 bp->req_line_speed = SPEED_1000;
1914 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1915 bp->req_line_speed = SPEED_2500;
1916 }
1917 }
1918
1919 static void
1920 bnx2_set_default_link(struct bnx2 *bp)
1921 {
1922 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1923 bnx2_set_default_remote_link(bp);
1924 return;
1925 }
1926
1927 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1928 bp->req_line_speed = 0;
1929 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1930 u32 reg;
1931
1932 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1933
1934 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1935 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1936 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1937 bp->autoneg = 0;
1938 bp->req_line_speed = bp->line_speed = SPEED_1000;
1939 bp->req_duplex = DUPLEX_FULL;
1940 }
1941 } else
1942 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1943 }
1944
1945 static void
1946 bnx2_send_heart_beat(struct bnx2 *bp)
1947 {
1948 u32 msg;
1949 u32 addr;
1950
1951 spin_lock(&bp->indirect_lock);
1952 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1953 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1954 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1955 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1956 spin_unlock(&bp->indirect_lock);
1957 }
1958
1959 static void
1960 bnx2_remote_phy_event(struct bnx2 *bp)
1961 {
1962 u32 msg;
1963 u8 link_up = bp->link_up;
1964 u8 old_port;
1965
1966 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1967
1968 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1969 bnx2_send_heart_beat(bp);
1970
1971 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1972
1973 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1974 bp->link_up = 0;
1975 else {
1976 u32 speed;
1977
1978 bp->link_up = 1;
1979 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1980 bp->duplex = DUPLEX_FULL;
1981 switch (speed) {
1982 case BNX2_LINK_STATUS_10HALF:
1983 bp->duplex = DUPLEX_HALF;
1984 case BNX2_LINK_STATUS_10FULL:
1985 bp->line_speed = SPEED_10;
1986 break;
1987 case BNX2_LINK_STATUS_100HALF:
1988 bp->duplex = DUPLEX_HALF;
1989 case BNX2_LINK_STATUS_100BASE_T4:
1990 case BNX2_LINK_STATUS_100FULL:
1991 bp->line_speed = SPEED_100;
1992 break;
1993 case BNX2_LINK_STATUS_1000HALF:
1994 bp->duplex = DUPLEX_HALF;
1995 case BNX2_LINK_STATUS_1000FULL:
1996 bp->line_speed = SPEED_1000;
1997 break;
1998 case BNX2_LINK_STATUS_2500HALF:
1999 bp->duplex = DUPLEX_HALF;
2000 case BNX2_LINK_STATUS_2500FULL:
2001 bp->line_speed = SPEED_2500;
2002 break;
2003 default:
2004 bp->line_speed = 0;
2005 break;
2006 }
2007
2008 bp->flow_ctrl = 0;
2009 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
2010 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
2011 if (bp->duplex == DUPLEX_FULL)
2012 bp->flow_ctrl = bp->req_flow_ctrl;
2013 } else {
2014 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
2015 bp->flow_ctrl |= FLOW_CTRL_TX;
2016 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
2017 bp->flow_ctrl |= FLOW_CTRL_RX;
2018 }
2019
2020 old_port = bp->phy_port;
2021 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
2022 bp->phy_port = PORT_FIBRE;
2023 else
2024 bp->phy_port = PORT_TP;
2025
2026 if (old_port != bp->phy_port)
2027 bnx2_set_default_link(bp);
2028
2029 }
2030 if (bp->link_up != link_up)
2031 bnx2_report_link(bp);
2032
2033 bnx2_set_mac_link(bp);
2034 }
2035
2036 static int
2037 bnx2_set_remote_link(struct bnx2 *bp)
2038 {
2039 u32 evt_code;
2040
2041 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
2042 switch (evt_code) {
2043 case BNX2_FW_EVT_CODE_LINK_EVENT:
2044 bnx2_remote_phy_event(bp);
2045 break;
2046 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
2047 default:
2048 bnx2_send_heart_beat(bp);
2049 break;
2050 }
2051 return 0;
2052 }
2053
2054 static int
2055 bnx2_setup_copper_phy(struct bnx2 *bp)
2056 __releases(&bp->phy_lock)
2057 __acquires(&bp->phy_lock)
2058 {
2059 u32 bmcr;
2060 u32 new_bmcr;
2061
2062 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
2063
2064 if (bp->autoneg & AUTONEG_SPEED) {
2065 u32 adv_reg, adv1000_reg;
2066 u32 new_adv_reg = 0;
2067 u32 new_adv1000_reg = 0;
2068
2069 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
2070 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
2071 ADVERTISE_PAUSE_ASYM);
2072
2073 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
2074 adv1000_reg &= PHY_ALL_1000_SPEED;
2075
2076 if (bp->advertising & ADVERTISED_10baseT_Half)
2077 new_adv_reg |= ADVERTISE_10HALF;
2078 if (bp->advertising & ADVERTISED_10baseT_Full)
2079 new_adv_reg |= ADVERTISE_10FULL;
2080 if (bp->advertising & ADVERTISED_100baseT_Half)
2081 new_adv_reg |= ADVERTISE_100HALF;
2082 if (bp->advertising & ADVERTISED_100baseT_Full)
2083 new_adv_reg |= ADVERTISE_100FULL;
2084 if (bp->advertising & ADVERTISED_1000baseT_Full)
2085 new_adv1000_reg |= ADVERTISE_1000FULL;
2086
2087 new_adv_reg |= ADVERTISE_CSMA;
2088
2089 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
2090
2091 if ((adv1000_reg != new_adv1000_reg) ||
2092 (adv_reg != new_adv_reg) ||
2093 ((bmcr & BMCR_ANENABLE) == 0)) {
2094
2095 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
2096 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
2097 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
2098 BMCR_ANENABLE);
2099 }
2100 else if (bp->link_up) {
2101 /* Flow ctrl may have changed from auto to forced */
2102 /* or vice-versa. */
2103
2104 bnx2_resolve_flow_ctrl(bp);
2105 bnx2_set_mac_link(bp);
2106 }
2107 return 0;
2108 }
2109
2110 new_bmcr = 0;
2111 if (bp->req_line_speed == SPEED_100) {
2112 new_bmcr |= BMCR_SPEED100;
2113 }
2114 if (bp->req_duplex == DUPLEX_FULL) {
2115 new_bmcr |= BMCR_FULLDPLX;
2116 }
2117 if (new_bmcr != bmcr) {
2118 u32 bmsr;
2119
2120 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2121 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2122
2123 if (bmsr & BMSR_LSTATUS) {
2124 /* Force link down */
2125 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
2126 spin_unlock_bh(&bp->phy_lock);
2127 msleep(50);
2128 spin_lock_bh(&bp->phy_lock);
2129
2130 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2131 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
2132 }
2133
2134 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
2135
2136 /* Normally, the new speed is setup after the link has
2137 * gone down and up again. In some cases, link will not go
2138 * down so we need to set up the new speed here.
2139 */
2140 if (bmsr & BMSR_LSTATUS) {
2141 bp->line_speed = bp->req_line_speed;
2142 bp->duplex = bp->req_duplex;
2143 bnx2_resolve_flow_ctrl(bp);
2144 bnx2_set_mac_link(bp);
2145 }
2146 } else {
2147 bnx2_resolve_flow_ctrl(bp);
2148 bnx2_set_mac_link(bp);
2149 }
2150 return 0;
2151 }
2152
2153 static int
2154 bnx2_setup_phy(struct bnx2 *bp, u8 port)
2155 __releases(&bp->phy_lock)
2156 __acquires(&bp->phy_lock)
2157 {
2158 if (bp->loopback == MAC_LOOPBACK)
2159 return 0;
2160
2161 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2162 return (bnx2_setup_serdes_phy(bp, port));
2163 }
2164 else {
2165 return (bnx2_setup_copper_phy(bp));
2166 }
2167 }
2168
2169 static int
2170 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
2171 {
2172 u32 val;
2173
2174 bp->mii_bmcr = MII_BMCR + 0x10;
2175 bp->mii_bmsr = MII_BMSR + 0x10;
2176 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
2177 bp->mii_adv = MII_ADVERTISE + 0x10;
2178 bp->mii_lpa = MII_LPA + 0x10;
2179 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
2180
2181 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
2182 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2183
2184 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2185 if (reset_phy)
2186 bnx2_reset_phy(bp);
2187
2188 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2189
2190 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2191 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2192 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2193 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2194
2195 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2196 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2197 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2198 val |= BCM5708S_UP1_2G5;
2199 else
2200 val &= ~BCM5708S_UP1_2G5;
2201 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2202
2203 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2204 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2205 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2206 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2207
2208 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2209
2210 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2211 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2212 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2213
2214 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2215
2216 return 0;
2217 }
2218
2219 static int
2220 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2221 {
2222 u32 val;
2223
2224 if (reset_phy)
2225 bnx2_reset_phy(bp);
2226
2227 bp->mii_up1 = BCM5708S_UP1;
2228
2229 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2230 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2231 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2232
2233 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2234 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2235 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2236
2237 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2238 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2239 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2240
2241 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2242 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2243 val |= BCM5708S_UP1_2G5;
2244 bnx2_write_phy(bp, BCM5708S_UP1, val);
2245 }
2246
2247 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2248 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2249 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2250 /* increase tx signal amplitude */
2251 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2252 BCM5708S_BLK_ADDR_TX_MISC);
2253 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2254 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2255 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2256 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2257 }
2258
2259 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2260 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2261
2262 if (val) {
2263 u32 is_backplane;
2264
2265 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2266 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2267 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2268 BCM5708S_BLK_ADDR_TX_MISC);
2269 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2270 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2271 BCM5708S_BLK_ADDR_DIG);
2272 }
2273 }
2274 return 0;
2275 }
2276
2277 static int
2278 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2279 {
2280 if (reset_phy)
2281 bnx2_reset_phy(bp);
2282
2283 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2284
2285 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2286 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2287
2288 if (bp->dev->mtu > 1500) {
2289 u32 val;
2290
2291 /* Set extended packet length bit */
2292 bnx2_write_phy(bp, 0x18, 0x7);
2293 bnx2_read_phy(bp, 0x18, &val);
2294 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2295
2296 bnx2_write_phy(bp, 0x1c, 0x6c00);
2297 bnx2_read_phy(bp, 0x1c, &val);
2298 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2299 }
2300 else {
2301 u32 val;
2302
2303 bnx2_write_phy(bp, 0x18, 0x7);
2304 bnx2_read_phy(bp, 0x18, &val);
2305 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2306
2307 bnx2_write_phy(bp, 0x1c, 0x6c00);
2308 bnx2_read_phy(bp, 0x1c, &val);
2309 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2310 }
2311
2312 return 0;
2313 }
2314
2315 static int
2316 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2317 {
2318 u32 val;
2319
2320 if (reset_phy)
2321 bnx2_reset_phy(bp);
2322
2323 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2324 bnx2_write_phy(bp, 0x18, 0x0c00);
2325 bnx2_write_phy(bp, 0x17, 0x000a);
2326 bnx2_write_phy(bp, 0x15, 0x310b);
2327 bnx2_write_phy(bp, 0x17, 0x201f);
2328 bnx2_write_phy(bp, 0x15, 0x9506);
2329 bnx2_write_phy(bp, 0x17, 0x401f);
2330 bnx2_write_phy(bp, 0x15, 0x14e2);
2331 bnx2_write_phy(bp, 0x18, 0x0400);
2332 }
2333
2334 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2335 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2336 MII_BNX2_DSP_EXPAND_REG | 0x8);
2337 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2338 val &= ~(1 << 8);
2339 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2340 }
2341
2342 if (bp->dev->mtu > 1500) {
2343 /* Set extended packet length bit */
2344 bnx2_write_phy(bp, 0x18, 0x7);
2345 bnx2_read_phy(bp, 0x18, &val);
2346 bnx2_write_phy(bp, 0x18, val | 0x4000);
2347
2348 bnx2_read_phy(bp, 0x10, &val);
2349 bnx2_write_phy(bp, 0x10, val | 0x1);
2350 }
2351 else {
2352 bnx2_write_phy(bp, 0x18, 0x7);
2353 bnx2_read_phy(bp, 0x18, &val);
2354 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2355
2356 bnx2_read_phy(bp, 0x10, &val);
2357 bnx2_write_phy(bp, 0x10, val & ~0x1);
2358 }
2359
2360 /* ethernet@wirespeed */
2361 bnx2_write_phy(bp, 0x18, 0x7007);
2362 bnx2_read_phy(bp, 0x18, &val);
2363 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2364 return 0;
2365 }
2366
2367
2368 static int
2369 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2370 __releases(&bp->phy_lock)
2371 __acquires(&bp->phy_lock)
2372 {
2373 u32 val;
2374 int rc = 0;
2375
2376 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2377 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2378
2379 bp->mii_bmcr = MII_BMCR;
2380 bp->mii_bmsr = MII_BMSR;
2381 bp->mii_bmsr1 = MII_BMSR;
2382 bp->mii_adv = MII_ADVERTISE;
2383 bp->mii_lpa = MII_LPA;
2384
2385 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2386
2387 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2388 goto setup_phy;
2389
2390 bnx2_read_phy(bp, MII_PHYSID1, &val);
2391 bp->phy_id = val << 16;
2392 bnx2_read_phy(bp, MII_PHYSID2, &val);
2393 bp->phy_id |= val & 0xffff;
2394
2395 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2396 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2397 rc = bnx2_init_5706s_phy(bp, reset_phy);
2398 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2399 rc = bnx2_init_5708s_phy(bp, reset_phy);
2400 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2401 rc = bnx2_init_5709s_phy(bp, reset_phy);
2402 }
2403 else {
2404 rc = bnx2_init_copper_phy(bp, reset_phy);
2405 }
2406
2407 setup_phy:
2408 if (!rc)
2409 rc = bnx2_setup_phy(bp, bp->phy_port);
2410
2411 return rc;
2412 }
2413
2414 static int
2415 bnx2_set_mac_loopback(struct bnx2 *bp)
2416 {
2417 u32 mac_mode;
2418
2419 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2420 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2421 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2422 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2423 bp->link_up = 1;
2424 return 0;
2425 }
2426
2427 static int bnx2_test_link(struct bnx2 *);
2428
2429 static int
2430 bnx2_set_phy_loopback(struct bnx2 *bp)
2431 {
2432 u32 mac_mode;
2433 int rc, i;
2434
2435 spin_lock_bh(&bp->phy_lock);
2436 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2437 BMCR_SPEED1000);
2438 spin_unlock_bh(&bp->phy_lock);
2439 if (rc)
2440 return rc;
2441
2442 for (i = 0; i < 10; i++) {
2443 if (bnx2_test_link(bp) == 0)
2444 break;
2445 msleep(100);
2446 }
2447
2448 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2449 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2450 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2451 BNX2_EMAC_MODE_25G_MODE);
2452
2453 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2454 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2455 bp->link_up = 1;
2456 return 0;
2457 }
2458
2459 static int
2460 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2461 {
2462 int i;
2463 u32 val;
2464
2465 bp->fw_wr_seq++;
2466 msg_data |= bp->fw_wr_seq;
2467
2468 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2469
2470 if (!ack)
2471 return 0;
2472
2473 /* wait for an acknowledgement. */
2474 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2475 msleep(10);
2476
2477 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2478
2479 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2480 break;
2481 }
2482 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2483 return 0;
2484
2485 /* If we timed out, inform the firmware that this is the case. */
2486 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2487 if (!silent)
2488 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2489 "%x\n", msg_data);
2490
2491 msg_data &= ~BNX2_DRV_MSG_CODE;
2492 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2493
2494 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2495
2496 return -EBUSY;
2497 }
2498
2499 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2500 return -EIO;
2501
2502 return 0;
2503 }
2504
2505 static int
2506 bnx2_init_5709_context(struct bnx2 *bp)
2507 {
2508 int i, ret = 0;
2509 u32 val;
2510
2511 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2512 val |= (BCM_PAGE_BITS - 8) << 16;
2513 REG_WR(bp, BNX2_CTX_COMMAND, val);
2514 for (i = 0; i < 10; i++) {
2515 val = REG_RD(bp, BNX2_CTX_COMMAND);
2516 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2517 break;
2518 udelay(2);
2519 }
2520 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2521 return -EBUSY;
2522
2523 for (i = 0; i < bp->ctx_pages; i++) {
2524 int j;
2525
2526 if (bp->ctx_blk[i])
2527 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2528 else
2529 return -ENOMEM;
2530
2531 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2532 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2533 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2534 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2535 (u64) bp->ctx_blk_mapping[i] >> 32);
2536 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2537 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2538 for (j = 0; j < 10; j++) {
2539
2540 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2541 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2542 break;
2543 udelay(5);
2544 }
2545 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2546 ret = -EBUSY;
2547 break;
2548 }
2549 }
2550 return ret;
2551 }
2552
2553 static void
2554 bnx2_init_context(struct bnx2 *bp)
2555 {
2556 u32 vcid;
2557
2558 vcid = 96;
2559 while (vcid) {
2560 u32 vcid_addr, pcid_addr, offset;
2561 int i;
2562
2563 vcid--;
2564
2565 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2566 u32 new_vcid;
2567
2568 vcid_addr = GET_PCID_ADDR(vcid);
2569 if (vcid & 0x8) {
2570 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2571 }
2572 else {
2573 new_vcid = vcid;
2574 }
2575 pcid_addr = GET_PCID_ADDR(new_vcid);
2576 }
2577 else {
2578 vcid_addr = GET_CID_ADDR(vcid);
2579 pcid_addr = vcid_addr;
2580 }
2581
2582 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2583 vcid_addr += (i << PHY_CTX_SHIFT);
2584 pcid_addr += (i << PHY_CTX_SHIFT);
2585
2586 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2587 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2588
2589 /* Zero out the context. */
2590 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2591 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2592 }
2593 }
2594 }
2595
2596 static int
2597 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2598 {
2599 u16 *good_mbuf;
2600 u32 good_mbuf_cnt;
2601 u32 val;
2602
2603 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2604 if (good_mbuf == NULL) {
2605 printk(KERN_ERR PFX "Failed to allocate memory in "
2606 "bnx2_alloc_bad_rbuf\n");
2607 return -ENOMEM;
2608 }
2609
2610 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2611 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2612
2613 good_mbuf_cnt = 0;
2614
2615 /* Allocate a bunch of mbufs and save the good ones in an array. */
2616 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2617 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2618 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2619 BNX2_RBUF_COMMAND_ALLOC_REQ);
2620
2621 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2622
2623 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2624
2625 /* The addresses with Bit 9 set are bad memory blocks. */
2626 if (!(val & (1 << 9))) {
2627 good_mbuf[good_mbuf_cnt] = (u16) val;
2628 good_mbuf_cnt++;
2629 }
2630
2631 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2632 }
2633
2634 /* Free the good ones back to the mbuf pool thus discarding
2635 * all the bad ones. */
2636 while (good_mbuf_cnt) {
2637 good_mbuf_cnt--;
2638
2639 val = good_mbuf[good_mbuf_cnt];
2640 val = (val << 9) | val | 1;
2641
2642 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2643 }
2644 kfree(good_mbuf);
2645 return 0;
2646 }
2647
2648 static void
2649 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2650 {
2651 u32 val;
2652
2653 val = (mac_addr[0] << 8) | mac_addr[1];
2654
2655 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2656
2657 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2658 (mac_addr[4] << 8) | mac_addr[5];
2659
2660 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2661 }
2662
2663 static inline int
2664 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2665 {
2666 dma_addr_t mapping;
2667 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2668 struct rx_bd *rxbd =
2669 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2670 struct page *page = alloc_page(GFP_ATOMIC);
2671
2672 if (!page)
2673 return -ENOMEM;
2674 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2675 PCI_DMA_FROMDEVICE);
2676 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2677 __free_page(page);
2678 return -EIO;
2679 }
2680
2681 rx_pg->page = page;
2682 pci_unmap_addr_set(rx_pg, mapping, mapping);
2683 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2684 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2685 return 0;
2686 }
2687
2688 static void
2689 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2690 {
2691 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2692 struct page *page = rx_pg->page;
2693
2694 if (!page)
2695 return;
2696
2697 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2698 PCI_DMA_FROMDEVICE);
2699
2700 __free_page(page);
2701 rx_pg->page = NULL;
2702 }
2703
2704 static inline int
2705 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2706 {
2707 struct sk_buff *skb;
2708 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2709 dma_addr_t mapping;
2710 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2711 unsigned long align;
2712
2713 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2714 if (skb == NULL) {
2715 return -ENOMEM;
2716 }
2717
2718 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2719 skb_reserve(skb, BNX2_RX_ALIGN - align);
2720
2721 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2722 PCI_DMA_FROMDEVICE);
2723 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2724 dev_kfree_skb(skb);
2725 return -EIO;
2726 }
2727
2728 rx_buf->skb = skb;
2729 pci_unmap_addr_set(rx_buf, mapping, mapping);
2730
2731 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2732 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2733
2734 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2735
2736 return 0;
2737 }
2738
2739 static int
2740 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2741 {
2742 struct status_block *sblk = bnapi->status_blk.msi;
2743 u32 new_link_state, old_link_state;
2744 int is_set = 1;
2745
2746 new_link_state = sblk->status_attn_bits & event;
2747 old_link_state = sblk->status_attn_bits_ack & event;
2748 if (new_link_state != old_link_state) {
2749 if (new_link_state)
2750 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2751 else
2752 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2753 } else
2754 is_set = 0;
2755
2756 return is_set;
2757 }
2758
2759 static void
2760 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2761 {
2762 spin_lock(&bp->phy_lock);
2763
2764 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2765 bnx2_set_link(bp);
2766 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2767 bnx2_set_remote_link(bp);
2768
2769 spin_unlock(&bp->phy_lock);
2770
2771 }
2772
2773 static inline u16
2774 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2775 {
2776 u16 cons;
2777
2778 /* Tell compiler that status block fields can change. */
2779 barrier();
2780 cons = *bnapi->hw_tx_cons_ptr;
2781 barrier();
2782 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2783 cons++;
2784 return cons;
2785 }
2786
2787 static int
2788 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2789 {
2790 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2791 u16 hw_cons, sw_cons, sw_ring_cons;
2792 int tx_pkt = 0, index;
2793 struct netdev_queue *txq;
2794
2795 index = (bnapi - bp->bnx2_napi);
2796 txq = netdev_get_tx_queue(bp->dev, index);
2797
2798 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2799 sw_cons = txr->tx_cons;
2800
2801 while (sw_cons != hw_cons) {
2802 struct sw_tx_bd *tx_buf;
2803 struct sk_buff *skb;
2804 int i, last;
2805
2806 sw_ring_cons = TX_RING_IDX(sw_cons);
2807
2808 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2809 skb = tx_buf->skb;
2810
2811 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
2812 prefetch(&skb->end);
2813
2814 /* partial BD completions possible with TSO packets */
2815 if (tx_buf->is_gso) {
2816 u16 last_idx, last_ring_idx;
2817
2818 last_idx = sw_cons + tx_buf->nr_frags + 1;
2819 last_ring_idx = sw_ring_cons + tx_buf->nr_frags + 1;
2820 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2821 last_idx++;
2822 }
2823 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2824 break;
2825 }
2826 }
2827
2828 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2829 skb_headlen(skb), PCI_DMA_TODEVICE);
2830
2831 tx_buf->skb = NULL;
2832 last = tx_buf->nr_frags;
2833
2834 for (i = 0; i < last; i++) {
2835 sw_cons = NEXT_TX_BD(sw_cons);
2836
2837 pci_unmap_page(bp->pdev,
2838 pci_unmap_addr(
2839 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2840 mapping),
2841 skb_shinfo(skb)->frags[i].size,
2842 PCI_DMA_TODEVICE);
2843 }
2844
2845 sw_cons = NEXT_TX_BD(sw_cons);
2846
2847 dev_kfree_skb(skb);
2848 tx_pkt++;
2849 if (tx_pkt == budget)
2850 break;
2851
2852 if (hw_cons == sw_cons)
2853 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2854 }
2855
2856 txr->hw_tx_cons = hw_cons;
2857 txr->tx_cons = sw_cons;
2858
2859 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2860 * before checking for netif_tx_queue_stopped(). Without the
2861 * memory barrier, there is a small possibility that bnx2_start_xmit()
2862 * will miss it and cause the queue to be stopped forever.
2863 */
2864 smp_mb();
2865
2866 if (unlikely(netif_tx_queue_stopped(txq)) &&
2867 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2868 __netif_tx_lock(txq, smp_processor_id());
2869 if ((netif_tx_queue_stopped(txq)) &&
2870 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2871 netif_tx_wake_queue(txq);
2872 __netif_tx_unlock(txq);
2873 }
2874
2875 return tx_pkt;
2876 }
2877
2878 static void
2879 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2880 struct sk_buff *skb, int count)
2881 {
2882 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2883 struct rx_bd *cons_bd, *prod_bd;
2884 int i;
2885 u16 hw_prod, prod;
2886 u16 cons = rxr->rx_pg_cons;
2887
2888 cons_rx_pg = &rxr->rx_pg_ring[cons];
2889
2890 /* The caller was unable to allocate a new page to replace the
2891 * last one in the frags array, so we need to recycle that page
2892 * and then free the skb.
2893 */
2894 if (skb) {
2895 struct page *page;
2896 struct skb_shared_info *shinfo;
2897
2898 shinfo = skb_shinfo(skb);
2899 shinfo->nr_frags--;
2900 page = shinfo->frags[shinfo->nr_frags].page;
2901 shinfo->frags[shinfo->nr_frags].page = NULL;
2902
2903 cons_rx_pg->page = page;
2904 dev_kfree_skb(skb);
2905 }
2906
2907 hw_prod = rxr->rx_pg_prod;
2908
2909 for (i = 0; i < count; i++) {
2910 prod = RX_PG_RING_IDX(hw_prod);
2911
2912 prod_rx_pg = &rxr->rx_pg_ring[prod];
2913 cons_rx_pg = &rxr->rx_pg_ring[cons];
2914 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2915 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2916
2917 if (prod != cons) {
2918 prod_rx_pg->page = cons_rx_pg->page;
2919 cons_rx_pg->page = NULL;
2920 pci_unmap_addr_set(prod_rx_pg, mapping,
2921 pci_unmap_addr(cons_rx_pg, mapping));
2922
2923 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2924 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2925
2926 }
2927 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2928 hw_prod = NEXT_RX_BD(hw_prod);
2929 }
2930 rxr->rx_pg_prod = hw_prod;
2931 rxr->rx_pg_cons = cons;
2932 }
2933
2934 static inline void
2935 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2936 struct sk_buff *skb, u16 cons, u16 prod)
2937 {
2938 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2939 struct rx_bd *cons_bd, *prod_bd;
2940
2941 cons_rx_buf = &rxr->rx_buf_ring[cons];
2942 prod_rx_buf = &rxr->rx_buf_ring[prod];
2943
2944 pci_dma_sync_single_for_device(bp->pdev,
2945 pci_unmap_addr(cons_rx_buf, mapping),
2946 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2947
2948 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2949
2950 prod_rx_buf->skb = skb;
2951
2952 if (cons == prod)
2953 return;
2954
2955 pci_unmap_addr_set(prod_rx_buf, mapping,
2956 pci_unmap_addr(cons_rx_buf, mapping));
2957
2958 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2959 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2960 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2961 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2962 }
2963
2964 static int
2965 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2966 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2967 u32 ring_idx)
2968 {
2969 int err;
2970 u16 prod = ring_idx & 0xffff;
2971
2972 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2973 if (unlikely(err)) {
2974 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2975 if (hdr_len) {
2976 unsigned int raw_len = len + 4;
2977 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2978
2979 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2980 }
2981 return err;
2982 }
2983
2984 skb_reserve(skb, BNX2_RX_OFFSET);
2985 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2986 PCI_DMA_FROMDEVICE);
2987
2988 if (hdr_len == 0) {
2989 skb_put(skb, len);
2990 return 0;
2991 } else {
2992 unsigned int i, frag_len, frag_size, pages;
2993 struct sw_pg *rx_pg;
2994 u16 pg_cons = rxr->rx_pg_cons;
2995 u16 pg_prod = rxr->rx_pg_prod;
2996
2997 frag_size = len + 4 - hdr_len;
2998 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2999 skb_put(skb, hdr_len);
3000
3001 for (i = 0; i < pages; i++) {
3002 dma_addr_t mapping_old;
3003
3004 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
3005 if (unlikely(frag_len <= 4)) {
3006 unsigned int tail = 4 - frag_len;
3007
3008 rxr->rx_pg_cons = pg_cons;
3009 rxr->rx_pg_prod = pg_prod;
3010 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
3011 pages - i);
3012 skb->len -= tail;
3013 if (i == 0) {
3014 skb->tail -= tail;
3015 } else {
3016 skb_frag_t *frag =
3017 &skb_shinfo(skb)->frags[i - 1];
3018 frag->size -= tail;
3019 skb->data_len -= tail;
3020 skb->truesize -= tail;
3021 }
3022 return 0;
3023 }
3024 rx_pg = &rxr->rx_pg_ring[pg_cons];
3025
3026 /* Don't unmap yet. If we're unable to allocate a new
3027 * page, we need to recycle the page and the DMA addr.
3028 */
3029 mapping_old = pci_unmap_addr(rx_pg, mapping);
3030 if (i == pages - 1)
3031 frag_len -= 4;
3032
3033 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
3034 rx_pg->page = NULL;
3035
3036 err = bnx2_alloc_rx_page(bp, rxr,
3037 RX_PG_RING_IDX(pg_prod));
3038 if (unlikely(err)) {
3039 rxr->rx_pg_cons = pg_cons;
3040 rxr->rx_pg_prod = pg_prod;
3041 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
3042 pages - i);
3043 return err;
3044 }
3045
3046 pci_unmap_page(bp->pdev, mapping_old,
3047 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3048
3049 frag_size -= frag_len;
3050 skb->data_len += frag_len;
3051 skb->truesize += frag_len;
3052 skb->len += frag_len;
3053
3054 pg_prod = NEXT_RX_BD(pg_prod);
3055 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
3056 }
3057 rxr->rx_pg_prod = pg_prod;
3058 rxr->rx_pg_cons = pg_cons;
3059 }
3060 return 0;
3061 }
3062
3063 static inline u16
3064 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
3065 {
3066 u16 cons;
3067
3068 /* Tell compiler that status block fields can change. */
3069 barrier();
3070 cons = *bnapi->hw_rx_cons_ptr;
3071 barrier();
3072 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
3073 cons++;
3074 return cons;
3075 }
3076
3077 static int
3078 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
3079 {
3080 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3081 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
3082 struct l2_fhdr *rx_hdr;
3083 int rx_pkt = 0, pg_ring_used = 0;
3084
3085 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3086 sw_cons = rxr->rx_cons;
3087 sw_prod = rxr->rx_prod;
3088
3089 /* Memory barrier necessary as speculative reads of the rx
3090 * buffer can be ahead of the index in the status block
3091 */
3092 rmb();
3093 while (sw_cons != hw_cons) {
3094 unsigned int len, hdr_len;
3095 u32 status;
3096 struct sw_bd *rx_buf;
3097 struct sk_buff *skb;
3098 dma_addr_t dma_addr;
3099 u16 vtag = 0;
3100 int hw_vlan __maybe_unused = 0;
3101
3102 sw_ring_cons = RX_RING_IDX(sw_cons);
3103 sw_ring_prod = RX_RING_IDX(sw_prod);
3104
3105 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
3106 skb = rx_buf->skb;
3107
3108 rx_buf->skb = NULL;
3109
3110 dma_addr = pci_unmap_addr(rx_buf, mapping);
3111
3112 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
3113 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
3114 PCI_DMA_FROMDEVICE);
3115
3116 rx_hdr = (struct l2_fhdr *) skb->data;
3117 len = rx_hdr->l2_fhdr_pkt_len;
3118 status = rx_hdr->l2_fhdr_status;
3119
3120 hdr_len = 0;
3121 if (status & L2_FHDR_STATUS_SPLIT) {
3122 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
3123 pg_ring_used = 1;
3124 } else if (len > bp->rx_jumbo_thresh) {
3125 hdr_len = bp->rx_jumbo_thresh;
3126 pg_ring_used = 1;
3127 }
3128
3129 if (unlikely(status & (L2_FHDR_ERRORS_BAD_CRC |
3130 L2_FHDR_ERRORS_PHY_DECODE |
3131 L2_FHDR_ERRORS_ALIGNMENT |
3132 L2_FHDR_ERRORS_TOO_SHORT |
3133 L2_FHDR_ERRORS_GIANT_FRAME))) {
3134
3135 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3136 sw_ring_prod);
3137 if (pg_ring_used) {
3138 int pages;
3139
3140 pages = PAGE_ALIGN(len - hdr_len) >> PAGE_SHIFT;
3141
3142 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
3143 }
3144 goto next_rx;
3145 }
3146
3147 len -= 4;
3148
3149 if (len <= bp->rx_copy_thresh) {
3150 struct sk_buff *new_skb;
3151
3152 new_skb = netdev_alloc_skb(bp->dev, len + 6);
3153 if (new_skb == NULL) {
3154 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
3155 sw_ring_prod);
3156 goto next_rx;
3157 }
3158
3159 /* aligned copy */
3160 skb_copy_from_linear_data_offset(skb,
3161 BNX2_RX_OFFSET - 6,
3162 new_skb->data, len + 6);
3163 skb_reserve(new_skb, 6);
3164 skb_put(new_skb, len);
3165
3166 bnx2_reuse_rx_skb(bp, rxr, skb,
3167 sw_ring_cons, sw_ring_prod);
3168
3169 skb = new_skb;
3170 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
3171 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
3172 goto next_rx;
3173
3174 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
3175 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
3176 vtag = rx_hdr->l2_fhdr_vlan_tag;
3177 #ifdef BCM_VLAN
3178 if (bp->vlgrp)
3179 hw_vlan = 1;
3180 else
3181 #endif
3182 {
3183 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
3184 __skb_push(skb, 4);
3185
3186 memmove(ve, skb->data + 4, ETH_ALEN * 2);
3187 ve->h_vlan_proto = htons(ETH_P_8021Q);
3188 ve->h_vlan_TCI = htons(vtag);
3189 len += 4;
3190 }
3191 }
3192
3193 skb->protocol = eth_type_trans(skb, bp->dev);
3194
3195 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
3196 (ntohs(skb->protocol) != 0x8100)) {
3197
3198 dev_kfree_skb(skb);
3199 goto next_rx;
3200
3201 }
3202
3203 skb->ip_summed = CHECKSUM_NONE;
3204 if (bp->rx_csum &&
3205 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3206 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3207
3208 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3209 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3210 skb->ip_summed = CHECKSUM_UNNECESSARY;
3211 }
3212
3213 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3214
3215 #ifdef BCM_VLAN
3216 if (hw_vlan)
3217 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3218 else
3219 #endif
3220 netif_receive_skb(skb);
3221
3222 rx_pkt++;
3223
3224 next_rx:
3225 sw_cons = NEXT_RX_BD(sw_cons);
3226 sw_prod = NEXT_RX_BD(sw_prod);
3227
3228 if ((rx_pkt == budget))
3229 break;
3230
3231 /* Refresh hw_cons to see if there is new work */
3232 if (sw_cons == hw_cons) {
3233 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3234 rmb();
3235 }
3236 }
3237 rxr->rx_cons = sw_cons;
3238 rxr->rx_prod = sw_prod;
3239
3240 if (pg_ring_used)
3241 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3242
3243 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3244
3245 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3246
3247 mmiowb();
3248
3249 return rx_pkt;
3250
3251 }
3252
3253 /* MSI ISR - The only difference between this and the INTx ISR
3254 * is that the MSI interrupt is always serviced.
3255 */
3256 static irqreturn_t
3257 bnx2_msi(int irq, void *dev_instance)
3258 {
3259 struct bnx2_napi *bnapi = dev_instance;
3260 struct bnx2 *bp = bnapi->bp;
3261
3262 prefetch(bnapi->status_blk.msi);
3263 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3264 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3265 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3266
3267 /* Return here if interrupt is disabled. */
3268 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3269 return IRQ_HANDLED;
3270
3271 napi_schedule(&bnapi->napi);
3272
3273 return IRQ_HANDLED;
3274 }
3275
3276 static irqreturn_t
3277 bnx2_msi_1shot(int irq, void *dev_instance)
3278 {
3279 struct bnx2_napi *bnapi = dev_instance;
3280 struct bnx2 *bp = bnapi->bp;
3281
3282 prefetch(bnapi->status_blk.msi);
3283
3284 /* Return here if interrupt is disabled. */
3285 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3286 return IRQ_HANDLED;
3287
3288 napi_schedule(&bnapi->napi);
3289
3290 return IRQ_HANDLED;
3291 }
3292
3293 static irqreturn_t
3294 bnx2_interrupt(int irq, void *dev_instance)
3295 {
3296 struct bnx2_napi *bnapi = dev_instance;
3297 struct bnx2 *bp = bnapi->bp;
3298 struct status_block *sblk = bnapi->status_blk.msi;
3299
3300 /* When using INTx, it is possible for the interrupt to arrive
3301 * at the CPU before the status block posted prior to the
3302 * interrupt. Reading a register will flush the status block.
3303 * When using MSI, the MSI message will always complete after
3304 * the status block write.
3305 */
3306 if ((sblk->status_idx == bnapi->last_status_idx) &&
3307 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3308 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3309 return IRQ_NONE;
3310
3311 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3312 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3313 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3314
3315 /* Read back to deassert IRQ immediately to avoid too many
3316 * spurious interrupts.
3317 */
3318 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3319
3320 /* Return here if interrupt is shared and is disabled. */
3321 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3322 return IRQ_HANDLED;
3323
3324 if (napi_schedule_prep(&bnapi->napi)) {
3325 bnapi->last_status_idx = sblk->status_idx;
3326 __napi_schedule(&bnapi->napi);
3327 }
3328
3329 return IRQ_HANDLED;
3330 }
3331
3332 static inline int
3333 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3334 {
3335 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3336 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3337
3338 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3339 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3340 return 1;
3341 return 0;
3342 }
3343
3344 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3345 STATUS_ATTN_BITS_TIMER_ABORT)
3346
3347 static inline int
3348 bnx2_has_work(struct bnx2_napi *bnapi)
3349 {
3350 struct status_block *sblk = bnapi->status_blk.msi;
3351
3352 if (bnx2_has_fast_work(bnapi))
3353 return 1;
3354
3355 #ifdef BCM_CNIC
3356 if (bnapi->cnic_present && (bnapi->cnic_tag != sblk->status_idx))
3357 return 1;
3358 #endif
3359
3360 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3361 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3362 return 1;
3363
3364 return 0;
3365 }
3366
3367 static void
3368 bnx2_chk_missed_msi(struct bnx2 *bp)
3369 {
3370 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3371 u32 msi_ctrl;
3372
3373 if (bnx2_has_work(bnapi)) {
3374 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3375 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3376 return;
3377
3378 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3379 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3380 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3381 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3382 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3383 }
3384 }
3385
3386 bp->idle_chk_status_idx = bnapi->last_status_idx;
3387 }
3388
3389 #ifdef BCM_CNIC
3390 static void bnx2_poll_cnic(struct bnx2 *bp, struct bnx2_napi *bnapi)
3391 {
3392 struct cnic_ops *c_ops;
3393
3394 if (!bnapi->cnic_present)
3395 return;
3396
3397 rcu_read_lock();
3398 c_ops = rcu_dereference(bp->cnic_ops);
3399 if (c_ops)
3400 bnapi->cnic_tag = c_ops->cnic_handler(bp->cnic_data,
3401 bnapi->status_blk.msi);
3402 rcu_read_unlock();
3403 }
3404 #endif
3405
3406 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3407 {
3408 struct status_block *sblk = bnapi->status_blk.msi;
3409 u32 status_attn_bits = sblk->status_attn_bits;
3410 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3411
3412 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3413 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3414
3415 bnx2_phy_int(bp, bnapi);
3416
3417 /* This is needed to take care of transient status
3418 * during link changes.
3419 */
3420 REG_WR(bp, BNX2_HC_COMMAND,
3421 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3422 REG_RD(bp, BNX2_HC_COMMAND);
3423 }
3424 }
3425
3426 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3427 int work_done, int budget)
3428 {
3429 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3430 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3431
3432 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3433 bnx2_tx_int(bp, bnapi, 0);
3434
3435 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3436 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3437
3438 return work_done;
3439 }
3440
3441 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3442 {
3443 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3444 struct bnx2 *bp = bnapi->bp;
3445 int work_done = 0;
3446 struct status_block_msix *sblk = bnapi->status_blk.msix;
3447
3448 while (1) {
3449 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3450 if (unlikely(work_done >= budget))
3451 break;
3452
3453 bnapi->last_status_idx = sblk->status_idx;
3454 /* status idx must be read before checking for more work. */
3455 rmb();
3456 if (likely(!bnx2_has_fast_work(bnapi))) {
3457
3458 napi_complete(napi);
3459 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3460 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3461 bnapi->last_status_idx);
3462 break;
3463 }
3464 }
3465 return work_done;
3466 }
3467
3468 static int bnx2_poll(struct napi_struct *napi, int budget)
3469 {
3470 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3471 struct bnx2 *bp = bnapi->bp;
3472 int work_done = 0;
3473 struct status_block *sblk = bnapi->status_blk.msi;
3474
3475 while (1) {
3476 bnx2_poll_link(bp, bnapi);
3477
3478 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3479
3480 #ifdef BCM_CNIC
3481 bnx2_poll_cnic(bp, bnapi);
3482 #endif
3483
3484 /* bnapi->last_status_idx is used below to tell the hw how
3485 * much work has been processed, so we must read it before
3486 * checking for more work.
3487 */
3488 bnapi->last_status_idx = sblk->status_idx;
3489
3490 if (unlikely(work_done >= budget))
3491 break;
3492
3493 rmb();
3494 if (likely(!bnx2_has_work(bnapi))) {
3495 napi_complete(napi);
3496 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3497 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3498 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3499 bnapi->last_status_idx);
3500 break;
3501 }
3502 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3503 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3504 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3505 bnapi->last_status_idx);
3506
3507 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3508 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3509 bnapi->last_status_idx);
3510 break;
3511 }
3512 }
3513
3514 return work_done;
3515 }
3516
3517 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3518 * from set_multicast.
3519 */
3520 static void
3521 bnx2_set_rx_mode(struct net_device *dev)
3522 {
3523 struct bnx2 *bp = netdev_priv(dev);
3524 u32 rx_mode, sort_mode;
3525 struct netdev_hw_addr *ha;
3526 int i;
3527
3528 if (!netif_running(dev))
3529 return;
3530
3531 spin_lock_bh(&bp->phy_lock);
3532
3533 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3534 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3535 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3536 #ifdef BCM_VLAN
3537 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3538 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3539 #else
3540 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3541 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3542 #endif
3543 if (dev->flags & IFF_PROMISC) {
3544 /* Promiscuous mode. */
3545 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3546 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3547 BNX2_RPM_SORT_USER0_PROM_VLAN;
3548 }
3549 else if (dev->flags & IFF_ALLMULTI) {
3550 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3551 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3552 0xffffffff);
3553 }
3554 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3555 }
3556 else {
3557 /* Accept one or more multicast(s). */
3558 struct dev_mc_list *mclist;
3559 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3560 u32 regidx;
3561 u32 bit;
3562 u32 crc;
3563
3564 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3565
3566 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3567 i++, mclist = mclist->next) {
3568
3569 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3570 bit = crc & 0xff;
3571 regidx = (bit & 0xe0) >> 5;
3572 bit &= 0x1f;
3573 mc_filter[regidx] |= (1 << bit);
3574 }
3575
3576 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3577 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3578 mc_filter[i]);
3579 }
3580
3581 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3582 }
3583
3584 if (dev->uc.count > BNX2_MAX_UNICAST_ADDRESSES) {
3585 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3586 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3587 BNX2_RPM_SORT_USER0_PROM_VLAN;
3588 } else if (!(dev->flags & IFF_PROMISC)) {
3589 /* Add all entries into to the match filter list */
3590 i = 0;
3591 list_for_each_entry(ha, &dev->uc.list, list) {
3592 bnx2_set_mac_addr(bp, ha->addr,
3593 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3594 sort_mode |= (1 <<
3595 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3596 i++;
3597 }
3598
3599 }
3600
3601 if (rx_mode != bp->rx_mode) {
3602 bp->rx_mode = rx_mode;
3603 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3604 }
3605
3606 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3607 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3608 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3609
3610 spin_unlock_bh(&bp->phy_lock);
3611 }
3612
3613 static int __devinit
3614 check_fw_section(const struct firmware *fw,
3615 const struct bnx2_fw_file_section *section,
3616 u32 alignment, bool non_empty)
3617 {
3618 u32 offset = be32_to_cpu(section->offset);
3619 u32 len = be32_to_cpu(section->len);
3620
3621 if ((offset == 0 && len != 0) || offset >= fw->size || offset & 3)
3622 return -EINVAL;
3623 if ((non_empty && len == 0) || len > fw->size - offset ||
3624 len & (alignment - 1))
3625 return -EINVAL;
3626 return 0;
3627 }
3628
3629 static int __devinit
3630 check_mips_fw_entry(const struct firmware *fw,
3631 const struct bnx2_mips_fw_file_entry *entry)
3632 {
3633 if (check_fw_section(fw, &entry->text, 4, true) ||
3634 check_fw_section(fw, &entry->data, 4, false) ||
3635 check_fw_section(fw, &entry->rodata, 4, false))
3636 return -EINVAL;
3637 return 0;
3638 }
3639
3640 static int __devinit
3641 bnx2_request_firmware(struct bnx2 *bp)
3642 {
3643 const char *mips_fw_file, *rv2p_fw_file;
3644 const struct bnx2_mips_fw_file *mips_fw;
3645 const struct bnx2_rv2p_fw_file *rv2p_fw;
3646 int rc;
3647
3648 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3649 mips_fw_file = FW_MIPS_FILE_09;
3650 if ((CHIP_ID(bp) == CHIP_ID_5709_A0) ||
3651 (CHIP_ID(bp) == CHIP_ID_5709_A1))
3652 rv2p_fw_file = FW_RV2P_FILE_09_Ax;
3653 else
3654 rv2p_fw_file = FW_RV2P_FILE_09;
3655 } else {
3656 mips_fw_file = FW_MIPS_FILE_06;
3657 rv2p_fw_file = FW_RV2P_FILE_06;
3658 }
3659
3660 rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev);
3661 if (rc) {
3662 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3663 mips_fw_file);
3664 return rc;
3665 }
3666
3667 rc = request_firmware(&bp->rv2p_firmware, rv2p_fw_file, &bp->pdev->dev);
3668 if (rc) {
3669 printk(KERN_ERR PFX "Can't load firmware file \"%s\"\n",
3670 rv2p_fw_file);
3671 return rc;
3672 }
3673 mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3674 rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3675 if (bp->mips_firmware->size < sizeof(*mips_fw) ||
3676 check_mips_fw_entry(bp->mips_firmware, &mips_fw->com) ||
3677 check_mips_fw_entry(bp->mips_firmware, &mips_fw->cp) ||
3678 check_mips_fw_entry(bp->mips_firmware, &mips_fw->rxp) ||
3679 check_mips_fw_entry(bp->mips_firmware, &mips_fw->tpat) ||
3680 check_mips_fw_entry(bp->mips_firmware, &mips_fw->txp)) {
3681 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3682 mips_fw_file);
3683 return -EINVAL;
3684 }
3685 if (bp->rv2p_firmware->size < sizeof(*rv2p_fw) ||
3686 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc1.rv2p, 8, true) ||
3687 check_fw_section(bp->rv2p_firmware, &rv2p_fw->proc2.rv2p, 8, true)) {
3688 printk(KERN_ERR PFX "Firmware file \"%s\" is invalid\n",
3689 rv2p_fw_file);
3690 return -EINVAL;
3691 }
3692
3693 return 0;
3694 }
3695
3696 static u32
3697 rv2p_fw_fixup(u32 rv2p_proc, int idx, u32 loc, u32 rv2p_code)
3698 {
3699 switch (idx) {
3700 case RV2P_P1_FIXUP_PAGE_SIZE_IDX:
3701 rv2p_code &= ~RV2P_BD_PAGE_SIZE_MSK;
3702 rv2p_code |= RV2P_BD_PAGE_SIZE;
3703 break;
3704 }
3705 return rv2p_code;
3706 }
3707
3708 static int
3709 load_rv2p_fw(struct bnx2 *bp, u32 rv2p_proc,
3710 const struct bnx2_rv2p_fw_file_entry *fw_entry)
3711 {
3712 u32 rv2p_code_len, file_offset;
3713 __be32 *rv2p_code;
3714 int i;
3715 u32 val, cmd, addr;
3716
3717 rv2p_code_len = be32_to_cpu(fw_entry->rv2p.len);
3718 file_offset = be32_to_cpu(fw_entry->rv2p.offset);
3719
3720 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3721
3722 if (rv2p_proc == RV2P_PROC1) {
3723 cmd = BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3724 addr = BNX2_RV2P_PROC1_ADDR_CMD;
3725 } else {
3726 cmd = BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3727 addr = BNX2_RV2P_PROC2_ADDR_CMD;
3728 }
3729
3730 for (i = 0; i < rv2p_code_len; i += 8) {
3731 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, be32_to_cpu(*rv2p_code));
3732 rv2p_code++;
3733 REG_WR(bp, BNX2_RV2P_INSTR_LOW, be32_to_cpu(*rv2p_code));
3734 rv2p_code++;
3735
3736 val = (i / 8) | cmd;
3737 REG_WR(bp, addr, val);
3738 }
3739
3740 rv2p_code = (__be32 *)(bp->rv2p_firmware->data + file_offset);
3741 for (i = 0; i < 8; i++) {
3742 u32 loc, code;
3743
3744 loc = be32_to_cpu(fw_entry->fixup[i]);
3745 if (loc && ((loc * 4) < rv2p_code_len)) {
3746 code = be32_to_cpu(*(rv2p_code + loc - 1));
3747 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, code);
3748 code = be32_to_cpu(*(rv2p_code + loc));
3749 code = rv2p_fw_fixup(rv2p_proc, i, loc, code);
3750 REG_WR(bp, BNX2_RV2P_INSTR_LOW, code);
3751
3752 val = (loc / 2) | cmd;
3753 REG_WR(bp, addr, val);
3754 }
3755 }
3756
3757 /* Reset the processor, un-stall is done later. */
3758 if (rv2p_proc == RV2P_PROC1) {
3759 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3760 }
3761 else {
3762 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3763 }
3764
3765 return 0;
3766 }
3767
3768 static int
3769 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg,
3770 const struct bnx2_mips_fw_file_entry *fw_entry)
3771 {
3772 u32 addr, len, file_offset;
3773 __be32 *data;
3774 u32 offset;
3775 u32 val;
3776
3777 /* Halt the CPU. */
3778 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3779 val |= cpu_reg->mode_value_halt;
3780 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3781 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3782
3783 /* Load the Text area. */
3784 addr = be32_to_cpu(fw_entry->text.addr);
3785 len = be32_to_cpu(fw_entry->text.len);
3786 file_offset = be32_to_cpu(fw_entry->text.offset);
3787 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3788
3789 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3790 if (len) {
3791 int j;
3792
3793 for (j = 0; j < (len / 4); j++, offset += 4)
3794 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3795 }
3796
3797 /* Load the Data area. */
3798 addr = be32_to_cpu(fw_entry->data.addr);
3799 len = be32_to_cpu(fw_entry->data.len);
3800 file_offset = be32_to_cpu(fw_entry->data.offset);
3801 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3802
3803 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3804 if (len) {
3805 int j;
3806
3807 for (j = 0; j < (len / 4); j++, offset += 4)
3808 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3809 }
3810
3811 /* Load the Read-Only area. */
3812 addr = be32_to_cpu(fw_entry->rodata.addr);
3813 len = be32_to_cpu(fw_entry->rodata.len);
3814 file_offset = be32_to_cpu(fw_entry->rodata.offset);
3815 data = (__be32 *)(bp->mips_firmware->data + file_offset);
3816
3817 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base);
3818 if (len) {
3819 int j;
3820
3821 for (j = 0; j < (len / 4); j++, offset += 4)
3822 bnx2_reg_wr_ind(bp, offset, be32_to_cpu(data[j]));
3823 }
3824
3825 /* Clear the pre-fetch instruction. */
3826 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3827
3828 val = be32_to_cpu(fw_entry->start_addr);
3829 bnx2_reg_wr_ind(bp, cpu_reg->pc, val);
3830
3831 /* Start the CPU. */
3832 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3833 val &= ~cpu_reg->mode_value_halt;
3834 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3835 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3836
3837 return 0;
3838 }
3839
3840 static int
3841 bnx2_init_cpus(struct bnx2 *bp)
3842 {
3843 const struct bnx2_mips_fw_file *mips_fw =
3844 (const struct bnx2_mips_fw_file *) bp->mips_firmware->data;
3845 const struct bnx2_rv2p_fw_file *rv2p_fw =
3846 (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data;
3847 int rc;
3848
3849 /* Initialize the RV2P processor. */
3850 load_rv2p_fw(bp, RV2P_PROC1, &rv2p_fw->proc1);
3851 load_rv2p_fw(bp, RV2P_PROC2, &rv2p_fw->proc2);
3852
3853 /* Initialize the RX Processor. */
3854 rc = load_cpu_fw(bp, &cpu_reg_rxp, &mips_fw->rxp);
3855 if (rc)
3856 goto init_cpu_err;
3857
3858 /* Initialize the TX Processor. */
3859 rc = load_cpu_fw(bp, &cpu_reg_txp, &mips_fw->txp);
3860 if (rc)
3861 goto init_cpu_err;
3862
3863 /* Initialize the TX Patch-up Processor. */
3864 rc = load_cpu_fw(bp, &cpu_reg_tpat, &mips_fw->tpat);
3865 if (rc)
3866 goto init_cpu_err;
3867
3868 /* Initialize the Completion Processor. */
3869 rc = load_cpu_fw(bp, &cpu_reg_com, &mips_fw->com);
3870 if (rc)
3871 goto init_cpu_err;
3872
3873 /* Initialize the Command Processor. */
3874 rc = load_cpu_fw(bp, &cpu_reg_cp, &mips_fw->cp);
3875
3876 init_cpu_err:
3877 return rc;
3878 }
3879
3880 static int
3881 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3882 {
3883 u16 pmcsr;
3884
3885 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3886
3887 switch (state) {
3888 case PCI_D0: {
3889 u32 val;
3890
3891 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3892 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3893 PCI_PM_CTRL_PME_STATUS);
3894
3895 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3896 /* delay required during transition out of D3hot */
3897 msleep(20);
3898
3899 val = REG_RD(bp, BNX2_EMAC_MODE);
3900 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3901 val &= ~BNX2_EMAC_MODE_MPKT;
3902 REG_WR(bp, BNX2_EMAC_MODE, val);
3903
3904 val = REG_RD(bp, BNX2_RPM_CONFIG);
3905 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3906 REG_WR(bp, BNX2_RPM_CONFIG, val);
3907 break;
3908 }
3909 case PCI_D3hot: {
3910 int i;
3911 u32 val, wol_msg;
3912
3913 if (bp->wol) {
3914 u32 advertising;
3915 u8 autoneg;
3916
3917 autoneg = bp->autoneg;
3918 advertising = bp->advertising;
3919
3920 if (bp->phy_port == PORT_TP) {
3921 bp->autoneg = AUTONEG_SPEED;
3922 bp->advertising = ADVERTISED_10baseT_Half |
3923 ADVERTISED_10baseT_Full |
3924 ADVERTISED_100baseT_Half |
3925 ADVERTISED_100baseT_Full |
3926 ADVERTISED_Autoneg;
3927 }
3928
3929 spin_lock_bh(&bp->phy_lock);
3930 bnx2_setup_phy(bp, bp->phy_port);
3931 spin_unlock_bh(&bp->phy_lock);
3932
3933 bp->autoneg = autoneg;
3934 bp->advertising = advertising;
3935
3936 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3937
3938 val = REG_RD(bp, BNX2_EMAC_MODE);
3939
3940 /* Enable port mode. */
3941 val &= ~BNX2_EMAC_MODE_PORT;
3942 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3943 BNX2_EMAC_MODE_ACPI_RCVD |
3944 BNX2_EMAC_MODE_MPKT;
3945 if (bp->phy_port == PORT_TP)
3946 val |= BNX2_EMAC_MODE_PORT_MII;
3947 else {
3948 val |= BNX2_EMAC_MODE_PORT_GMII;
3949 if (bp->line_speed == SPEED_2500)
3950 val |= BNX2_EMAC_MODE_25G_MODE;
3951 }
3952
3953 REG_WR(bp, BNX2_EMAC_MODE, val);
3954
3955 /* receive all multicast */
3956 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3957 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3958 0xffffffff);
3959 }
3960 REG_WR(bp, BNX2_EMAC_RX_MODE,
3961 BNX2_EMAC_RX_MODE_SORT_MODE);
3962
3963 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3964 BNX2_RPM_SORT_USER0_MC_EN;
3965 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3966 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3967 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3968 BNX2_RPM_SORT_USER0_ENA);
3969
3970 /* Need to enable EMAC and RPM for WOL. */
3971 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3972 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3973 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3974 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3975
3976 val = REG_RD(bp, BNX2_RPM_CONFIG);
3977 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3978 REG_WR(bp, BNX2_RPM_CONFIG, val);
3979
3980 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3981 }
3982 else {
3983 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3984 }
3985
3986 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3987 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3988 1, 0);
3989
3990 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3991 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3992 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3993
3994 if (bp->wol)
3995 pmcsr |= 3;
3996 }
3997 else {
3998 pmcsr |= 3;
3999 }
4000 if (bp->wol) {
4001 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
4002 }
4003 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
4004 pmcsr);
4005
4006 /* No more memory access after this point until
4007 * device is brought back to D0.
4008 */
4009 udelay(50);
4010 break;
4011 }
4012 default:
4013 return -EINVAL;
4014 }
4015 return 0;
4016 }
4017
4018 static int
4019 bnx2_acquire_nvram_lock(struct bnx2 *bp)
4020 {
4021 u32 val;
4022 int j;
4023
4024 /* Request access to the flash interface. */
4025 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
4026 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4027 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4028 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
4029 break;
4030
4031 udelay(5);
4032 }
4033
4034 if (j >= NVRAM_TIMEOUT_COUNT)
4035 return -EBUSY;
4036
4037 return 0;
4038 }
4039
4040 static int
4041 bnx2_release_nvram_lock(struct bnx2 *bp)
4042 {
4043 int j;
4044 u32 val;
4045
4046 /* Relinquish nvram interface. */
4047 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
4048
4049 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4050 val = REG_RD(bp, BNX2_NVM_SW_ARB);
4051 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
4052 break;
4053
4054 udelay(5);
4055 }
4056
4057 if (j >= NVRAM_TIMEOUT_COUNT)
4058 return -EBUSY;
4059
4060 return 0;
4061 }
4062
4063
4064 static int
4065 bnx2_enable_nvram_write(struct bnx2 *bp)
4066 {
4067 u32 val;
4068
4069 val = REG_RD(bp, BNX2_MISC_CFG);
4070 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
4071
4072 if (bp->flash_info->flags & BNX2_NV_WREN) {
4073 int j;
4074
4075 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4076 REG_WR(bp, BNX2_NVM_COMMAND,
4077 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
4078
4079 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4080 udelay(5);
4081
4082 val = REG_RD(bp, BNX2_NVM_COMMAND);
4083 if (val & BNX2_NVM_COMMAND_DONE)
4084 break;
4085 }
4086
4087 if (j >= NVRAM_TIMEOUT_COUNT)
4088 return -EBUSY;
4089 }
4090 return 0;
4091 }
4092
4093 static void
4094 bnx2_disable_nvram_write(struct bnx2 *bp)
4095 {
4096 u32 val;
4097
4098 val = REG_RD(bp, BNX2_MISC_CFG);
4099 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
4100 }
4101
4102
4103 static void
4104 bnx2_enable_nvram_access(struct bnx2 *bp)
4105 {
4106 u32 val;
4107
4108 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4109 /* Enable both bits, even on read. */
4110 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4111 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
4112 }
4113
4114 static void
4115 bnx2_disable_nvram_access(struct bnx2 *bp)
4116 {
4117 u32 val;
4118
4119 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
4120 /* Disable both bits, even after read. */
4121 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
4122 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
4123 BNX2_NVM_ACCESS_ENABLE_WR_EN));
4124 }
4125
4126 static int
4127 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
4128 {
4129 u32 cmd;
4130 int j;
4131
4132 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
4133 /* Buffered flash, no erase needed */
4134 return 0;
4135
4136 /* Build an erase command */
4137 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
4138 BNX2_NVM_COMMAND_DOIT;
4139
4140 /* Need to clear DONE bit separately. */
4141 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4142
4143 /* Address of the NVRAM to read from. */
4144 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4145
4146 /* Issue an erase command. */
4147 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4148
4149 /* Wait for completion. */
4150 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4151 u32 val;
4152
4153 udelay(5);
4154
4155 val = REG_RD(bp, BNX2_NVM_COMMAND);
4156 if (val & BNX2_NVM_COMMAND_DONE)
4157 break;
4158 }
4159
4160 if (j >= NVRAM_TIMEOUT_COUNT)
4161 return -EBUSY;
4162
4163 return 0;
4164 }
4165
4166 static int
4167 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
4168 {
4169 u32 cmd;
4170 int j;
4171
4172 /* Build the command word. */
4173 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
4174
4175 /* Calculate an offset of a buffered flash, not needed for 5709. */
4176 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4177 offset = ((offset / bp->flash_info->page_size) <<
4178 bp->flash_info->page_bits) +
4179 (offset % bp->flash_info->page_size);
4180 }
4181
4182 /* Need to clear DONE bit separately. */
4183 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4184
4185 /* Address of the NVRAM to read from. */
4186 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4187
4188 /* Issue a read command. */
4189 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4190
4191 /* Wait for completion. */
4192 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4193 u32 val;
4194
4195 udelay(5);
4196
4197 val = REG_RD(bp, BNX2_NVM_COMMAND);
4198 if (val & BNX2_NVM_COMMAND_DONE) {
4199 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
4200 memcpy(ret_val, &v, 4);
4201 break;
4202 }
4203 }
4204 if (j >= NVRAM_TIMEOUT_COUNT)
4205 return -EBUSY;
4206
4207 return 0;
4208 }
4209
4210
4211 static int
4212 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
4213 {
4214 u32 cmd;
4215 __be32 val32;
4216 int j;
4217
4218 /* Build the command word. */
4219 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
4220
4221 /* Calculate an offset of a buffered flash, not needed for 5709. */
4222 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
4223 offset = ((offset / bp->flash_info->page_size) <<
4224 bp->flash_info->page_bits) +
4225 (offset % bp->flash_info->page_size);
4226 }
4227
4228 /* Need to clear DONE bit separately. */
4229 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
4230
4231 memcpy(&val32, val, 4);
4232
4233 /* Write the data. */
4234 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
4235
4236 /* Address of the NVRAM to write to. */
4237 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
4238
4239 /* Issue the write command. */
4240 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
4241
4242 /* Wait for completion. */
4243 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
4244 udelay(5);
4245
4246 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
4247 break;
4248 }
4249 if (j >= NVRAM_TIMEOUT_COUNT)
4250 return -EBUSY;
4251
4252 return 0;
4253 }
4254
4255 static int
4256 bnx2_init_nvram(struct bnx2 *bp)
4257 {
4258 u32 val;
4259 int j, entry_count, rc = 0;
4260 const struct flash_spec *flash;
4261
4262 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4263 bp->flash_info = &flash_5709;
4264 goto get_flash_size;
4265 }
4266
4267 /* Determine the selected interface. */
4268 val = REG_RD(bp, BNX2_NVM_CFG1);
4269
4270 entry_count = ARRAY_SIZE(flash_table);
4271
4272 if (val & 0x40000000) {
4273
4274 /* Flash interface has been reconfigured */
4275 for (j = 0, flash = &flash_table[0]; j < entry_count;
4276 j++, flash++) {
4277 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4278 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4279 bp->flash_info = flash;
4280 break;
4281 }
4282 }
4283 }
4284 else {
4285 u32 mask;
4286 /* Not yet been reconfigured */
4287
4288 if (val & (1 << 23))
4289 mask = FLASH_BACKUP_STRAP_MASK;
4290 else
4291 mask = FLASH_STRAP_MASK;
4292
4293 for (j = 0, flash = &flash_table[0]; j < entry_count;
4294 j++, flash++) {
4295
4296 if ((val & mask) == (flash->strapping & mask)) {
4297 bp->flash_info = flash;
4298
4299 /* Request access to the flash interface. */
4300 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4301 return rc;
4302
4303 /* Enable access to flash interface */
4304 bnx2_enable_nvram_access(bp);
4305
4306 /* Reconfigure the flash interface */
4307 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4308 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4309 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4310 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4311
4312 /* Disable access to flash interface */
4313 bnx2_disable_nvram_access(bp);
4314 bnx2_release_nvram_lock(bp);
4315
4316 break;
4317 }
4318 }
4319 } /* if (val & 0x40000000) */
4320
4321 if (j == entry_count) {
4322 bp->flash_info = NULL;
4323 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4324 return -ENODEV;
4325 }
4326
4327 get_flash_size:
4328 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4329 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4330 if (val)
4331 bp->flash_size = val;
4332 else
4333 bp->flash_size = bp->flash_info->total_size;
4334
4335 return rc;
4336 }
4337
4338 static int
4339 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4340 int buf_size)
4341 {
4342 int rc = 0;
4343 u32 cmd_flags, offset32, len32, extra;
4344
4345 if (buf_size == 0)
4346 return 0;
4347
4348 /* Request access to the flash interface. */
4349 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4350 return rc;
4351
4352 /* Enable access to flash interface */
4353 bnx2_enable_nvram_access(bp);
4354
4355 len32 = buf_size;
4356 offset32 = offset;
4357 extra = 0;
4358
4359 cmd_flags = 0;
4360
4361 if (offset32 & 3) {
4362 u8 buf[4];
4363 u32 pre_len;
4364
4365 offset32 &= ~3;
4366 pre_len = 4 - (offset & 3);
4367
4368 if (pre_len >= len32) {
4369 pre_len = len32;
4370 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4371 BNX2_NVM_COMMAND_LAST;
4372 }
4373 else {
4374 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4375 }
4376
4377 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4378
4379 if (rc)
4380 return rc;
4381
4382 memcpy(ret_buf, buf + (offset & 3), pre_len);
4383
4384 offset32 += 4;
4385 ret_buf += pre_len;
4386 len32 -= pre_len;
4387 }
4388 if (len32 & 3) {
4389 extra = 4 - (len32 & 3);
4390 len32 = (len32 + 4) & ~3;
4391 }
4392
4393 if (len32 == 4) {
4394 u8 buf[4];
4395
4396 if (cmd_flags)
4397 cmd_flags = BNX2_NVM_COMMAND_LAST;
4398 else
4399 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4400 BNX2_NVM_COMMAND_LAST;
4401
4402 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4403
4404 memcpy(ret_buf, buf, 4 - extra);
4405 }
4406 else if (len32 > 0) {
4407 u8 buf[4];
4408
4409 /* Read the first word. */
4410 if (cmd_flags)
4411 cmd_flags = 0;
4412 else
4413 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4414
4415 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4416
4417 /* Advance to the next dword. */
4418 offset32 += 4;
4419 ret_buf += 4;
4420 len32 -= 4;
4421
4422 while (len32 > 4 && rc == 0) {
4423 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4424
4425 /* Advance to the next dword. */
4426 offset32 += 4;
4427 ret_buf += 4;
4428 len32 -= 4;
4429 }
4430
4431 if (rc)
4432 return rc;
4433
4434 cmd_flags = BNX2_NVM_COMMAND_LAST;
4435 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4436
4437 memcpy(ret_buf, buf, 4 - extra);
4438 }
4439
4440 /* Disable access to flash interface */
4441 bnx2_disable_nvram_access(bp);
4442
4443 bnx2_release_nvram_lock(bp);
4444
4445 return rc;
4446 }
4447
4448 static int
4449 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4450 int buf_size)
4451 {
4452 u32 written, offset32, len32;
4453 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4454 int rc = 0;
4455 int align_start, align_end;
4456
4457 buf = data_buf;
4458 offset32 = offset;
4459 len32 = buf_size;
4460 align_start = align_end = 0;
4461
4462 if ((align_start = (offset32 & 3))) {
4463 offset32 &= ~3;
4464 len32 += align_start;
4465 if (len32 < 4)
4466 len32 = 4;
4467 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4468 return rc;
4469 }
4470
4471 if (len32 & 3) {
4472 align_end = 4 - (len32 & 3);
4473 len32 += align_end;
4474 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4475 return rc;
4476 }
4477
4478 if (align_start || align_end) {
4479 align_buf = kmalloc(len32, GFP_KERNEL);
4480 if (align_buf == NULL)
4481 return -ENOMEM;
4482 if (align_start) {
4483 memcpy(align_buf, start, 4);
4484 }
4485 if (align_end) {
4486 memcpy(align_buf + len32 - 4, end, 4);
4487 }
4488 memcpy(align_buf + align_start, data_buf, buf_size);
4489 buf = align_buf;
4490 }
4491
4492 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4493 flash_buffer = kmalloc(264, GFP_KERNEL);
4494 if (flash_buffer == NULL) {
4495 rc = -ENOMEM;
4496 goto nvram_write_end;
4497 }
4498 }
4499
4500 written = 0;
4501 while ((written < len32) && (rc == 0)) {
4502 u32 page_start, page_end, data_start, data_end;
4503 u32 addr, cmd_flags;
4504 int i;
4505
4506 /* Find the page_start addr */
4507 page_start = offset32 + written;
4508 page_start -= (page_start % bp->flash_info->page_size);
4509 /* Find the page_end addr */
4510 page_end = page_start + bp->flash_info->page_size;
4511 /* Find the data_start addr */
4512 data_start = (written == 0) ? offset32 : page_start;
4513 /* Find the data_end addr */
4514 data_end = (page_end > offset32 + len32) ?
4515 (offset32 + len32) : page_end;
4516
4517 /* Request access to the flash interface. */
4518 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4519 goto nvram_write_end;
4520
4521 /* Enable access to flash interface */
4522 bnx2_enable_nvram_access(bp);
4523
4524 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4525 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4526 int j;
4527
4528 /* Read the whole page into the buffer
4529 * (non-buffer flash only) */
4530 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4531 if (j == (bp->flash_info->page_size - 4)) {
4532 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4533 }
4534 rc = bnx2_nvram_read_dword(bp,
4535 page_start + j,
4536 &flash_buffer[j],
4537 cmd_flags);
4538
4539 if (rc)
4540 goto nvram_write_end;
4541
4542 cmd_flags = 0;
4543 }
4544 }
4545
4546 /* Enable writes to flash interface (unlock write-protect) */
4547 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4548 goto nvram_write_end;
4549
4550 /* Loop to write back the buffer data from page_start to
4551 * data_start */
4552 i = 0;
4553 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4554 /* Erase the page */
4555 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4556 goto nvram_write_end;
4557
4558 /* Re-enable the write again for the actual write */
4559 bnx2_enable_nvram_write(bp);
4560
4561 for (addr = page_start; addr < data_start;
4562 addr += 4, i += 4) {
4563
4564 rc = bnx2_nvram_write_dword(bp, addr,
4565 &flash_buffer[i], cmd_flags);
4566
4567 if (rc != 0)
4568 goto nvram_write_end;
4569
4570 cmd_flags = 0;
4571 }
4572 }
4573
4574 /* Loop to write the new data from data_start to data_end */
4575 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4576 if ((addr == page_end - 4) ||
4577 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4578 (addr == data_end - 4))) {
4579
4580 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4581 }
4582 rc = bnx2_nvram_write_dword(bp, addr, buf,
4583 cmd_flags);
4584
4585 if (rc != 0)
4586 goto nvram_write_end;
4587
4588 cmd_flags = 0;
4589 buf += 4;
4590 }
4591
4592 /* Loop to write back the buffer data from data_end
4593 * to page_end */
4594 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4595 for (addr = data_end; addr < page_end;
4596 addr += 4, i += 4) {
4597
4598 if (addr == page_end-4) {
4599 cmd_flags = BNX2_NVM_COMMAND_LAST;
4600 }
4601 rc = bnx2_nvram_write_dword(bp, addr,
4602 &flash_buffer[i], cmd_flags);
4603
4604 if (rc != 0)
4605 goto nvram_write_end;
4606
4607 cmd_flags = 0;
4608 }
4609 }
4610
4611 /* Disable writes to flash interface (lock write-protect) */
4612 bnx2_disable_nvram_write(bp);
4613
4614 /* Disable access to flash interface */
4615 bnx2_disable_nvram_access(bp);
4616 bnx2_release_nvram_lock(bp);
4617
4618 /* Increment written */
4619 written += data_end - data_start;
4620 }
4621
4622 nvram_write_end:
4623 kfree(flash_buffer);
4624 kfree(align_buf);
4625 return rc;
4626 }
4627
4628 static void
4629 bnx2_init_fw_cap(struct bnx2 *bp)
4630 {
4631 u32 val, sig = 0;
4632
4633 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4634 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4635
4636 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4637 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4638
4639 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4640 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4641 return;
4642
4643 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4644 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4645 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4646 }
4647
4648 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4649 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4650 u32 link;
4651
4652 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4653
4654 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4655 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4656 bp->phy_port = PORT_FIBRE;
4657 else
4658 bp->phy_port = PORT_TP;
4659
4660 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4661 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4662 }
4663
4664 if (netif_running(bp->dev) && sig)
4665 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4666 }
4667
4668 static void
4669 bnx2_setup_msix_tbl(struct bnx2 *bp)
4670 {
4671 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4672
4673 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4674 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4675 }
4676
4677 static int
4678 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4679 {
4680 u32 val;
4681 int i, rc = 0;
4682 u8 old_port;
4683
4684 /* Wait for the current PCI transaction to complete before
4685 * issuing a reset. */
4686 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4687 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4688 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4689 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4690 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4691 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4692 udelay(5);
4693
4694 /* Wait for the firmware to tell us it is ok to issue a reset. */
4695 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4696
4697 /* Deposit a driver reset signature so the firmware knows that
4698 * this is a soft reset. */
4699 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4700 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4701
4702 /* Do a dummy read to force the chip to complete all current transaction
4703 * before we issue a reset. */
4704 val = REG_RD(bp, BNX2_MISC_ID);
4705
4706 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4707 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4708 REG_RD(bp, BNX2_MISC_COMMAND);
4709 udelay(5);
4710
4711 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4712 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4713
4714 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4715
4716 } else {
4717 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4718 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4719 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4720
4721 /* Chip reset. */
4722 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4723
4724 /* Reading back any register after chip reset will hang the
4725 * bus on 5706 A0 and A1. The msleep below provides plenty
4726 * of margin for write posting.
4727 */
4728 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4729 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4730 msleep(20);
4731
4732 /* Reset takes approximate 30 usec */
4733 for (i = 0; i < 10; i++) {
4734 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4735 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4736 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4737 break;
4738 udelay(10);
4739 }
4740
4741 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4742 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4743 printk(KERN_ERR PFX "Chip reset did not complete\n");
4744 return -EBUSY;
4745 }
4746 }
4747
4748 /* Make sure byte swapping is properly configured. */
4749 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4750 if (val != 0x01020304) {
4751 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4752 return -ENODEV;
4753 }
4754
4755 /* Wait for the firmware to finish its initialization. */
4756 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4757 if (rc)
4758 return rc;
4759
4760 spin_lock_bh(&bp->phy_lock);
4761 old_port = bp->phy_port;
4762 bnx2_init_fw_cap(bp);
4763 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4764 old_port != bp->phy_port)
4765 bnx2_set_default_remote_link(bp);
4766 spin_unlock_bh(&bp->phy_lock);
4767
4768 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4769 /* Adjust the voltage regular to two steps lower. The default
4770 * of this register is 0x0000000e. */
4771 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4772
4773 /* Remove bad rbuf memory from the free pool. */
4774 rc = bnx2_alloc_bad_rbuf(bp);
4775 }
4776
4777 if (bp->flags & BNX2_FLAG_USING_MSIX) {
4778 bnx2_setup_msix_tbl(bp);
4779 /* Prevent MSIX table reads and write from timing out */
4780 REG_WR(bp, BNX2_MISC_ECO_HW_CTL,
4781 BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN);
4782 }
4783
4784 return rc;
4785 }
4786
4787 static int
4788 bnx2_init_chip(struct bnx2 *bp)
4789 {
4790 u32 val, mtu;
4791 int rc, i;
4792
4793 /* Make sure the interrupt is not active. */
4794 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4795
4796 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4797 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4798 #ifdef __BIG_ENDIAN
4799 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4800 #endif
4801 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4802 DMA_READ_CHANS << 12 |
4803 DMA_WRITE_CHANS << 16;
4804
4805 val |= (0x2 << 20) | (1 << 11);
4806
4807 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4808 val |= (1 << 23);
4809
4810 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4811 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4812 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4813
4814 REG_WR(bp, BNX2_DMA_CONFIG, val);
4815
4816 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4817 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4818 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4819 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4820 }
4821
4822 if (bp->flags & BNX2_FLAG_PCIX) {
4823 u16 val16;
4824
4825 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4826 &val16);
4827 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4828 val16 & ~PCI_X_CMD_ERO);
4829 }
4830
4831 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4832 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4833 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4834 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4835
4836 /* Initialize context mapping and zero out the quick contexts. The
4837 * context block must have already been enabled. */
4838 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4839 rc = bnx2_init_5709_context(bp);
4840 if (rc)
4841 return rc;
4842 } else
4843 bnx2_init_context(bp);
4844
4845 if ((rc = bnx2_init_cpus(bp)) != 0)
4846 return rc;
4847
4848 bnx2_init_nvram(bp);
4849
4850 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4851
4852 val = REG_RD(bp, BNX2_MQ_CONFIG);
4853 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4854 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4855 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4856 val |= BNX2_MQ_CONFIG_BIN_MQ_MODE;
4857 if (CHIP_REV(bp) == CHIP_REV_Ax)
4858 val |= BNX2_MQ_CONFIG_HALT_DIS;
4859 }
4860
4861 REG_WR(bp, BNX2_MQ_CONFIG, val);
4862
4863 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4864 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4865 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4866
4867 val = (BCM_PAGE_BITS - 8) << 24;
4868 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4869
4870 /* Configure page size. */
4871 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4872 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4873 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4874 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4875
4876 val = bp->mac_addr[0] +
4877 (bp->mac_addr[1] << 8) +
4878 (bp->mac_addr[2] << 16) +
4879 bp->mac_addr[3] +
4880 (bp->mac_addr[4] << 8) +
4881 (bp->mac_addr[5] << 16);
4882 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4883
4884 /* Program the MTU. Also include 4 bytes for CRC32. */
4885 mtu = bp->dev->mtu;
4886 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4887 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4888 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4889 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4890
4891 if (mtu < 1500)
4892 mtu = 1500;
4893
4894 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4895 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4896 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4897
4898 memset(bp->bnx2_napi[0].status_blk.msi, 0, bp->status_stats_size);
4899 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4900 bp->bnx2_napi[i].last_status_idx = 0;
4901
4902 bp->idle_chk_status_idx = 0xffff;
4903
4904 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4905
4906 /* Set up how to generate a link change interrupt. */
4907 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4908
4909 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4910 (u64) bp->status_blk_mapping & 0xffffffff);
4911 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4912
4913 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4914 (u64) bp->stats_blk_mapping & 0xffffffff);
4915 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4916 (u64) bp->stats_blk_mapping >> 32);
4917
4918 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4919 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4920
4921 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4922 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4923
4924 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4925 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4926
4927 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4928
4929 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4930
4931 REG_WR(bp, BNX2_HC_COM_TICKS,
4932 (bp->com_ticks_int << 16) | bp->com_ticks);
4933
4934 REG_WR(bp, BNX2_HC_CMD_TICKS,
4935 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4936
4937 if (bp->flags & BNX2_FLAG_BROKEN_STATS)
4938 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4939 else
4940 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4941 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4942
4943 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4944 val = BNX2_HC_CONFIG_COLLECT_STATS;
4945 else {
4946 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4947 BNX2_HC_CONFIG_COLLECT_STATS;
4948 }
4949
4950 if (bp->irq_nvecs > 1) {
4951 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4952 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4953
4954 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4955 }
4956
4957 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4958 val |= BNX2_HC_CONFIG_ONE_SHOT | BNX2_HC_CONFIG_USE_INT_PARAM;
4959
4960 REG_WR(bp, BNX2_HC_CONFIG, val);
4961
4962 for (i = 1; i < bp->irq_nvecs; i++) {
4963 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4964 BNX2_HC_SB_CONFIG_1;
4965
4966 REG_WR(bp, base,
4967 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4968 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4969 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4970
4971 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4972 (bp->tx_quick_cons_trip_int << 16) |
4973 bp->tx_quick_cons_trip);
4974
4975 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4976 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4977
4978 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4979 (bp->rx_quick_cons_trip_int << 16) |
4980 bp->rx_quick_cons_trip);
4981
4982 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4983 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4984 }
4985
4986 /* Clear internal stats counters. */
4987 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4988
4989 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4990
4991 /* Initialize the receive filter. */
4992 bnx2_set_rx_mode(bp->dev);
4993
4994 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4995 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4996 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4997 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4998 }
4999 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
5000 1, 0);
5001
5002 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
5003 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
5004
5005 udelay(20);
5006
5007 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
5008
5009 return rc;
5010 }
5011
5012 static void
5013 bnx2_clear_ring_states(struct bnx2 *bp)
5014 {
5015 struct bnx2_napi *bnapi;
5016 struct bnx2_tx_ring_info *txr;
5017 struct bnx2_rx_ring_info *rxr;
5018 int i;
5019
5020 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5021 bnapi = &bp->bnx2_napi[i];
5022 txr = &bnapi->tx_ring;
5023 rxr = &bnapi->rx_ring;
5024
5025 txr->tx_cons = 0;
5026 txr->hw_tx_cons = 0;
5027 rxr->rx_prod_bseq = 0;
5028 rxr->rx_prod = 0;
5029 rxr->rx_cons = 0;
5030 rxr->rx_pg_prod = 0;
5031 rxr->rx_pg_cons = 0;
5032 }
5033 }
5034
5035 static void
5036 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
5037 {
5038 u32 val, offset0, offset1, offset2, offset3;
5039 u32 cid_addr = GET_CID_ADDR(cid);
5040
5041 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5042 offset0 = BNX2_L2CTX_TYPE_XI;
5043 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
5044 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
5045 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
5046 } else {
5047 offset0 = BNX2_L2CTX_TYPE;
5048 offset1 = BNX2_L2CTX_CMD_TYPE;
5049 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
5050 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
5051 }
5052 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
5053 bnx2_ctx_wr(bp, cid_addr, offset0, val);
5054
5055 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5056 bnx2_ctx_wr(bp, cid_addr, offset1, val);
5057
5058 val = (u64) txr->tx_desc_mapping >> 32;
5059 bnx2_ctx_wr(bp, cid_addr, offset2, val);
5060
5061 val = (u64) txr->tx_desc_mapping & 0xffffffff;
5062 bnx2_ctx_wr(bp, cid_addr, offset3, val);
5063 }
5064
5065 static void
5066 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
5067 {
5068 struct tx_bd *txbd;
5069 u32 cid = TX_CID;
5070 struct bnx2_napi *bnapi;
5071 struct bnx2_tx_ring_info *txr;
5072
5073 bnapi = &bp->bnx2_napi[ring_num];
5074 txr = &bnapi->tx_ring;
5075
5076 if (ring_num == 0)
5077 cid = TX_CID;
5078 else
5079 cid = TX_TSS_CID + ring_num - 1;
5080
5081 bp->tx_wake_thresh = bp->tx_ring_size / 2;
5082
5083 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
5084
5085 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
5086 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
5087
5088 txr->tx_prod = 0;
5089 txr->tx_prod_bseq = 0;
5090
5091 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
5092 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
5093
5094 bnx2_init_tx_context(bp, cid, txr);
5095 }
5096
5097 static void
5098 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
5099 int num_rings)
5100 {
5101 int i;
5102 struct rx_bd *rxbd;
5103
5104 for (i = 0; i < num_rings; i++) {
5105 int j;
5106
5107 rxbd = &rx_ring[i][0];
5108 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
5109 rxbd->rx_bd_len = buf_size;
5110 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
5111 }
5112 if (i == (num_rings - 1))
5113 j = 0;
5114 else
5115 j = i + 1;
5116 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
5117 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
5118 }
5119 }
5120
5121 static void
5122 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
5123 {
5124 int i;
5125 u16 prod, ring_prod;
5126 u32 cid, rx_cid_addr, val;
5127 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
5128 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5129
5130 if (ring_num == 0)
5131 cid = RX_CID;
5132 else
5133 cid = RX_RSS_CID + ring_num - 1;
5134
5135 rx_cid_addr = GET_CID_ADDR(cid);
5136
5137 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
5138 bp->rx_buf_use_size, bp->rx_max_ring);
5139
5140 bnx2_init_rx_context(bp, cid);
5141
5142 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5143 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
5144 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
5145 }
5146
5147 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
5148 if (bp->rx_pg_ring_size) {
5149 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
5150 rxr->rx_pg_desc_mapping,
5151 PAGE_SIZE, bp->rx_max_pg_ring);
5152 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
5153 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
5154 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
5155 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
5156
5157 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
5158 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
5159
5160 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
5161 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
5162
5163 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5164 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
5165 }
5166
5167 val = (u64) rxr->rx_desc_mapping[0] >> 32;
5168 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
5169
5170 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
5171 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
5172
5173 ring_prod = prod = rxr->rx_pg_prod;
5174 for (i = 0; i < bp->rx_pg_ring_size; i++) {
5175 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0) {
5176 printk(KERN_WARNING PFX "%s: init'ed rx page ring %d "
5177 "with %d/%d pages only\n",
5178 bp->dev->name, ring_num, i, bp->rx_pg_ring_size);
5179 break;
5180 }
5181 prod = NEXT_RX_BD(prod);
5182 ring_prod = RX_PG_RING_IDX(prod);
5183 }
5184 rxr->rx_pg_prod = prod;
5185
5186 ring_prod = prod = rxr->rx_prod;
5187 for (i = 0; i < bp->rx_ring_size; i++) {
5188 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0) {
5189 printk(KERN_WARNING PFX "%s: init'ed rx ring %d with "
5190 "%d/%d skbs only\n",
5191 bp->dev->name, ring_num, i, bp->rx_ring_size);
5192 break;
5193 }
5194 prod = NEXT_RX_BD(prod);
5195 ring_prod = RX_RING_IDX(prod);
5196 }
5197 rxr->rx_prod = prod;
5198
5199 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
5200 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
5201 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
5202
5203 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
5204 REG_WR16(bp, rxr->rx_bidx_addr, prod);
5205
5206 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
5207 }
5208
5209 static void
5210 bnx2_init_all_rings(struct bnx2 *bp)
5211 {
5212 int i;
5213 u32 val;
5214
5215 bnx2_clear_ring_states(bp);
5216
5217 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
5218 for (i = 0; i < bp->num_tx_rings; i++)
5219 bnx2_init_tx_ring(bp, i);
5220
5221 if (bp->num_tx_rings > 1)
5222 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
5223 (TX_TSS_CID << 7));
5224
5225 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
5226 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
5227
5228 for (i = 0; i < bp->num_rx_rings; i++)
5229 bnx2_init_rx_ring(bp, i);
5230
5231 if (bp->num_rx_rings > 1) {
5232 u32 tbl_32;
5233 u8 *tbl = (u8 *) &tbl_32;
5234
5235 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
5236 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
5237
5238 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
5239 tbl[i % 4] = i % (bp->num_rx_rings - 1);
5240 if ((i % 4) == 3)
5241 bnx2_reg_wr_ind(bp,
5242 BNX2_RXP_SCRATCH_RSS_TBL + i,
5243 cpu_to_be32(tbl_32));
5244 }
5245
5246 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
5247 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
5248
5249 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
5250
5251 }
5252 }
5253
5254 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
5255 {
5256 u32 max, num_rings = 1;
5257
5258 while (ring_size > MAX_RX_DESC_CNT) {
5259 ring_size -= MAX_RX_DESC_CNT;
5260 num_rings++;
5261 }
5262 /* round to next power of 2 */
5263 max = max_size;
5264 while ((max & num_rings) == 0)
5265 max >>= 1;
5266
5267 if (num_rings != max)
5268 max <<= 1;
5269
5270 return max;
5271 }
5272
5273 static void
5274 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
5275 {
5276 u32 rx_size, rx_space, jumbo_size;
5277
5278 /* 8 for CRC and VLAN */
5279 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
5280
5281 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
5282 sizeof(struct skb_shared_info);
5283
5284 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
5285 bp->rx_pg_ring_size = 0;
5286 bp->rx_max_pg_ring = 0;
5287 bp->rx_max_pg_ring_idx = 0;
5288 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
5289 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
5290
5291 jumbo_size = size * pages;
5292 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
5293 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5294
5295 bp->rx_pg_ring_size = jumbo_size;
5296 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5297 MAX_RX_PG_RINGS);
5298 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5299 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5300 bp->rx_copy_thresh = 0;
5301 }
5302
5303 bp->rx_buf_use_size = rx_size;
5304 /* hw alignment */
5305 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5306 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5307 bp->rx_ring_size = size;
5308 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5309 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5310 }
5311
5312 static void
5313 bnx2_free_tx_skbs(struct bnx2 *bp)
5314 {
5315 int i;
5316
5317 for (i = 0; i < bp->num_tx_rings; i++) {
5318 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5319 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5320 int j;
5321
5322 if (txr->tx_buf_ring == NULL)
5323 continue;
5324
5325 for (j = 0; j < TX_DESC_CNT; ) {
5326 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5327 struct sk_buff *skb = tx_buf->skb;
5328 int k, last;
5329
5330 if (skb == NULL) {
5331 j++;
5332 continue;
5333 }
5334
5335 pci_unmap_single(bp->pdev,
5336 pci_unmap_addr(tx_buf, mapping),
5337 skb_headlen(skb),
5338 PCI_DMA_TODEVICE);
5339
5340 tx_buf->skb = NULL;
5341
5342 last = tx_buf->nr_frags;
5343 j++;
5344 for (k = 0; k < last; k++, j++) {
5345 tx_buf = &txr->tx_buf_ring[TX_RING_IDX(j)];
5346 pci_unmap_page(bp->pdev,
5347 pci_unmap_addr(tx_buf, mapping),
5348 skb_shinfo(skb)->frags[k].size,
5349 PCI_DMA_TODEVICE);
5350 }
5351 dev_kfree_skb(skb);
5352 }
5353 }
5354 }
5355
5356 static void
5357 bnx2_free_rx_skbs(struct bnx2 *bp)
5358 {
5359 int i;
5360
5361 for (i = 0; i < bp->num_rx_rings; i++) {
5362 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5363 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5364 int j;
5365
5366 if (rxr->rx_buf_ring == NULL)
5367 return;
5368
5369 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5370 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5371 struct sk_buff *skb = rx_buf->skb;
5372
5373 if (skb == NULL)
5374 continue;
5375
5376 pci_unmap_single(bp->pdev,
5377 pci_unmap_addr(rx_buf, mapping),
5378 bp->rx_buf_use_size,
5379 PCI_DMA_FROMDEVICE);
5380
5381 rx_buf->skb = NULL;
5382
5383 dev_kfree_skb(skb);
5384 }
5385 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5386 bnx2_free_rx_page(bp, rxr, j);
5387 }
5388 }
5389
5390 static void
5391 bnx2_free_skbs(struct bnx2 *bp)
5392 {
5393 bnx2_free_tx_skbs(bp);
5394 bnx2_free_rx_skbs(bp);
5395 }
5396
5397 static int
5398 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5399 {
5400 int rc;
5401
5402 rc = bnx2_reset_chip(bp, reset_code);
5403 bnx2_free_skbs(bp);
5404 if (rc)
5405 return rc;
5406
5407 if ((rc = bnx2_init_chip(bp)) != 0)
5408 return rc;
5409
5410 bnx2_init_all_rings(bp);
5411 return 0;
5412 }
5413
5414 static int
5415 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5416 {
5417 int rc;
5418
5419 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5420 return rc;
5421
5422 spin_lock_bh(&bp->phy_lock);
5423 bnx2_init_phy(bp, reset_phy);
5424 bnx2_set_link(bp);
5425 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5426 bnx2_remote_phy_event(bp);
5427 spin_unlock_bh(&bp->phy_lock);
5428 return 0;
5429 }
5430
5431 static int
5432 bnx2_shutdown_chip(struct bnx2 *bp)
5433 {
5434 u32 reset_code;
5435
5436 if (bp->flags & BNX2_FLAG_NO_WOL)
5437 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5438 else if (bp->wol)
5439 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5440 else
5441 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5442
5443 return bnx2_reset_chip(bp, reset_code);
5444 }
5445
5446 static int
5447 bnx2_test_registers(struct bnx2 *bp)
5448 {
5449 int ret;
5450 int i, is_5709;
5451 static const struct {
5452 u16 offset;
5453 u16 flags;
5454 #define BNX2_FL_NOT_5709 1
5455 u32 rw_mask;
5456 u32 ro_mask;
5457 } reg_tbl[] = {
5458 { 0x006c, 0, 0x00000000, 0x0000003f },
5459 { 0x0090, 0, 0xffffffff, 0x00000000 },
5460 { 0x0094, 0, 0x00000000, 0x00000000 },
5461
5462 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5463 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5464 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5465 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5466 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5467 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5468 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5469 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5470 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5471
5472 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5473 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5474 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5475 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5476 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5477 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5478
5479 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5480 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5481 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5482
5483 { 0x1000, 0, 0x00000000, 0x00000001 },
5484 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5485
5486 { 0x1408, 0, 0x01c00800, 0x00000000 },
5487 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5488 { 0x14a8, 0, 0x00000000, 0x000001ff },
5489 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5490 { 0x14b0, 0, 0x00000002, 0x00000001 },
5491 { 0x14b8, 0, 0x00000000, 0x00000000 },
5492 { 0x14c0, 0, 0x00000000, 0x00000009 },
5493 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5494 { 0x14cc, 0, 0x00000000, 0x00000001 },
5495 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5496
5497 { 0x1800, 0, 0x00000000, 0x00000001 },
5498 { 0x1804, 0, 0x00000000, 0x00000003 },
5499
5500 { 0x2800, 0, 0x00000000, 0x00000001 },
5501 { 0x2804, 0, 0x00000000, 0x00003f01 },
5502 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5503 { 0x2810, 0, 0xffff0000, 0x00000000 },
5504 { 0x2814, 0, 0xffff0000, 0x00000000 },
5505 { 0x2818, 0, 0xffff0000, 0x00000000 },
5506 { 0x281c, 0, 0xffff0000, 0x00000000 },
5507 { 0x2834, 0, 0xffffffff, 0x00000000 },
5508 { 0x2840, 0, 0x00000000, 0xffffffff },
5509 { 0x2844, 0, 0x00000000, 0xffffffff },
5510 { 0x2848, 0, 0xffffffff, 0x00000000 },
5511 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5512
5513 { 0x2c00, 0, 0x00000000, 0x00000011 },
5514 { 0x2c04, 0, 0x00000000, 0x00030007 },
5515
5516 { 0x3c00, 0, 0x00000000, 0x00000001 },
5517 { 0x3c04, 0, 0x00000000, 0x00070000 },
5518 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5519 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5520 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5521 { 0x3c14, 0, 0x00000000, 0xffffffff },
5522 { 0x3c18, 0, 0x00000000, 0xffffffff },
5523 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5524 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5525
5526 { 0x5004, 0, 0x00000000, 0x0000007f },
5527 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5528
5529 { 0x5c00, 0, 0x00000000, 0x00000001 },
5530 { 0x5c04, 0, 0x00000000, 0x0003000f },
5531 { 0x5c08, 0, 0x00000003, 0x00000000 },
5532 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5533 { 0x5c10, 0, 0x00000000, 0xffffffff },
5534 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5535 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5536 { 0x5c88, 0, 0x00000000, 0x00077373 },
5537 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5538
5539 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5540 { 0x680c, 0, 0xffffffff, 0x00000000 },
5541 { 0x6810, 0, 0xffffffff, 0x00000000 },
5542 { 0x6814, 0, 0xffffffff, 0x00000000 },
5543 { 0x6818, 0, 0xffffffff, 0x00000000 },
5544 { 0x681c, 0, 0xffffffff, 0x00000000 },
5545 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5546 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5547 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5548 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5549 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5550 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5551 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5552 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5553 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5554 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5555 { 0x684c, 0, 0xffffffff, 0x00000000 },
5556 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5557 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5558 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5559 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5560 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5561 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5562
5563 { 0xffff, 0, 0x00000000, 0x00000000 },
5564 };
5565
5566 ret = 0;
5567 is_5709 = 0;
5568 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5569 is_5709 = 1;
5570
5571 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5572 u32 offset, rw_mask, ro_mask, save_val, val;
5573 u16 flags = reg_tbl[i].flags;
5574
5575 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5576 continue;
5577
5578 offset = (u32) reg_tbl[i].offset;
5579 rw_mask = reg_tbl[i].rw_mask;
5580 ro_mask = reg_tbl[i].ro_mask;
5581
5582 save_val = readl(bp->regview + offset);
5583
5584 writel(0, bp->regview + offset);
5585
5586 val = readl(bp->regview + offset);
5587 if ((val & rw_mask) != 0) {
5588 goto reg_test_err;
5589 }
5590
5591 if ((val & ro_mask) != (save_val & ro_mask)) {
5592 goto reg_test_err;
5593 }
5594
5595 writel(0xffffffff, bp->regview + offset);
5596
5597 val = readl(bp->regview + offset);
5598 if ((val & rw_mask) != rw_mask) {
5599 goto reg_test_err;
5600 }
5601
5602 if ((val & ro_mask) != (save_val & ro_mask)) {
5603 goto reg_test_err;
5604 }
5605
5606 writel(save_val, bp->regview + offset);
5607 continue;
5608
5609 reg_test_err:
5610 writel(save_val, bp->regview + offset);
5611 ret = -ENODEV;
5612 break;
5613 }
5614 return ret;
5615 }
5616
5617 static int
5618 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5619 {
5620 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5621 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5622 int i;
5623
5624 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5625 u32 offset;
5626
5627 for (offset = 0; offset < size; offset += 4) {
5628
5629 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5630
5631 if (bnx2_reg_rd_ind(bp, start + offset) !=
5632 test_pattern[i]) {
5633 return -ENODEV;
5634 }
5635 }
5636 }
5637 return 0;
5638 }
5639
5640 static int
5641 bnx2_test_memory(struct bnx2 *bp)
5642 {
5643 int ret = 0;
5644 int i;
5645 static struct mem_entry {
5646 u32 offset;
5647 u32 len;
5648 } mem_tbl_5706[] = {
5649 { 0x60000, 0x4000 },
5650 { 0xa0000, 0x3000 },
5651 { 0xe0000, 0x4000 },
5652 { 0x120000, 0x4000 },
5653 { 0x1a0000, 0x4000 },
5654 { 0x160000, 0x4000 },
5655 { 0xffffffff, 0 },
5656 },
5657 mem_tbl_5709[] = {
5658 { 0x60000, 0x4000 },
5659 { 0xa0000, 0x3000 },
5660 { 0xe0000, 0x4000 },
5661 { 0x120000, 0x4000 },
5662 { 0x1a0000, 0x4000 },
5663 { 0xffffffff, 0 },
5664 };
5665 struct mem_entry *mem_tbl;
5666
5667 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5668 mem_tbl = mem_tbl_5709;
5669 else
5670 mem_tbl = mem_tbl_5706;
5671
5672 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5673 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5674 mem_tbl[i].len)) != 0) {
5675 return ret;
5676 }
5677 }
5678
5679 return ret;
5680 }
5681
5682 #define BNX2_MAC_LOOPBACK 0
5683 #define BNX2_PHY_LOOPBACK 1
5684
5685 static int
5686 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5687 {
5688 unsigned int pkt_size, num_pkts, i;
5689 struct sk_buff *skb, *rx_skb;
5690 unsigned char *packet;
5691 u16 rx_start_idx, rx_idx;
5692 dma_addr_t map;
5693 struct tx_bd *txbd;
5694 struct sw_bd *rx_buf;
5695 struct l2_fhdr *rx_hdr;
5696 int ret = -ENODEV;
5697 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5698 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5699 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5700
5701 tx_napi = bnapi;
5702
5703 txr = &tx_napi->tx_ring;
5704 rxr = &bnapi->rx_ring;
5705 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5706 bp->loopback = MAC_LOOPBACK;
5707 bnx2_set_mac_loopback(bp);
5708 }
5709 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5710 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5711 return 0;
5712
5713 bp->loopback = PHY_LOOPBACK;
5714 bnx2_set_phy_loopback(bp);
5715 }
5716 else
5717 return -EINVAL;
5718
5719 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5720 skb = netdev_alloc_skb(bp->dev, pkt_size);
5721 if (!skb)
5722 return -ENOMEM;
5723 packet = skb_put(skb, pkt_size);
5724 memcpy(packet, bp->dev->dev_addr, 6);
5725 memset(packet + 6, 0x0, 8);
5726 for (i = 14; i < pkt_size; i++)
5727 packet[i] = (unsigned char) (i & 0xff);
5728
5729 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5730 PCI_DMA_TODEVICE);
5731 if (pci_dma_mapping_error(bp->pdev, map)) {
5732 dev_kfree_skb(skb);
5733 return -EIO;
5734 }
5735
5736 REG_WR(bp, BNX2_HC_COMMAND,
5737 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5738
5739 REG_RD(bp, BNX2_HC_COMMAND);
5740
5741 udelay(5);
5742 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5743
5744 num_pkts = 0;
5745
5746 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5747
5748 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5749 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5750 txbd->tx_bd_mss_nbytes = pkt_size;
5751 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5752
5753 num_pkts++;
5754 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5755 txr->tx_prod_bseq += pkt_size;
5756
5757 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5758 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5759
5760 udelay(100);
5761
5762 REG_WR(bp, BNX2_HC_COMMAND,
5763 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5764
5765 REG_RD(bp, BNX2_HC_COMMAND);
5766
5767 udelay(5);
5768
5769 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5770 dev_kfree_skb(skb);
5771
5772 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5773 goto loopback_test_done;
5774
5775 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5776 if (rx_idx != rx_start_idx + num_pkts) {
5777 goto loopback_test_done;
5778 }
5779
5780 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5781 rx_skb = rx_buf->skb;
5782
5783 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5784 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5785
5786 pci_dma_sync_single_for_cpu(bp->pdev,
5787 pci_unmap_addr(rx_buf, mapping),
5788 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5789
5790 if (rx_hdr->l2_fhdr_status &
5791 (L2_FHDR_ERRORS_BAD_CRC |
5792 L2_FHDR_ERRORS_PHY_DECODE |
5793 L2_FHDR_ERRORS_ALIGNMENT |
5794 L2_FHDR_ERRORS_TOO_SHORT |
5795 L2_FHDR_ERRORS_GIANT_FRAME)) {
5796
5797 goto loopback_test_done;
5798 }
5799
5800 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5801 goto loopback_test_done;
5802 }
5803
5804 for (i = 14; i < pkt_size; i++) {
5805 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5806 goto loopback_test_done;
5807 }
5808 }
5809
5810 ret = 0;
5811
5812 loopback_test_done:
5813 bp->loopback = 0;
5814 return ret;
5815 }
5816
5817 #define BNX2_MAC_LOOPBACK_FAILED 1
5818 #define BNX2_PHY_LOOPBACK_FAILED 2
5819 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5820 BNX2_PHY_LOOPBACK_FAILED)
5821
5822 static int
5823 bnx2_test_loopback(struct bnx2 *bp)
5824 {
5825 int rc = 0;
5826
5827 if (!netif_running(bp->dev))
5828 return BNX2_LOOPBACK_FAILED;
5829
5830 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5831 spin_lock_bh(&bp->phy_lock);
5832 bnx2_init_phy(bp, 1);
5833 spin_unlock_bh(&bp->phy_lock);
5834 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5835 rc |= BNX2_MAC_LOOPBACK_FAILED;
5836 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5837 rc |= BNX2_PHY_LOOPBACK_FAILED;
5838 return rc;
5839 }
5840
5841 #define NVRAM_SIZE 0x200
5842 #define CRC32_RESIDUAL 0xdebb20e3
5843
5844 static int
5845 bnx2_test_nvram(struct bnx2 *bp)
5846 {
5847 __be32 buf[NVRAM_SIZE / 4];
5848 u8 *data = (u8 *) buf;
5849 int rc = 0;
5850 u32 magic, csum;
5851
5852 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5853 goto test_nvram_done;
5854
5855 magic = be32_to_cpu(buf[0]);
5856 if (magic != 0x669955aa) {
5857 rc = -ENODEV;
5858 goto test_nvram_done;
5859 }
5860
5861 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5862 goto test_nvram_done;
5863
5864 csum = ether_crc_le(0x100, data);
5865 if (csum != CRC32_RESIDUAL) {
5866 rc = -ENODEV;
5867 goto test_nvram_done;
5868 }
5869
5870 csum = ether_crc_le(0x100, data + 0x100);
5871 if (csum != CRC32_RESIDUAL) {
5872 rc = -ENODEV;
5873 }
5874
5875 test_nvram_done:
5876 return rc;
5877 }
5878
5879 static int
5880 bnx2_test_link(struct bnx2 *bp)
5881 {
5882 u32 bmsr;
5883
5884 if (!netif_running(bp->dev))
5885 return -ENODEV;
5886
5887 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5888 if (bp->link_up)
5889 return 0;
5890 return -ENODEV;
5891 }
5892 spin_lock_bh(&bp->phy_lock);
5893 bnx2_enable_bmsr1(bp);
5894 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5895 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5896 bnx2_disable_bmsr1(bp);
5897 spin_unlock_bh(&bp->phy_lock);
5898
5899 if (bmsr & BMSR_LSTATUS) {
5900 return 0;
5901 }
5902 return -ENODEV;
5903 }
5904
5905 static int
5906 bnx2_test_intr(struct bnx2 *bp)
5907 {
5908 int i;
5909 u16 status_idx;
5910
5911 if (!netif_running(bp->dev))
5912 return -ENODEV;
5913
5914 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5915
5916 /* This register is not touched during run-time. */
5917 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5918 REG_RD(bp, BNX2_HC_COMMAND);
5919
5920 for (i = 0; i < 10; i++) {
5921 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5922 status_idx) {
5923
5924 break;
5925 }
5926
5927 msleep_interruptible(10);
5928 }
5929 if (i < 10)
5930 return 0;
5931
5932 return -ENODEV;
5933 }
5934
5935 /* Determining link for parallel detection. */
5936 static int
5937 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5938 {
5939 u32 mode_ctl, an_dbg, exp;
5940
5941 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5942 return 0;
5943
5944 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5945 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5946
5947 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5948 return 0;
5949
5950 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5951 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5952 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5953
5954 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5955 return 0;
5956
5957 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5958 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5959 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5960
5961 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5962 return 0;
5963
5964 return 1;
5965 }
5966
5967 static void
5968 bnx2_5706_serdes_timer(struct bnx2 *bp)
5969 {
5970 int check_link = 1;
5971
5972 spin_lock(&bp->phy_lock);
5973 if (bp->serdes_an_pending) {
5974 bp->serdes_an_pending--;
5975 check_link = 0;
5976 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5977 u32 bmcr;
5978
5979 bp->current_interval = BNX2_TIMER_INTERVAL;
5980
5981 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5982
5983 if (bmcr & BMCR_ANENABLE) {
5984 if (bnx2_5706_serdes_has_link(bp)) {
5985 bmcr &= ~BMCR_ANENABLE;
5986 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5987 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5988 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5989 }
5990 }
5991 }
5992 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5993 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5994 u32 phy2;
5995
5996 bnx2_write_phy(bp, 0x17, 0x0f01);
5997 bnx2_read_phy(bp, 0x15, &phy2);
5998 if (phy2 & 0x20) {
5999 u32 bmcr;
6000
6001 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6002 bmcr |= BMCR_ANENABLE;
6003 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
6004
6005 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
6006 }
6007 } else
6008 bp->current_interval = BNX2_TIMER_INTERVAL;
6009
6010 if (check_link) {
6011 u32 val;
6012
6013 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
6014 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6015 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
6016
6017 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
6018 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
6019 bnx2_5706s_force_link_dn(bp, 1);
6020 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
6021 } else
6022 bnx2_set_link(bp);
6023 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
6024 bnx2_set_link(bp);
6025 }
6026 spin_unlock(&bp->phy_lock);
6027 }
6028
6029 static void
6030 bnx2_5708_serdes_timer(struct bnx2 *bp)
6031 {
6032 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
6033 return;
6034
6035 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
6036 bp->serdes_an_pending = 0;
6037 return;
6038 }
6039
6040 spin_lock(&bp->phy_lock);
6041 if (bp->serdes_an_pending)
6042 bp->serdes_an_pending--;
6043 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
6044 u32 bmcr;
6045
6046 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6047 if (bmcr & BMCR_ANENABLE) {
6048 bnx2_enable_forced_2g5(bp);
6049 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
6050 } else {
6051 bnx2_disable_forced_2g5(bp);
6052 bp->serdes_an_pending = 2;
6053 bp->current_interval = BNX2_TIMER_INTERVAL;
6054 }
6055
6056 } else
6057 bp->current_interval = BNX2_TIMER_INTERVAL;
6058
6059 spin_unlock(&bp->phy_lock);
6060 }
6061
6062 static void
6063 bnx2_timer(unsigned long data)
6064 {
6065 struct bnx2 *bp = (struct bnx2 *) data;
6066
6067 if (!netif_running(bp->dev))
6068 return;
6069
6070 if (atomic_read(&bp->intr_sem) != 0)
6071 goto bnx2_restart_timer;
6072
6073 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
6074 BNX2_FLAG_USING_MSI)
6075 bnx2_chk_missed_msi(bp);
6076
6077 bnx2_send_heart_beat(bp);
6078
6079 bp->stats_blk->stat_FwRxDrop =
6080 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
6081
6082 /* workaround occasional corrupted counters */
6083 if ((bp->flags & BNX2_FLAG_BROKEN_STATS) && bp->stats_ticks)
6084 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
6085 BNX2_HC_COMMAND_STATS_NOW);
6086
6087 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6088 if (CHIP_NUM(bp) == CHIP_NUM_5706)
6089 bnx2_5706_serdes_timer(bp);
6090 else
6091 bnx2_5708_serdes_timer(bp);
6092 }
6093
6094 bnx2_restart_timer:
6095 mod_timer(&bp->timer, jiffies + bp->current_interval);
6096 }
6097
6098 static int
6099 bnx2_request_irq(struct bnx2 *bp)
6100 {
6101 unsigned long flags;
6102 struct bnx2_irq *irq;
6103 int rc = 0, i;
6104
6105 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
6106 flags = 0;
6107 else
6108 flags = IRQF_SHARED;
6109
6110 for (i = 0; i < bp->irq_nvecs; i++) {
6111 irq = &bp->irq_tbl[i];
6112 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
6113 &bp->bnx2_napi[i]);
6114 if (rc)
6115 break;
6116 irq->requested = 1;
6117 }
6118 return rc;
6119 }
6120
6121 static void
6122 bnx2_free_irq(struct bnx2 *bp)
6123 {
6124 struct bnx2_irq *irq;
6125 int i;
6126
6127 for (i = 0; i < bp->irq_nvecs; i++) {
6128 irq = &bp->irq_tbl[i];
6129 if (irq->requested)
6130 free_irq(irq->vector, &bp->bnx2_napi[i]);
6131 irq->requested = 0;
6132 }
6133 if (bp->flags & BNX2_FLAG_USING_MSI)
6134 pci_disable_msi(bp->pdev);
6135 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6136 pci_disable_msix(bp->pdev);
6137
6138 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
6139 }
6140
6141 static void
6142 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
6143 {
6144 int i, rc;
6145 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
6146 struct net_device *dev = bp->dev;
6147 const int len = sizeof(bp->irq_tbl[0].name);
6148
6149 bnx2_setup_msix_tbl(bp);
6150 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
6151 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
6152 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
6153
6154 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6155 msix_ent[i].entry = i;
6156 msix_ent[i].vector = 0;
6157 }
6158
6159 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
6160 if (rc != 0)
6161 return;
6162
6163 bp->irq_nvecs = msix_vecs;
6164 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
6165 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
6166 bp->irq_tbl[i].vector = msix_ent[i].vector;
6167 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
6168 bp->irq_tbl[i].handler = bnx2_msi_1shot;
6169 }
6170 }
6171
6172 static void
6173 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
6174 {
6175 int cpus = num_online_cpus();
6176 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
6177
6178 bp->irq_tbl[0].handler = bnx2_interrupt;
6179 strcpy(bp->irq_tbl[0].name, bp->dev->name);
6180 bp->irq_nvecs = 1;
6181 bp->irq_tbl[0].vector = bp->pdev->irq;
6182
6183 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
6184 bnx2_enable_msix(bp, msix_vecs);
6185
6186 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
6187 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
6188 if (pci_enable_msi(bp->pdev) == 0) {
6189 bp->flags |= BNX2_FLAG_USING_MSI;
6190 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6191 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
6192 bp->irq_tbl[0].handler = bnx2_msi_1shot;
6193 } else
6194 bp->irq_tbl[0].handler = bnx2_msi;
6195
6196 bp->irq_tbl[0].vector = bp->pdev->irq;
6197 }
6198 }
6199
6200 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
6201 bp->dev->real_num_tx_queues = bp->num_tx_rings;
6202
6203 bp->num_rx_rings = bp->irq_nvecs;
6204 }
6205
6206 /* Called with rtnl_lock */
6207 static int
6208 bnx2_open(struct net_device *dev)
6209 {
6210 struct bnx2 *bp = netdev_priv(dev);
6211 int rc;
6212
6213 netif_carrier_off(dev);
6214
6215 bnx2_set_power_state(bp, PCI_D0);
6216 bnx2_disable_int(bp);
6217
6218 bnx2_setup_int_mode(bp, disable_msi);
6219 bnx2_init_napi(bp);
6220 bnx2_napi_enable(bp);
6221 rc = bnx2_alloc_mem(bp);
6222 if (rc)
6223 goto open_err;
6224
6225 rc = bnx2_request_irq(bp);
6226 if (rc)
6227 goto open_err;
6228
6229 rc = bnx2_init_nic(bp, 1);
6230 if (rc)
6231 goto open_err;
6232
6233 mod_timer(&bp->timer, jiffies + bp->current_interval);
6234
6235 atomic_set(&bp->intr_sem, 0);
6236
6237 bnx2_enable_int(bp);
6238
6239 if (bp->flags & BNX2_FLAG_USING_MSI) {
6240 /* Test MSI to make sure it is working
6241 * If MSI test fails, go back to INTx mode
6242 */
6243 if (bnx2_test_intr(bp) != 0) {
6244 printk(KERN_WARNING PFX "%s: No interrupt was generated"
6245 " using MSI, switching to INTx mode. Please"
6246 " report this failure to the PCI maintainer"
6247 " and include system chipset information.\n",
6248 bp->dev->name);
6249
6250 bnx2_disable_int(bp);
6251 bnx2_free_irq(bp);
6252
6253 bnx2_setup_int_mode(bp, 1);
6254
6255 rc = bnx2_init_nic(bp, 0);
6256
6257 if (!rc)
6258 rc = bnx2_request_irq(bp);
6259
6260 if (rc) {
6261 del_timer_sync(&bp->timer);
6262 goto open_err;
6263 }
6264 bnx2_enable_int(bp);
6265 }
6266 }
6267 if (bp->flags & BNX2_FLAG_USING_MSI)
6268 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
6269 else if (bp->flags & BNX2_FLAG_USING_MSIX)
6270 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
6271
6272 netif_tx_start_all_queues(dev);
6273
6274 return 0;
6275
6276 open_err:
6277 bnx2_napi_disable(bp);
6278 bnx2_free_skbs(bp);
6279 bnx2_free_irq(bp);
6280 bnx2_free_mem(bp);
6281 return rc;
6282 }
6283
6284 static void
6285 bnx2_reset_task(struct work_struct *work)
6286 {
6287 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
6288
6289 rtnl_lock();
6290 if (!netif_running(bp->dev)) {
6291 rtnl_unlock();
6292 return;
6293 }
6294
6295 bnx2_netif_stop(bp);
6296
6297 bnx2_init_nic(bp, 1);
6298
6299 atomic_set(&bp->intr_sem, 1);
6300 bnx2_netif_start(bp);
6301 rtnl_unlock();
6302 }
6303
6304 static void
6305 bnx2_dump_state(struct bnx2 *bp)
6306 {
6307 struct net_device *dev = bp->dev;
6308
6309 printk(KERN_ERR PFX "%s DEBUG: intr_sem[%x]\n", dev->name,
6310 atomic_read(&bp->intr_sem));
6311 printk(KERN_ERR PFX "%s DEBUG: EMAC_TX_STATUS[%08x] "
6312 "RPM_MGMT_PKT_CTRL[%08x]\n", dev->name,
6313 REG_RD(bp, BNX2_EMAC_TX_STATUS),
6314 REG_RD(bp, BNX2_RPM_MGMT_PKT_CTRL));
6315 printk(KERN_ERR PFX "%s DEBUG: MCP_STATE_P0[%08x] MCP_STATE_P1[%08x]\n",
6316 dev->name, bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P0),
6317 bnx2_reg_rd_ind(bp, BNX2_MCP_STATE_P1));
6318 printk(KERN_ERR PFX "%s DEBUG: HC_STATS_INTERRUPT_STATUS[%08x]\n",
6319 dev->name, REG_RD(bp, BNX2_HC_STATS_INTERRUPT_STATUS));
6320 if (bp->flags & BNX2_FLAG_USING_MSIX)
6321 printk(KERN_ERR PFX "%s DEBUG: PBA[%08x]\n", dev->name,
6322 REG_RD(bp, BNX2_PCI_GRC_WINDOW3_BASE));
6323 }
6324
6325 static void
6326 bnx2_tx_timeout(struct net_device *dev)
6327 {
6328 struct bnx2 *bp = netdev_priv(dev);
6329
6330 bnx2_dump_state(bp);
6331
6332 /* This allows the netif to be shutdown gracefully before resetting */
6333 schedule_work(&bp->reset_task);
6334 }
6335
6336 #ifdef BCM_VLAN
6337 /* Called with rtnl_lock */
6338 static void
6339 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6340 {
6341 struct bnx2 *bp = netdev_priv(dev);
6342
6343 if (netif_running(dev))
6344 bnx2_netif_stop(bp);
6345
6346 bp->vlgrp = vlgrp;
6347
6348 if (!netif_running(dev))
6349 return;
6350
6351 bnx2_set_rx_mode(dev);
6352 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6353 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6354
6355 bnx2_netif_start(bp);
6356 }
6357 #endif
6358
6359 /* Called with netif_tx_lock.
6360 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6361 * netif_wake_queue().
6362 */
6363 static netdev_tx_t
6364 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6365 {
6366 struct bnx2 *bp = netdev_priv(dev);
6367 dma_addr_t mapping;
6368 struct tx_bd *txbd;
6369 struct sw_tx_bd *tx_buf;
6370 u32 len, vlan_tag_flags, last_frag, mss;
6371 u16 prod, ring_prod;
6372 int i;
6373 struct bnx2_napi *bnapi;
6374 struct bnx2_tx_ring_info *txr;
6375 struct netdev_queue *txq;
6376
6377 /* Determine which tx ring we will be placed on */
6378 i = skb_get_queue_mapping(skb);
6379 bnapi = &bp->bnx2_napi[i];
6380 txr = &bnapi->tx_ring;
6381 txq = netdev_get_tx_queue(dev, i);
6382
6383 if (unlikely(bnx2_tx_avail(bp, txr) <
6384 (skb_shinfo(skb)->nr_frags + 1))) {
6385 netif_tx_stop_queue(txq);
6386 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6387 dev->name);
6388
6389 return NETDEV_TX_BUSY;
6390 }
6391 len = skb_headlen(skb);
6392 prod = txr->tx_prod;
6393 ring_prod = TX_RING_IDX(prod);
6394
6395 vlan_tag_flags = 0;
6396 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6397 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6398 }
6399
6400 #ifdef BCM_VLAN
6401 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6402 vlan_tag_flags |=
6403 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6404 }
6405 #endif
6406 if ((mss = skb_shinfo(skb)->gso_size)) {
6407 u32 tcp_opt_len;
6408 struct iphdr *iph;
6409
6410 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6411
6412 tcp_opt_len = tcp_optlen(skb);
6413
6414 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6415 u32 tcp_off = skb_transport_offset(skb) -
6416 sizeof(struct ipv6hdr) - ETH_HLEN;
6417
6418 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6419 TX_BD_FLAGS_SW_FLAGS;
6420 if (likely(tcp_off == 0))
6421 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6422 else {
6423 tcp_off >>= 3;
6424 vlan_tag_flags |= ((tcp_off & 0x3) <<
6425 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6426 ((tcp_off & 0x10) <<
6427 TX_BD_FLAGS_TCP6_OFF4_SHL);
6428 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6429 }
6430 } else {
6431 iph = ip_hdr(skb);
6432 if (tcp_opt_len || (iph->ihl > 5)) {
6433 vlan_tag_flags |= ((iph->ihl - 5) +
6434 (tcp_opt_len >> 2)) << 8;
6435 }
6436 }
6437 } else
6438 mss = 0;
6439
6440 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6441 if (pci_dma_mapping_error(bp->pdev, mapping)) {
6442 dev_kfree_skb(skb);
6443 return NETDEV_TX_OK;
6444 }
6445
6446 tx_buf = &txr->tx_buf_ring[ring_prod];
6447 tx_buf->skb = skb;
6448 pci_unmap_addr_set(tx_buf, mapping, mapping);
6449
6450 txbd = &txr->tx_desc_ring[ring_prod];
6451
6452 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6453 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6454 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6455 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6456
6457 last_frag = skb_shinfo(skb)->nr_frags;
6458 tx_buf->nr_frags = last_frag;
6459 tx_buf->is_gso = skb_is_gso(skb);
6460
6461 for (i = 0; i < last_frag; i++) {
6462 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6463
6464 prod = NEXT_TX_BD(prod);
6465 ring_prod = TX_RING_IDX(prod);
6466 txbd = &txr->tx_desc_ring[ring_prod];
6467
6468 len = frag->size;
6469 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6470 len, PCI_DMA_TODEVICE);
6471 if (pci_dma_mapping_error(bp->pdev, mapping))
6472 goto dma_error;
6473 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod], mapping,
6474 mapping);
6475
6476 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6477 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6478 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6479 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6480
6481 }
6482 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6483
6484 prod = NEXT_TX_BD(prod);
6485 txr->tx_prod_bseq += skb->len;
6486
6487 REG_WR16(bp, txr->tx_bidx_addr, prod);
6488 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6489
6490 mmiowb();
6491
6492 txr->tx_prod = prod;
6493
6494 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6495 netif_tx_stop_queue(txq);
6496 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6497 netif_tx_wake_queue(txq);
6498 }
6499
6500 return NETDEV_TX_OK;
6501 dma_error:
6502 /* save value of frag that failed */
6503 last_frag = i;
6504
6505 /* start back at beginning and unmap skb */
6506 prod = txr->tx_prod;
6507 ring_prod = TX_RING_IDX(prod);
6508 tx_buf = &txr->tx_buf_ring[ring_prod];
6509 tx_buf->skb = NULL;
6510 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6511 skb_headlen(skb), PCI_DMA_TODEVICE);
6512
6513 /* unmap remaining mapped pages */
6514 for (i = 0; i < last_frag; i++) {
6515 prod = NEXT_TX_BD(prod);
6516 ring_prod = TX_RING_IDX(prod);
6517 tx_buf = &txr->tx_buf_ring[ring_prod];
6518 pci_unmap_page(bp->pdev, pci_unmap_addr(tx_buf, mapping),
6519 skb_shinfo(skb)->frags[i].size,
6520 PCI_DMA_TODEVICE);
6521 }
6522
6523 dev_kfree_skb(skb);
6524 return NETDEV_TX_OK;
6525 }
6526
6527 /* Called with rtnl_lock */
6528 static int
6529 bnx2_close(struct net_device *dev)
6530 {
6531 struct bnx2 *bp = netdev_priv(dev);
6532
6533 cancel_work_sync(&bp->reset_task);
6534
6535 bnx2_disable_int_sync(bp);
6536 bnx2_napi_disable(bp);
6537 del_timer_sync(&bp->timer);
6538 bnx2_shutdown_chip(bp);
6539 bnx2_free_irq(bp);
6540 bnx2_free_skbs(bp);
6541 bnx2_free_mem(bp);
6542 bp->link_up = 0;
6543 netif_carrier_off(bp->dev);
6544 bnx2_set_power_state(bp, PCI_D3hot);
6545 return 0;
6546 }
6547
6548 #define GET_NET_STATS64(ctr) \
6549 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6550 (unsigned long) (ctr##_lo)
6551
6552 #define GET_NET_STATS32(ctr) \
6553 (ctr##_lo)
6554
6555 #if (BITS_PER_LONG == 64)
6556 #define GET_NET_STATS GET_NET_STATS64
6557 #else
6558 #define GET_NET_STATS GET_NET_STATS32
6559 #endif
6560
6561 static struct net_device_stats *
6562 bnx2_get_stats(struct net_device *dev)
6563 {
6564 struct bnx2 *bp = netdev_priv(dev);
6565 struct statistics_block *stats_blk = bp->stats_blk;
6566 struct net_device_stats *net_stats = &dev->stats;
6567
6568 if (bp->stats_blk == NULL) {
6569 return net_stats;
6570 }
6571 net_stats->rx_packets =
6572 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6573 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6574 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6575
6576 net_stats->tx_packets =
6577 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6578 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6579 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6580
6581 net_stats->rx_bytes =
6582 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6583
6584 net_stats->tx_bytes =
6585 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6586
6587 net_stats->multicast =
6588 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6589
6590 net_stats->collisions =
6591 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6592
6593 net_stats->rx_length_errors =
6594 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6595 stats_blk->stat_EtherStatsOverrsizePkts);
6596
6597 net_stats->rx_over_errors =
6598 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6599 stats_blk->stat_IfInMBUFDiscards);
6600
6601 net_stats->rx_frame_errors =
6602 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6603
6604 net_stats->rx_crc_errors =
6605 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6606
6607 net_stats->rx_errors = net_stats->rx_length_errors +
6608 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6609 net_stats->rx_crc_errors;
6610
6611 net_stats->tx_aborted_errors =
6612 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6613 stats_blk->stat_Dot3StatsLateCollisions);
6614
6615 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6616 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6617 net_stats->tx_carrier_errors = 0;
6618 else {
6619 net_stats->tx_carrier_errors =
6620 (unsigned long)
6621 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6622 }
6623
6624 net_stats->tx_errors =
6625 (unsigned long)
6626 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6627 +
6628 net_stats->tx_aborted_errors +
6629 net_stats->tx_carrier_errors;
6630
6631 net_stats->rx_missed_errors =
6632 (unsigned long) (stats_blk->stat_IfInFTQDiscards +
6633 stats_blk->stat_IfInMBUFDiscards + stats_blk->stat_FwRxDrop);
6634
6635 return net_stats;
6636 }
6637
6638 /* All ethtool functions called with rtnl_lock */
6639
6640 static int
6641 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6642 {
6643 struct bnx2 *bp = netdev_priv(dev);
6644 int support_serdes = 0, support_copper = 0;
6645
6646 cmd->supported = SUPPORTED_Autoneg;
6647 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6648 support_serdes = 1;
6649 support_copper = 1;
6650 } else if (bp->phy_port == PORT_FIBRE)
6651 support_serdes = 1;
6652 else
6653 support_copper = 1;
6654
6655 if (support_serdes) {
6656 cmd->supported |= SUPPORTED_1000baseT_Full |
6657 SUPPORTED_FIBRE;
6658 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6659 cmd->supported |= SUPPORTED_2500baseX_Full;
6660
6661 }
6662 if (support_copper) {
6663 cmd->supported |= SUPPORTED_10baseT_Half |
6664 SUPPORTED_10baseT_Full |
6665 SUPPORTED_100baseT_Half |
6666 SUPPORTED_100baseT_Full |
6667 SUPPORTED_1000baseT_Full |
6668 SUPPORTED_TP;
6669
6670 }
6671
6672 spin_lock_bh(&bp->phy_lock);
6673 cmd->port = bp->phy_port;
6674 cmd->advertising = bp->advertising;
6675
6676 if (bp->autoneg & AUTONEG_SPEED) {
6677 cmd->autoneg = AUTONEG_ENABLE;
6678 }
6679 else {
6680 cmd->autoneg = AUTONEG_DISABLE;
6681 }
6682
6683 if (netif_carrier_ok(dev)) {
6684 cmd->speed = bp->line_speed;
6685 cmd->duplex = bp->duplex;
6686 }
6687 else {
6688 cmd->speed = -1;
6689 cmd->duplex = -1;
6690 }
6691 spin_unlock_bh(&bp->phy_lock);
6692
6693 cmd->transceiver = XCVR_INTERNAL;
6694 cmd->phy_address = bp->phy_addr;
6695
6696 return 0;
6697 }
6698
6699 static int
6700 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6701 {
6702 struct bnx2 *bp = netdev_priv(dev);
6703 u8 autoneg = bp->autoneg;
6704 u8 req_duplex = bp->req_duplex;
6705 u16 req_line_speed = bp->req_line_speed;
6706 u32 advertising = bp->advertising;
6707 int err = -EINVAL;
6708
6709 spin_lock_bh(&bp->phy_lock);
6710
6711 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6712 goto err_out_unlock;
6713
6714 if (cmd->port != bp->phy_port &&
6715 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6716 goto err_out_unlock;
6717
6718 /* If device is down, we can store the settings only if the user
6719 * is setting the currently active port.
6720 */
6721 if (!netif_running(dev) && cmd->port != bp->phy_port)
6722 goto err_out_unlock;
6723
6724 if (cmd->autoneg == AUTONEG_ENABLE) {
6725 autoneg |= AUTONEG_SPEED;
6726
6727 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6728
6729 /* allow advertising 1 speed */
6730 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6731 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6732 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6733 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6734
6735 if (cmd->port == PORT_FIBRE)
6736 goto err_out_unlock;
6737
6738 advertising = cmd->advertising;
6739
6740 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6741 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6742 (cmd->port == PORT_TP))
6743 goto err_out_unlock;
6744 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6745 advertising = cmd->advertising;
6746 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6747 goto err_out_unlock;
6748 else {
6749 if (cmd->port == PORT_FIBRE)
6750 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6751 else
6752 advertising = ETHTOOL_ALL_COPPER_SPEED;
6753 }
6754 advertising |= ADVERTISED_Autoneg;
6755 }
6756 else {
6757 if (cmd->port == PORT_FIBRE) {
6758 if ((cmd->speed != SPEED_1000 &&
6759 cmd->speed != SPEED_2500) ||
6760 (cmd->duplex != DUPLEX_FULL))
6761 goto err_out_unlock;
6762
6763 if (cmd->speed == SPEED_2500 &&
6764 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6765 goto err_out_unlock;
6766 }
6767 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6768 goto err_out_unlock;
6769
6770 autoneg &= ~AUTONEG_SPEED;
6771 req_line_speed = cmd->speed;
6772 req_duplex = cmd->duplex;
6773 advertising = 0;
6774 }
6775
6776 bp->autoneg = autoneg;
6777 bp->advertising = advertising;
6778 bp->req_line_speed = req_line_speed;
6779 bp->req_duplex = req_duplex;
6780
6781 err = 0;
6782 /* If device is down, the new settings will be picked up when it is
6783 * brought up.
6784 */
6785 if (netif_running(dev))
6786 err = bnx2_setup_phy(bp, cmd->port);
6787
6788 err_out_unlock:
6789 spin_unlock_bh(&bp->phy_lock);
6790
6791 return err;
6792 }
6793
6794 static void
6795 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6796 {
6797 struct bnx2 *bp = netdev_priv(dev);
6798
6799 strcpy(info->driver, DRV_MODULE_NAME);
6800 strcpy(info->version, DRV_MODULE_VERSION);
6801 strcpy(info->bus_info, pci_name(bp->pdev));
6802 strcpy(info->fw_version, bp->fw_version);
6803 }
6804
6805 #define BNX2_REGDUMP_LEN (32 * 1024)
6806
6807 static int
6808 bnx2_get_regs_len(struct net_device *dev)
6809 {
6810 return BNX2_REGDUMP_LEN;
6811 }
6812
6813 static void
6814 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6815 {
6816 u32 *p = _p, i, offset;
6817 u8 *orig_p = _p;
6818 struct bnx2 *bp = netdev_priv(dev);
6819 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6820 0x0800, 0x0880, 0x0c00, 0x0c10,
6821 0x0c30, 0x0d08, 0x1000, 0x101c,
6822 0x1040, 0x1048, 0x1080, 0x10a4,
6823 0x1400, 0x1490, 0x1498, 0x14f0,
6824 0x1500, 0x155c, 0x1580, 0x15dc,
6825 0x1600, 0x1658, 0x1680, 0x16d8,
6826 0x1800, 0x1820, 0x1840, 0x1854,
6827 0x1880, 0x1894, 0x1900, 0x1984,
6828 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6829 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6830 0x2000, 0x2030, 0x23c0, 0x2400,
6831 0x2800, 0x2820, 0x2830, 0x2850,
6832 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6833 0x3c00, 0x3c94, 0x4000, 0x4010,
6834 0x4080, 0x4090, 0x43c0, 0x4458,
6835 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6836 0x4fc0, 0x5010, 0x53c0, 0x5444,
6837 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6838 0x5fc0, 0x6000, 0x6400, 0x6428,
6839 0x6800, 0x6848, 0x684c, 0x6860,
6840 0x6888, 0x6910, 0x8000 };
6841
6842 regs->version = 0;
6843
6844 memset(p, 0, BNX2_REGDUMP_LEN);
6845
6846 if (!netif_running(bp->dev))
6847 return;
6848
6849 i = 0;
6850 offset = reg_boundaries[0];
6851 p += offset;
6852 while (offset < BNX2_REGDUMP_LEN) {
6853 *p++ = REG_RD(bp, offset);
6854 offset += 4;
6855 if (offset == reg_boundaries[i + 1]) {
6856 offset = reg_boundaries[i + 2];
6857 p = (u32 *) (orig_p + offset);
6858 i += 2;
6859 }
6860 }
6861 }
6862
6863 static void
6864 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6865 {
6866 struct bnx2 *bp = netdev_priv(dev);
6867
6868 if (bp->flags & BNX2_FLAG_NO_WOL) {
6869 wol->supported = 0;
6870 wol->wolopts = 0;
6871 }
6872 else {
6873 wol->supported = WAKE_MAGIC;
6874 if (bp->wol)
6875 wol->wolopts = WAKE_MAGIC;
6876 else
6877 wol->wolopts = 0;
6878 }
6879 memset(&wol->sopass, 0, sizeof(wol->sopass));
6880 }
6881
6882 static int
6883 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6884 {
6885 struct bnx2 *bp = netdev_priv(dev);
6886
6887 if (wol->wolopts & ~WAKE_MAGIC)
6888 return -EINVAL;
6889
6890 if (wol->wolopts & WAKE_MAGIC) {
6891 if (bp->flags & BNX2_FLAG_NO_WOL)
6892 return -EINVAL;
6893
6894 bp->wol = 1;
6895 }
6896 else {
6897 bp->wol = 0;
6898 }
6899 return 0;
6900 }
6901
6902 static int
6903 bnx2_nway_reset(struct net_device *dev)
6904 {
6905 struct bnx2 *bp = netdev_priv(dev);
6906 u32 bmcr;
6907
6908 if (!netif_running(dev))
6909 return -EAGAIN;
6910
6911 if (!(bp->autoneg & AUTONEG_SPEED)) {
6912 return -EINVAL;
6913 }
6914
6915 spin_lock_bh(&bp->phy_lock);
6916
6917 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6918 int rc;
6919
6920 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6921 spin_unlock_bh(&bp->phy_lock);
6922 return rc;
6923 }
6924
6925 /* Force a link down visible on the other side */
6926 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6927 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6928 spin_unlock_bh(&bp->phy_lock);
6929
6930 msleep(20);
6931
6932 spin_lock_bh(&bp->phy_lock);
6933
6934 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6935 bp->serdes_an_pending = 1;
6936 mod_timer(&bp->timer, jiffies + bp->current_interval);
6937 }
6938
6939 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6940 bmcr &= ~BMCR_LOOPBACK;
6941 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6942
6943 spin_unlock_bh(&bp->phy_lock);
6944
6945 return 0;
6946 }
6947
6948 static u32
6949 bnx2_get_link(struct net_device *dev)
6950 {
6951 struct bnx2 *bp = netdev_priv(dev);
6952
6953 return bp->link_up;
6954 }
6955
6956 static int
6957 bnx2_get_eeprom_len(struct net_device *dev)
6958 {
6959 struct bnx2 *bp = netdev_priv(dev);
6960
6961 if (bp->flash_info == NULL)
6962 return 0;
6963
6964 return (int) bp->flash_size;
6965 }
6966
6967 static int
6968 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6969 u8 *eebuf)
6970 {
6971 struct bnx2 *bp = netdev_priv(dev);
6972 int rc;
6973
6974 if (!netif_running(dev))
6975 return -EAGAIN;
6976
6977 /* parameters already validated in ethtool_get_eeprom */
6978
6979 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6980
6981 return rc;
6982 }
6983
6984 static int
6985 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6986 u8 *eebuf)
6987 {
6988 struct bnx2 *bp = netdev_priv(dev);
6989 int rc;
6990
6991 if (!netif_running(dev))
6992 return -EAGAIN;
6993
6994 /* parameters already validated in ethtool_set_eeprom */
6995
6996 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6997
6998 return rc;
6999 }
7000
7001 static int
7002 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7003 {
7004 struct bnx2 *bp = netdev_priv(dev);
7005
7006 memset(coal, 0, sizeof(struct ethtool_coalesce));
7007
7008 coal->rx_coalesce_usecs = bp->rx_ticks;
7009 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
7010 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
7011 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
7012
7013 coal->tx_coalesce_usecs = bp->tx_ticks;
7014 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
7015 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
7016 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
7017
7018 coal->stats_block_coalesce_usecs = bp->stats_ticks;
7019
7020 return 0;
7021 }
7022
7023 static int
7024 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
7025 {
7026 struct bnx2 *bp = netdev_priv(dev);
7027
7028 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
7029 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
7030
7031 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
7032 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
7033
7034 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
7035 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
7036
7037 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
7038 if (bp->rx_quick_cons_trip_int > 0xff)
7039 bp->rx_quick_cons_trip_int = 0xff;
7040
7041 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
7042 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
7043
7044 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
7045 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
7046
7047 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
7048 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
7049
7050 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
7051 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
7052 0xff;
7053
7054 bp->stats_ticks = coal->stats_block_coalesce_usecs;
7055 if (bp->flags & BNX2_FLAG_BROKEN_STATS) {
7056 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
7057 bp->stats_ticks = USEC_PER_SEC;
7058 }
7059 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
7060 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7061 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7062
7063 if (netif_running(bp->dev)) {
7064 bnx2_netif_stop(bp);
7065 bnx2_init_nic(bp, 0);
7066 bnx2_netif_start(bp);
7067 }
7068
7069 return 0;
7070 }
7071
7072 static void
7073 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7074 {
7075 struct bnx2 *bp = netdev_priv(dev);
7076
7077 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
7078 ering->rx_mini_max_pending = 0;
7079 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
7080
7081 ering->rx_pending = bp->rx_ring_size;
7082 ering->rx_mini_pending = 0;
7083 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
7084
7085 ering->tx_max_pending = MAX_TX_DESC_CNT;
7086 ering->tx_pending = bp->tx_ring_size;
7087 }
7088
7089 static int
7090 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
7091 {
7092 if (netif_running(bp->dev)) {
7093 bnx2_netif_stop(bp);
7094 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
7095 bnx2_free_skbs(bp);
7096 bnx2_free_mem(bp);
7097 }
7098
7099 bnx2_set_rx_ring_size(bp, rx);
7100 bp->tx_ring_size = tx;
7101
7102 if (netif_running(bp->dev)) {
7103 int rc;
7104
7105 rc = bnx2_alloc_mem(bp);
7106 if (!rc)
7107 rc = bnx2_init_nic(bp, 0);
7108
7109 if (rc) {
7110 bnx2_napi_enable(bp);
7111 dev_close(bp->dev);
7112 return rc;
7113 }
7114 bnx2_netif_start(bp);
7115 }
7116 return 0;
7117 }
7118
7119 static int
7120 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7121 {
7122 struct bnx2 *bp = netdev_priv(dev);
7123 int rc;
7124
7125 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
7126 (ering->tx_pending > MAX_TX_DESC_CNT) ||
7127 (ering->tx_pending <= MAX_SKB_FRAGS)) {
7128
7129 return -EINVAL;
7130 }
7131 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
7132 return rc;
7133 }
7134
7135 static void
7136 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7137 {
7138 struct bnx2 *bp = netdev_priv(dev);
7139
7140 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
7141 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
7142 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
7143 }
7144
7145 static int
7146 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7147 {
7148 struct bnx2 *bp = netdev_priv(dev);
7149
7150 bp->req_flow_ctrl = 0;
7151 if (epause->rx_pause)
7152 bp->req_flow_ctrl |= FLOW_CTRL_RX;
7153 if (epause->tx_pause)
7154 bp->req_flow_ctrl |= FLOW_CTRL_TX;
7155
7156 if (epause->autoneg) {
7157 bp->autoneg |= AUTONEG_FLOW_CTRL;
7158 }
7159 else {
7160 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
7161 }
7162
7163 if (netif_running(dev)) {
7164 spin_lock_bh(&bp->phy_lock);
7165 bnx2_setup_phy(bp, bp->phy_port);
7166 spin_unlock_bh(&bp->phy_lock);
7167 }
7168
7169 return 0;
7170 }
7171
7172 static u32
7173 bnx2_get_rx_csum(struct net_device *dev)
7174 {
7175 struct bnx2 *bp = netdev_priv(dev);
7176
7177 return bp->rx_csum;
7178 }
7179
7180 static int
7181 bnx2_set_rx_csum(struct net_device *dev, u32 data)
7182 {
7183 struct bnx2 *bp = netdev_priv(dev);
7184
7185 bp->rx_csum = data;
7186 return 0;
7187 }
7188
7189 static int
7190 bnx2_set_tso(struct net_device *dev, u32 data)
7191 {
7192 struct bnx2 *bp = netdev_priv(dev);
7193
7194 if (data) {
7195 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7196 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7197 dev->features |= NETIF_F_TSO6;
7198 } else
7199 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
7200 NETIF_F_TSO_ECN);
7201 return 0;
7202 }
7203
7204 static struct {
7205 char string[ETH_GSTRING_LEN];
7206 } bnx2_stats_str_arr[] = {
7207 { "rx_bytes" },
7208 { "rx_error_bytes" },
7209 { "tx_bytes" },
7210 { "tx_error_bytes" },
7211 { "rx_ucast_packets" },
7212 { "rx_mcast_packets" },
7213 { "rx_bcast_packets" },
7214 { "tx_ucast_packets" },
7215 { "tx_mcast_packets" },
7216 { "tx_bcast_packets" },
7217 { "tx_mac_errors" },
7218 { "tx_carrier_errors" },
7219 { "rx_crc_errors" },
7220 { "rx_align_errors" },
7221 { "tx_single_collisions" },
7222 { "tx_multi_collisions" },
7223 { "tx_deferred" },
7224 { "tx_excess_collisions" },
7225 { "tx_late_collisions" },
7226 { "tx_total_collisions" },
7227 { "rx_fragments" },
7228 { "rx_jabbers" },
7229 { "rx_undersize_packets" },
7230 { "rx_oversize_packets" },
7231 { "rx_64_byte_packets" },
7232 { "rx_65_to_127_byte_packets" },
7233 { "rx_128_to_255_byte_packets" },
7234 { "rx_256_to_511_byte_packets" },
7235 { "rx_512_to_1023_byte_packets" },
7236 { "rx_1024_to_1522_byte_packets" },
7237 { "rx_1523_to_9022_byte_packets" },
7238 { "tx_64_byte_packets" },
7239 { "tx_65_to_127_byte_packets" },
7240 { "tx_128_to_255_byte_packets" },
7241 { "tx_256_to_511_byte_packets" },
7242 { "tx_512_to_1023_byte_packets" },
7243 { "tx_1024_to_1522_byte_packets" },
7244 { "tx_1523_to_9022_byte_packets" },
7245 { "rx_xon_frames" },
7246 { "rx_xoff_frames" },
7247 { "tx_xon_frames" },
7248 { "tx_xoff_frames" },
7249 { "rx_mac_ctrl_frames" },
7250 { "rx_filtered_packets" },
7251 { "rx_ftq_discards" },
7252 { "rx_discards" },
7253 { "rx_fw_discards" },
7254 };
7255
7256 #define BNX2_NUM_STATS (sizeof(bnx2_stats_str_arr)/\
7257 sizeof(bnx2_stats_str_arr[0]))
7258
7259 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
7260
7261 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
7262 STATS_OFFSET32(stat_IfHCInOctets_hi),
7263 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
7264 STATS_OFFSET32(stat_IfHCOutOctets_hi),
7265 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
7266 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
7267 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
7268 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
7269 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
7270 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
7271 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
7272 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
7273 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
7274 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
7275 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
7276 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
7277 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
7278 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
7279 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
7280 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
7281 STATS_OFFSET32(stat_EtherStatsCollisions),
7282 STATS_OFFSET32(stat_EtherStatsFragments),
7283 STATS_OFFSET32(stat_EtherStatsJabbers),
7284 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
7285 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
7286 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
7287 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
7288 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
7289 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
7290 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
7291 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
7292 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
7293 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
7294 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
7295 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
7296 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
7297 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
7298 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
7299 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
7300 STATS_OFFSET32(stat_XonPauseFramesReceived),
7301 STATS_OFFSET32(stat_XoffPauseFramesReceived),
7302 STATS_OFFSET32(stat_OutXonSent),
7303 STATS_OFFSET32(stat_OutXoffSent),
7304 STATS_OFFSET32(stat_MacControlFramesReceived),
7305 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
7306 STATS_OFFSET32(stat_IfInFTQDiscards),
7307 STATS_OFFSET32(stat_IfInMBUFDiscards),
7308 STATS_OFFSET32(stat_FwRxDrop),
7309 };
7310
7311 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
7312 * skipped because of errata.
7313 */
7314 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
7315 8,0,8,8,8,8,8,8,8,8,
7316 4,0,4,4,4,4,4,4,4,4,
7317 4,4,4,4,4,4,4,4,4,4,
7318 4,4,4,4,4,4,4,4,4,4,
7319 4,4,4,4,4,4,4,
7320 };
7321
7322 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
7323 8,0,8,8,8,8,8,8,8,8,
7324 4,4,4,4,4,4,4,4,4,4,
7325 4,4,4,4,4,4,4,4,4,4,
7326 4,4,4,4,4,4,4,4,4,4,
7327 4,4,4,4,4,4,4,
7328 };
7329
7330 #define BNX2_NUM_TESTS 6
7331
7332 static struct {
7333 char string[ETH_GSTRING_LEN];
7334 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
7335 { "register_test (offline)" },
7336 { "memory_test (offline)" },
7337 { "loopback_test (offline)" },
7338 { "nvram_test (online)" },
7339 { "interrupt_test (online)" },
7340 { "link_test (online)" },
7341 };
7342
7343 static int
7344 bnx2_get_sset_count(struct net_device *dev, int sset)
7345 {
7346 switch (sset) {
7347 case ETH_SS_TEST:
7348 return BNX2_NUM_TESTS;
7349 case ETH_SS_STATS:
7350 return BNX2_NUM_STATS;
7351 default:
7352 return -EOPNOTSUPP;
7353 }
7354 }
7355
7356 static void
7357 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
7358 {
7359 struct bnx2 *bp = netdev_priv(dev);
7360
7361 bnx2_set_power_state(bp, PCI_D0);
7362
7363 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
7364 if (etest->flags & ETH_TEST_FL_OFFLINE) {
7365 int i;
7366
7367 bnx2_netif_stop(bp);
7368 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
7369 bnx2_free_skbs(bp);
7370
7371 if (bnx2_test_registers(bp) != 0) {
7372 buf[0] = 1;
7373 etest->flags |= ETH_TEST_FL_FAILED;
7374 }
7375 if (bnx2_test_memory(bp) != 0) {
7376 buf[1] = 1;
7377 etest->flags |= ETH_TEST_FL_FAILED;
7378 }
7379 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
7380 etest->flags |= ETH_TEST_FL_FAILED;
7381
7382 if (!netif_running(bp->dev))
7383 bnx2_shutdown_chip(bp);
7384 else {
7385 bnx2_init_nic(bp, 1);
7386 bnx2_netif_start(bp);
7387 }
7388
7389 /* wait for link up */
7390 for (i = 0; i < 7; i++) {
7391 if (bp->link_up)
7392 break;
7393 msleep_interruptible(1000);
7394 }
7395 }
7396
7397 if (bnx2_test_nvram(bp) != 0) {
7398 buf[3] = 1;
7399 etest->flags |= ETH_TEST_FL_FAILED;
7400 }
7401 if (bnx2_test_intr(bp) != 0) {
7402 buf[4] = 1;
7403 etest->flags |= ETH_TEST_FL_FAILED;
7404 }
7405
7406 if (bnx2_test_link(bp) != 0) {
7407 buf[5] = 1;
7408 etest->flags |= ETH_TEST_FL_FAILED;
7409
7410 }
7411 if (!netif_running(bp->dev))
7412 bnx2_set_power_state(bp, PCI_D3hot);
7413 }
7414
7415 static void
7416 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7417 {
7418 switch (stringset) {
7419 case ETH_SS_STATS:
7420 memcpy(buf, bnx2_stats_str_arr,
7421 sizeof(bnx2_stats_str_arr));
7422 break;
7423 case ETH_SS_TEST:
7424 memcpy(buf, bnx2_tests_str_arr,
7425 sizeof(bnx2_tests_str_arr));
7426 break;
7427 }
7428 }
7429
7430 static void
7431 bnx2_get_ethtool_stats(struct net_device *dev,
7432 struct ethtool_stats *stats, u64 *buf)
7433 {
7434 struct bnx2 *bp = netdev_priv(dev);
7435 int i;
7436 u32 *hw_stats = (u32 *) bp->stats_blk;
7437 u8 *stats_len_arr = NULL;
7438
7439 if (hw_stats == NULL) {
7440 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7441 return;
7442 }
7443
7444 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7445 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7446 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7447 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7448 stats_len_arr = bnx2_5706_stats_len_arr;
7449 else
7450 stats_len_arr = bnx2_5708_stats_len_arr;
7451
7452 for (i = 0; i < BNX2_NUM_STATS; i++) {
7453 if (stats_len_arr[i] == 0) {
7454 /* skip this counter */
7455 buf[i] = 0;
7456 continue;
7457 }
7458 if (stats_len_arr[i] == 4) {
7459 /* 4-byte counter */
7460 buf[i] = (u64)
7461 *(hw_stats + bnx2_stats_offset_arr[i]);
7462 continue;
7463 }
7464 /* 8-byte counter */
7465 buf[i] = (((u64) *(hw_stats +
7466 bnx2_stats_offset_arr[i])) << 32) +
7467 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7468 }
7469 }
7470
7471 static int
7472 bnx2_phys_id(struct net_device *dev, u32 data)
7473 {
7474 struct bnx2 *bp = netdev_priv(dev);
7475 int i;
7476 u32 save;
7477
7478 bnx2_set_power_state(bp, PCI_D0);
7479
7480 if (data == 0)
7481 data = 2;
7482
7483 save = REG_RD(bp, BNX2_MISC_CFG);
7484 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7485
7486 for (i = 0; i < (data * 2); i++) {
7487 if ((i % 2) == 0) {
7488 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7489 }
7490 else {
7491 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7492 BNX2_EMAC_LED_1000MB_OVERRIDE |
7493 BNX2_EMAC_LED_100MB_OVERRIDE |
7494 BNX2_EMAC_LED_10MB_OVERRIDE |
7495 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7496 BNX2_EMAC_LED_TRAFFIC);
7497 }
7498 msleep_interruptible(500);
7499 if (signal_pending(current))
7500 break;
7501 }
7502 REG_WR(bp, BNX2_EMAC_LED, 0);
7503 REG_WR(bp, BNX2_MISC_CFG, save);
7504
7505 if (!netif_running(dev))
7506 bnx2_set_power_state(bp, PCI_D3hot);
7507
7508 return 0;
7509 }
7510
7511 static int
7512 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7513 {
7514 struct bnx2 *bp = netdev_priv(dev);
7515
7516 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7517 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7518 else
7519 return (ethtool_op_set_tx_csum(dev, data));
7520 }
7521
7522 static const struct ethtool_ops bnx2_ethtool_ops = {
7523 .get_settings = bnx2_get_settings,
7524 .set_settings = bnx2_set_settings,
7525 .get_drvinfo = bnx2_get_drvinfo,
7526 .get_regs_len = bnx2_get_regs_len,
7527 .get_regs = bnx2_get_regs,
7528 .get_wol = bnx2_get_wol,
7529 .set_wol = bnx2_set_wol,
7530 .nway_reset = bnx2_nway_reset,
7531 .get_link = bnx2_get_link,
7532 .get_eeprom_len = bnx2_get_eeprom_len,
7533 .get_eeprom = bnx2_get_eeprom,
7534 .set_eeprom = bnx2_set_eeprom,
7535 .get_coalesce = bnx2_get_coalesce,
7536 .set_coalesce = bnx2_set_coalesce,
7537 .get_ringparam = bnx2_get_ringparam,
7538 .set_ringparam = bnx2_set_ringparam,
7539 .get_pauseparam = bnx2_get_pauseparam,
7540 .set_pauseparam = bnx2_set_pauseparam,
7541 .get_rx_csum = bnx2_get_rx_csum,
7542 .set_rx_csum = bnx2_set_rx_csum,
7543 .set_tx_csum = bnx2_set_tx_csum,
7544 .set_sg = ethtool_op_set_sg,
7545 .set_tso = bnx2_set_tso,
7546 .self_test = bnx2_self_test,
7547 .get_strings = bnx2_get_strings,
7548 .phys_id = bnx2_phys_id,
7549 .get_ethtool_stats = bnx2_get_ethtool_stats,
7550 .get_sset_count = bnx2_get_sset_count,
7551 };
7552
7553 /* Called with rtnl_lock */
7554 static int
7555 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7556 {
7557 struct mii_ioctl_data *data = if_mii(ifr);
7558 struct bnx2 *bp = netdev_priv(dev);
7559 int err;
7560
7561 switch(cmd) {
7562 case SIOCGMIIPHY:
7563 data->phy_id = bp->phy_addr;
7564
7565 /* fallthru */
7566 case SIOCGMIIREG: {
7567 u32 mii_regval;
7568
7569 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7570 return -EOPNOTSUPP;
7571
7572 if (!netif_running(dev))
7573 return -EAGAIN;
7574
7575 spin_lock_bh(&bp->phy_lock);
7576 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7577 spin_unlock_bh(&bp->phy_lock);
7578
7579 data->val_out = mii_regval;
7580
7581 return err;
7582 }
7583
7584 case SIOCSMIIREG:
7585 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7586 return -EOPNOTSUPP;
7587
7588 if (!netif_running(dev))
7589 return -EAGAIN;
7590
7591 spin_lock_bh(&bp->phy_lock);
7592 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7593 spin_unlock_bh(&bp->phy_lock);
7594
7595 return err;
7596
7597 default:
7598 /* do nothing */
7599 break;
7600 }
7601 return -EOPNOTSUPP;
7602 }
7603
7604 /* Called with rtnl_lock */
7605 static int
7606 bnx2_change_mac_addr(struct net_device *dev, void *p)
7607 {
7608 struct sockaddr *addr = p;
7609 struct bnx2 *bp = netdev_priv(dev);
7610
7611 if (!is_valid_ether_addr(addr->sa_data))
7612 return -EINVAL;
7613
7614 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7615 if (netif_running(dev))
7616 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7617
7618 return 0;
7619 }
7620
7621 /* Called with rtnl_lock */
7622 static int
7623 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7624 {
7625 struct bnx2 *bp = netdev_priv(dev);
7626
7627 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7628 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7629 return -EINVAL;
7630
7631 dev->mtu = new_mtu;
7632 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7633 }
7634
7635 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7636 static void
7637 poll_bnx2(struct net_device *dev)
7638 {
7639 struct bnx2 *bp = netdev_priv(dev);
7640 int i;
7641
7642 for (i = 0; i < bp->irq_nvecs; i++) {
7643 disable_irq(bp->irq_tbl[i].vector);
7644 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7645 enable_irq(bp->irq_tbl[i].vector);
7646 }
7647 }
7648 #endif
7649
7650 static void __devinit
7651 bnx2_get_5709_media(struct bnx2 *bp)
7652 {
7653 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7654 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7655 u32 strap;
7656
7657 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7658 return;
7659 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7660 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7661 return;
7662 }
7663
7664 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7665 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7666 else
7667 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7668
7669 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7670 switch (strap) {
7671 case 0x4:
7672 case 0x5:
7673 case 0x6:
7674 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7675 return;
7676 }
7677 } else {
7678 switch (strap) {
7679 case 0x1:
7680 case 0x2:
7681 case 0x4:
7682 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7683 return;
7684 }
7685 }
7686 }
7687
7688 static void __devinit
7689 bnx2_get_pci_speed(struct bnx2 *bp)
7690 {
7691 u32 reg;
7692
7693 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7694 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7695 u32 clkreg;
7696
7697 bp->flags |= BNX2_FLAG_PCIX;
7698
7699 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7700
7701 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7702 switch (clkreg) {
7703 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7704 bp->bus_speed_mhz = 133;
7705 break;
7706
7707 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7708 bp->bus_speed_mhz = 100;
7709 break;
7710
7711 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7712 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7713 bp->bus_speed_mhz = 66;
7714 break;
7715
7716 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7717 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7718 bp->bus_speed_mhz = 50;
7719 break;
7720
7721 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7722 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7723 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7724 bp->bus_speed_mhz = 33;
7725 break;
7726 }
7727 }
7728 else {
7729 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7730 bp->bus_speed_mhz = 66;
7731 else
7732 bp->bus_speed_mhz = 33;
7733 }
7734
7735 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7736 bp->flags |= BNX2_FLAG_PCI_32BIT;
7737
7738 }
7739
7740 static void __devinit
7741 bnx2_read_vpd_fw_ver(struct bnx2 *bp)
7742 {
7743 int rc, i, v0_len = 0;
7744 u8 *data;
7745 u8 *v0_str = NULL;
7746 bool mn_match = false;
7747
7748 #define BNX2_VPD_NVRAM_OFFSET 0x300
7749 #define BNX2_VPD_LEN 128
7750 #define BNX2_MAX_VER_SLEN 30
7751
7752 data = kmalloc(256, GFP_KERNEL);
7753 if (!data)
7754 return;
7755
7756 rc = bnx2_nvram_read(bp, BNX2_VPD_NVRAM_OFFSET, data + BNX2_VPD_LEN,
7757 BNX2_VPD_LEN);
7758 if (rc)
7759 goto vpd_done;
7760
7761 for (i = 0; i < BNX2_VPD_LEN; i += 4) {
7762 data[i] = data[i + BNX2_VPD_LEN + 3];
7763 data[i + 1] = data[i + BNX2_VPD_LEN + 2];
7764 data[i + 2] = data[i + BNX2_VPD_LEN + 1];
7765 data[i + 3] = data[i + BNX2_VPD_LEN];
7766 }
7767
7768 for (i = 0; i <= BNX2_VPD_LEN - 3; ) {
7769 unsigned char val = data[i];
7770 unsigned int block_end;
7771
7772 if (val == 0x82 || val == 0x91) {
7773 i = (i + 3 + (data[i + 1] + (data[i + 2] << 8)));
7774 continue;
7775 }
7776
7777 if (val != 0x90)
7778 goto vpd_done;
7779
7780 block_end = (i + 3 + (data[i + 1] + (data[i + 2] << 8)));
7781 i += 3;
7782
7783 if (block_end > BNX2_VPD_LEN)
7784 goto vpd_done;
7785
7786 while (i < (block_end - 2)) {
7787 int len = data[i + 2];
7788
7789 if (i + 3 + len > block_end)
7790 goto vpd_done;
7791
7792 if (data[i] == 'M' && data[i + 1] == 'N') {
7793 if (len != 4 ||
7794 memcmp(&data[i + 3], "1028", 4))
7795 goto vpd_done;
7796 mn_match = true;
7797
7798 } else if (data[i] == 'V' && data[i + 1] == '0') {
7799 if (len > BNX2_MAX_VER_SLEN)
7800 goto vpd_done;
7801
7802 v0_len = len;
7803 v0_str = &data[i + 3];
7804 }
7805 i += 3 + len;
7806
7807 if (mn_match && v0_str) {
7808 memcpy(bp->fw_version, v0_str, v0_len);
7809 bp->fw_version[v0_len] = ' ';
7810 goto vpd_done;
7811 }
7812 }
7813 goto vpd_done;
7814 }
7815
7816 vpd_done:
7817 kfree(data);
7818 }
7819
7820 static int __devinit
7821 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7822 {
7823 struct bnx2 *bp;
7824 unsigned long mem_len;
7825 int rc, i, j;
7826 u32 reg;
7827 u64 dma_mask, persist_dma_mask;
7828
7829 SET_NETDEV_DEV(dev, &pdev->dev);
7830 bp = netdev_priv(dev);
7831
7832 bp->flags = 0;
7833 bp->phy_flags = 0;
7834
7835 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7836 rc = pci_enable_device(pdev);
7837 if (rc) {
7838 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7839 goto err_out;
7840 }
7841
7842 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7843 dev_err(&pdev->dev,
7844 "Cannot find PCI device base address, aborting.\n");
7845 rc = -ENODEV;
7846 goto err_out_disable;
7847 }
7848
7849 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7850 if (rc) {
7851 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7852 goto err_out_disable;
7853 }
7854
7855 pci_set_master(pdev);
7856 pci_save_state(pdev);
7857
7858 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7859 if (bp->pm_cap == 0) {
7860 dev_err(&pdev->dev,
7861 "Cannot find power management capability, aborting.\n");
7862 rc = -EIO;
7863 goto err_out_release;
7864 }
7865
7866 bp->dev = dev;
7867 bp->pdev = pdev;
7868
7869 spin_lock_init(&bp->phy_lock);
7870 spin_lock_init(&bp->indirect_lock);
7871 #ifdef BCM_CNIC
7872 mutex_init(&bp->cnic_lock);
7873 #endif
7874 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7875
7876 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7877 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS + 1);
7878 dev->mem_end = dev->mem_start + mem_len;
7879 dev->irq = pdev->irq;
7880
7881 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7882
7883 if (!bp->regview) {
7884 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7885 rc = -ENOMEM;
7886 goto err_out_release;
7887 }
7888
7889 /* Configure byte swap and enable write to the reg_window registers.
7890 * Rely on CPU to do target byte swapping on big endian systems
7891 * The chip's target access swapping will not swap all accesses
7892 */
7893 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7894 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7895 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7896
7897 bnx2_set_power_state(bp, PCI_D0);
7898
7899 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7900
7901 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7902 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7903 dev_err(&pdev->dev,
7904 "Cannot find PCIE capability, aborting.\n");
7905 rc = -EIO;
7906 goto err_out_unmap;
7907 }
7908 bp->flags |= BNX2_FLAG_PCIE;
7909 if (CHIP_REV(bp) == CHIP_REV_Ax)
7910 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7911 } else {
7912 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7913 if (bp->pcix_cap == 0) {
7914 dev_err(&pdev->dev,
7915 "Cannot find PCIX capability, aborting.\n");
7916 rc = -EIO;
7917 goto err_out_unmap;
7918 }
7919 bp->flags |= BNX2_FLAG_BROKEN_STATS;
7920 }
7921
7922 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7923 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7924 bp->flags |= BNX2_FLAG_MSIX_CAP;
7925 }
7926
7927 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7928 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7929 bp->flags |= BNX2_FLAG_MSI_CAP;
7930 }
7931
7932 /* 5708 cannot support DMA addresses > 40-bit. */
7933 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7934 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
7935 else
7936 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
7937
7938 /* Configure DMA attributes. */
7939 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7940 dev->features |= NETIF_F_HIGHDMA;
7941 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7942 if (rc) {
7943 dev_err(&pdev->dev,
7944 "pci_set_consistent_dma_mask failed, aborting.\n");
7945 goto err_out_unmap;
7946 }
7947 } else if ((rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
7948 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7949 goto err_out_unmap;
7950 }
7951
7952 if (!(bp->flags & BNX2_FLAG_PCIE))
7953 bnx2_get_pci_speed(bp);
7954
7955 /* 5706A0 may falsely detect SERR and PERR. */
7956 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7957 reg = REG_RD(bp, PCI_COMMAND);
7958 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7959 REG_WR(bp, PCI_COMMAND, reg);
7960 }
7961 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7962 !(bp->flags & BNX2_FLAG_PCIX)) {
7963
7964 dev_err(&pdev->dev,
7965 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7966 goto err_out_unmap;
7967 }
7968
7969 bnx2_init_nvram(bp);
7970
7971 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7972
7973 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7974 BNX2_SHM_HDR_SIGNATURE_SIG) {
7975 u32 off = PCI_FUNC(pdev->devfn) << 2;
7976
7977 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7978 } else
7979 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7980
7981 /* Get the permanent MAC address. First we need to make sure the
7982 * firmware is actually running.
7983 */
7984 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7985
7986 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7987 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7988 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7989 rc = -ENODEV;
7990 goto err_out_unmap;
7991 }
7992
7993 bnx2_read_vpd_fw_ver(bp);
7994
7995 j = strlen(bp->fw_version);
7996 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7997 for (i = 0; i < 3 && j < 24; i++) {
7998 u8 num, k, skip0;
7999
8000 if (i == 0) {
8001 bp->fw_version[j++] = 'b';
8002 bp->fw_version[j++] = 'c';
8003 bp->fw_version[j++] = ' ';
8004 }
8005 num = (u8) (reg >> (24 - (i * 8)));
8006 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
8007 if (num >= k || !skip0 || k == 1) {
8008 bp->fw_version[j++] = (num / k) + '0';
8009 skip0 = 0;
8010 }
8011 }
8012 if (i != 2)
8013 bp->fw_version[j++] = '.';
8014 }
8015 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
8016 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
8017 bp->wol = 1;
8018
8019 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
8020 bp->flags |= BNX2_FLAG_ASF_ENABLE;
8021
8022 for (i = 0; i < 30; i++) {
8023 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8024 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
8025 break;
8026 msleep(10);
8027 }
8028 }
8029 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
8030 reg &= BNX2_CONDITION_MFW_RUN_MASK;
8031 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
8032 reg != BNX2_CONDITION_MFW_RUN_NONE) {
8033 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
8034
8035 if (j < 32)
8036 bp->fw_version[j++] = ' ';
8037 for (i = 0; i < 3 && j < 28; i++) {
8038 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
8039 reg = swab32(reg);
8040 memcpy(&bp->fw_version[j], &reg, 4);
8041 j += 4;
8042 }
8043 }
8044
8045 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
8046 bp->mac_addr[0] = (u8) (reg >> 8);
8047 bp->mac_addr[1] = (u8) reg;
8048
8049 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
8050 bp->mac_addr[2] = (u8) (reg >> 24);
8051 bp->mac_addr[3] = (u8) (reg >> 16);
8052 bp->mac_addr[4] = (u8) (reg >> 8);
8053 bp->mac_addr[5] = (u8) reg;
8054
8055 bp->tx_ring_size = MAX_TX_DESC_CNT;
8056 bnx2_set_rx_ring_size(bp, 255);
8057
8058 bp->rx_csum = 1;
8059
8060 bp->tx_quick_cons_trip_int = 2;
8061 bp->tx_quick_cons_trip = 20;
8062 bp->tx_ticks_int = 18;
8063 bp->tx_ticks = 80;
8064
8065 bp->rx_quick_cons_trip_int = 2;
8066 bp->rx_quick_cons_trip = 12;
8067 bp->rx_ticks_int = 18;
8068 bp->rx_ticks = 18;
8069
8070 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
8071
8072 bp->current_interval = BNX2_TIMER_INTERVAL;
8073
8074 bp->phy_addr = 1;
8075
8076 /* Disable WOL support if we are running on a SERDES chip. */
8077 if (CHIP_NUM(bp) == CHIP_NUM_5709)
8078 bnx2_get_5709_media(bp);
8079 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
8080 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
8081
8082 bp->phy_port = PORT_TP;
8083 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
8084 bp->phy_port = PORT_FIBRE;
8085 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
8086 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
8087 bp->flags |= BNX2_FLAG_NO_WOL;
8088 bp->wol = 0;
8089 }
8090 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
8091 /* Don't do parallel detect on this board because of
8092 * some board problems. The link will not go down
8093 * if we do parallel detect.
8094 */
8095 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
8096 pdev->subsystem_device == 0x310c)
8097 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
8098 } else {
8099 bp->phy_addr = 2;
8100 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
8101 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
8102 }
8103 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
8104 CHIP_NUM(bp) == CHIP_NUM_5708)
8105 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
8106 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
8107 (CHIP_REV(bp) == CHIP_REV_Ax ||
8108 CHIP_REV(bp) == CHIP_REV_Bx))
8109 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
8110
8111 bnx2_init_fw_cap(bp);
8112
8113 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
8114 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
8115 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
8116 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
8117 bp->flags |= BNX2_FLAG_NO_WOL;
8118 bp->wol = 0;
8119 }
8120
8121 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
8122 bp->tx_quick_cons_trip_int =
8123 bp->tx_quick_cons_trip;
8124 bp->tx_ticks_int = bp->tx_ticks;
8125 bp->rx_quick_cons_trip_int =
8126 bp->rx_quick_cons_trip;
8127 bp->rx_ticks_int = bp->rx_ticks;
8128 bp->comp_prod_trip_int = bp->comp_prod_trip;
8129 bp->com_ticks_int = bp->com_ticks;
8130 bp->cmd_ticks_int = bp->cmd_ticks;
8131 }
8132
8133 /* Disable MSI on 5706 if AMD 8132 bridge is found.
8134 *
8135 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
8136 * with byte enables disabled on the unused 32-bit word. This is legal
8137 * but causes problems on the AMD 8132 which will eventually stop
8138 * responding after a while.
8139 *
8140 * AMD believes this incompatibility is unique to the 5706, and
8141 * prefers to locally disable MSI rather than globally disabling it.
8142 */
8143 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
8144 struct pci_dev *amd_8132 = NULL;
8145
8146 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
8147 PCI_DEVICE_ID_AMD_8132_BRIDGE,
8148 amd_8132))) {
8149
8150 if (amd_8132->revision >= 0x10 &&
8151 amd_8132->revision <= 0x13) {
8152 disable_msi = 1;
8153 pci_dev_put(amd_8132);
8154 break;
8155 }
8156 }
8157 }
8158
8159 bnx2_set_default_link(bp);
8160 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
8161
8162 init_timer(&bp->timer);
8163 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
8164 bp->timer.data = (unsigned long) bp;
8165 bp->timer.function = bnx2_timer;
8166
8167 return 0;
8168
8169 err_out_unmap:
8170 if (bp->regview) {
8171 iounmap(bp->regview);
8172 bp->regview = NULL;
8173 }
8174
8175 err_out_release:
8176 pci_release_regions(pdev);
8177
8178 err_out_disable:
8179 pci_disable_device(pdev);
8180 pci_set_drvdata(pdev, NULL);
8181
8182 err_out:
8183 return rc;
8184 }
8185
8186 static char * __devinit
8187 bnx2_bus_string(struct bnx2 *bp, char *str)
8188 {
8189 char *s = str;
8190
8191 if (bp->flags & BNX2_FLAG_PCIE) {
8192 s += sprintf(s, "PCI Express");
8193 } else {
8194 s += sprintf(s, "PCI");
8195 if (bp->flags & BNX2_FLAG_PCIX)
8196 s += sprintf(s, "-X");
8197 if (bp->flags & BNX2_FLAG_PCI_32BIT)
8198 s += sprintf(s, " 32-bit");
8199 else
8200 s += sprintf(s, " 64-bit");
8201 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
8202 }
8203 return str;
8204 }
8205
8206 static void __devinit
8207 bnx2_init_napi(struct bnx2 *bp)
8208 {
8209 int i;
8210
8211 for (i = 0; i < bp->irq_nvecs; i++) {
8212 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
8213 int (*poll)(struct napi_struct *, int);
8214
8215 if (i == 0)
8216 poll = bnx2_poll;
8217 else
8218 poll = bnx2_poll_msix;
8219
8220 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
8221 bnapi->bp = bp;
8222 }
8223 }
8224
8225 static const struct net_device_ops bnx2_netdev_ops = {
8226 .ndo_open = bnx2_open,
8227 .ndo_start_xmit = bnx2_start_xmit,
8228 .ndo_stop = bnx2_close,
8229 .ndo_get_stats = bnx2_get_stats,
8230 .ndo_set_rx_mode = bnx2_set_rx_mode,
8231 .ndo_do_ioctl = bnx2_ioctl,
8232 .ndo_validate_addr = eth_validate_addr,
8233 .ndo_set_mac_address = bnx2_change_mac_addr,
8234 .ndo_change_mtu = bnx2_change_mtu,
8235 .ndo_tx_timeout = bnx2_tx_timeout,
8236 #ifdef BCM_VLAN
8237 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
8238 #endif
8239 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
8240 .ndo_poll_controller = poll_bnx2,
8241 #endif
8242 };
8243
8244 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
8245 {
8246 #ifdef BCM_VLAN
8247 dev->vlan_features |= flags;
8248 #endif
8249 }
8250
8251 static int __devinit
8252 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8253 {
8254 static int version_printed = 0;
8255 struct net_device *dev = NULL;
8256 struct bnx2 *bp;
8257 int rc;
8258 char str[40];
8259
8260 if (version_printed++ == 0)
8261 printk(KERN_INFO "%s", version);
8262
8263 /* dev zeroed in init_etherdev */
8264 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
8265
8266 if (!dev)
8267 return -ENOMEM;
8268
8269 rc = bnx2_init_board(pdev, dev);
8270 if (rc < 0) {
8271 free_netdev(dev);
8272 return rc;
8273 }
8274
8275 dev->netdev_ops = &bnx2_netdev_ops;
8276 dev->watchdog_timeo = TX_TIMEOUT;
8277 dev->ethtool_ops = &bnx2_ethtool_ops;
8278
8279 bp = netdev_priv(dev);
8280
8281 pci_set_drvdata(pdev, dev);
8282
8283 rc = bnx2_request_firmware(bp);
8284 if (rc)
8285 goto error;
8286
8287 memcpy(dev->dev_addr, bp->mac_addr, 6);
8288 memcpy(dev->perm_addr, bp->mac_addr, 6);
8289
8290 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
8291 vlan_features_add(dev, NETIF_F_IP_CSUM | NETIF_F_SG);
8292 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8293 dev->features |= NETIF_F_IPV6_CSUM;
8294 vlan_features_add(dev, NETIF_F_IPV6_CSUM);
8295 }
8296 #ifdef BCM_VLAN
8297 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
8298 #endif
8299 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
8300 vlan_features_add(dev, NETIF_F_TSO | NETIF_F_TSO_ECN);
8301 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
8302 dev->features |= NETIF_F_TSO6;
8303 vlan_features_add(dev, NETIF_F_TSO6);
8304 }
8305 if ((rc = register_netdev(dev))) {
8306 dev_err(&pdev->dev, "Cannot register net device\n");
8307 goto error;
8308 }
8309
8310 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
8311 "IRQ %d, node addr %pM\n",
8312 dev->name,
8313 board_info[ent->driver_data].name,
8314 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
8315 ((CHIP_ID(bp) & 0x0ff0) >> 4),
8316 bnx2_bus_string(bp, str),
8317 dev->base_addr,
8318 bp->pdev->irq, dev->dev_addr);
8319
8320 return 0;
8321
8322 error:
8323 if (bp->mips_firmware)
8324 release_firmware(bp->mips_firmware);
8325 if (bp->rv2p_firmware)
8326 release_firmware(bp->rv2p_firmware);
8327
8328 if (bp->regview)
8329 iounmap(bp->regview);
8330 pci_release_regions(pdev);
8331 pci_disable_device(pdev);
8332 pci_set_drvdata(pdev, NULL);
8333 free_netdev(dev);
8334 return rc;
8335 }
8336
8337 static void __devexit
8338 bnx2_remove_one(struct pci_dev *pdev)
8339 {
8340 struct net_device *dev = pci_get_drvdata(pdev);
8341 struct bnx2 *bp = netdev_priv(dev);
8342
8343 flush_scheduled_work();
8344
8345 unregister_netdev(dev);
8346
8347 if (bp->mips_firmware)
8348 release_firmware(bp->mips_firmware);
8349 if (bp->rv2p_firmware)
8350 release_firmware(bp->rv2p_firmware);
8351
8352 if (bp->regview)
8353 iounmap(bp->regview);
8354
8355 free_netdev(dev);
8356 pci_release_regions(pdev);
8357 pci_disable_device(pdev);
8358 pci_set_drvdata(pdev, NULL);
8359 }
8360
8361 static int
8362 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
8363 {
8364 struct net_device *dev = pci_get_drvdata(pdev);
8365 struct bnx2 *bp = netdev_priv(dev);
8366
8367 /* PCI register 4 needs to be saved whether netif_running() or not.
8368 * MSI address and data need to be saved if using MSI and
8369 * netif_running().
8370 */
8371 pci_save_state(pdev);
8372 if (!netif_running(dev))
8373 return 0;
8374
8375 flush_scheduled_work();
8376 bnx2_netif_stop(bp);
8377 netif_device_detach(dev);
8378 del_timer_sync(&bp->timer);
8379 bnx2_shutdown_chip(bp);
8380 bnx2_free_skbs(bp);
8381 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
8382 return 0;
8383 }
8384
8385 static int
8386 bnx2_resume(struct pci_dev *pdev)
8387 {
8388 struct net_device *dev = pci_get_drvdata(pdev);
8389 struct bnx2 *bp = netdev_priv(dev);
8390
8391 pci_restore_state(pdev);
8392 if (!netif_running(dev))
8393 return 0;
8394
8395 bnx2_set_power_state(bp, PCI_D0);
8396 netif_device_attach(dev);
8397 bnx2_init_nic(bp, 1);
8398 bnx2_netif_start(bp);
8399 return 0;
8400 }
8401
8402 /**
8403 * bnx2_io_error_detected - called when PCI error is detected
8404 * @pdev: Pointer to PCI device
8405 * @state: The current pci connection state
8406 *
8407 * This function is called after a PCI bus error affecting
8408 * this device has been detected.
8409 */
8410 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
8411 pci_channel_state_t state)
8412 {
8413 struct net_device *dev = pci_get_drvdata(pdev);
8414 struct bnx2 *bp = netdev_priv(dev);
8415
8416 rtnl_lock();
8417 netif_device_detach(dev);
8418
8419 if (state == pci_channel_io_perm_failure) {
8420 rtnl_unlock();
8421 return PCI_ERS_RESULT_DISCONNECT;
8422 }
8423
8424 if (netif_running(dev)) {
8425 bnx2_netif_stop(bp);
8426 del_timer_sync(&bp->timer);
8427 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
8428 }
8429
8430 pci_disable_device(pdev);
8431 rtnl_unlock();
8432
8433 /* Request a slot slot reset. */
8434 return PCI_ERS_RESULT_NEED_RESET;
8435 }
8436
8437 /**
8438 * bnx2_io_slot_reset - called after the pci bus has been reset.
8439 * @pdev: Pointer to PCI device
8440 *
8441 * Restart the card from scratch, as if from a cold-boot.
8442 */
8443 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
8444 {
8445 struct net_device *dev = pci_get_drvdata(pdev);
8446 struct bnx2 *bp = netdev_priv(dev);
8447
8448 rtnl_lock();
8449 if (pci_enable_device(pdev)) {
8450 dev_err(&pdev->dev,
8451 "Cannot re-enable PCI device after reset.\n");
8452 rtnl_unlock();
8453 return PCI_ERS_RESULT_DISCONNECT;
8454 }
8455 pci_set_master(pdev);
8456 pci_restore_state(pdev);
8457 pci_save_state(pdev);
8458
8459 if (netif_running(dev)) {
8460 bnx2_set_power_state(bp, PCI_D0);
8461 bnx2_init_nic(bp, 1);
8462 }
8463
8464 rtnl_unlock();
8465 return PCI_ERS_RESULT_RECOVERED;
8466 }
8467
8468 /**
8469 * bnx2_io_resume - called when traffic can start flowing again.
8470 * @pdev: Pointer to PCI device
8471 *
8472 * This callback is called when the error recovery driver tells us that
8473 * its OK to resume normal operation.
8474 */
8475 static void bnx2_io_resume(struct pci_dev *pdev)
8476 {
8477 struct net_device *dev = pci_get_drvdata(pdev);
8478 struct bnx2 *bp = netdev_priv(dev);
8479
8480 rtnl_lock();
8481 if (netif_running(dev))
8482 bnx2_netif_start(bp);
8483
8484 netif_device_attach(dev);
8485 rtnl_unlock();
8486 }
8487
8488 static struct pci_error_handlers bnx2_err_handler = {
8489 .error_detected = bnx2_io_error_detected,
8490 .slot_reset = bnx2_io_slot_reset,
8491 .resume = bnx2_io_resume,
8492 };
8493
8494 static struct pci_driver bnx2_pci_driver = {
8495 .name = DRV_MODULE_NAME,
8496 .id_table = bnx2_pci_tbl,
8497 .probe = bnx2_init_one,
8498 .remove = __devexit_p(bnx2_remove_one),
8499 .suspend = bnx2_suspend,
8500 .resume = bnx2_resume,
8501 .err_handler = &bnx2_err_handler,
8502 };
8503
8504 static int __init bnx2_init(void)
8505 {
8506 return pci_register_driver(&bnx2_pci_driver);
8507 }
8508
8509 static void __exit bnx2_cleanup(void)
8510 {
8511 pci_unregister_driver(&bnx2_pci_driver);
8512 }
8513
8514 module_init(bnx2_init);
8515 module_exit(bnx2_cleanup);
8516
8517
8518
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree