3 * Local APIC virtualization
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affilates.
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/kvm.h>
24 #include <linux/highmem.h>
25 #include <linux/smp.h>
26 #include <linux/hrtimer.h>
28 #include <linux/module.h>
29 #include <linux/math64.h>
30 #include <linux/slab.h>
31 #include <asm/processor.h>
34 #include <asm/current.h>
35 #include <asm/apicdef.h>
36 #include <asm/atomic.h>
37 #include "kvm_cache_regs.h"
43 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
45 #define mod_64(x, y) ((x) % (y))
53 #define APIC_BUS_CYCLE_NS 1
55 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
56 #define apic_debug(fmt, arg...)
58 #define APIC_LVT_NUM 6
59 /* 14 is the version for Xeon and Pentium 8.4.8*/
60 #define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
61 #define LAPIC_MMIO_LENGTH (1 << 12)
62 /* followed define is not in apicdef.h */
63 #define APIC_SHORT_MASK 0xc0000
64 #define APIC_DEST_NOSHORT 0x0
65 #define APIC_DEST_MASK 0x800
66 #define MAX_APIC_VECTOR 256
68 #define VEC_POS(v) ((v) & (32 - 1))
69 #define REG_POS(v) (((v) >> 5) << 4)
71 static inline u32
apic_get_reg(struct kvm_lapic
*apic
, int reg_off
)
73 return *((u32
*) (apic
->regs
+ reg_off
));
76 static inline void apic_set_reg(struct kvm_lapic
*apic
, int reg_off
, u32 val
)
78 *((u32
*) (apic
->regs
+ reg_off
)) = val
;
81 static inline int apic_test_and_set_vector(int vec
, void *bitmap
)
83 return test_and_set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
86 static inline int apic_test_and_clear_vector(int vec
, void *bitmap
)
88 return test_and_clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
91 static inline void apic_set_vector(int vec
, void *bitmap
)
93 set_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
96 static inline void apic_clear_vector(int vec
, void *bitmap
)
98 clear_bit(VEC_POS(vec
), (bitmap
) + REG_POS(vec
));
101 static inline int apic_hw_enabled(struct kvm_lapic
*apic
)
103 return (apic
)->vcpu
->arch
.apic_base
& MSR_IA32_APICBASE_ENABLE
;
106 static inline int apic_sw_enabled(struct kvm_lapic
*apic
)
108 return apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_APIC_ENABLED
;
111 static inline int apic_enabled(struct kvm_lapic
*apic
)
113 return apic_sw_enabled(apic
) && apic_hw_enabled(apic
);
117 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
120 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
121 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
123 static inline int kvm_apic_id(struct kvm_lapic
*apic
)
125 return (apic_get_reg(apic
, APIC_ID
) >> 24) & 0xff;
128 static inline int apic_lvt_enabled(struct kvm_lapic
*apic
, int lvt_type
)
130 return !(apic_get_reg(apic
, lvt_type
) & APIC_LVT_MASKED
);
133 static inline int apic_lvt_vector(struct kvm_lapic
*apic
, int lvt_type
)
135 return apic_get_reg(apic
, lvt_type
) & APIC_VECTOR_MASK
;
138 static inline int apic_lvtt_period(struct kvm_lapic
*apic
)
140 return apic_get_reg(apic
, APIC_LVTT
) & APIC_LVT_TIMER_PERIODIC
;
143 static inline int apic_lvt_nmi_mode(u32 lvt_val
)
145 return (lvt_val
& (APIC_MODE_MASK
| APIC_LVT_MASKED
)) == APIC_DM_NMI
;
148 void kvm_apic_set_version(struct kvm_vcpu
*vcpu
)
150 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
151 struct kvm_cpuid_entry2
*feat
;
152 u32 v
= APIC_VERSION
;
154 if (!irqchip_in_kernel(vcpu
->kvm
))
157 feat
= kvm_find_cpuid_entry(apic
->vcpu
, 0x1, 0);
158 if (feat
&& (feat
->ecx
& (1 << (X86_FEATURE_X2APIC
& 31))))
159 v
|= APIC_LVR_DIRECTED_EOI
;
160 apic_set_reg(apic
, APIC_LVR
, v
);
163 static inline int apic_x2apic_mode(struct kvm_lapic
*apic
)
165 return apic
->vcpu
->arch
.apic_base
& X2APIC_ENABLE
;
168 static unsigned int apic_lvt_mask
[APIC_LVT_NUM
] = {
169 LVT_MASK
| APIC_LVT_TIMER_PERIODIC
, /* LVTT */
170 LVT_MASK
| APIC_MODE_MASK
, /* LVTTHMR */
171 LVT_MASK
| APIC_MODE_MASK
, /* LVTPC */
172 LINT_MASK
, LINT_MASK
, /* LVT0-1 */
173 LVT_MASK
/* LVTERR */
176 static int find_highest_vector(void *bitmap
)
179 int word_offset
= MAX_APIC_VECTOR
>> 5;
181 while ((word_offset
!= 0) && (word
[(--word_offset
) << 2] == 0))
184 if (likely(!word_offset
&& !word
[0]))
187 return fls(word
[word_offset
<< 2]) - 1 + (word_offset
<< 5);
190 static inline int apic_test_and_set_irr(int vec
, struct kvm_lapic
*apic
)
192 apic
->irr_pending
= true;
193 return apic_test_and_set_vector(vec
, apic
->regs
+ APIC_IRR
);
196 static inline int apic_search_irr(struct kvm_lapic
*apic
)
198 return find_highest_vector(apic
->regs
+ APIC_IRR
);
201 static inline int apic_find_highest_irr(struct kvm_lapic
*apic
)
205 if (!apic
->irr_pending
)
208 result
= apic_search_irr(apic
);
209 ASSERT(result
== -1 || result
>= 16);
214 static inline void apic_clear_irr(int vec
, struct kvm_lapic
*apic
)
216 apic
->irr_pending
= false;
217 apic_clear_vector(vec
, apic
->regs
+ APIC_IRR
);
218 if (apic_search_irr(apic
) != -1)
219 apic
->irr_pending
= true;
222 int kvm_lapic_find_highest_irr(struct kvm_vcpu
*vcpu
)
224 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
227 /* This may race with setting of irr in __apic_accept_irq() and
228 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
229 * will cause vmexit immediately and the value will be recalculated
230 * on the next vmentry.
234 highest_irr
= apic_find_highest_irr(apic
);
239 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
240 int vector
, int level
, int trig_mode
);
242 int kvm_apic_set_irq(struct kvm_vcpu
*vcpu
, struct kvm_lapic_irq
*irq
)
244 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
246 return __apic_accept_irq(apic
, irq
->delivery_mode
, irq
->vector
,
247 irq
->level
, irq
->trig_mode
);
250 static inline int apic_find_highest_isr(struct kvm_lapic
*apic
)
254 result
= find_highest_vector(apic
->regs
+ APIC_ISR
);
255 ASSERT(result
== -1 || result
>= 16);
260 static void apic_update_ppr(struct kvm_lapic
*apic
)
265 tpr
= apic_get_reg(apic
, APIC_TASKPRI
);
266 isr
= apic_find_highest_isr(apic
);
267 isrv
= (isr
!= -1) ? isr
: 0;
269 if ((tpr
& 0xf0) >= (isrv
& 0xf0))
274 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
275 apic
, ppr
, isr
, isrv
);
277 apic_set_reg(apic
, APIC_PROCPRI
, ppr
);
280 static void apic_set_tpr(struct kvm_lapic
*apic
, u32 tpr
)
282 apic_set_reg(apic
, APIC_TASKPRI
, tpr
);
283 apic_update_ppr(apic
);
286 int kvm_apic_match_physical_addr(struct kvm_lapic
*apic
, u16 dest
)
288 return dest
== 0xff || kvm_apic_id(apic
) == dest
;
291 int kvm_apic_match_logical_addr(struct kvm_lapic
*apic
, u8 mda
)
296 if (apic_x2apic_mode(apic
)) {
297 logical_id
= apic_get_reg(apic
, APIC_LDR
);
298 return logical_id
& mda
;
301 logical_id
= GET_APIC_LOGICAL_ID(apic_get_reg(apic
, APIC_LDR
));
303 switch (apic_get_reg(apic
, APIC_DFR
)) {
305 if (logical_id
& mda
)
308 case APIC_DFR_CLUSTER
:
309 if (((logical_id
>> 4) == (mda
>> 0x4))
310 && (logical_id
& mda
& 0xf))
314 printk(KERN_WARNING
"Bad DFR vcpu %d: %08x\n",
315 apic
->vcpu
->vcpu_id
, apic_get_reg(apic
, APIC_DFR
));
322 int kvm_apic_match_dest(struct kvm_vcpu
*vcpu
, struct kvm_lapic
*source
,
323 int short_hand
, int dest
, int dest_mode
)
326 struct kvm_lapic
*target
= vcpu
->arch
.apic
;
328 apic_debug("target %p, source %p, dest 0x%x, "
329 "dest_mode 0x%x, short_hand 0x%x\n",
330 target
, source
, dest
, dest_mode
, short_hand
);
333 switch (short_hand
) {
334 case APIC_DEST_NOSHORT
:
337 result
= kvm_apic_match_physical_addr(target
, dest
);
340 result
= kvm_apic_match_logical_addr(target
, dest
);
343 result
= (target
== source
);
345 case APIC_DEST_ALLINC
:
348 case APIC_DEST_ALLBUT
:
349 result
= (target
!= source
);
352 printk(KERN_WARNING
"Bad dest shorthand value %x\n",
361 * Add a pending IRQ into lapic.
362 * Return 1 if successfully added and 0 if discarded.
364 static int __apic_accept_irq(struct kvm_lapic
*apic
, int delivery_mode
,
365 int vector
, int level
, int trig_mode
)
368 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
370 switch (delivery_mode
) {
372 vcpu
->arch
.apic_arb_prio
++;
374 /* FIXME add logic for vcpu on reset */
375 if (unlikely(!apic_enabled(apic
)))
379 apic_debug("level trig mode for vector %d", vector
);
380 apic_set_vector(vector
, apic
->regs
+ APIC_TMR
);
382 apic_clear_vector(vector
, apic
->regs
+ APIC_TMR
);
384 result
= !apic_test_and_set_irr(vector
, apic
);
385 trace_kvm_apic_accept_irq(vcpu
->vcpu_id
, delivery_mode
,
386 trig_mode
, vector
, !result
);
389 apic_debug("level trig mode repeatedly for "
390 "vector %d", vector
);
398 printk(KERN_DEBUG
"Ignoring delivery mode 3\n");
402 printk(KERN_DEBUG
"Ignoring guest SMI\n");
407 kvm_inject_nmi(vcpu
);
414 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_RUNNABLE
)
416 "INIT on a runnable vcpu %d\n",
418 vcpu
->arch
.mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
421 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
426 case APIC_DM_STARTUP
:
427 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
428 vcpu
->vcpu_id
, vector
);
429 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_INIT_RECEIVED
) {
431 vcpu
->arch
.sipi_vector
= vector
;
432 vcpu
->arch
.mp_state
= KVM_MP_STATE_SIPI_RECEIVED
;
439 * Should only be called by kvm_apic_local_deliver() with LVT0,
440 * before NMI watchdog was enabled. Already handled by
441 * kvm_apic_accept_pic_intr().
446 printk(KERN_ERR
"TODO: unsupported delivery mode %x\n",
453 int kvm_apic_compare_prio(struct kvm_vcpu
*vcpu1
, struct kvm_vcpu
*vcpu2
)
455 return vcpu1
->arch
.apic_arb_prio
- vcpu2
->arch
.apic_arb_prio
;
458 static void apic_set_eoi(struct kvm_lapic
*apic
)
460 int vector
= apic_find_highest_isr(apic
);
463 * Not every write EOI will has corresponding ISR,
464 * one example is when Kernel check timer on setup_IO_APIC
469 apic_clear_vector(vector
, apic
->regs
+ APIC_ISR
);
470 apic_update_ppr(apic
);
472 if (apic_test_and_clear_vector(vector
, apic
->regs
+ APIC_TMR
))
473 trigger_mode
= IOAPIC_LEVEL_TRIG
;
475 trigger_mode
= IOAPIC_EDGE_TRIG
;
476 if (!(apic_get_reg(apic
, APIC_SPIV
) & APIC_SPIV_DIRECTED_EOI
))
477 kvm_ioapic_update_eoi(apic
->vcpu
->kvm
, vector
, trigger_mode
);
480 static void apic_send_ipi(struct kvm_lapic
*apic
)
482 u32 icr_low
= apic_get_reg(apic
, APIC_ICR
);
483 u32 icr_high
= apic_get_reg(apic
, APIC_ICR2
);
484 struct kvm_lapic_irq irq
;
486 irq
.vector
= icr_low
& APIC_VECTOR_MASK
;
487 irq
.delivery_mode
= icr_low
& APIC_MODE_MASK
;
488 irq
.dest_mode
= icr_low
& APIC_DEST_MASK
;
489 irq
.level
= icr_low
& APIC_INT_ASSERT
;
490 irq
.trig_mode
= icr_low
& APIC_INT_LEVELTRIG
;
491 irq
.shorthand
= icr_low
& APIC_SHORT_MASK
;
492 if (apic_x2apic_mode(apic
))
493 irq
.dest_id
= icr_high
;
495 irq
.dest_id
= GET_APIC_DEST_FIELD(icr_high
);
497 trace_kvm_apic_ipi(icr_low
, irq
.dest_id
);
499 apic_debug("icr_high 0x%x, icr_low 0x%x, "
500 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
501 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
502 icr_high
, icr_low
, irq
.shorthand
, irq
.dest_id
,
503 irq
.trig_mode
, irq
.level
, irq
.dest_mode
, irq
.delivery_mode
,
506 kvm_irq_delivery_to_apic(apic
->vcpu
->kvm
, apic
, &irq
);
509 static u32
apic_get_tmcct(struct kvm_lapic
*apic
)
515 ASSERT(apic
!= NULL
);
517 /* if initial count is 0, current count should also be 0 */
518 if (apic_get_reg(apic
, APIC_TMICT
) == 0)
521 remaining
= hrtimer_get_remaining(&apic
->lapic_timer
.timer
);
522 if (ktime_to_ns(remaining
) < 0)
523 remaining
= ktime_set(0, 0);
525 ns
= mod_64(ktime_to_ns(remaining
), apic
->lapic_timer
.period
);
526 tmcct
= div64_u64(ns
,
527 (APIC_BUS_CYCLE_NS
* apic
->divide_count
));
532 static void __report_tpr_access(struct kvm_lapic
*apic
, bool write
)
534 struct kvm_vcpu
*vcpu
= apic
->vcpu
;
535 struct kvm_run
*run
= vcpu
->run
;
537 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS
, vcpu
);
538 run
->tpr_access
.rip
= kvm_rip_read(vcpu
);
539 run
->tpr_access
.is_write
= write
;
542 static inline void report_tpr_access(struct kvm_lapic
*apic
, bool write
)
544 if (apic
->vcpu
->arch
.tpr_access_reporting
)
545 __report_tpr_access(apic
, write
);
548 static u32
__apic_read(struct kvm_lapic
*apic
, unsigned int offset
)
552 if (offset
>= LAPIC_MMIO_LENGTH
)
557 if (apic_x2apic_mode(apic
))
558 val
= kvm_apic_id(apic
);
560 val
= kvm_apic_id(apic
) << 24;
563 printk(KERN_WARNING
"Access APIC ARBPRI register "
564 "which is for P6\n");
567 case APIC_TMCCT
: /* Timer CCR */
568 val
= apic_get_tmcct(apic
);
572 report_tpr_access(apic
, false);
575 apic_update_ppr(apic
);
576 val
= apic_get_reg(apic
, offset
);
583 static inline struct kvm_lapic
*to_lapic(struct kvm_io_device
*dev
)
585 return container_of(dev
, struct kvm_lapic
, dev
);
588 static int apic_reg_read(struct kvm_lapic
*apic
, u32 offset
, int len
,
591 unsigned char alignment
= offset
& 0xf;
593 /* this bitmask has a bit cleared for each reserver register */
594 static const u64 rmask
= 0x43ff01ffffffe70cULL
;
596 if ((alignment
+ len
) > 4) {
597 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
602 if (offset
> 0x3f0 || !(rmask
& (1ULL << (offset
>> 4)))) {
603 apic_debug("KVM_APIC_READ: read reserved register %x\n",
608 result
= __apic_read(apic
, offset
& ~0xf);
610 trace_kvm_apic_read(offset
, result
);
616 memcpy(data
, (char *)&result
+ alignment
, len
);
619 printk(KERN_ERR
"Local APIC read with len = %x, "
620 "should be 1,2, or 4 instead\n", len
);
626 static int apic_mmio_in_range(struct kvm_lapic
*apic
, gpa_t addr
)
628 return apic_hw_enabled(apic
) &&
629 addr
>= apic
->base_address
&&
630 addr
< apic
->base_address
+ LAPIC_MMIO_LENGTH
;
633 static int apic_mmio_read(struct kvm_io_device
*this,
634 gpa_t address
, int len
, void *data
)
636 struct kvm_lapic
*apic
= to_lapic(this);
637 u32 offset
= address
- apic
->base_address
;
639 if (!apic_mmio_in_range(apic
, address
))
642 apic_reg_read(apic
, offset
, len
, data
);
647 static void update_divide_count(struct kvm_lapic
*apic
)
649 u32 tmp1
, tmp2
, tdcr
;
651 tdcr
= apic_get_reg(apic
, APIC_TDCR
);
653 tmp2
= ((tmp1
& 0x3) | ((tmp1
& 0x8) >> 1)) + 1;
654 apic
->divide_count
= 0x1 << (tmp2
& 0x7);
656 apic_debug("timer divide count is 0x%x\n",
660 static void start_apic_timer(struct kvm_lapic
*apic
)
662 ktime_t now
= apic
->lapic_timer
.timer
.base
->get_time();
664 apic
->lapic_timer
.period
= (u64
)apic_get_reg(apic
, APIC_TMICT
) *
665 APIC_BUS_CYCLE_NS
* apic
->divide_count
;
666 atomic_set(&apic
->lapic_timer
.pending
, 0);
668 if (!apic
->lapic_timer
.period
)
671 * Do not allow the guest to program periodic timers with small
672 * interval, since the hrtimers are not throttled by the host
675 if (apic_lvtt_period(apic
)) {
676 if (apic
->lapic_timer
.period
< NSEC_PER_MSEC
/2)
677 apic
->lapic_timer
.period
= NSEC_PER_MSEC
/2;
680 hrtimer_start(&apic
->lapic_timer
.timer
,
681 ktime_add_ns(now
, apic
->lapic_timer
.period
),
684 apic_debug("%s: bus cycle is %" PRId64
"ns, now 0x%016"
686 "timer initial count 0x%x, period %lldns, "
687 "expire @ 0x%016" PRIx64
".\n", __func__
,
688 APIC_BUS_CYCLE_NS
, ktime_to_ns(now
),
689 apic_get_reg(apic
, APIC_TMICT
),
690 apic
->lapic_timer
.period
,
691 ktime_to_ns(ktime_add_ns(now
,
692 apic
->lapic_timer
.period
)));
695 static void apic_manage_nmi_watchdog(struct kvm_lapic
*apic
, u32 lvt0_val
)
697 int nmi_wd_enabled
= apic_lvt_nmi_mode(apic_get_reg(apic
, APIC_LVT0
));
699 if (apic_lvt_nmi_mode(lvt0_val
)) {
700 if (!nmi_wd_enabled
) {
701 apic_debug("Receive NMI setting on APIC_LVT0 "
702 "for cpu %d\n", apic
->vcpu
->vcpu_id
);
703 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
++;
705 } else if (nmi_wd_enabled
)
706 apic
->vcpu
->kvm
->arch
.vapics_in_nmi_mode
--;
709 static int apic_reg_write(struct kvm_lapic
*apic
, u32 reg
, u32 val
)
713 trace_kvm_apic_write(reg
, val
);
716 case APIC_ID
: /* Local APIC ID */
717 if (!apic_x2apic_mode(apic
))
718 apic_set_reg(apic
, APIC_ID
, val
);
724 report_tpr_access(apic
, true);
725 apic_set_tpr(apic
, val
& 0xff);
733 if (!apic_x2apic_mode(apic
))
734 apic_set_reg(apic
, APIC_LDR
, val
& APIC_LDR_MASK
);
740 if (!apic_x2apic_mode(apic
))
741 apic_set_reg(apic
, APIC_DFR
, val
| 0x0FFFFFFF);
748 if (apic_get_reg(apic
, APIC_LVR
) & APIC_LVR_DIRECTED_EOI
)
749 mask
|= APIC_SPIV_DIRECTED_EOI
;
750 apic_set_reg(apic
, APIC_SPIV
, val
& mask
);
751 if (!(val
& APIC_SPIV_APIC_ENABLED
)) {
755 for (i
= 0; i
< APIC_LVT_NUM
; i
++) {
756 lvt_val
= apic_get_reg(apic
,
757 APIC_LVTT
+ 0x10 * i
);
758 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
,
759 lvt_val
| APIC_LVT_MASKED
);
761 atomic_set(&apic
->lapic_timer
.pending
, 0);
767 /* No delay here, so we always clear the pending bit */
768 apic_set_reg(apic
, APIC_ICR
, val
& ~(1 << 12));
773 if (!apic_x2apic_mode(apic
))
775 apic_set_reg(apic
, APIC_ICR2
, val
);
779 apic_manage_nmi_watchdog(apic
, val
);
785 /* TODO: Check vector */
786 if (!apic_sw_enabled(apic
))
787 val
|= APIC_LVT_MASKED
;
789 val
&= apic_lvt_mask
[(reg
- APIC_LVTT
) >> 4];
790 apic_set_reg(apic
, reg
, val
);
795 hrtimer_cancel(&apic
->lapic_timer
.timer
);
796 apic_set_reg(apic
, APIC_TMICT
, val
);
797 start_apic_timer(apic
);
802 printk(KERN_ERR
"KVM_WRITE:TDCR %x\n", val
);
803 apic_set_reg(apic
, APIC_TDCR
, val
);
804 update_divide_count(apic
);
808 if (apic_x2apic_mode(apic
) && val
!= 0) {
809 printk(KERN_ERR
"KVM_WRITE:ESR not zero %x\n", val
);
815 if (apic_x2apic_mode(apic
)) {
816 apic_reg_write(apic
, APIC_ICR
, 0x40000 | (val
& 0xff));
825 apic_debug("Local APIC Write to read-only register %x\n", reg
);
829 static int apic_mmio_write(struct kvm_io_device
*this,
830 gpa_t address
, int len
, const void *data
)
832 struct kvm_lapic
*apic
= to_lapic(this);
833 unsigned int offset
= address
- apic
->base_address
;
836 if (!apic_mmio_in_range(apic
, address
))
840 * APIC register must be aligned on 128-bits boundary.
841 * 32/64/128 bits registers must be accessed thru 32 bits.
844 if (len
!= 4 || (offset
& 0xf)) {
845 /* Don't shout loud, $infamous_os would cause only noise. */
846 apic_debug("apic write: bad size=%d %lx\n", len
, (long)address
);
852 /* too common printing */
853 if (offset
!= APIC_EOI
)
854 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
855 "0x%x\n", __func__
, offset
, len
, val
);
857 apic_reg_write(apic
, offset
& 0xff0, val
);
862 void kvm_free_lapic(struct kvm_vcpu
*vcpu
)
864 if (!vcpu
->arch
.apic
)
867 hrtimer_cancel(&vcpu
->arch
.apic
->lapic_timer
.timer
);
869 if (vcpu
->arch
.apic
->regs_page
)
870 __free_page(vcpu
->arch
.apic
->regs_page
);
872 kfree(vcpu
->arch
.apic
);
876 *----------------------------------------------------------------------
878 *----------------------------------------------------------------------
881 void kvm_lapic_set_tpr(struct kvm_vcpu
*vcpu
, unsigned long cr8
)
883 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
887 apic_set_tpr(apic
, ((cr8
& 0x0f) << 4)
888 | (apic_get_reg(apic
, APIC_TASKPRI
) & 4));
891 u64
kvm_lapic_get_cr8(struct kvm_vcpu
*vcpu
)
893 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
898 tpr
= (u64
) apic_get_reg(apic
, APIC_TASKPRI
);
900 return (tpr
& 0xf0) >> 4;
903 void kvm_lapic_set_base(struct kvm_vcpu
*vcpu
, u64 value
)
905 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
908 value
|= MSR_IA32_APICBASE_BSP
;
909 vcpu
->arch
.apic_base
= value
;
913 if (!kvm_vcpu_is_bsp(apic
->vcpu
))
914 value
&= ~MSR_IA32_APICBASE_BSP
;
916 vcpu
->arch
.apic_base
= value
;
917 if (apic_x2apic_mode(apic
)) {
918 u32 id
= kvm_apic_id(apic
);
919 u32 ldr
= ((id
& ~0xf) << 16) | (1 << (id
& 0xf));
920 apic_set_reg(apic
, APIC_LDR
, ldr
);
922 apic
->base_address
= apic
->vcpu
->arch
.apic_base
&
923 MSR_IA32_APICBASE_BASE
;
925 /* with FSB delivery interrupt, we can restart APIC functionality */
926 apic_debug("apic base msr is 0x%016" PRIx64
", and base address is "
927 "0x%lx.\n", apic
->vcpu
->arch
.apic_base
, apic
->base_address
);
931 void kvm_lapic_reset(struct kvm_vcpu
*vcpu
)
933 struct kvm_lapic
*apic
;
936 apic_debug("%s\n", __func__
);
939 apic
= vcpu
->arch
.apic
;
940 ASSERT(apic
!= NULL
);
942 /* Stop the timer in case it's a reset to an active apic */
943 hrtimer_cancel(&apic
->lapic_timer
.timer
);
945 apic_set_reg(apic
, APIC_ID
, vcpu
->vcpu_id
<< 24);
946 kvm_apic_set_version(apic
->vcpu
);
948 for (i
= 0; i
< APIC_LVT_NUM
; i
++)
949 apic_set_reg(apic
, APIC_LVTT
+ 0x10 * i
, APIC_LVT_MASKED
);
950 apic_set_reg(apic
, APIC_LVT0
,
951 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT
));
953 apic_set_reg(apic
, APIC_DFR
, 0xffffffffU
);
954 apic_set_reg(apic
, APIC_SPIV
, 0xff);
955 apic_set_reg(apic
, APIC_TASKPRI
, 0);
956 apic_set_reg(apic
, APIC_LDR
, 0);
957 apic_set_reg(apic
, APIC_ESR
, 0);
958 apic_set_reg(apic
, APIC_ICR
, 0);
959 apic_set_reg(apic
, APIC_ICR2
, 0);
960 apic_set_reg(apic
, APIC_TDCR
, 0);
961 apic_set_reg(apic
, APIC_TMICT
, 0);
962 for (i
= 0; i
< 8; i
++) {
963 apic_set_reg(apic
, APIC_IRR
+ 0x10 * i
, 0);
964 apic_set_reg(apic
, APIC_ISR
+ 0x10 * i
, 0);
965 apic_set_reg(apic
, APIC_TMR
+ 0x10 * i
, 0);
967 apic
->irr_pending
= false;
968 update_divide_count(apic
);
969 atomic_set(&apic
->lapic_timer
.pending
, 0);
970 if (kvm_vcpu_is_bsp(vcpu
))
971 vcpu
->arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
972 apic_update_ppr(apic
);
974 vcpu
->arch
.apic_arb_prio
= 0;
976 apic_debug(KERN_INFO
"%s: vcpu=%p, id=%d, base_msr="
977 "0x%016" PRIx64
", base_address=0x%0lx.\n", __func__
,
978 vcpu
, kvm_apic_id(apic
),
979 vcpu
->arch
.apic_base
, apic
->base_address
);
982 bool kvm_apic_present(struct kvm_vcpu
*vcpu
)
984 return vcpu
->arch
.apic
&& apic_hw_enabled(vcpu
->arch
.apic
);
987 int kvm_lapic_enabled(struct kvm_vcpu
*vcpu
)
989 return kvm_apic_present(vcpu
) && apic_sw_enabled(vcpu
->arch
.apic
);
993 *----------------------------------------------------------------------
995 *----------------------------------------------------------------------
998 static bool lapic_is_periodic(struct kvm_timer
*ktimer
)
1000 struct kvm_lapic
*apic
= container_of(ktimer
, struct kvm_lapic
,
1002 return apic_lvtt_period(apic
);
1005 int apic_has_pending_timer(struct kvm_vcpu
*vcpu
)
1007 struct kvm_lapic
*lapic
= vcpu
->arch
.apic
;
1009 if (lapic
&& apic_enabled(lapic
) && apic_lvt_enabled(lapic
, APIC_LVTT
))
1010 return atomic_read(&lapic
->lapic_timer
.pending
);
1015 static int kvm_apic_local_deliver(struct kvm_lapic
*apic
, int lvt_type
)
1017 u32 reg
= apic_get_reg(apic
, lvt_type
);
1018 int vector
, mode
, trig_mode
;
1020 if (apic_hw_enabled(apic
) && !(reg
& APIC_LVT_MASKED
)) {
1021 vector
= reg
& APIC_VECTOR_MASK
;
1022 mode
= reg
& APIC_MODE_MASK
;
1023 trig_mode
= reg
& APIC_LVT_LEVEL_TRIGGER
;
1024 return __apic_accept_irq(apic
, mode
, vector
, 1, trig_mode
);
1029 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu
*vcpu
)
1031 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1034 kvm_apic_local_deliver(apic
, APIC_LVT0
);
1037 static struct kvm_timer_ops lapic_timer_ops
= {
1038 .is_periodic
= lapic_is_periodic
,
1041 static const struct kvm_io_device_ops apic_mmio_ops
= {
1042 .read
= apic_mmio_read
,
1043 .write
= apic_mmio_write
,
1046 int kvm_create_lapic(struct kvm_vcpu
*vcpu
)
1048 struct kvm_lapic
*apic
;
1050 ASSERT(vcpu
!= NULL
);
1051 apic_debug("apic_init %d\n", vcpu
->vcpu_id
);
1053 apic
= kzalloc(sizeof(*apic
), GFP_KERNEL
);
1057 vcpu
->arch
.apic
= apic
;
1059 apic
->regs_page
= alloc_page(GFP_KERNEL
);
1060 if (apic
->regs_page
== NULL
) {
1061 printk(KERN_ERR
"malloc apic regs error for vcpu %x\n",
1063 goto nomem_free_apic
;
1065 apic
->regs
= page_address(apic
->regs_page
);
1066 memset(apic
->regs
, 0, PAGE_SIZE
);
1069 hrtimer_init(&apic
->lapic_timer
.timer
, CLOCK_MONOTONIC
,
1071 apic
->lapic_timer
.timer
.function
= kvm_timer_fn
;
1072 apic
->lapic_timer
.t_ops
= &lapic_timer_ops
;
1073 apic
->lapic_timer
.kvm
= vcpu
->kvm
;
1074 apic
->lapic_timer
.vcpu
= vcpu
;
1076 apic
->base_address
= APIC_DEFAULT_PHYS_BASE
;
1077 vcpu
->arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
;
1079 kvm_lapic_reset(vcpu
);
1080 kvm_iodevice_init(&apic
->dev
, &apic_mmio_ops
);
1089 int kvm_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
1091 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1094 if (!apic
|| !apic_enabled(apic
))
1097 apic_update_ppr(apic
);
1098 highest_irr
= apic_find_highest_irr(apic
);
1099 if ((highest_irr
== -1) ||
1100 ((highest_irr
& 0xF0) <= apic_get_reg(apic
, APIC_PROCPRI
)))
1105 int kvm_apic_accept_pic_intr(struct kvm_vcpu
*vcpu
)
1107 u32 lvt0
= apic_get_reg(vcpu
->arch
.apic
, APIC_LVT0
);
1110 if (!apic_hw_enabled(vcpu
->arch
.apic
))
1112 if ((lvt0
& APIC_LVT_MASKED
) == 0 &&
1113 GET_APIC_DELIVERY_MODE(lvt0
) == APIC_MODE_EXTINT
)
1118 void kvm_inject_apic_timer_irqs(struct kvm_vcpu
*vcpu
)
1120 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1122 if (apic
&& atomic_read(&apic
->lapic_timer
.pending
) > 0) {
1123 if (kvm_apic_local_deliver(apic
, APIC_LVTT
))
1124 atomic_dec(&apic
->lapic_timer
.pending
);
1128 int kvm_get_apic_interrupt(struct kvm_vcpu
*vcpu
)
1130 int vector
= kvm_apic_has_interrupt(vcpu
);
1131 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1136 apic_set_vector(vector
, apic
->regs
+ APIC_ISR
);
1137 apic_update_ppr(apic
);
1138 apic_clear_irr(vector
, apic
);
1142 void kvm_apic_post_state_restore(struct kvm_vcpu
*vcpu
)
1144 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1146 apic
->base_address
= vcpu
->arch
.apic_base
&
1147 MSR_IA32_APICBASE_BASE
;
1148 kvm_apic_set_version(vcpu
);
1150 apic_update_ppr(apic
);
1151 hrtimer_cancel(&apic
->lapic_timer
.timer
);
1152 update_divide_count(apic
);
1153 start_apic_timer(apic
);
1154 apic
->irr_pending
= true;
1157 void __kvm_migrate_apic_timer(struct kvm_vcpu
*vcpu
)
1159 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1160 struct hrtimer
*timer
;
1165 timer
= &apic
->lapic_timer
.timer
;
1166 if (hrtimer_cancel(timer
))
1167 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS
);
1170 void kvm_lapic_sync_from_vapic(struct kvm_vcpu
*vcpu
)
1175 if (!irqchip_in_kernel(vcpu
->kvm
) || !vcpu
->arch
.apic
->vapic_addr
)
1178 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
, KM_USER0
);
1179 data
= *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
));
1180 kunmap_atomic(vapic
, KM_USER0
);
1182 apic_set_tpr(vcpu
->arch
.apic
, data
& 0xff);
1185 void kvm_lapic_sync_to_vapic(struct kvm_vcpu
*vcpu
)
1188 int max_irr
, max_isr
;
1189 struct kvm_lapic
*apic
;
1192 if (!irqchip_in_kernel(vcpu
->kvm
) || !vcpu
->arch
.apic
->vapic_addr
)
1195 apic
= vcpu
->arch
.apic
;
1196 tpr
= apic_get_reg(apic
, APIC_TASKPRI
) & 0xff;
1197 max_irr
= apic_find_highest_irr(apic
);
1200 max_isr
= apic_find_highest_isr(apic
);
1203 data
= (tpr
& 0xff) | ((max_isr
& 0xf0) << 8) | (max_irr
<< 24);
1205 vapic
= kmap_atomic(vcpu
->arch
.apic
->vapic_page
, KM_USER0
);
1206 *(u32
*)(vapic
+ offset_in_page(vcpu
->arch
.apic
->vapic_addr
)) = data
;
1207 kunmap_atomic(vapic
, KM_USER0
);
1210 void kvm_lapic_set_vapic_addr(struct kvm_vcpu
*vcpu
, gpa_t vapic_addr
)
1212 if (!irqchip_in_kernel(vcpu
->kvm
))
1215 vcpu
->arch
.apic
->vapic_addr
= vapic_addr
;
1218 int kvm_x2apic_msr_write(struct kvm_vcpu
*vcpu
, u32 msr
, u64 data
)
1220 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1221 u32 reg
= (msr
- APIC_BASE_MSR
) << 4;
1223 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1226 /* if this is ICR write vector before command */
1228 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1229 return apic_reg_write(apic
, reg
, (u32
)data
);
1232 int kvm_x2apic_msr_read(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
1234 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1235 u32 reg
= (msr
- APIC_BASE_MSR
) << 4, low
, high
= 0;
1237 if (!irqchip_in_kernel(vcpu
->kvm
) || !apic_x2apic_mode(apic
))
1240 if (apic_reg_read(apic
, reg
, 4, &low
))
1243 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1245 *data
= (((u64
)high
) << 32) | low
;
1250 int kvm_hv_vapic_msr_write(struct kvm_vcpu
*vcpu
, u32 reg
, u64 data
)
1252 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1254 if (!irqchip_in_kernel(vcpu
->kvm
))
1257 /* if this is ICR write vector before command */
1258 if (reg
== APIC_ICR
)
1259 apic_reg_write(apic
, APIC_ICR2
, (u32
)(data
>> 32));
1260 return apic_reg_write(apic
, reg
, (u32
)data
);
1263 int kvm_hv_vapic_msr_read(struct kvm_vcpu
*vcpu
, u32 reg
, u64
*data
)
1265 struct kvm_lapic
*apic
= vcpu
->arch
.apic
;
1268 if (!irqchip_in_kernel(vcpu
->kvm
))
1271 if (apic_reg_read(apic
, reg
, 4, &low
))
1273 if (reg
== APIC_ICR
)
1274 apic_reg_read(apic
, APIC_ICR2
, 4, &high
);
1276 *data
= (((u64
)high
) << 32) | low
;