drivers/video/geode/display_gx1.h

   1 /*
   2  * drivers/video/geode/display_gx1.h
   3  *   -- Geode GX1 display controller
   4  *
   5  * Copyright (C) 2005 Arcom Control Systems Ltd.
   6  *
   7  * Based on AMD's original 2.4 driver:
   8  *   Copyright (C) 2004 Advanced Micro Devices, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15 #ifndef __DISPLAY_GX1_H__
  16 #define __DISPLAY_GX1_H__
  17
  18 unsigned gx1_gx_base(void);
  19 int gx1_frame_buffer_size(void);
  20
  21 extern struct geode_dc_ops gx1_dc_ops;
  22
  23 /* GX1 configuration I/O registers */
  24
  25 #define CONFIG_CCR3 0xc3
  26 #  define CONFIG_CCR3_MAPEN 0x10
  27 #define CONFIG_GCR  0xb8
  28
  29 /* Memory controller registers */
  30
  31 #define MC_BANK_CFG             0x08
  32 #  define MC_BCFG_DIMM0_SZ_MASK         0x00000700
  33 #  define MC_BCFG_DIMM0_PG_SZ_MASK      0x00000070
  34 #  define MC_BCFG_DIMM0_PG_SZ_NO_DIMM   0x00000070
  35
  36 #define MC_GBASE_ADD            0x14
  37 #  define MC_GADD_GBADD_MASK            0x000003ff
  38
  39 /* Display controller registers */
  40
  41 #define DC_PAL_ADDRESS          0x70
  42 #define DC_PAL_DATA             0x74
  43
  44 #define DC_UNLOCK               0x00
  45 #  define DC_UNLOCK_CODE                0x00004758
  46
  47 #define DC_GENERAL_CFG          0x04
  48 #  define DC_GCFG_DFLE                  0x00000001
  49 #  define DC_GCFG_CURE                  0x00000002
  50 #  define DC_GCFG_VCLK_DIV              0x00000004
  51 #  define DC_GCFG_PLNO                  0x00000004
  52 #  define DC_GCFG_PPC                   0x00000008
  53 #  define DC_GCFG_CMPE                  0x00000010
  54 #  define DC_GCFG_DECE                  0x00000020
  55 #  define DC_GCFG_DCLK_MASK             0x000000C0
  56 #  define DC_GCFG_DCLK_DIV_1            0x00000080
  57 #  define DC_GCFG_DFHPSL_MASK           0x00000F00
  58 #  define DC_GCFG_DFHPSL_POS                     8
  59 #  define DC_GCFG_DFHPEL_MASK           0x0000F000
  60 #  define DC_GCFG_DFHPEL_POS                    12
  61 #  define DC_GCFG_CIM_MASK              0x00030000
  62 #  define DC_GCFG_CIM_POS                       16
  63 #  define DC_GCFG_FDTY                  0x00040000
  64 #  define DC_GCFG_RTPM                  0x00080000
  65 #  define DC_GCFG_DAC_RS_MASK           0x00700000
  66 #  define DC_GCFG_DAC_RS_POS                    20
  67 #  define DC_GCFG_CKWR                  0x00800000
  68 #  define DC_GCFG_LDBL                  0x01000000
  69 #  define DC_GCFG_DIAG                  0x02000000
  70 #  define DC_GCFG_CH4S                  0x04000000
  71 #  define DC_GCFG_SSLC                  0x08000000
  72 #  define DC_GCFG_VIDE                  0x10000000
  73 #  define DC_GCFG_VRDY                  0x20000000
  74 #  define DC_GCFG_DPCK                  0x40000000
  75 #  define DC_GCFG_DDCK                  0x80000000
  76
  77 #define DC_TIMING_CFG           0x08
  78 #  define DC_TCFG_FPPE                  0x00000001
  79 #  define DC_TCFG_HSYE                  0x00000002
  80 #  define DC_TCFG_VSYE                  0x00000004
  81 #  define DC_TCFG_BLKE                  0x00000008
  82 #  define DC_TCFG_DDCK                  0x00000010
  83 #  define DC_TCFG_TGEN                  0x00000020
  84 #  define DC_TCFG_VIEN                  0x00000040
  85 #  define DC_TCFG_BLNK                  0x00000080
  86 #  define DC_TCFG_CHSP                  0x00000100
  87 #  define DC_TCFG_CVSP                  0x00000200
  88 #  define DC_TCFG_FHSP                  0x00000400
  89 #  define DC_TCFG_FVSP                  0x00000800
  90 #  define DC_TCFG_FCEN                  0x00001000
  91 #  define DC_TCFG_CDCE                  0x00002000
  92 #  define DC_TCFG_PLNR                  0x00002000
  93 #  define DC_TCFG_INTL                  0x00004000
  94 #  define DC_TCFG_PXDB                  0x00008000
  95 #  define DC_TCFG_BKRT                  0x00010000
  96 #  define DC_TCFG_PSD_MASK              0x000E0000
  97 #  define DC_TCFG_PSD_POS                       17
  98 #  define DC_TCFG_DDCI                  0x08000000
  99 #  define DC_TCFG_SENS                  0x10000000
 100 #  define DC_TCFG_DNA                   0x20000000
 101 #  define DC_TCFG_VNA                   0x40000000
 102 #  define DC_TCFG_VINT                  0x80000000
 103
 104 #define DC_OUTPUT_CFG           0x0C
 105 #  define DC_OCFG_8BPP                  0x00000001
 106 #  define DC_OCFG_555                   0x00000002
 107 #  define DC_OCFG_PCKE                  0x00000004
 108 #  define DC_OCFG_FRME                  0x00000008
 109 #  define DC_OCFG_DITE                  0x00000010
 110 #  define DC_OCFG_2PXE                  0x00000020
 111 #  define DC_OCFG_2XCK                  0x00000040
 112 #  define DC_OCFG_2IND                  0x00000080
 113 #  define DC_OCFG_34ADD                 0x00000100
 114 #  define DC_OCFG_FRMS                  0x00000200
 115 #  define DC_OCFG_CKSL                  0x00000400
 116 #  define DC_OCFG_PRMP                  0x00000800
 117 #  define DC_OCFG_PDEL                  0x00001000
 118 #  define DC_OCFG_PDEH                  0x00002000
 119 #  define DC_OCFG_CFRW                  0x00004000
 120 #  define DC_OCFG_DIAG                  0x00008000
 121
 122 #define DC_FB_ST_OFFSET         0x10
 123 #define DC_CB_ST_OFFSET         0x14
 124 #define DC_CURS_ST_OFFSET       0x18
 125 #define DC_ICON_ST_OFFSET       0x1C
 126 #define DC_VID_ST_OFFSET        0x20
 127 #define DC_LINE_DELTA           0x24
 128 #define DC_BUF_SIZE             0x28
 129
 130 #define DC_H_TIMING_1           0x30
 131 #define DC_H_TIMING_2           0x34
 132 #define DC_H_TIMING_3           0x38
 133 #define DC_FP_H_TIMING          0x3C
 134
 135 #define DC_V_TIMING_1           0x40
 136 #define DC_V_TIMING_2           0x44
 137 #define DC_V_TIMING_3           0x48
 138 #define DC_FP_V_TIMING          0x4C
 139
 140 #define DC_CURSOR_X             0x50
 141 #define DC_ICON_X               0x54
 142 #define DC_V_LINE_CNT           0x54
 143 #define DC_CURSOR_Y             0x58
 144 #define DC_ICON_Y               0x5C
 145 #define DC_SS_LINE_CMP          0x5C
 146 #define DC_CURSOR_COLOR         0x60
 147 #define DC_ICON_COLOR           0x64
 148 #define DC_BORDER_COLOR         0x68
 149 #define DC_PAL_ADDRESS          0x70
 150 #define DC_PAL_DATA             0x74
 151 #define DC_DFIFO_DIAG           0x78
 152 #define DC_CFIFO_DIAG           0x7C
 153
 154 #endif /* !__DISPLAY_GX1_H__ */