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E100: work around the driver using streaming DMA mapping for RX descriptors.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e100.c
blob014dfb679856e68f8eeac80073e7e60fbbb60242
1 /*******************************************************************************
2
3 Intel PRO/100 Linux driver
4 Copyright(c) 1999 - 2006 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * e100.c: Intel(R) PRO/100 ethernet driver
31 *
32 * (Re)written 2003 by scott.feldman@intel.com. Based loosely on
33 * original e100 driver, but better described as a munging of
34 * e100, e1000, eepro100, tg3, 8139cp, and other drivers.
35 *
36 * References:
37 * Intel 8255x 10/100 Mbps Ethernet Controller Family,
38 * Open Source Software Developers Manual,
39 * http://sourceforge.net/projects/e1000
40 *
41 *
42 * Theory of Operation
43 *
44 * I. General
45 *
46 * The driver supports Intel(R) 10/100 Mbps PCI Fast Ethernet
47 * controller family, which includes the 82557, 82558, 82559, 82550,
48 * 82551, and 82562 devices. 82558 and greater controllers
49 * integrate the Intel 82555 PHY. The controllers are used in
50 * server and client network interface cards, as well as in
51 * LAN-On-Motherboard (LOM), CardBus, MiniPCI, and ICHx
52 * configurations. 8255x supports a 32-bit linear addressing
53 * mode and operates at 33Mhz PCI clock rate.
54 *
55 * II. Driver Operation
56 *
57 * Memory-mapped mode is used exclusively to access the device's
58 * shared-memory structure, the Control/Status Registers (CSR). All
59 * setup, configuration, and control of the device, including queuing
60 * of Tx, Rx, and configuration commands is through the CSR.
61 * cmd_lock serializes accesses to the CSR command register. cb_lock
62 * protects the shared Command Block List (CBL).
63 *
64 * 8255x is highly MII-compliant and all access to the PHY go
65 * through the Management Data Interface (MDI). Consequently, the
66 * driver leverages the mii.c library shared with other MII-compliant
67 * devices.
68 *
69 * Big- and Little-Endian byte order as well as 32- and 64-bit
70 * archs are supported. Weak-ordered memory and non-cache-coherent
71 * archs are supported.
72 *
73 * III. Transmit
74 *
75 * A Tx skb is mapped and hangs off of a TCB. TCBs are linked
76 * together in a fixed-size ring (CBL) thus forming the flexible mode
77 * memory structure. A TCB marked with the suspend-bit indicates
78 * the end of the ring. The last TCB processed suspends the
79 * controller, and the controller can be restarted by issue a CU
80 * resume command to continue from the suspend point, or a CU start
81 * command to start at a given position in the ring.
82 *
83 * Non-Tx commands (config, multicast setup, etc) are linked
84 * into the CBL ring along with Tx commands. The common structure
85 * used for both Tx and non-Tx commands is the Command Block (CB).
86 *
87 * cb_to_use is the next CB to use for queuing a command; cb_to_clean
88 * is the next CB to check for completion; cb_to_send is the first
89 * CB to start on in case of a previous failure to resume. CB clean
90 * up happens in interrupt context in response to a CU interrupt.
91 * cbs_avail keeps track of number of free CB resources available.
92 *
93 * Hardware padding of short packets to minimum packet size is
94 * enabled. 82557 pads with 7Eh, while the later controllers pad
95 * with 00h.
96 *
97 * IV. Receive
98 *
99 * The Receive Frame Area (RFA) comprises a ring of Receive Frame
100 * Descriptors (RFD) + data buffer, thus forming the simplified mode
101 * memory structure. Rx skbs are allocated to contain both the RFD
102 * and the data buffer, but the RFD is pulled off before the skb is
103 * indicated. The data buffer is aligned such that encapsulated
104 * protocol headers are u32-aligned. Since the RFD is part of the
105 * mapped shared memory, and completion status is contained within
106 * the RFD, the RFD must be dma_sync'ed to maintain a consistent
107 * view from software and hardware.
108 *
109 * In order to keep updates to the RFD link field from colliding with
110 * hardware writes to mark packets complete, we use the feature that
111 * hardware will not write to a size 0 descriptor and mark the previous
112 * packet as end-of-list (EL). After updating the link, we remove EL
113 * and only then restore the size such that hardware may use the
114 * previous-to-end RFD.
115 *
116 * Under typical operation, the receive unit (RU) is start once,
117 * and the controller happily fills RFDs as frames arrive. If
118 * replacement RFDs cannot be allocated, or the RU goes non-active,
119 * the RU must be restarted. Frame arrival generates an interrupt,
120 * and Rx indication and re-allocation happen in the same context,
121 * therefore no locking is required. A software-generated interrupt
122 * is generated from the watchdog to recover from a failed allocation
123 * scenario where all Rx resources have been indicated and none re-
124 * placed.
125 *
126 * V. Miscellaneous
127 *
128 * VLAN offloading of tagging, stripping and filtering is not
129 * supported, but driver will accommodate the extra 4-byte VLAN tag
130 * for processing by upper layers. Tx/Rx Checksum offloading is not
131 * supported. Tx Scatter/Gather is not supported. Jumbo Frames is
132 * not supported (hardware limitation).
133 *
134 * MagicPacket(tm) WoL support is enabled/disabled via ethtool.
135 *
136 * Thanks to JC (jchapman@katalix.com) for helping with
137 * testing/troubleshooting the development driver.
138 *
139 * TODO:
140 * o several entry points race with dev->close
141 * o check for tx-no-resources/stop Q races with tx clean/wake Q
142 *
143 * FIXES:
144 * 2005/12/02 - Michael O'Donnell <Michael.ODonnell at stratus dot com>
145 * - Stratus87247: protect MDI control register manipulations
146 */
147
148 #include <linux/module.h>
149 #include <linux/moduleparam.h>
150 #include <linux/kernel.h>
151 #include <linux/types.h>
152 #include <linux/slab.h>
153 #include <linux/delay.h>
154 #include <linux/init.h>
155 #include <linux/pci.h>
156 #include <linux/dma-mapping.h>
157 #include <linux/netdevice.h>
158 #include <linux/etherdevice.h>
159 #include <linux/mii.h>
160 #include <linux/if_vlan.h>
161 #include <linux/skbuff.h>
162 #include <linux/ethtool.h>
163 #include <linux/string.h>
164 #include <linux/firmware.h>
165 #include <asm/unaligned.h>
166
167
168 #define DRV_NAME "e100"
169 #define DRV_EXT "-NAPI"
170 #define DRV_VERSION "3.5.24-k2"DRV_EXT
171 #define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
172 #define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
173 #define PFX DRV_NAME ": "
174
175 #define E100_WATCHDOG_PERIOD (2 * HZ)
176 #define E100_NAPI_WEIGHT 16
177
178 #define FIRMWARE_D101M "e100/d101m_ucode.bin"
179 #define FIRMWARE_D101S "e100/d101s_ucode.bin"
180 #define FIRMWARE_D102E "e100/d102e_ucode.bin"
181
182 MODULE_DESCRIPTION(DRV_DESCRIPTION);
183 MODULE_AUTHOR(DRV_COPYRIGHT);
184 MODULE_LICENSE("GPL");
185 MODULE_VERSION(DRV_VERSION);
186 MODULE_FIRMWARE(FIRMWARE_D101M);
187 MODULE_FIRMWARE(FIRMWARE_D101S);
188 MODULE_FIRMWARE(FIRMWARE_D102E);
189
190 static int debug = 3;
191 static int eeprom_bad_csum_allow = 0;
192 static int use_io = 0;
193 module_param(debug, int, 0);
194 module_param(eeprom_bad_csum_allow, int, 0);
195 module_param(use_io, int, 0);
196 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
197 MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
198 MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
199 #define DPRINTK(nlevel, klevel, fmt, args...) \
200 (void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
201 printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
202 __func__ , ## args))
203
204 #define INTEL_8255X_ETHERNET_DEVICE(device_id, ich) {\
205 PCI_VENDOR_ID_INTEL, device_id, PCI_ANY_ID, PCI_ANY_ID, \
206 PCI_CLASS_NETWORK_ETHERNET << 8, 0xFFFF00, ich }
207 static struct pci_device_id e100_id_table[] = {
208 INTEL_8255X_ETHERNET_DEVICE(0x1029, 0),
209 INTEL_8255X_ETHERNET_DEVICE(0x1030, 0),
210 INTEL_8255X_ETHERNET_DEVICE(0x1031, 3),
211 INTEL_8255X_ETHERNET_DEVICE(0x1032, 3),
212 INTEL_8255X_ETHERNET_DEVICE(0x1033, 3),
213 INTEL_8255X_ETHERNET_DEVICE(0x1034, 3),
214 INTEL_8255X_ETHERNET_DEVICE(0x1038, 3),
215 INTEL_8255X_ETHERNET_DEVICE(0x1039, 4),
216 INTEL_8255X_ETHERNET_DEVICE(0x103A, 4),
217 INTEL_8255X_ETHERNET_DEVICE(0x103B, 4),
218 INTEL_8255X_ETHERNET_DEVICE(0x103C, 4),
219 INTEL_8255X_ETHERNET_DEVICE(0x103D, 4),
220 INTEL_8255X_ETHERNET_DEVICE(0x103E, 4),
221 INTEL_8255X_ETHERNET_DEVICE(0x1050, 5),
222 INTEL_8255X_ETHERNET_DEVICE(0x1051, 5),
223 INTEL_8255X_ETHERNET_DEVICE(0x1052, 5),
224 INTEL_8255X_ETHERNET_DEVICE(0x1053, 5),
225 INTEL_8255X_ETHERNET_DEVICE(0x1054, 5),
226 INTEL_8255X_ETHERNET_DEVICE(0x1055, 5),
227 INTEL_8255X_ETHERNET_DEVICE(0x1056, 5),
228 INTEL_8255X_ETHERNET_DEVICE(0x1057, 5),
229 INTEL_8255X_ETHERNET_DEVICE(0x1059, 0),
230 INTEL_8255X_ETHERNET_DEVICE(0x1064, 6),
231 INTEL_8255X_ETHERNET_DEVICE(0x1065, 6),
232 INTEL_8255X_ETHERNET_DEVICE(0x1066, 6),
233 INTEL_8255X_ETHERNET_DEVICE(0x1067, 6),
234 INTEL_8255X_ETHERNET_DEVICE(0x1068, 6),
235 INTEL_8255X_ETHERNET_DEVICE(0x1069, 6),
236 INTEL_8255X_ETHERNET_DEVICE(0x106A, 6),
237 INTEL_8255X_ETHERNET_DEVICE(0x106B, 6),
238 INTEL_8255X_ETHERNET_DEVICE(0x1091, 7),
239 INTEL_8255X_ETHERNET_DEVICE(0x1092, 7),
240 INTEL_8255X_ETHERNET_DEVICE(0x1093, 7),
241 INTEL_8255X_ETHERNET_DEVICE(0x1094, 7),
242 INTEL_8255X_ETHERNET_DEVICE(0x1095, 7),
243 INTEL_8255X_ETHERNET_DEVICE(0x10fe, 7),
244 INTEL_8255X_ETHERNET_DEVICE(0x1209, 0),
245 INTEL_8255X_ETHERNET_DEVICE(0x1229, 0),
246 INTEL_8255X_ETHERNET_DEVICE(0x2449, 2),
247 INTEL_8255X_ETHERNET_DEVICE(0x2459, 2),
248 INTEL_8255X_ETHERNET_DEVICE(0x245D, 2),
249 INTEL_8255X_ETHERNET_DEVICE(0x27DC, 7),
250 { 0, }
251 };
252 MODULE_DEVICE_TABLE(pci, e100_id_table);
253
254 enum mac {
255 mac_82557_D100_A = 0,
256 mac_82557_D100_B = 1,
257 mac_82557_D100_C = 2,
258 mac_82558_D101_A4 = 4,
259 mac_82558_D101_B0 = 5,
260 mac_82559_D101M = 8,
261 mac_82559_D101S = 9,
262 mac_82550_D102 = 12,
263 mac_82550_D102_C = 13,
264 mac_82551_E = 14,
265 mac_82551_F = 15,
266 mac_82551_10 = 16,
267 mac_unknown = 0xFF,
268 };
269
270 enum phy {
271 phy_100a = 0x000003E0,
272 phy_100c = 0x035002A8,
273 phy_82555_tx = 0x015002A8,
274 phy_nsc_tx = 0x5C002000,
275 phy_82562_et = 0x033002A8,
276 phy_82562_em = 0x032002A8,
277 phy_82562_ek = 0x031002A8,
278 phy_82562_eh = 0x017002A8,
279 phy_82552_v = 0xd061004d,
280 phy_unknown = 0xFFFFFFFF,
281 };
282
283 /* CSR (Control/Status Registers) */
284 struct csr {
285 struct {
286 u8 status;
287 u8 stat_ack;
288 u8 cmd_lo;
289 u8 cmd_hi;
290 u32 gen_ptr;
291 } scb;
292 u32 port;
293 u16 flash_ctrl;
294 u8 eeprom_ctrl_lo;
295 u8 eeprom_ctrl_hi;
296 u32 mdi_ctrl;
297 u32 rx_dma_count;
298 };
299
300 enum scb_status {
301 rus_no_res = 0x08,
302 rus_ready = 0x10,
303 rus_mask = 0x3C,
304 };
305
306 enum ru_state {
307 RU_SUSPENDED = 0,
308 RU_RUNNING = 1,
309 RU_UNINITIALIZED = -1,
310 };
311
312 enum scb_stat_ack {
313 stat_ack_not_ours = 0x00,
314 stat_ack_sw_gen = 0x04,
315 stat_ack_rnr = 0x10,
316 stat_ack_cu_idle = 0x20,
317 stat_ack_frame_rx = 0x40,
318 stat_ack_cu_cmd_done = 0x80,
319 stat_ack_not_present = 0xFF,
320 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
321 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
322 };
323
324 enum scb_cmd_hi {
325 irq_mask_none = 0x00,
326 irq_mask_all = 0x01,
327 irq_sw_gen = 0x02,
328 };
329
330 enum scb_cmd_lo {
331 cuc_nop = 0x00,
332 ruc_start = 0x01,
333 ruc_load_base = 0x06,
334 cuc_start = 0x10,
335 cuc_resume = 0x20,
336 cuc_dump_addr = 0x40,
337 cuc_dump_stats = 0x50,
338 cuc_load_base = 0x60,
339 cuc_dump_reset = 0x70,
340 };
341
342 enum cuc_dump {
343 cuc_dump_complete = 0x0000A005,
344 cuc_dump_reset_complete = 0x0000A007,
345 };
346
347 enum port {
348 software_reset = 0x0000,
349 selftest = 0x0001,
350 selective_reset = 0x0002,
351 };
352
353 enum eeprom_ctrl_lo {
354 eesk = 0x01,
355 eecs = 0x02,
356 eedi = 0x04,
357 eedo = 0x08,
358 };
359
360 enum mdi_ctrl {
361 mdi_write = 0x04000000,
362 mdi_read = 0x08000000,
363 mdi_ready = 0x10000000,
364 };
365
366 enum eeprom_op {
367 op_write = 0x05,
368 op_read = 0x06,
369 op_ewds = 0x10,
370 op_ewen = 0x13,
371 };
372
373 enum eeprom_offsets {
374 eeprom_cnfg_mdix = 0x03,
375 eeprom_id = 0x0A,
376 eeprom_config_asf = 0x0D,
377 eeprom_smbus_addr = 0x90,
378 };
379
380 enum eeprom_cnfg_mdix {
381 eeprom_mdix_enabled = 0x0080,
382 };
383
384 enum eeprom_id {
385 eeprom_id_wol = 0x0020,
386 };
387
388 enum eeprom_config_asf {
389 eeprom_asf = 0x8000,
390 eeprom_gcl = 0x4000,
391 };
392
393 enum cb_status {
394 cb_complete = 0x8000,
395 cb_ok = 0x2000,
396 };
397
398 enum cb_command {
399 cb_nop = 0x0000,
400 cb_iaaddr = 0x0001,
401 cb_config = 0x0002,
402 cb_multi = 0x0003,
403 cb_tx = 0x0004,
404 cb_ucode = 0x0005,
405 cb_dump = 0x0006,
406 cb_tx_sf = 0x0008,
407 cb_cid = 0x1f00,
408 cb_i = 0x2000,
409 cb_s = 0x4000,
410 cb_el = 0x8000,
411 };
412
413 struct rfd {
414 __le16 status;
415 __le16 command;
416 __le32 link;
417 __le32 rbd;
418 __le16 actual_size;
419 __le16 size;
420 };
421
422 struct rx {
423 struct rx *next, *prev;
424 struct sk_buff *skb;
425 dma_addr_t dma_addr;
426 };
427
428 #if defined(__BIG_ENDIAN_BITFIELD)
429 #define X(a,b) b,a
430 #else
431 #define X(a,b) a,b
432 #endif
433 struct config {
434 /*0*/ u8 X(byte_count:6, pad0:2);
435 /*1*/ u8 X(X(rx_fifo_limit:4, tx_fifo_limit:3), pad1:1);
436 /*2*/ u8 adaptive_ifs;
437 /*3*/ u8 X(X(X(X(mwi_enable:1, type_enable:1), read_align_enable:1),
438 term_write_cache_line:1), pad3:4);
439 /*4*/ u8 X(rx_dma_max_count:7, pad4:1);
440 /*5*/ u8 X(tx_dma_max_count:7, dma_max_count_enable:1);
441 /*6*/ u8 X(X(X(X(X(X(X(late_scb_update:1, direct_rx_dma:1),
442 tno_intr:1), cna_intr:1), standard_tcb:1), standard_stat_counter:1),
443 rx_discard_overruns:1), rx_save_bad_frames:1);
444 /*7*/ u8 X(X(X(X(X(rx_discard_short_frames:1, tx_underrun_retry:2),
445 pad7:2), rx_extended_rfd:1), tx_two_frames_in_fifo:1),
446 tx_dynamic_tbd:1);
447 /*8*/ u8 X(X(mii_mode:1, pad8:6), csma_disabled:1);
448 /*9*/ u8 X(X(X(X(X(rx_tcpudp_checksum:1, pad9:3), vlan_arp_tco:1),
449 link_status_wake:1), arp_wake:1), mcmatch_wake:1);
450 /*10*/ u8 X(X(X(pad10:3, no_source_addr_insertion:1), preamble_length:2),
451 loopback:2);
452 /*11*/ u8 X(linear_priority:3, pad11:5);
453 /*12*/ u8 X(X(linear_priority_mode:1, pad12:3), ifs:4);
454 /*13*/ u8 ip_addr_lo;
455 /*14*/ u8 ip_addr_hi;
456 /*15*/ u8 X(X(X(X(X(X(X(promiscuous_mode:1, broadcast_disabled:1),
457 wait_after_win:1), pad15_1:1), ignore_ul_bit:1), crc_16_bit:1),
458 pad15_2:1), crs_or_cdt:1);
459 /*16*/ u8 fc_delay_lo;
460 /*17*/ u8 fc_delay_hi;
461 /*18*/ u8 X(X(X(X(X(rx_stripping:1, tx_padding:1), rx_crc_transfer:1),
462 rx_long_ok:1), fc_priority_threshold:3), pad18:1);
463 /*19*/ u8 X(X(X(X(X(X(X(addr_wake:1, magic_packet_disable:1),
464 fc_disable:1), fc_restop:1), fc_restart:1), fc_reject:1),
465 full_duplex_force:1), full_duplex_pin:1);
466 /*20*/ u8 X(X(X(pad20_1:5, fc_priority_location:1), multi_ia:1), pad20_2:1);
467 /*21*/ u8 X(X(pad21_1:3, multicast_all:1), pad21_2:4);
468 /*22*/ u8 X(X(rx_d102_mode:1, rx_vlan_drop:1), pad22:6);
469 u8 pad_d102[9];
470 };
471
472 #define E100_MAX_MULTICAST_ADDRS 64
473 struct multi {
474 __le16 count;
475 u8 addr[E100_MAX_MULTICAST_ADDRS * ETH_ALEN + 2/*pad*/];
476 };
477
478 /* Important: keep total struct u32-aligned */
479 #define UCODE_SIZE 134
480 struct cb {
481 __le16 status;
482 __le16 command;
483 __le32 link;
484 union {
485 u8 iaaddr[ETH_ALEN];
486 __le32 ucode[UCODE_SIZE];
487 struct config config;
488 struct multi multi;
489 struct {
490 u32 tbd_array;
491 u16 tcb_byte_count;
492 u8 threshold;
493 u8 tbd_count;
494 struct {
495 __le32 buf_addr;
496 __le16 size;
497 u16 eol;
498 } tbd;
499 } tcb;
500 __le32 dump_buffer_addr;
501 } u;
502 struct cb *next, *prev;
503 dma_addr_t dma_addr;
504 struct sk_buff *skb;
505 };
506
507 enum loopback {
508 lb_none = 0, lb_mac = 1, lb_phy = 3,
509 };
510
511 struct stats {
512 __le32 tx_good_frames, tx_max_collisions, tx_late_collisions,
513 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
514 tx_multiple_collisions, tx_total_collisions;
515 __le32 rx_good_frames, rx_crc_errors, rx_alignment_errors,
516 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
517 rx_short_frame_errors;
518 __le32 fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
519 __le16 xmt_tco_frames, rcv_tco_frames;
520 __le32 complete;
521 };
522
523 struct mem {
524 struct {
525 u32 signature;
526 u32 result;
527 } selftest;
528 struct stats stats;
529 u8 dump_buf[596];
530 };
531
532 struct param_range {
533 u32 min;
534 u32 max;
535 u32 count;
536 };
537
538 struct params {
539 struct param_range rfds;
540 struct param_range cbs;
541 };
542
543 struct nic {
544 /* Begin: frequently used values: keep adjacent for cache effect */
545 u32 msg_enable ____cacheline_aligned;
546 struct net_device *netdev;
547 struct pci_dev *pdev;
548
549 struct rx *rxs ____cacheline_aligned;
550 struct rx *rx_to_use;
551 struct rx *rx_to_clean;
552 struct rfd blank_rfd;
553 enum ru_state ru_running;
554
555 spinlock_t cb_lock ____cacheline_aligned;
556 spinlock_t cmd_lock;
557 struct csr __iomem *csr;
558 enum scb_cmd_lo cuc_cmd;
559 unsigned int cbs_avail;
560 struct napi_struct napi;
561 struct cb *cbs;
562 struct cb *cb_to_use;
563 struct cb *cb_to_send;
564 struct cb *cb_to_clean;
565 __le16 tx_command;
566 /* End: frequently used values: keep adjacent for cache effect */
567
568 enum {
569 ich = (1 << 0),
570 promiscuous = (1 << 1),
571 multicast_all = (1 << 2),
572 wol_magic = (1 << 3),
573 ich_10h_workaround = (1 << 4),
574 } flags ____cacheline_aligned;
575
576 enum mac mac;
577 enum phy phy;
578 struct params params;
579 struct timer_list watchdog;
580 struct timer_list blink_timer;
581 struct mii_if_info mii;
582 struct work_struct tx_timeout_task;
583 enum loopback loopback;
584
585 struct mem *mem;
586 dma_addr_t dma_addr;
587
588 dma_addr_t cbs_dma_addr;
589 u8 adaptive_ifs;
590 u8 tx_threshold;
591 u32 tx_frames;
592 u32 tx_collisions;
593 u32 tx_deferred;
594 u32 tx_single_collisions;
595 u32 tx_multiple_collisions;
596 u32 tx_fc_pause;
597 u32 tx_tco_frames;
598
599 u32 rx_fc_pause;
600 u32 rx_fc_unsupported;
601 u32 rx_tco_frames;
602 u32 rx_over_length_errors;
603
604 u16 leds;
605 u16 eeprom_wc;
606 __le16 eeprom[256];
607 spinlock_t mdio_lock;
608 };
609
610 static inline void e100_write_flush(struct nic *nic)
611 {
612 /* Flush previous PCI writes through intermediate bridges
613 * by doing a benign read */
614 (void)ioread8(&nic->csr->scb.status);
615 }
616
617 static void e100_enable_irq(struct nic *nic)
618 {
619 unsigned long flags;
620
621 spin_lock_irqsave(&nic->cmd_lock, flags);
622 iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
623 e100_write_flush(nic);
624 spin_unlock_irqrestore(&nic->cmd_lock, flags);
625 }
626
627 static void e100_disable_irq(struct nic *nic)
628 {
629 unsigned long flags;
630
631 spin_lock_irqsave(&nic->cmd_lock, flags);
632 iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
633 e100_write_flush(nic);
634 spin_unlock_irqrestore(&nic->cmd_lock, flags);
635 }
636
637 static void e100_hw_reset(struct nic *nic)
638 {
639 /* Put CU and RU into idle with a selective reset to get
640 * device off of PCI bus */
641 iowrite32(selective_reset, &nic->csr->port);
642 e100_write_flush(nic); udelay(20);
643
644 /* Now fully reset device */
645 iowrite32(software_reset, &nic->csr->port);
646 e100_write_flush(nic); udelay(20);
647
648 /* Mask off our interrupt line - it's unmasked after reset */
649 e100_disable_irq(nic);
650 }
651
652 static int e100_self_test(struct nic *nic)
653 {
654 u32 dma_addr = nic->dma_addr + offsetof(struct mem, selftest);
655
656 /* Passing the self-test is a pretty good indication
657 * that the device can DMA to/from host memory */
658
659 nic->mem->selftest.signature = 0;
660 nic->mem->selftest.result = 0xFFFFFFFF;
661
662 iowrite32(selftest | dma_addr, &nic->csr->port);
663 e100_write_flush(nic);
664 /* Wait 10 msec for self-test to complete */
665 msleep(10);
666
667 /* Interrupts are enabled after self-test */
668 e100_disable_irq(nic);
669
670 /* Check results of self-test */
671 if (nic->mem->selftest.result != 0) {
672 DPRINTK(HW, ERR, "Self-test failed: result=0x%08X\n",
673 nic->mem->selftest.result);
674 return -ETIMEDOUT;
675 }
676 if (nic->mem->selftest.signature == 0) {
677 DPRINTK(HW, ERR, "Self-test failed: timed out\n");
678 return -ETIMEDOUT;
679 }
680
681 return 0;
682 }
683
684 static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, __le16 data)
685 {
686 u32 cmd_addr_data[3];
687 u8 ctrl;
688 int i, j;
689
690 /* Three cmds: write/erase enable, write data, write/erase disable */
691 cmd_addr_data[0] = op_ewen << (addr_len - 2);
692 cmd_addr_data[1] = (((op_write << addr_len) | addr) << 16) |
693 le16_to_cpu(data);
694 cmd_addr_data[2] = op_ewds << (addr_len - 2);
695
696 /* Bit-bang cmds to write word to eeprom */
697 for (j = 0; j < 3; j++) {
698
699 /* Chip select */
700 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
701 e100_write_flush(nic); udelay(4);
702
703 for (i = 31; i >= 0; i--) {
704 ctrl = (cmd_addr_data[j] & (1 << i)) ?
705 eecs | eedi : eecs;
706 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
707 e100_write_flush(nic); udelay(4);
708
709 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
710 e100_write_flush(nic); udelay(4);
711 }
712 /* Wait 10 msec for cmd to complete */
713 msleep(10);
714
715 /* Chip deselect */
716 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
717 e100_write_flush(nic); udelay(4);
718 }
719 };
720
721 /* General technique stolen from the eepro100 driver - very clever */
722 static __le16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
723 {
724 u32 cmd_addr_data;
725 u16 data = 0;
726 u8 ctrl;
727 int i;
728
729 cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
730
731 /* Chip select */
732 iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
733 e100_write_flush(nic); udelay(4);
734
735 /* Bit-bang to read word from eeprom */
736 for (i = 31; i >= 0; i--) {
737 ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
738 iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
739 e100_write_flush(nic); udelay(4);
740
741 iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
742 e100_write_flush(nic); udelay(4);
743
744 /* Eeprom drives a dummy zero to EEDO after receiving
745 * complete address. Use this to adjust addr_len. */
746 ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
747 if (!(ctrl & eedo) && i > 16) {
748 *addr_len -= (i - 16);
749 i = 17;
750 }
751
752 data = (data << 1) | (ctrl & eedo ? 1 : 0);
753 }
754
755 /* Chip deselect */
756 iowrite8(0, &nic->csr->eeprom_ctrl_lo);
757 e100_write_flush(nic); udelay(4);
758
759 return cpu_to_le16(data);
760 };
761
762 /* Load entire EEPROM image into driver cache and validate checksum */
763 static int e100_eeprom_load(struct nic *nic)
764 {
765 u16 addr, addr_len = 8, checksum = 0;
766
767 /* Try reading with an 8-bit addr len to discover actual addr len */
768 e100_eeprom_read(nic, &addr_len, 0);
769 nic->eeprom_wc = 1 << addr_len;
770
771 for (addr = 0; addr < nic->eeprom_wc; addr++) {
772 nic->eeprom[addr] = e100_eeprom_read(nic, &addr_len, addr);
773 if (addr < nic->eeprom_wc - 1)
774 checksum += le16_to_cpu(nic->eeprom[addr]);
775 }
776
777 /* The checksum, stored in the last word, is calculated such that
778 * the sum of words should be 0xBABA */
779 if (cpu_to_le16(0xBABA - checksum) != nic->eeprom[nic->eeprom_wc - 1]) {
780 DPRINTK(PROBE, ERR, "EEPROM corrupted\n");
781 if (!eeprom_bad_csum_allow)
782 return -EAGAIN;
783 }
784
785 return 0;
786 }
787
788 /* Save (portion of) driver EEPROM cache to device and update checksum */
789 static int e100_eeprom_save(struct nic *nic, u16 start, u16 count)
790 {
791 u16 addr, addr_len = 8, checksum = 0;
792
793 /* Try reading with an 8-bit addr len to discover actual addr len */
794 e100_eeprom_read(nic, &addr_len, 0);
795 nic->eeprom_wc = 1 << addr_len;
796
797 if (start + count >= nic->eeprom_wc)
798 return -EINVAL;
799
800 for (addr = start; addr < start + count; addr++)
801 e100_eeprom_write(nic, addr_len, addr, nic->eeprom[addr]);
802
803 /* The checksum, stored in the last word, is calculated such that
804 * the sum of words should be 0xBABA */
805 for (addr = 0; addr < nic->eeprom_wc - 1; addr++)
806 checksum += le16_to_cpu(nic->eeprom[addr]);
807 nic->eeprom[nic->eeprom_wc - 1] = cpu_to_le16(0xBABA - checksum);
808 e100_eeprom_write(nic, addr_len, nic->eeprom_wc - 1,
809 nic->eeprom[nic->eeprom_wc - 1]);
810
811 return 0;
812 }
813
814 #define E100_WAIT_SCB_TIMEOUT 20000 /* we might have to wait 100ms!!! */
815 #define E100_WAIT_SCB_FAST 20 /* delay like the old code */
816 static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
817 {
818 unsigned long flags;
819 unsigned int i;
820 int err = 0;
821
822 spin_lock_irqsave(&nic->cmd_lock, flags);
823
824 /* Previous command is accepted when SCB clears */
825 for (i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
826 if (likely(!ioread8(&nic->csr->scb.cmd_lo)))
827 break;
828 cpu_relax();
829 if (unlikely(i > E100_WAIT_SCB_FAST))
830 udelay(5);
831 }
832 if (unlikely(i == E100_WAIT_SCB_TIMEOUT)) {
833 err = -EAGAIN;
834 goto err_unlock;
835 }
836
837 if (unlikely(cmd != cuc_resume))
838 iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
839 iowrite8(cmd, &nic->csr->scb.cmd_lo);
840
841 err_unlock:
842 spin_unlock_irqrestore(&nic->cmd_lock, flags);
843
844 return err;
845 }
846
847 static int e100_exec_cb(struct nic *nic, struct sk_buff *skb,
848 void (*cb_prepare)(struct nic *, struct cb *, struct sk_buff *))
849 {
850 struct cb *cb;
851 unsigned long flags;
852 int err = 0;
853
854 spin_lock_irqsave(&nic->cb_lock, flags);
855
856 if (unlikely(!nic->cbs_avail)) {
857 err = -ENOMEM;
858 goto err_unlock;
859 }
860
861 cb = nic->cb_to_use;
862 nic->cb_to_use = cb->next;
863 nic->cbs_avail--;
864 cb->skb = skb;
865
866 if (unlikely(!nic->cbs_avail))
867 err = -ENOSPC;
868
869 cb_prepare(nic, cb, skb);
870
871 /* Order is important otherwise we'll be in a race with h/w:
872 * set S-bit in current first, then clear S-bit in previous. */
873 cb->command |= cpu_to_le16(cb_s);
874 wmb();
875 cb->prev->command &= cpu_to_le16(~cb_s);
876
877 while (nic->cb_to_send != nic->cb_to_use) {
878 if (unlikely(e100_exec_cmd(nic, nic->cuc_cmd,
879 nic->cb_to_send->dma_addr))) {
880 /* Ok, here's where things get sticky. It's
881 * possible that we can't schedule the command
882 * because the controller is too busy, so
883 * let's just queue the command and try again
884 * when another command is scheduled. */
885 if (err == -ENOSPC) {
886 //request a reset
887 schedule_work(&nic->tx_timeout_task);
888 }
889 break;
890 } else {
891 nic->cuc_cmd = cuc_resume;
892 nic->cb_to_send = nic->cb_to_send->next;
893 }
894 }
895
896 err_unlock:
897 spin_unlock_irqrestore(&nic->cb_lock, flags);
898
899 return err;
900 }
901
902 static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
903 {
904 u32 data_out = 0;
905 unsigned int i;
906 unsigned long flags;
907
908
909 /*
910 * Stratus87247: we shouldn't be writing the MDI control
911 * register until the Ready bit shows True. Also, since
912 * manipulation of the MDI control registers is a multi-step
913 * procedure it should be done under lock.
914 */
915 spin_lock_irqsave(&nic->mdio_lock, flags);
916 for (i = 100; i; --i) {
917 if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
918 break;
919 udelay(20);
920 }
921 if (unlikely(!i)) {
922 printk("e100.mdio_ctrl(%s) won't go Ready\n",
923 nic->netdev->name );
924 spin_unlock_irqrestore(&nic->mdio_lock, flags);
925 return 0; /* No way to indicate timeout error */
926 }
927 iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
928
929 for (i = 0; i < 100; i++) {
930 udelay(20);
931 if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
932 break;
933 }
934 spin_unlock_irqrestore(&nic->mdio_lock, flags);
935 DPRINTK(HW, DEBUG,
936 "%s:addr=%d, reg=%d, data_in=0x%04X, data_out=0x%04X\n",
937 dir == mdi_read ? "READ" : "WRITE", addr, reg, data, data_out);
938 return (u16)data_out;
939 }
940
941 static int mdio_read(struct net_device *netdev, int addr, int reg)
942 {
943 return mdio_ctrl(netdev_priv(netdev), addr, mdi_read, reg, 0);
944 }
945
946 static void mdio_write(struct net_device *netdev, int addr, int reg, int data)
947 {
948 struct nic *nic = netdev_priv(netdev);
949
950 if ((nic->phy == phy_82552_v) && (reg == MII_BMCR) &&
951 (data & (BMCR_ANRESTART | BMCR_ANENABLE))) {
952 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
953
954 /*
955 * Workaround Si issue where sometimes the part will not
956 * autoneg to 100Mbps even when advertised.
957 */
958 if (advert & ADVERTISE_100FULL)
959 data |= BMCR_SPEED100 | BMCR_FULLDPLX;
960 else if (advert & ADVERTISE_100HALF)
961 data |= BMCR_SPEED100;
962 }
963
964 mdio_ctrl(netdev_priv(netdev), addr, mdi_write, reg, data);
965 }
966
967 static void e100_get_defaults(struct nic *nic)
968 {
969 struct param_range rfds = { .min = 16, .max = 256, .count = 256 };
970 struct param_range cbs = { .min = 64, .max = 256, .count = 128 };
971
972 /* MAC type is encoded as rev ID; exception: ICH is treated as 82559 */
973 nic->mac = (nic->flags & ich) ? mac_82559_D101M : nic->pdev->revision;
974 if (nic->mac == mac_unknown)
975 nic->mac = mac_82557_D100_A;
976
977 nic->params.rfds = rfds;
978 nic->params.cbs = cbs;
979
980 /* Quadwords to DMA into FIFO before starting frame transmit */
981 nic->tx_threshold = 0xE0;
982
983 /* no interrupt for every tx completion, delay = 256us if not 557 */
984 nic->tx_command = cpu_to_le16(cb_tx | cb_tx_sf |
985 ((nic->mac >= mac_82558_D101_A4) ? cb_cid : cb_i));
986
987 /* Template for a freshly allocated RFD */
988 nic->blank_rfd.command = 0;
989 nic->blank_rfd.rbd = cpu_to_le32(0xFFFFFFFF);
990 nic->blank_rfd.size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
991
992 /* MII setup */
993 nic->mii.phy_id_mask = 0x1F;
994 nic->mii.reg_num_mask = 0x1F;
995 nic->mii.dev = nic->netdev;
996 nic->mii.mdio_read = mdio_read;
997 nic->mii.mdio_write = mdio_write;
998 }
999
1000 static void e100_configure(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1001 {
1002 struct config *config = &cb->u.config;
1003 u8 *c = (u8 *)config;
1004
1005 cb->command = cpu_to_le16(cb_config);
1006
1007 memset(config, 0, sizeof(struct config));
1008
1009 config->byte_count = 0x16; /* bytes in this struct */
1010 config->rx_fifo_limit = 0x8; /* bytes in FIFO before DMA */
1011 config->direct_rx_dma = 0x1; /* reserved */
1012 config->standard_tcb = 0x1; /* 1=standard, 0=extended */
1013 config->standard_stat_counter = 0x1; /* 1=standard, 0=extended */
1014 config->rx_discard_short_frames = 0x1; /* 1=discard, 0=pass */
1015 config->tx_underrun_retry = 0x3; /* # of underrun retries */
1016 config->mii_mode = 0x1; /* 1=MII mode, 0=503 mode */
1017 config->pad10 = 0x6;
1018 config->no_source_addr_insertion = 0x1; /* 1=no, 0=yes */
1019 config->preamble_length = 0x2; /* 0=1, 1=3, 2=7, 3=15 bytes */
1020 config->ifs = 0x6; /* x16 = inter frame spacing */
1021 config->ip_addr_hi = 0xF2; /* ARP IP filter - not used */
1022 config->pad15_1 = 0x1;
1023 config->pad15_2 = 0x1;
1024 config->crs_or_cdt = 0x0; /* 0=CRS only, 1=CRS or CDT */
1025 config->fc_delay_hi = 0x40; /* time delay for fc frame */
1026 config->tx_padding = 0x1; /* 1=pad short frames */
1027 config->fc_priority_threshold = 0x7; /* 7=priority fc disabled */
1028 config->pad18 = 0x1;
1029 config->full_duplex_pin = 0x1; /* 1=examine FDX# pin */
1030 config->pad20_1 = 0x1F;
1031 config->fc_priority_location = 0x1; /* 1=byte#31, 0=byte#19 */
1032 config->pad21_1 = 0x5;
1033
1034 config->adaptive_ifs = nic->adaptive_ifs;
1035 config->loopback = nic->loopback;
1036
1037 if (nic->mii.force_media && nic->mii.full_duplex)
1038 config->full_duplex_force = 0x1; /* 1=force, 0=auto */
1039
1040 if (nic->flags & promiscuous || nic->loopback) {
1041 config->rx_save_bad_frames = 0x1; /* 1=save, 0=discard */
1042 config->rx_discard_short_frames = 0x0; /* 1=discard, 0=save */
1043 config->promiscuous_mode = 0x1; /* 1=on, 0=off */
1044 }
1045
1046 if (nic->flags & multicast_all)
1047 config->multicast_all = 0x1; /* 1=accept, 0=no */
1048
1049 /* disable WoL when up */
1050 if (netif_running(nic->netdev) || !(nic->flags & wol_magic))
1051 config->magic_packet_disable = 0x1; /* 1=off, 0=on */
1052
1053 if (nic->mac >= mac_82558_D101_A4) {
1054 config->fc_disable = 0x1; /* 1=Tx fc off, 0=Tx fc on */
1055 config->mwi_enable = 0x1; /* 1=enable, 0=disable */
1056 config->standard_tcb = 0x0; /* 1=standard, 0=extended */
1057 config->rx_long_ok = 0x1; /* 1=VLANs ok, 0=standard */
1058 if (nic->mac >= mac_82559_D101M) {
1059 config->tno_intr = 0x1; /* TCO stats enable */
1060 /* Enable TCO in extended config */
1061 if (nic->mac >= mac_82551_10) {
1062 config->byte_count = 0x20; /* extended bytes */
1063 config->rx_d102_mode = 0x1; /* GMRC for TCO */
1064 }
1065 } else {
1066 config->standard_stat_counter = 0x0;
1067 }
1068 }
1069
1070 DPRINTK(HW, DEBUG, "[00-07]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1071 c[0], c[1], c[2], c[3], c[4], c[5], c[6], c[7]);
1072 DPRINTK(HW, DEBUG, "[08-15]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1073 c[8], c[9], c[10], c[11], c[12], c[13], c[14], c[15]);
1074 DPRINTK(HW, DEBUG, "[16-23]=%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n",
1075 c[16], c[17], c[18], c[19], c[20], c[21], c[22], c[23]);
1076 }
1077
1078 /*************************************************************************
1079 * CPUSaver parameters
1080 *
1081 * All CPUSaver parameters are 16-bit literals that are part of a
1082 * "move immediate value" instruction. By changing the value of
1083 * the literal in the instruction before the code is loaded, the
1084 * driver can change the algorithm.
1085 *
1086 * INTDELAY - This loads the dead-man timer with its initial value.
1087 * When this timer expires the interrupt is asserted, and the
1088 * timer is reset each time a new packet is received. (see
1089 * BUNDLEMAX below to set the limit on number of chained packets)
1090 * The current default is 0x600 or 1536. Experiments show that
1091 * the value should probably stay within the 0x200 - 0x1000.
1092 *
1093 * BUNDLEMAX -
1094 * This sets the maximum number of frames that will be bundled. In
1095 * some situations, such as the TCP windowing algorithm, it may be
1096 * better to limit the growth of the bundle size than let it go as
1097 * high as it can, because that could cause too much added latency.
1098 * The default is six, because this is the number of packets in the
1099 * default TCP window size. A value of 1 would make CPUSaver indicate
1100 * an interrupt for every frame received. If you do not want to put
1101 * a limit on the bundle size, set this value to xFFFF.
1102 *
1103 * BUNDLESMALL -
1104 * This contains a bit-mask describing the minimum size frame that
1105 * will be bundled. The default masks the lower 7 bits, which means
1106 * that any frame less than 128 bytes in length will not be bundled,
1107 * but will instead immediately generate an interrupt. This does
1108 * not affect the current bundle in any way. Any frame that is 128
1109 * bytes or large will be bundled normally. This feature is meant
1110 * to provide immediate indication of ACK frames in a TCP environment.
1111 * Customers were seeing poor performance when a machine with CPUSaver
1112 * enabled was sending but not receiving. The delay introduced when
1113 * the ACKs were received was enough to reduce total throughput, because
1114 * the sender would sit idle until the ACK was finally seen.
1115 *
1116 * The current default is 0xFF80, which masks out the lower 7 bits.
1117 * This means that any frame which is x7F (127) bytes or smaller
1118 * will cause an immediate interrupt. Because this value must be a
1119 * bit mask, there are only a few valid values that can be used. To
1120 * turn this feature off, the driver can write the value xFFFF to the
1121 * lower word of this instruction (in the same way that the other
1122 * parameters are used). Likewise, a value of 0xF800 (2047) would
1123 * cause an interrupt to be generated for every frame, because all
1124 * standard Ethernet frames are <= 2047 bytes in length.
1125 *************************************************************************/
1126
1127 /* if you wish to disable the ucode functionality, while maintaining the
1128 * workarounds it provides, set the following defines to:
1129 * BUNDLESMALL 0
1130 * BUNDLEMAX 1
1131 * INTDELAY 1
1132 */
1133 #define BUNDLESMALL 1
1134 #define BUNDLEMAX (u16)6
1135 #define INTDELAY (u16)1536 /* 0x600 */
1136
1137 /* Initialize firmware */
1138 static const struct firmware *e100_request_firmware(struct nic *nic)
1139 {
1140 const char *fw_name;
1141 const struct firmware *fw;
1142 u8 timer, bundle, min_size;
1143 int err;
1144
1145 /* do not load u-code for ICH devices */
1146 if (nic->flags & ich)
1147 return NULL;
1148
1149 /* Search for ucode match against h/w revision */
1150 if (nic->mac == mac_82559_D101M)
1151 fw_name = FIRMWARE_D101M;
1152 else if (nic->mac == mac_82559_D101S)
1153 fw_name = FIRMWARE_D101S;
1154 else if (nic->mac == mac_82551_F || nic->mac == mac_82551_10)
1155 fw_name = FIRMWARE_D102E;
1156 else /* No ucode on other devices */
1157 return NULL;
1158
1159 err = request_firmware(&fw, fw_name, &nic->pdev->dev);
1160 if (err) {
1161 DPRINTK(PROBE, ERR, "Failed to load firmware \"%s\": %d\n",
1162 fw_name, err);
1163 return ERR_PTR(err);
1164 }
1165 /* Firmware should be precisely UCODE_SIZE (words) plus three bytes
1166 indicating the offsets for BUNDLESMALL, BUNDLEMAX, INTDELAY */
1167 if (fw->size != UCODE_SIZE * 4 + 3) {
1168 DPRINTK(PROBE, ERR, "Firmware \"%s\" has wrong size %zu\n",
1169 fw_name, fw->size);
1170 release_firmware(fw);
1171 return ERR_PTR(-EINVAL);
1172 }
1173
1174 /* Read timer, bundle and min_size from end of firmware blob */
1175 timer = fw->data[UCODE_SIZE * 4];
1176 bundle = fw->data[UCODE_SIZE * 4 + 1];
1177 min_size = fw->data[UCODE_SIZE * 4 + 2];
1178
1179 if (timer >= UCODE_SIZE || bundle >= UCODE_SIZE ||
1180 min_size >= UCODE_SIZE) {
1181 DPRINTK(PROBE, ERR,
1182 "\"%s\" has bogus offset values (0x%x,0x%x,0x%x)\n",
1183 fw_name, timer, bundle, min_size);
1184 release_firmware(fw);
1185 return ERR_PTR(-EINVAL);
1186 }
1187 /* OK, firmware is validated and ready to use... */
1188 return fw;
1189 }
1190
1191 static void e100_setup_ucode(struct nic *nic, struct cb *cb,
1192 struct sk_buff *skb)
1193 {
1194 const struct firmware *fw = (void *)skb;
1195 u8 timer, bundle, min_size;
1196
1197 /* It's not a real skb; we just abused the fact that e100_exec_cb
1198 will pass it through to here... */
1199 cb->skb = NULL;
1200
1201 /* firmware is stored as little endian already */
1202 memcpy(cb->u.ucode, fw->data, UCODE_SIZE * 4);
1203
1204 /* Read timer, bundle and min_size from end of firmware blob */
1205 timer = fw->data[UCODE_SIZE * 4];
1206 bundle = fw->data[UCODE_SIZE * 4 + 1];
1207 min_size = fw->data[UCODE_SIZE * 4 + 2];
1208
1209 /* Insert user-tunable settings in cb->u.ucode */
1210 cb->u.ucode[timer] &= cpu_to_le32(0xFFFF0000);
1211 cb->u.ucode[timer] |= cpu_to_le32(INTDELAY);
1212 cb->u.ucode[bundle] &= cpu_to_le32(0xFFFF0000);
1213 cb->u.ucode[bundle] |= cpu_to_le32(BUNDLEMAX);
1214 cb->u.ucode[min_size] &= cpu_to_le32(0xFFFF0000);
1215 cb->u.ucode[min_size] |= cpu_to_le32((BUNDLESMALL) ? 0xFFFF : 0xFF80);
1216
1217 cb->command = cpu_to_le16(cb_ucode | cb_el);
1218 }
1219
1220 static inline int e100_load_ucode_wait(struct nic *nic)
1221 {
1222 const struct firmware *fw;
1223 int err = 0, counter = 50;
1224 struct cb *cb = nic->cb_to_clean;
1225
1226 fw = e100_request_firmware(nic);
1227 /* If it's NULL, then no ucode is required */
1228 if (!fw || IS_ERR(fw))
1229 return PTR_ERR(fw);
1230
1231 if ((err = e100_exec_cb(nic, (void *)fw, e100_setup_ucode)))
1232 DPRINTK(PROBE,ERR, "ucode cmd failed with error %d\n", err);
1233
1234 /* must restart cuc */
1235 nic->cuc_cmd = cuc_start;
1236
1237 /* wait for completion */
1238 e100_write_flush(nic);
1239 udelay(10);
1240
1241 /* wait for possibly (ouch) 500ms */
1242 while (!(cb->status & cpu_to_le16(cb_complete))) {
1243 msleep(10);
1244 if (!--counter) break;
1245 }
1246
1247 /* ack any interrupts, something could have been set */
1248 iowrite8(~0, &nic->csr->scb.stat_ack);
1249
1250 /* if the command failed, or is not OK, notify and return */
1251 if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
1252 DPRINTK(PROBE,ERR, "ucode load failed\n");
1253 err = -EPERM;
1254 }
1255
1256 return err;
1257 }
1258
1259 static void e100_setup_iaaddr(struct nic *nic, struct cb *cb,
1260 struct sk_buff *skb)
1261 {
1262 cb->command = cpu_to_le16(cb_iaaddr);
1263 memcpy(cb->u.iaaddr, nic->netdev->dev_addr, ETH_ALEN);
1264 }
1265
1266 static void e100_dump(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1267 {
1268 cb->command = cpu_to_le16(cb_dump);
1269 cb->u.dump_buffer_addr = cpu_to_le32(nic->dma_addr +
1270 offsetof(struct mem, dump_buf));
1271 }
1272
1273 #define NCONFIG_AUTO_SWITCH 0x0080
1274 #define MII_NSC_CONG MII_RESV1
1275 #define NSC_CONG_ENABLE 0x0100
1276 #define NSC_CONG_TXREADY 0x0400
1277 #define ADVERTISE_FC_SUPPORTED 0x0400
1278 static int e100_phy_init(struct nic *nic)
1279 {
1280 struct net_device *netdev = nic->netdev;
1281 u32 addr;
1282 u16 bmcr, stat, id_lo, id_hi, cong;
1283
1284 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
1285 for (addr = 0; addr < 32; addr++) {
1286 nic->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
1287 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1288 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1289 stat = mdio_read(netdev, nic->mii.phy_id, MII_BMSR);
1290 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
1291 break;
1292 }
1293 DPRINTK(HW, DEBUG, "phy_addr = %d\n", nic->mii.phy_id);
1294 if (addr == 32)
1295 return -EAGAIN;
1296
1297 /* Isolate all the PHY ids */
1298 for (addr = 0; addr < 32; addr++)
1299 mdio_write(netdev, addr, MII_BMCR, BMCR_ISOLATE);
1300 /* Select the discovered PHY */
1301 bmcr &= ~BMCR_ISOLATE;
1302 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1303
1304 /* Get phy ID */
1305 id_lo = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID1);
1306 id_hi = mdio_read(netdev, nic->mii.phy_id, MII_PHYSID2);
1307 nic->phy = (u32)id_hi << 16 | (u32)id_lo;
1308 DPRINTK(HW, DEBUG, "phy ID = 0x%08X\n", nic->phy);
1309
1310 /* Handle National tx phys */
1311 #define NCS_PHY_MODEL_MASK 0xFFF0FFFF
1312 if ((nic->phy & NCS_PHY_MODEL_MASK) == phy_nsc_tx) {
1313 /* Disable congestion control */
1314 cong = mdio_read(netdev, nic->mii.phy_id, MII_NSC_CONG);
1315 cong |= NSC_CONG_TXREADY;
1316 cong &= ~NSC_CONG_ENABLE;
1317 mdio_write(netdev, nic->mii.phy_id, MII_NSC_CONG, cong);
1318 }
1319
1320 if (nic->phy == phy_82552_v) {
1321 u16 advert = mdio_read(netdev, nic->mii.phy_id, MII_ADVERTISE);
1322
1323 /* Workaround Si not advertising flow-control during autoneg */
1324 advert |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1325 mdio_write(netdev, nic->mii.phy_id, MII_ADVERTISE, advert);
1326
1327 /* Reset for the above changes to take effect */
1328 bmcr = mdio_read(netdev, nic->mii.phy_id, MII_BMCR);
1329 bmcr |= BMCR_RESET;
1330 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, bmcr);
1331 } else if ((nic->mac >= mac_82550_D102) || ((nic->flags & ich) &&
1332 (mdio_read(netdev, nic->mii.phy_id, MII_TPISTATUS) & 0x8000) &&
1333 !(nic->eeprom[eeprom_cnfg_mdix] & eeprom_mdix_enabled))) {
1334 /* enable/disable MDI/MDI-X auto-switching. */
1335 mdio_write(netdev, nic->mii.phy_id, MII_NCONFIG,
1336 nic->mii.force_media ? 0 : NCONFIG_AUTO_SWITCH);
1337 }
1338
1339 return 0;
1340 }
1341
1342 static int e100_hw_init(struct nic *nic)
1343 {
1344 int err;
1345
1346 e100_hw_reset(nic);
1347
1348 DPRINTK(HW, ERR, "e100_hw_init\n");
1349 if (!in_interrupt() && (err = e100_self_test(nic)))
1350 return err;
1351
1352 if ((err = e100_phy_init(nic)))
1353 return err;
1354 if ((err = e100_exec_cmd(nic, cuc_load_base, 0)))
1355 return err;
1356 if ((err = e100_exec_cmd(nic, ruc_load_base, 0)))
1357 return err;
1358 if ((err = e100_load_ucode_wait(nic)))
1359 return err;
1360 if ((err = e100_exec_cb(nic, NULL, e100_configure)))
1361 return err;
1362 if ((err = e100_exec_cb(nic, NULL, e100_setup_iaaddr)))
1363 return err;
1364 if ((err = e100_exec_cmd(nic, cuc_dump_addr,
1365 nic->dma_addr + offsetof(struct mem, stats))))
1366 return err;
1367 if ((err = e100_exec_cmd(nic, cuc_dump_reset, 0)))
1368 return err;
1369
1370 e100_disable_irq(nic);
1371
1372 return 0;
1373 }
1374
1375 static void e100_multi(struct nic *nic, struct cb *cb, struct sk_buff *skb)
1376 {
1377 struct net_device *netdev = nic->netdev;
1378 struct dev_mc_list *list = netdev->mc_list;
1379 u16 i, count = min(netdev->mc_count, E100_MAX_MULTICAST_ADDRS);
1380
1381 cb->command = cpu_to_le16(cb_multi);
1382 cb->u.multi.count = cpu_to_le16(count * ETH_ALEN);
1383 for (i = 0; list && i < count; i++, list = list->next)
1384 memcpy(&cb->u.multi.addr[i*ETH_ALEN], &list->dmi_addr,
1385 ETH_ALEN);
1386 }
1387
1388 static void e100_set_multicast_list(struct net_device *netdev)
1389 {
1390 struct nic *nic = netdev_priv(netdev);
1391
1392 DPRINTK(HW, DEBUG, "mc_count=%d, flags=0x%04X\n",
1393 netdev->mc_count, netdev->flags);
1394
1395 if (netdev->flags & IFF_PROMISC)
1396 nic->flags |= promiscuous;
1397 else
1398 nic->flags &= ~promiscuous;
1399
1400 if (netdev->flags & IFF_ALLMULTI ||
1401 netdev->mc_count > E100_MAX_MULTICAST_ADDRS)
1402 nic->flags |= multicast_all;
1403 else
1404 nic->flags &= ~multicast_all;
1405
1406 e100_exec_cb(nic, NULL, e100_configure);
1407 e100_exec_cb(nic, NULL, e100_multi);
1408 }
1409
1410 static void e100_update_stats(struct nic *nic)
1411 {
1412 struct net_device *dev = nic->netdev;
1413 struct net_device_stats *ns = &dev->stats;
1414 struct stats *s = &nic->mem->stats;
1415 __le32 *complete = (nic->mac < mac_82558_D101_A4) ? &s->fc_xmt_pause :
1416 (nic->mac < mac_82559_D101M) ? (__le32 *)&s->xmt_tco_frames :
1417 &s->complete;
1418
1419 /* Device's stats reporting may take several microseconds to
1420 * complete, so we're always waiting for results of the
1421 * previous command. */
1422
1423 if (*complete == cpu_to_le32(cuc_dump_reset_complete)) {
1424 *complete = 0;
1425 nic->tx_frames = le32_to_cpu(s->tx_good_frames);
1426 nic->tx_collisions = le32_to_cpu(s->tx_total_collisions);
1427 ns->tx_aborted_errors += le32_to_cpu(s->tx_max_collisions);
1428 ns->tx_window_errors += le32_to_cpu(s->tx_late_collisions);
1429 ns->tx_carrier_errors += le32_to_cpu(s->tx_lost_crs);
1430 ns->tx_fifo_errors += le32_to_cpu(s->tx_underruns);
1431 ns->collisions += nic->tx_collisions;
1432 ns->tx_errors += le32_to_cpu(s->tx_max_collisions) +
1433 le32_to_cpu(s->tx_lost_crs);
1434 ns->rx_length_errors += le32_to_cpu(s->rx_short_frame_errors) +
1435 nic->rx_over_length_errors;
1436 ns->rx_crc_errors += le32_to_cpu(s->rx_crc_errors);
1437 ns->rx_frame_errors += le32_to_cpu(s->rx_alignment_errors);
1438 ns->rx_over_errors += le32_to_cpu(s->rx_overrun_errors);
1439 ns->rx_fifo_errors += le32_to_cpu(s->rx_overrun_errors);
1440 ns->rx_missed_errors += le32_to_cpu(s->rx_resource_errors);
1441 ns->rx_errors += le32_to_cpu(s->rx_crc_errors) +
1442 le32_to_cpu(s->rx_alignment_errors) +
1443 le32_to_cpu(s->rx_short_frame_errors) +
1444 le32_to_cpu(s->rx_cdt_errors);
1445 nic->tx_deferred += le32_to_cpu(s->tx_deferred);
1446 nic->tx_single_collisions +=
1447 le32_to_cpu(s->tx_single_collisions);
1448 nic->tx_multiple_collisions +=
1449 le32_to_cpu(s->tx_multiple_collisions);
1450 if (nic->mac >= mac_82558_D101_A4) {
1451 nic->tx_fc_pause += le32_to_cpu(s->fc_xmt_pause);
1452 nic->rx_fc_pause += le32_to_cpu(s->fc_rcv_pause);
1453 nic->rx_fc_unsupported +=
1454 le32_to_cpu(s->fc_rcv_unsupported);
1455 if (nic->mac >= mac_82559_D101M) {
1456 nic->tx_tco_frames +=
1457 le16_to_cpu(s->xmt_tco_frames);
1458 nic->rx_tco_frames +=
1459 le16_to_cpu(s->rcv_tco_frames);
1460 }
1461 }
1462 }
1463
1464
1465 if (e100_exec_cmd(nic, cuc_dump_reset, 0))
1466 DPRINTK(TX_ERR, DEBUG, "exec cuc_dump_reset failed\n");
1467 }
1468
1469 static void e100_adjust_adaptive_ifs(struct nic *nic, int speed, int duplex)
1470 {
1471 /* Adjust inter-frame-spacing (IFS) between two transmits if
1472 * we're getting collisions on a half-duplex connection. */
1473
1474 if (duplex == DUPLEX_HALF) {
1475 u32 prev = nic->adaptive_ifs;
1476 u32 min_frames = (speed == SPEED_100) ? 1000 : 100;
1477
1478 if ((nic->tx_frames / 32 < nic->tx_collisions) &&
1479 (nic->tx_frames > min_frames)) {
1480 if (nic->adaptive_ifs < 60)
1481 nic->adaptive_ifs += 5;
1482 } else if (nic->tx_frames < min_frames) {
1483 if (nic->adaptive_ifs >= 5)
1484 nic->adaptive_ifs -= 5;
1485 }
1486 if (nic->adaptive_ifs != prev)
1487 e100_exec_cb(nic, NULL, e100_configure);
1488 }
1489 }
1490
1491 static void e100_watchdog(unsigned long data)
1492 {
1493 struct nic *nic = (struct nic *)data;
1494 struct ethtool_cmd cmd;
1495
1496 DPRINTK(TIMER, DEBUG, "right now = %ld\n", jiffies);
1497
1498 /* mii library handles link maintenance tasks */
1499
1500 mii_ethtool_gset(&nic->mii, &cmd);
1501
1502 if (mii_link_ok(&nic->mii) && !netif_carrier_ok(nic->netdev)) {
1503 printk(KERN_INFO "e100: %s NIC Link is Up %s Mbps %s Duplex\n",
1504 nic->netdev->name,
1505 cmd.speed == SPEED_100 ? "100" : "10",
1506 cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1507 } else if (!mii_link_ok(&nic->mii) && netif_carrier_ok(nic->netdev)) {
1508 printk(KERN_INFO "e100: %s NIC Link is Down\n",
1509 nic->netdev->name);
1510 }
1511
1512 mii_check_link(&nic->mii);
1513
1514 /* Software generated interrupt to recover from (rare) Rx
1515 * allocation failure.
1516 * Unfortunately have to use a spinlock to not re-enable interrupts
1517 * accidentally, due to hardware that shares a register between the
1518 * interrupt mask bit and the SW Interrupt generation bit */
1519 spin_lock_irq(&nic->cmd_lock);
1520 iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
1521 e100_write_flush(nic);
1522 spin_unlock_irq(&nic->cmd_lock);
1523
1524 e100_update_stats(nic);
1525 e100_adjust_adaptive_ifs(nic, cmd.speed, cmd.duplex);
1526
1527 if (nic->mac <= mac_82557_D100_C)
1528 /* Issue a multicast command to workaround a 557 lock up */
1529 e100_set_multicast_list(nic->netdev);
1530
1531 if (nic->flags & ich && cmd.speed==SPEED_10 && cmd.duplex==DUPLEX_HALF)
1532 /* Need SW workaround for ICH[x] 10Mbps/half duplex Tx hang. */
1533 nic->flags |= ich_10h_workaround;
1534 else
1535 nic->flags &= ~ich_10h_workaround;
1536
1537 mod_timer(&nic->watchdog,
1538 round_jiffies(jiffies + E100_WATCHDOG_PERIOD));
1539 }
1540
1541 static void e100_xmit_prepare(struct nic *nic, struct cb *cb,
1542 struct sk_buff *skb)
1543 {
1544 cb->command = nic->tx_command;
1545 /* interrupt every 16 packets regardless of delay */
1546 if ((nic->cbs_avail & ~15) == nic->cbs_avail)
1547 cb->command |= cpu_to_le16(cb_i);
1548 cb->u.tcb.tbd_array = cb->dma_addr + offsetof(struct cb, u.tcb.tbd);
1549 cb->u.tcb.tcb_byte_count = 0;
1550 cb->u.tcb.threshold = nic->tx_threshold;
1551 cb->u.tcb.tbd_count = 1;
1552 cb->u.tcb.tbd.buf_addr = cpu_to_le32(pci_map_single(nic->pdev,
1553 skb->data, skb->len, PCI_DMA_TODEVICE));
1554 /* check for mapping failure? */
1555 cb->u.tcb.tbd.size = cpu_to_le16(skb->len);
1556 }
1557
1558 static int e100_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1559 {
1560 struct nic *nic = netdev_priv(netdev);
1561 int err;
1562
1563 if (nic->flags & ich_10h_workaround) {
1564 /* SW workaround for ICH[x] 10Mbps/half duplex Tx hang.
1565 Issue a NOP command followed by a 1us delay before
1566 issuing the Tx command. */
1567 if (e100_exec_cmd(nic, cuc_nop, 0))
1568 DPRINTK(TX_ERR, DEBUG, "exec cuc_nop failed\n");
1569 udelay(1);
1570 }
1571
1572 err = e100_exec_cb(nic, skb, e100_xmit_prepare);
1573
1574 switch (err) {
1575 case -ENOSPC:
1576 /* We queued the skb, but now we're out of space. */
1577 DPRINTK(TX_ERR, DEBUG, "No space for CB\n");
1578 netif_stop_queue(netdev);
1579 break;
1580 case -ENOMEM:
1581 /* This is a hard error - log it. */
1582 DPRINTK(TX_ERR, DEBUG, "Out of Tx resources, returning skb\n");
1583 netif_stop_queue(netdev);
1584 return 1;
1585 }
1586
1587 netdev->trans_start = jiffies;
1588 return 0;
1589 }
1590
1591 static int e100_tx_clean(struct nic *nic)
1592 {
1593 struct net_device *dev = nic->netdev;
1594 struct cb *cb;
1595 int tx_cleaned = 0;
1596
1597 spin_lock(&nic->cb_lock);
1598
1599 /* Clean CBs marked complete */
1600 for (cb = nic->cb_to_clean;
1601 cb->status & cpu_to_le16(cb_complete);
1602 cb = nic->cb_to_clean = cb->next) {
1603 DPRINTK(TX_DONE, DEBUG, "cb[%d]->status = 0x%04X\n",
1604 (int)(((void*)cb - (void*)nic->cbs)/sizeof(struct cb)),
1605 cb->status);
1606
1607 if (likely(cb->skb != NULL)) {
1608 dev->stats.tx_packets++;
1609 dev->stats.tx_bytes += cb->skb->len;
1610
1611 pci_unmap_single(nic->pdev,
1612 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1613 le16_to_cpu(cb->u.tcb.tbd.size),
1614 PCI_DMA_TODEVICE);
1615 dev_kfree_skb_any(cb->skb);
1616 cb->skb = NULL;
1617 tx_cleaned = 1;
1618 }
1619 cb->status = 0;
1620 nic->cbs_avail++;
1621 }
1622
1623 spin_unlock(&nic->cb_lock);
1624
1625 /* Recover from running out of Tx resources in xmit_frame */
1626 if (unlikely(tx_cleaned && netif_queue_stopped(nic->netdev)))
1627 netif_wake_queue(nic->netdev);
1628
1629 return tx_cleaned;
1630 }
1631
1632 static void e100_clean_cbs(struct nic *nic)
1633 {
1634 if (nic->cbs) {
1635 while (nic->cbs_avail != nic->params.cbs.count) {
1636 struct cb *cb = nic->cb_to_clean;
1637 if (cb->skb) {
1638 pci_unmap_single(nic->pdev,
1639 le32_to_cpu(cb->u.tcb.tbd.buf_addr),
1640 le16_to_cpu(cb->u.tcb.tbd.size),
1641 PCI_DMA_TODEVICE);
1642 dev_kfree_skb(cb->skb);
1643 }
1644 nic->cb_to_clean = nic->cb_to_clean->next;
1645 nic->cbs_avail++;
1646 }
1647 pci_free_consistent(nic->pdev,
1648 sizeof(struct cb) * nic->params.cbs.count,
1649 nic->cbs, nic->cbs_dma_addr);
1650 nic->cbs = NULL;
1651 nic->cbs_avail = 0;
1652 }
1653 nic->cuc_cmd = cuc_start;
1654 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean =
1655 nic->cbs;
1656 }
1657
1658 static int e100_alloc_cbs(struct nic *nic)
1659 {
1660 struct cb *cb;
1661 unsigned int i, count = nic->params.cbs.count;
1662
1663 nic->cuc_cmd = cuc_start;
1664 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = NULL;
1665 nic->cbs_avail = 0;
1666
1667 nic->cbs = pci_alloc_consistent(nic->pdev,
1668 sizeof(struct cb) * count, &nic->cbs_dma_addr);
1669 if (!nic->cbs)
1670 return -ENOMEM;
1671
1672 for (cb = nic->cbs, i = 0; i < count; cb++, i++) {
1673 cb->next = (i + 1 < count) ? cb + 1 : nic->cbs;
1674 cb->prev = (i == 0) ? nic->cbs + count - 1 : cb - 1;
1675
1676 cb->dma_addr = nic->cbs_dma_addr + i * sizeof(struct cb);
1677 cb->link = cpu_to_le32(nic->cbs_dma_addr +
1678 ((i+1) % count) * sizeof(struct cb));
1679 cb->skb = NULL;
1680 }
1681
1682 nic->cb_to_use = nic->cb_to_send = nic->cb_to_clean = nic->cbs;
1683 nic->cbs_avail = count;
1684
1685 return 0;
1686 }
1687
1688 static inline void e100_start_receiver(struct nic *nic, struct rx *rx)
1689 {
1690 if (!nic->rxs) return;
1691 if (RU_SUSPENDED != nic->ru_running) return;
1692
1693 /* handle init time starts */
1694 if (!rx) rx = nic->rxs;
1695
1696 /* (Re)start RU if suspended or idle and RFA is non-NULL */
1697 if (rx->skb) {
1698 e100_exec_cmd(nic, ruc_start, rx->dma_addr);
1699 nic->ru_running = RU_RUNNING;
1700 }
1701 }
1702
1703 #define RFD_BUF_LEN (sizeof(struct rfd) + VLAN_ETH_FRAME_LEN)
1704 static int e100_rx_alloc_skb(struct nic *nic, struct rx *rx)
1705 {
1706 if (!(rx->skb = netdev_alloc_skb(nic->netdev, RFD_BUF_LEN + NET_IP_ALIGN)))
1707 return -ENOMEM;
1708
1709 /* Align, init, and map the RFD. */
1710 skb_reserve(rx->skb, NET_IP_ALIGN);
1711 skb_copy_to_linear_data(rx->skb, &nic->blank_rfd, sizeof(struct rfd));
1712 rx->dma_addr = pci_map_single(nic->pdev, rx->skb->data,
1713 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1714
1715 if (pci_dma_mapping_error(nic->pdev, rx->dma_addr)) {
1716 dev_kfree_skb_any(rx->skb);
1717 rx->skb = NULL;
1718 rx->dma_addr = 0;
1719 return -ENOMEM;
1720 }
1721
1722 /* Link the RFD to end of RFA by linking previous RFD to
1723 * this one. We are safe to touch the previous RFD because
1724 * it is protected by the before last buffer's el bit being set */
1725 if (rx->prev->skb) {
1726 struct rfd *prev_rfd = (struct rfd *)rx->prev->skb->data;
1727 put_unaligned_le32(rx->dma_addr, &prev_rfd->link);
1728 pci_dma_sync_single_for_device(nic->pdev, rx->prev->dma_addr,
1729 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1730 }
1731
1732 return 0;
1733 }
1734
1735 static int e100_rx_indicate(struct nic *nic, struct rx *rx,
1736 unsigned int *work_done, unsigned int work_to_do)
1737 {
1738 struct net_device *dev = nic->netdev;
1739 struct sk_buff *skb = rx->skb;
1740 struct rfd *rfd = (struct rfd *)skb->data;
1741 u16 rfd_status, actual_size;
1742
1743 if (unlikely(work_done && *work_done >= work_to_do))
1744 return -EAGAIN;
1745
1746 /* Need to sync before taking a peek at cb_complete bit */
1747 pci_dma_sync_single_for_cpu(nic->pdev, rx->dma_addr,
1748 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1749 rfd_status = le16_to_cpu(rfd->status);
1750
1751 DPRINTK(RX_STATUS, DEBUG, "status=0x%04X\n", rfd_status);
1752
1753 /* If data isn't ready, nothing to indicate */
1754 if (unlikely(!(rfd_status & cb_complete))) {
1755 /* If the next buffer has the el bit, but we think the receiver
1756 * is still running, check to see if it really stopped while
1757 * we had interrupts off.
1758 * This allows for a fast restart without re-enabling
1759 * interrupts */
1760 if ((le16_to_cpu(rfd->command) & cb_el) &&
1761 (RU_RUNNING == nic->ru_running))
1762
1763 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1764 nic->ru_running = RU_SUSPENDED;
1765 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1766 sizeof(struct rfd),
1767 PCI_DMA_BIDIRECTIONAL);
1768 return -ENODATA;
1769 }
1770
1771 /* Get actual data size */
1772 actual_size = le16_to_cpu(rfd->actual_size) & 0x3FFF;
1773 if (unlikely(actual_size > RFD_BUF_LEN - sizeof(struct rfd)))
1774 actual_size = RFD_BUF_LEN - sizeof(struct rfd);
1775
1776 /* Get data */
1777 pci_unmap_single(nic->pdev, rx->dma_addr,
1778 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1779
1780 /* If this buffer has the el bit, but we think the receiver
1781 * is still running, check to see if it really stopped while
1782 * we had interrupts off.
1783 * This allows for a fast restart without re-enabling interrupts.
1784 * This can happen when the RU sees the size change but also sees
1785 * the el bit set. */
1786 if ((le16_to_cpu(rfd->command) & cb_el) &&
1787 (RU_RUNNING == nic->ru_running)) {
1788
1789 if (ioread8(&nic->csr->scb.status) & rus_no_res)
1790 nic->ru_running = RU_SUSPENDED;
1791 }
1792
1793 /* Pull off the RFD and put the actual data (minus eth hdr) */
1794 skb_reserve(skb, sizeof(struct rfd));
1795 skb_put(skb, actual_size);
1796 skb->protocol = eth_type_trans(skb, nic->netdev);
1797
1798 if (unlikely(!(rfd_status & cb_ok))) {
1799 /* Don't indicate if hardware indicates errors */
1800 dev_kfree_skb_any(skb);
1801 } else if (actual_size > ETH_DATA_LEN + VLAN_ETH_HLEN) {
1802 /* Don't indicate oversized frames */
1803 nic->rx_over_length_errors++;
1804 dev_kfree_skb_any(skb);
1805 } else {
1806 dev->stats.rx_packets++;
1807 dev->stats.rx_bytes += actual_size;
1808 netif_receive_skb(skb);
1809 if (work_done)
1810 (*work_done)++;
1811 }
1812
1813 rx->skb = NULL;
1814
1815 return 0;
1816 }
1817
1818 static void e100_rx_clean(struct nic *nic, unsigned int *work_done,
1819 unsigned int work_to_do)
1820 {
1821 struct rx *rx;
1822 int restart_required = 0, err = 0;
1823 struct rx *old_before_last_rx, *new_before_last_rx;
1824 struct rfd *old_before_last_rfd, *new_before_last_rfd;
1825
1826 /* Indicate newly arrived packets */
1827 for (rx = nic->rx_to_clean; rx->skb; rx = nic->rx_to_clean = rx->next) {
1828 err = e100_rx_indicate(nic, rx, work_done, work_to_do);
1829 /* Hit quota or no more to clean */
1830 if (-EAGAIN == err || -ENODATA == err)
1831 break;
1832 }
1833
1834
1835 /* On EAGAIN, hit quota so have more work to do, restart once
1836 * cleanup is complete.
1837 * Else, are we already rnr? then pay attention!!! this ensures that
1838 * the state machine progression never allows a start with a
1839 * partially cleaned list, avoiding a race between hardware
1840 * and rx_to_clean when in NAPI mode */
1841 if (-EAGAIN != err && RU_SUSPENDED == nic->ru_running)
1842 restart_required = 1;
1843
1844 old_before_last_rx = nic->rx_to_use->prev->prev;
1845 old_before_last_rfd = (struct rfd *)old_before_last_rx->skb->data;
1846
1847 /* Alloc new skbs to refill list */
1848 for (rx = nic->rx_to_use; !rx->skb; rx = nic->rx_to_use = rx->next) {
1849 if (unlikely(e100_rx_alloc_skb(nic, rx)))
1850 break; /* Better luck next time (see watchdog) */
1851 }
1852
1853 new_before_last_rx = nic->rx_to_use->prev->prev;
1854 if (new_before_last_rx != old_before_last_rx) {
1855 /* Set the el-bit on the buffer that is before the last buffer.
1856 * This lets us update the next pointer on the last buffer
1857 * without worrying about hardware touching it.
1858 * We set the size to 0 to prevent hardware from touching this
1859 * buffer.
1860 * When the hardware hits the before last buffer with el-bit
1861 * and size of 0, it will RNR interrupt, the RUS will go into
1862 * the No Resources state. It will not complete nor write to
1863 * this buffer. */
1864 new_before_last_rfd =
1865 (struct rfd *)new_before_last_rx->skb->data;
1866 new_before_last_rfd->size = 0;
1867 new_before_last_rfd->command |= cpu_to_le16(cb_el);
1868 pci_dma_sync_single_for_device(nic->pdev,
1869 new_before_last_rx->dma_addr, sizeof(struct rfd),
1870 PCI_DMA_BIDIRECTIONAL);
1871
1872 /* Now that we have a new stopping point, we can clear the old
1873 * stopping point. We must sync twice to get the proper
1874 * ordering on the hardware side of things. */
1875 old_before_last_rfd->command &= ~cpu_to_le16(cb_el);
1876 pci_dma_sync_single_for_device(nic->pdev,
1877 old_before_last_rx->dma_addr, sizeof(struct rfd),
1878 PCI_DMA_BIDIRECTIONAL);
1879 old_before_last_rfd->size = cpu_to_le16(VLAN_ETH_FRAME_LEN);
1880 pci_dma_sync_single_for_device(nic->pdev,
1881 old_before_last_rx->dma_addr, sizeof(struct rfd),
1882 PCI_DMA_BIDIRECTIONAL);
1883 }
1884
1885 if (restart_required) {
1886 // ack the rnr?
1887 iowrite8(stat_ack_rnr, &nic->csr->scb.stat_ack);
1888 e100_start_receiver(nic, nic->rx_to_clean);
1889 if (work_done)
1890 (*work_done)++;
1891 }
1892 }
1893
1894 static void e100_rx_clean_list(struct nic *nic)
1895 {
1896 struct rx *rx;
1897 unsigned int i, count = nic->params.rfds.count;
1898
1899 nic->ru_running = RU_UNINITIALIZED;
1900
1901 if (nic->rxs) {
1902 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
1903 if (rx->skb) {
1904 pci_unmap_single(nic->pdev, rx->dma_addr,
1905 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
1906 dev_kfree_skb(rx->skb);
1907 }
1908 }
1909 kfree(nic->rxs);
1910 nic->rxs = NULL;
1911 }
1912
1913 nic->rx_to_use = nic->rx_to_clean = NULL;
1914 }
1915
1916 static int e100_rx_alloc_list(struct nic *nic)
1917 {
1918 struct rx *rx;
1919 unsigned int i, count = nic->params.rfds.count;
1920 struct rfd *before_last;
1921
1922 nic->rx_to_use = nic->rx_to_clean = NULL;
1923 nic->ru_running = RU_UNINITIALIZED;
1924
1925 if (!(nic->rxs = kcalloc(count, sizeof(struct rx), GFP_ATOMIC)))
1926 return -ENOMEM;
1927
1928 for (rx = nic->rxs, i = 0; i < count; rx++, i++) {
1929 rx->next = (i + 1 < count) ? rx + 1 : nic->rxs;
1930 rx->prev = (i == 0) ? nic->rxs + count - 1 : rx - 1;
1931 if (e100_rx_alloc_skb(nic, rx)) {
1932 e100_rx_clean_list(nic);
1933 return -ENOMEM;
1934 }
1935 }
1936 /* Set the el-bit on the buffer that is before the last buffer.
1937 * This lets us update the next pointer on the last buffer without
1938 * worrying about hardware touching it.
1939 * We set the size to 0 to prevent hardware from touching this buffer.
1940 * When the hardware hits the before last buffer with el-bit and size
1941 * of 0, it will RNR interrupt, the RU will go into the No Resources
1942 * state. It will not complete nor write to this buffer. */
1943 rx = nic->rxs->prev->prev;
1944 before_last = (struct rfd *)rx->skb->data;
1945 before_last->command |= cpu_to_le16(cb_el);
1946 before_last->size = 0;
1947 pci_dma_sync_single_for_device(nic->pdev, rx->dma_addr,
1948 sizeof(struct rfd), PCI_DMA_BIDIRECTIONAL);
1949
1950 nic->rx_to_use = nic->rx_to_clean = nic->rxs;
1951 nic->ru_running = RU_SUSPENDED;
1952
1953 return 0;
1954 }
1955
1956 static irqreturn_t e100_intr(int irq, void *dev_id)
1957 {
1958 struct net_device *netdev = dev_id;
1959 struct nic *nic = netdev_priv(netdev);
1960 u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
1961
1962 DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
1963
1964 if (stat_ack == stat_ack_not_ours || /* Not our interrupt */
1965 stat_ack == stat_ack_not_present) /* Hardware is ejected */
1966 return IRQ_NONE;
1967
1968 /* Ack interrupt(s) */
1969 iowrite8(stat_ack, &nic->csr->scb.stat_ack);
1970
1971 /* We hit Receive No Resource (RNR); restart RU after cleaning */
1972 if (stat_ack & stat_ack_rnr)
1973 nic->ru_running = RU_SUSPENDED;
1974
1975 if (likely(napi_schedule_prep(&nic->napi))) {
1976 e100_disable_irq(nic);
1977 __napi_schedule(&nic->napi);
1978 }
1979
1980 return IRQ_HANDLED;
1981 }
1982
1983 static int e100_poll(struct napi_struct *napi, int budget)
1984 {
1985 struct nic *nic = container_of(napi, struct nic, napi);
1986 unsigned int work_done = 0;
1987
1988 e100_rx_clean(nic, &work_done, budget);
1989 e100_tx_clean(nic);
1990
1991 /* If budget not fully consumed, exit the polling mode */
1992 if (work_done < budget) {
1993 napi_complete(napi);
1994 e100_enable_irq(nic);
1995 }
1996
1997 return work_done;
1998 }
1999
2000 #ifdef CONFIG_NET_POLL_CONTROLLER
2001 static void e100_netpoll(struct net_device *netdev)
2002 {
2003 struct nic *nic = netdev_priv(netdev);
2004
2005 e100_disable_irq(nic);
2006 e100_intr(nic->pdev->irq, netdev);
2007 e100_tx_clean(nic);
2008 e100_enable_irq(nic);
2009 }
2010 #endif
2011
2012 static int e100_set_mac_address(struct net_device *netdev, void *p)
2013 {
2014 struct nic *nic = netdev_priv(netdev);
2015 struct sockaddr *addr = p;
2016
2017 if (!is_valid_ether_addr(addr->sa_data))
2018 return -EADDRNOTAVAIL;
2019
2020 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2021 e100_exec_cb(nic, NULL, e100_setup_iaaddr);
2022
2023 return 0;
2024 }
2025
2026 static int e100_change_mtu(struct net_device *netdev, int new_mtu)
2027 {
2028 if (new_mtu < ETH_ZLEN || new_mtu > ETH_DATA_LEN)
2029 return -EINVAL;
2030 netdev->mtu = new_mtu;
2031 return 0;
2032 }
2033
2034 static int e100_asf(struct nic *nic)
2035 {
2036 /* ASF can be enabled from eeprom */
2037 return((nic->pdev->device >= 0x1050) && (nic->pdev->device <= 0x1057) &&
2038 (nic->eeprom[eeprom_config_asf] & eeprom_asf) &&
2039 !(nic->eeprom[eeprom_config_asf] & eeprom_gcl) &&
2040 ((nic->eeprom[eeprom_smbus_addr] & 0xFF) != 0xFE));
2041 }
2042
2043 static int e100_up(struct nic *nic)
2044 {
2045 int err;
2046
2047 if ((err = e100_rx_alloc_list(nic)))
2048 return err;
2049 if ((err = e100_alloc_cbs(nic)))
2050 goto err_rx_clean_list;
2051 if ((err = e100_hw_init(nic)))
2052 goto err_clean_cbs;
2053 e100_set_multicast_list(nic->netdev);
2054 e100_start_receiver(nic, NULL);
2055 mod_timer(&nic->watchdog, jiffies);
2056 if ((err = request_irq(nic->pdev->irq, e100_intr, IRQF_SHARED,
2057 nic->netdev->name, nic->netdev)))
2058 goto err_no_irq;
2059 netif_wake_queue(nic->netdev);
2060 napi_enable(&nic->napi);
2061 /* enable ints _after_ enabling poll, preventing a race between
2062 * disable ints+schedule */
2063 e100_enable_irq(nic);
2064 return 0;
2065
2066 err_no_irq:
2067 del_timer_sync(&nic->watchdog);
2068 err_clean_cbs:
2069 e100_clean_cbs(nic);
2070 err_rx_clean_list:
2071 e100_rx_clean_list(nic);
2072 return err;
2073 }
2074
2075 static void e100_down(struct nic *nic)
2076 {
2077 /* wait here for poll to complete */
2078 napi_disable(&nic->napi);
2079 netif_stop_queue(nic->netdev);
2080 e100_hw_reset(nic);
2081 free_irq(nic->pdev->irq, nic->netdev);
2082 del_timer_sync(&nic->watchdog);
2083 netif_carrier_off(nic->netdev);
2084 e100_clean_cbs(nic);
2085 e100_rx_clean_list(nic);
2086 }
2087
2088 static void e100_tx_timeout(struct net_device *netdev)
2089 {
2090 struct nic *nic = netdev_priv(netdev);
2091
2092 /* Reset outside of interrupt context, to avoid request_irq
2093 * in interrupt context */
2094 schedule_work(&nic->tx_timeout_task);
2095 }
2096
2097 static void e100_tx_timeout_task(struct work_struct *work)
2098 {
2099 struct nic *nic = container_of(work, struct nic, tx_timeout_task);
2100 struct net_device *netdev = nic->netdev;
2101
2102 DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
2103 ioread8(&nic->csr->scb.status));
2104 e100_down(netdev_priv(netdev));
2105 e100_up(netdev_priv(netdev));
2106 }
2107
2108 static int e100_loopback_test(struct nic *nic, enum loopback loopback_mode)
2109 {
2110 int err;
2111 struct sk_buff *skb;
2112
2113 /* Use driver resources to perform internal MAC or PHY
2114 * loopback test. A single packet is prepared and transmitted
2115 * in loopback mode, and the test passes if the received
2116 * packet compares byte-for-byte to the transmitted packet. */
2117
2118 if ((err = e100_rx_alloc_list(nic)))
2119 return err;
2120 if ((err = e100_alloc_cbs(nic)))
2121 goto err_clean_rx;
2122
2123 /* ICH PHY loopback is broken so do MAC loopback instead */
2124 if (nic->flags & ich && loopback_mode == lb_phy)
2125 loopback_mode = lb_mac;
2126
2127 nic->loopback = loopback_mode;
2128 if ((err = e100_hw_init(nic)))
2129 goto err_loopback_none;
2130
2131 if (loopback_mode == lb_phy)
2132 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR,
2133 BMCR_LOOPBACK);
2134
2135 e100_start_receiver(nic, NULL);
2136
2137 if (!(skb = netdev_alloc_skb(nic->netdev, ETH_DATA_LEN))) {
2138 err = -ENOMEM;
2139 goto err_loopback_none;
2140 }
2141 skb_put(skb, ETH_DATA_LEN);
2142 memset(skb->data, 0xFF, ETH_DATA_LEN);
2143 e100_xmit_frame(skb, nic->netdev);
2144
2145 msleep(10);
2146
2147 pci_dma_sync_single_for_cpu(nic->pdev, nic->rx_to_clean->dma_addr,
2148 RFD_BUF_LEN, PCI_DMA_BIDIRECTIONAL);
2149
2150 if (memcmp(nic->rx_to_clean->skb->data + sizeof(struct rfd),
2151 skb->data, ETH_DATA_LEN))
2152 err = -EAGAIN;
2153
2154 err_loopback_none:
2155 mdio_write(nic->netdev, nic->mii.phy_id, MII_BMCR, 0);
2156 nic->loopback = lb_none;
2157 e100_clean_cbs(nic);
2158 e100_hw_reset(nic);
2159 err_clean_rx:
2160 e100_rx_clean_list(nic);
2161 return err;
2162 }
2163
2164 #define MII_LED_CONTROL 0x1B
2165 #define E100_82552_LED_OVERRIDE 0x19
2166 #define E100_82552_LED_ON 0x000F /* LEDTX and LED_RX both on */
2167 #define E100_82552_LED_OFF 0x000A /* LEDTX and LED_RX both off */
2168 static void e100_blink_led(unsigned long data)
2169 {
2170 struct nic *nic = (struct nic *)data;
2171 enum led_state {
2172 led_on = 0x01,
2173 led_off = 0x04,
2174 led_on_559 = 0x05,
2175 led_on_557 = 0x07,
2176 };
2177 u16 led_reg = MII_LED_CONTROL;
2178
2179 if (nic->phy == phy_82552_v) {
2180 led_reg = E100_82552_LED_OVERRIDE;
2181
2182 nic->leds = (nic->leds == E100_82552_LED_ON) ?
2183 E100_82552_LED_OFF : E100_82552_LED_ON;
2184 } else {
2185 nic->leds = (nic->leds & led_on) ? led_off :
2186 (nic->mac < mac_82559_D101M) ? led_on_557 :
2187 led_on_559;
2188 }
2189 mdio_write(nic->netdev, nic->mii.phy_id, led_reg, nic->leds);
2190 mod_timer(&nic->blink_timer, jiffies + HZ / 4);
2191 }
2192
2193 static int e100_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2194 {
2195 struct nic *nic = netdev_priv(netdev);
2196 return mii_ethtool_gset(&nic->mii, cmd);
2197 }
2198
2199 static int e100_set_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
2200 {
2201 struct nic *nic = netdev_priv(netdev);
2202 int err;
2203
2204 mdio_write(netdev, nic->mii.phy_id, MII_BMCR, BMCR_RESET);
2205 err = mii_ethtool_sset(&nic->mii, cmd);
2206 e100_exec_cb(nic, NULL, e100_configure);
2207
2208 return err;
2209 }
2210
2211 static void e100_get_drvinfo(struct net_device *netdev,
2212 struct ethtool_drvinfo *info)
2213 {
2214 struct nic *nic = netdev_priv(netdev);
2215 strcpy(info->driver, DRV_NAME);
2216 strcpy(info->version, DRV_VERSION);
2217 strcpy(info->fw_version, "N/A");
2218 strcpy(info->bus_info, pci_name(nic->pdev));
2219 }
2220
2221 #define E100_PHY_REGS 0x1C
2222 static int e100_get_regs_len(struct net_device *netdev)
2223 {
2224 struct nic *nic = netdev_priv(netdev);
2225 return 1 + E100_PHY_REGS + sizeof(nic->mem->dump_buf);
2226 }
2227
2228 static void e100_get_regs(struct net_device *netdev,
2229 struct ethtool_regs *regs, void *p)
2230 {
2231 struct nic *nic = netdev_priv(netdev);
2232 u32 *buff = p;
2233 int i;
2234
2235 regs->version = (1 << 24) | nic->pdev->revision;
2236 buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
2237 ioread8(&nic->csr->scb.cmd_lo) << 16 |
2238 ioread16(&nic->csr->scb.status);
2239 for (i = E100_PHY_REGS; i >= 0; i--)
2240 buff[1 + E100_PHY_REGS - i] =
2241 mdio_read(netdev, nic->mii.phy_id, i);
2242 memset(nic->mem->dump_buf, 0, sizeof(nic->mem->dump_buf));
2243 e100_exec_cb(nic, NULL, e100_dump);
2244 msleep(10);
2245 memcpy(&buff[2 + E100_PHY_REGS], nic->mem->dump_buf,
2246 sizeof(nic->mem->dump_buf));
2247 }
2248
2249 static void e100_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2250 {
2251 struct nic *nic = netdev_priv(netdev);
2252 wol->supported = (nic->mac >= mac_82558_D101_A4) ? WAKE_MAGIC : 0;
2253 wol->wolopts = (nic->flags & wol_magic) ? WAKE_MAGIC : 0;
2254 }
2255
2256 static int e100_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2257 {
2258 struct nic *nic = netdev_priv(netdev);
2259
2260 if ((wol->wolopts && wol->wolopts != WAKE_MAGIC) ||
2261 !device_can_wakeup(&nic->pdev->dev))
2262 return -EOPNOTSUPP;
2263
2264 if (wol->wolopts)
2265 nic->flags |= wol_magic;
2266 else
2267 nic->flags &= ~wol_magic;
2268
2269 device_set_wakeup_enable(&nic->pdev->dev, wol->wolopts);
2270
2271 e100_exec_cb(nic, NULL, e100_configure);
2272
2273 return 0;
2274 }
2275
2276 static u32 e100_get_msglevel(struct net_device *netdev)
2277 {
2278 struct nic *nic = netdev_priv(netdev);
2279 return nic->msg_enable;
2280 }
2281
2282 static void e100_set_msglevel(struct net_device *netdev, u32 value)
2283 {
2284 struct nic *nic = netdev_priv(netdev);
2285 nic->msg_enable = value;
2286 }
2287
2288 static int e100_nway_reset(struct net_device *netdev)
2289 {
2290 struct nic *nic = netdev_priv(netdev);
2291 return mii_nway_restart(&nic->mii);
2292 }
2293
2294 static u32 e100_get_link(struct net_device *netdev)
2295 {
2296 struct nic *nic = netdev_priv(netdev);
2297 return mii_link_ok(&nic->mii);
2298 }
2299
2300 static int e100_get_eeprom_len(struct net_device *netdev)
2301 {
2302 struct nic *nic = netdev_priv(netdev);
2303 return nic->eeprom_wc << 1;
2304 }
2305
2306 #define E100_EEPROM_MAGIC 0x1234
2307 static int e100_get_eeprom(struct net_device *netdev,
2308 struct ethtool_eeprom *eeprom, u8 *bytes)
2309 {
2310 struct nic *nic = netdev_priv(netdev);
2311
2312 eeprom->magic = E100_EEPROM_MAGIC;
2313 memcpy(bytes, &((u8 *)nic->eeprom)[eeprom->offset], eeprom->len);
2314
2315 return 0;
2316 }
2317
2318 static int e100_set_eeprom(struct net_device *netdev,
2319 struct ethtool_eeprom *eeprom, u8 *bytes)
2320 {
2321 struct nic *nic = netdev_priv(netdev);
2322
2323 if (eeprom->magic != E100_EEPROM_MAGIC)
2324 return -EINVAL;
2325
2326 memcpy(&((u8 *)nic->eeprom)[eeprom->offset], bytes, eeprom->len);
2327
2328 return e100_eeprom_save(nic, eeprom->offset >> 1,
2329 (eeprom->len >> 1) + 1);
2330 }
2331
2332 static void e100_get_ringparam(struct net_device *netdev,
2333 struct ethtool_ringparam *ring)
2334 {
2335 struct nic *nic = netdev_priv(netdev);
2336 struct param_range *rfds = &nic->params.rfds;
2337 struct param_range *cbs = &nic->params.cbs;
2338
2339 ring->rx_max_pending = rfds->max;
2340 ring->tx_max_pending = cbs->max;
2341 ring->rx_mini_max_pending = 0;
2342 ring->rx_jumbo_max_pending = 0;
2343 ring->rx_pending = rfds->count;
2344 ring->tx_pending = cbs->count;
2345 ring->rx_mini_pending = 0;
2346 ring->rx_jumbo_pending = 0;
2347 }
2348
2349 static int e100_set_ringparam(struct net_device *netdev,
2350 struct ethtool_ringparam *ring)
2351 {
2352 struct nic *nic = netdev_priv(netdev);
2353 struct param_range *rfds = &nic->params.rfds;
2354 struct param_range *cbs = &nic->params.cbs;
2355
2356 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
2357 return -EINVAL;
2358
2359 if (netif_running(netdev))
2360 e100_down(nic);
2361 rfds->count = max(ring->rx_pending, rfds->min);
2362 rfds->count = min(rfds->count, rfds->max);
2363 cbs->count = max(ring->tx_pending, cbs->min);
2364 cbs->count = min(cbs->count, cbs->max);
2365 DPRINTK(DRV, INFO, "Ring Param settings: rx: %d, tx %d\n",
2366 rfds->count, cbs->count);
2367 if (netif_running(netdev))
2368 e100_up(nic);
2369
2370 return 0;
2371 }
2372
2373 static const char e100_gstrings_test[][ETH_GSTRING_LEN] = {
2374 "Link test (on/offline)",
2375 "Eeprom test (on/offline)",
2376 "Self test (offline)",
2377 "Mac loopback (offline)",
2378 "Phy loopback (offline)",
2379 };
2380 #define E100_TEST_LEN ARRAY_SIZE(e100_gstrings_test)
2381
2382 static void e100_diag_test(struct net_device *netdev,
2383 struct ethtool_test *test, u64 *data)
2384 {
2385 struct ethtool_cmd cmd;
2386 struct nic *nic = netdev_priv(netdev);
2387 int i, err;
2388
2389 memset(data, 0, E100_TEST_LEN * sizeof(u64));
2390 data[0] = !mii_link_ok(&nic->mii);
2391 data[1] = e100_eeprom_load(nic);
2392 if (test->flags & ETH_TEST_FL_OFFLINE) {
2393
2394 /* save speed, duplex & autoneg settings */
2395 err = mii_ethtool_gset(&nic->mii, &cmd);
2396
2397 if (netif_running(netdev))
2398 e100_down(nic);
2399 data[2] = e100_self_test(nic);
2400 data[3] = e100_loopback_test(nic, lb_mac);
2401 data[4] = e100_loopback_test(nic, lb_phy);
2402
2403 /* restore speed, duplex & autoneg settings */
2404 err = mii_ethtool_sset(&nic->mii, &cmd);
2405
2406 if (netif_running(netdev))
2407 e100_up(nic);
2408 }
2409 for (i = 0; i < E100_TEST_LEN; i++)
2410 test->flags |= data[i] ? ETH_TEST_FL_FAILED : 0;
2411
2412 msleep_interruptible(4 * 1000);
2413 }
2414
2415 static int e100_phys_id(struct net_device *netdev, u32 data)
2416 {
2417 struct nic *nic = netdev_priv(netdev);
2418 u16 led_reg = (nic->phy == phy_82552_v) ? E100_82552_LED_OVERRIDE :
2419 MII_LED_CONTROL;
2420
2421 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
2422 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
2423 mod_timer(&nic->blink_timer, jiffies);
2424 msleep_interruptible(data * 1000);
2425 del_timer_sync(&nic->blink_timer);
2426 mdio_write(netdev, nic->mii.phy_id, led_reg, 0);
2427
2428 return 0;
2429 }
2430
2431 static const char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
2432 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
2433 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
2434 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
2435 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
2436 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
2437 "tx_heartbeat_errors", "tx_window_errors",
2438 /* device-specific stats */
2439 "tx_deferred", "tx_single_collisions", "tx_multi_collisions",
2440 "tx_flow_control_pause", "rx_flow_control_pause",
2441 "rx_flow_control_unsupported", "tx_tco_packets", "rx_tco_packets",
2442 };
2443 #define E100_NET_STATS_LEN 21
2444 #define E100_STATS_LEN ARRAY_SIZE(e100_gstrings_stats)
2445
2446 static int e100_get_sset_count(struct net_device *netdev, int sset)
2447 {
2448 switch (sset) {
2449 case ETH_SS_TEST:
2450 return E100_TEST_LEN;
2451 case ETH_SS_STATS:
2452 return E100_STATS_LEN;
2453 default:
2454 return -EOPNOTSUPP;
2455 }
2456 }
2457
2458 static void e100_get_ethtool_stats(struct net_device *netdev,
2459 struct ethtool_stats *stats, u64 *data)
2460 {
2461 struct nic *nic = netdev_priv(netdev);
2462 int i;
2463
2464 for (i = 0; i < E100_NET_STATS_LEN; i++)
2465 data[i] = ((unsigned long *)&netdev->stats)[i];
2466
2467 data[i++] = nic->tx_deferred;
2468 data[i++] = nic->tx_single_collisions;
2469 data[i++] = nic->tx_multiple_collisions;
2470 data[i++] = nic->tx_fc_pause;
2471 data[i++] = nic->rx_fc_pause;
2472 data[i++] = nic->rx_fc_unsupported;
2473 data[i++] = nic->tx_tco_frames;
2474 data[i++] = nic->rx_tco_frames;
2475 }
2476
2477 static void e100_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2478 {
2479 switch (stringset) {
2480 case ETH_SS_TEST:
2481 memcpy(data, *e100_gstrings_test, sizeof(e100_gstrings_test));
2482 break;
2483 case ETH_SS_STATS:
2484 memcpy(data, *e100_gstrings_stats, sizeof(e100_gstrings_stats));
2485 break;
2486 }
2487 }
2488
2489 static const struct ethtool_ops e100_ethtool_ops = {
2490 .get_settings = e100_get_settings,
2491 .set_settings = e100_set_settings,
2492 .get_drvinfo = e100_get_drvinfo,
2493 .get_regs_len = e100_get_regs_len,
2494 .get_regs = e100_get_regs,
2495 .get_wol = e100_get_wol,
2496 .set_wol = e100_set_wol,
2497 .get_msglevel = e100_get_msglevel,
2498 .set_msglevel = e100_set_msglevel,
2499 .nway_reset = e100_nway_reset,
2500 .get_link = e100_get_link,
2501 .get_eeprom_len = e100_get_eeprom_len,
2502 .get_eeprom = e100_get_eeprom,
2503 .set_eeprom = e100_set_eeprom,
2504 .get_ringparam = e100_get_ringparam,
2505 .set_ringparam = e100_set_ringparam,
2506 .self_test = e100_diag_test,
2507 .get_strings = e100_get_strings,
2508 .phys_id = e100_phys_id,
2509 .get_ethtool_stats = e100_get_ethtool_stats,
2510 .get_sset_count = e100_get_sset_count,
2511 };
2512
2513 static int e100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2514 {
2515 struct nic *nic = netdev_priv(netdev);
2516
2517 return generic_mii_ioctl(&nic->mii, if_mii(ifr), cmd, NULL);
2518 }
2519
2520 static int e100_alloc(struct nic *nic)
2521 {
2522 nic->mem = pci_alloc_consistent(nic->pdev, sizeof(struct mem),
2523 &nic->dma_addr);
2524 return nic->mem ? 0 : -ENOMEM;
2525 }
2526
2527 static void e100_free(struct nic *nic)
2528 {
2529 if (nic->mem) {
2530 pci_free_consistent(nic->pdev, sizeof(struct mem),
2531 nic->mem, nic->dma_addr);
2532 nic->mem = NULL;
2533 }
2534 }
2535
2536 static int e100_open(struct net_device *netdev)
2537 {
2538 struct nic *nic = netdev_priv(netdev);
2539 int err = 0;
2540
2541 netif_carrier_off(netdev);
2542 if ((err = e100_up(nic)))
2543 DPRINTK(IFUP, ERR, "Cannot open interface, aborting.\n");
2544 return err;
2545 }
2546
2547 static int e100_close(struct net_device *netdev)
2548 {
2549 e100_down(netdev_priv(netdev));
2550 return 0;
2551 }
2552
2553 static const struct net_device_ops e100_netdev_ops = {
2554 .ndo_open = e100_open,
2555 .ndo_stop = e100_close,
2556 .ndo_start_xmit = e100_xmit_frame,
2557 .ndo_validate_addr = eth_validate_addr,
2558 .ndo_set_multicast_list = e100_set_multicast_list,
2559 .ndo_set_mac_address = e100_set_mac_address,
2560 .ndo_change_mtu = e100_change_mtu,
2561 .ndo_do_ioctl = e100_do_ioctl,
2562 .ndo_tx_timeout = e100_tx_timeout,
2563 #ifdef CONFIG_NET_POLL_CONTROLLER
2564 .ndo_poll_controller = e100_netpoll,
2565 #endif
2566 };
2567
2568 static int __devinit e100_probe(struct pci_dev *pdev,
2569 const struct pci_device_id *ent)
2570 {
2571 struct net_device *netdev;
2572 struct nic *nic;
2573 int err;
2574
2575 if (!(netdev = alloc_etherdev(sizeof(struct nic)))) {
2576 if (((1 << debug) - 1) & NETIF_MSG_PROBE)
2577 printk(KERN_ERR PFX "Etherdev alloc failed, abort.\n");
2578 return -ENOMEM;
2579 }
2580
2581 netdev->netdev_ops = &e100_netdev_ops;
2582 SET_ETHTOOL_OPS(netdev, &e100_ethtool_ops);
2583 netdev->watchdog_timeo = E100_WATCHDOG_PERIOD;
2584 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
2585
2586 nic = netdev_priv(netdev);
2587 netif_napi_add(netdev, &nic->napi, e100_poll, E100_NAPI_WEIGHT);
2588 nic->netdev = netdev;
2589 nic->pdev = pdev;
2590 nic->msg_enable = (1 << debug) - 1;
2591 pci_set_drvdata(pdev, netdev);
2592
2593 if ((err = pci_enable_device(pdev))) {
2594 DPRINTK(PROBE, ERR, "Cannot enable PCI device, aborting.\n");
2595 goto err_out_free_dev;
2596 }
2597
2598 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2599 DPRINTK(PROBE, ERR, "Cannot find proper PCI device "
2600 "base address, aborting.\n");
2601 err = -ENODEV;
2602 goto err_out_disable_pdev;
2603 }
2604
2605 if ((err = pci_request_regions(pdev, DRV_NAME))) {
2606 DPRINTK(PROBE, ERR, "Cannot obtain PCI resources, aborting.\n");
2607 goto err_out_disable_pdev;
2608 }
2609
2610 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
2611 DPRINTK(PROBE, ERR, "No usable DMA configuration, aborting.\n");
2612 goto err_out_free_res;
2613 }
2614
2615 SET_NETDEV_DEV(netdev, &pdev->dev);
2616
2617 if (use_io)
2618 DPRINTK(PROBE, INFO, "using i/o access mode\n");
2619
2620 nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
2621 if (!nic->csr) {
2622 DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
2623 err = -ENOMEM;
2624 goto err_out_free_res;
2625 }
2626
2627 if (ent->driver_data)
2628 nic->flags |= ich;
2629 else
2630 nic->flags &= ~ich;
2631
2632 e100_get_defaults(nic);
2633
2634 /* locks must be initialized before calling hw_reset */
2635 spin_lock_init(&nic->cb_lock);
2636 spin_lock_init(&nic->cmd_lock);
2637 spin_lock_init(&nic->mdio_lock);
2638
2639 /* Reset the device before pci_set_master() in case device is in some
2640 * funky state and has an interrupt pending - hint: we don't have the
2641 * interrupt handler registered yet. */
2642 e100_hw_reset(nic);
2643
2644 pci_set_master(pdev);
2645
2646 init_timer(&nic->watchdog);
2647 nic->watchdog.function = e100_watchdog;
2648 nic->watchdog.data = (unsigned long)nic;
2649 init_timer(&nic->blink_timer);
2650 nic->blink_timer.function = e100_blink_led;
2651 nic->blink_timer.data = (unsigned long)nic;
2652
2653 INIT_WORK(&nic->tx_timeout_task, e100_tx_timeout_task);
2654
2655 if ((err = e100_alloc(nic))) {
2656 DPRINTK(PROBE, ERR, "Cannot alloc driver memory, aborting.\n");
2657 goto err_out_iounmap;
2658 }
2659
2660 if ((err = e100_eeprom_load(nic)))
2661 goto err_out_free;
2662
2663 e100_phy_init(nic);
2664
2665 memcpy(netdev->dev_addr, nic->eeprom, ETH_ALEN);
2666 memcpy(netdev->perm_addr, nic->eeprom, ETH_ALEN);
2667 if (!is_valid_ether_addr(netdev->perm_addr)) {
2668 if (!eeprom_bad_csum_allow) {
2669 DPRINTK(PROBE, ERR, "Invalid MAC address from "
2670 "EEPROM, aborting.\n");
2671 err = -EAGAIN;
2672 goto err_out_free;
2673 } else {
2674 DPRINTK(PROBE, ERR, "Invalid MAC address from EEPROM, "
2675 "you MUST configure one.\n");
2676 }
2677 }
2678
2679 /* Wol magic packet can be enabled from eeprom */
2680 if ((nic->mac >= mac_82558_D101_A4) &&
2681 (nic->eeprom[eeprom_id] & eeprom_id_wol)) {
2682 nic->flags |= wol_magic;
2683 device_set_wakeup_enable(&pdev->dev, true);
2684 }
2685
2686 /* ack any pending wake events, disable PME */
2687 pci_pme_active(pdev, false);
2688
2689 strcpy(netdev->name, "eth%d");
2690 if ((err = register_netdev(netdev))) {
2691 DPRINTK(PROBE, ERR, "Cannot register net device, aborting.\n");
2692 goto err_out_free;
2693 }
2694
2695 DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, MAC addr %pM\n",
2696 (unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0),
2697 pdev->irq, netdev->dev_addr);
2698
2699 return 0;
2700
2701 err_out_free:
2702 e100_free(nic);
2703 err_out_iounmap:
2704 pci_iounmap(pdev, nic->csr);
2705 err_out_free_res:
2706 pci_release_regions(pdev);
2707 err_out_disable_pdev:
2708 pci_disable_device(pdev);
2709 err_out_free_dev:
2710 pci_set_drvdata(pdev, NULL);
2711 free_netdev(netdev);
2712 return err;
2713 }
2714
2715 static void __devexit e100_remove(struct pci_dev *pdev)
2716 {
2717 struct net_device *netdev = pci_get_drvdata(pdev);
2718
2719 if (netdev) {
2720 struct nic *nic = netdev_priv(netdev);
2721 unregister_netdev(netdev);
2722 e100_free(nic);
2723 pci_iounmap(pdev, nic->csr);
2724 free_netdev(netdev);
2725 pci_release_regions(pdev);
2726 pci_disable_device(pdev);
2727 pci_set_drvdata(pdev, NULL);
2728 }
2729 }
2730
2731 #define E100_82552_SMARTSPEED 0x14 /* SmartSpeed Ctrl register */
2732 #define E100_82552_REV_ANEG 0x0200 /* Reverse auto-negotiation */
2733 #define E100_82552_ANEG_NOW 0x0400 /* Auto-negotiate now */
2734 static void __e100_shutdown(struct pci_dev *pdev, bool *enable_wake)
2735 {
2736 struct net_device *netdev = pci_get_drvdata(pdev);
2737 struct nic *nic = netdev_priv(netdev);
2738
2739 if (netif_running(netdev))
2740 e100_down(nic);
2741 netif_device_detach(netdev);
2742
2743 pci_save_state(pdev);
2744
2745 if ((nic->flags & wol_magic) | e100_asf(nic)) {
2746 /* enable reverse auto-negotiation */
2747 if (nic->phy == phy_82552_v) {
2748 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2749 E100_82552_SMARTSPEED);
2750
2751 mdio_write(netdev, nic->mii.phy_id,
2752 E100_82552_SMARTSPEED, smartspeed |
2753 E100_82552_REV_ANEG | E100_82552_ANEG_NOW);
2754 }
2755 *enable_wake = true;
2756 } else {
2757 *enable_wake = false;
2758 }
2759
2760 pci_disable_device(pdev);
2761 }
2762
2763 static int __e100_power_off(struct pci_dev *pdev, bool wake)
2764 {
2765 if (wake) {
2766 return pci_prepare_to_sleep(pdev);
2767 } else {
2768 pci_wake_from_d3(pdev, false);
2769 return pci_set_power_state(pdev, PCI_D3hot);
2770 }
2771 }
2772
2773 #ifdef CONFIG_PM
2774 static int e100_suspend(struct pci_dev *pdev, pm_message_t state)
2775 {
2776 bool wake;
2777 __e100_shutdown(pdev, &wake);
2778 return __e100_power_off(pdev, wake);
2779 }
2780
2781 static int e100_resume(struct pci_dev *pdev)
2782 {
2783 struct net_device *netdev = pci_get_drvdata(pdev);
2784 struct nic *nic = netdev_priv(netdev);
2785
2786 pci_set_power_state(pdev, PCI_D0);
2787 pci_restore_state(pdev);
2788 /* ack any pending wake events, disable PME */
2789 pci_enable_wake(pdev, 0, 0);
2790
2791 /* disbale reverse auto-negotiation */
2792 if (nic->phy == phy_82552_v) {
2793 u16 smartspeed = mdio_read(netdev, nic->mii.phy_id,
2794 E100_82552_SMARTSPEED);
2795
2796 mdio_write(netdev, nic->mii.phy_id,
2797 E100_82552_SMARTSPEED,
2798 smartspeed & ~(E100_82552_REV_ANEG));
2799 }
2800
2801 netif_device_attach(netdev);
2802 if (netif_running(netdev))
2803 e100_up(nic);
2804
2805 return 0;
2806 }
2807 #endif /* CONFIG_PM */
2808
2809 static void e100_shutdown(struct pci_dev *pdev)
2810 {
2811 bool wake;
2812 __e100_shutdown(pdev, &wake);
2813 if (system_state == SYSTEM_POWER_OFF)
2814 __e100_power_off(pdev, wake);
2815 }
2816
2817 /* ------------------ PCI Error Recovery infrastructure -------------- */
2818 /**
2819 * e100_io_error_detected - called when PCI error is detected.
2820 * @pdev: Pointer to PCI device
2821 * @state: The current pci connection state
2822 */
2823 static pci_ers_result_t e100_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
2824 {
2825 struct net_device *netdev = pci_get_drvdata(pdev);
2826 struct nic *nic = netdev_priv(netdev);
2827
2828 /* Similar to calling e100_down(), but avoids adapter I/O. */
2829 e100_close(netdev);
2830
2831 /* Detach; put netif into a state similar to hotplug unplug. */
2832 napi_enable(&nic->napi);
2833 netif_device_detach(netdev);
2834 pci_disable_device(pdev);
2835
2836 /* Request a slot reset. */
2837 return PCI_ERS_RESULT_NEED_RESET;
2838 }
2839
2840 /**
2841 * e100_io_slot_reset - called after the pci bus has been reset.
2842 * @pdev: Pointer to PCI device
2843 *
2844 * Restart the card from scratch.
2845 */
2846 static pci_ers_result_t e100_io_slot_reset(struct pci_dev *pdev)
2847 {
2848 struct net_device *netdev = pci_get_drvdata(pdev);
2849 struct nic *nic = netdev_priv(netdev);
2850
2851 if (pci_enable_device(pdev)) {
2852 printk(KERN_ERR "e100: Cannot re-enable PCI device after reset.\n");
2853 return PCI_ERS_RESULT_DISCONNECT;
2854 }
2855 pci_set_master(pdev);
2856
2857 /* Only one device per card can do a reset */
2858 if (0 != PCI_FUNC(pdev->devfn))
2859 return PCI_ERS_RESULT_RECOVERED;
2860 e100_hw_reset(nic);
2861 e100_phy_init(nic);
2862
2863 return PCI_ERS_RESULT_RECOVERED;
2864 }
2865
2866 /**
2867 * e100_io_resume - resume normal operations
2868 * @pdev: Pointer to PCI device
2869 *
2870 * Resume normal operations after an error recovery
2871 * sequence has been completed.
2872 */
2873 static void e100_io_resume(struct pci_dev *pdev)
2874 {
2875 struct net_device *netdev = pci_get_drvdata(pdev);
2876 struct nic *nic = netdev_priv(netdev);
2877
2878 /* ack any pending wake events, disable PME */
2879 pci_enable_wake(pdev, 0, 0);
2880
2881 netif_device_attach(netdev);
2882 if (netif_running(netdev)) {
2883 e100_open(netdev);
2884 mod_timer(&nic->watchdog, jiffies);
2885 }
2886 }
2887
2888 static struct pci_error_handlers e100_err_handler = {
2889 .error_detected = e100_io_error_detected,
2890 .slot_reset = e100_io_slot_reset,
2891 .resume = e100_io_resume,
2892 };
2893
2894 static struct pci_driver e100_driver = {
2895 .name = DRV_NAME,
2896 .id_table = e100_id_table,
2897 .probe = e100_probe,
2898 .remove = __devexit_p(e100_remove),
2899 #ifdef CONFIG_PM
2900 /* Power Management hooks */
2901 .suspend = e100_suspend,
2902 .resume = e100_resume,
2903 #endif
2904 .shutdown = e100_shutdown,
2905 .err_handler = &e100_err_handler,
2906 };
2907
2908 static int __init e100_init_module(void)
2909 {
2910 if (((1 << debug) - 1) & NETIF_MSG_DRV) {
2911 printk(KERN_INFO PFX "%s, %s\n", DRV_DESCRIPTION, DRV_VERSION);
2912 printk(KERN_INFO PFX "%s\n", DRV_COPYRIGHT);
2913 }
2914 return pci_register_driver(&e100_driver);
2915 }
2916
2917 static void __exit e100_cleanup_module(void)
2918 {
2919 pci_unregister_driver(&e100_driver);
2920 }
2921
2922 module_init(e100_init_module);
2923 module_exit(e100_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree