drivers/staging/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2008, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/version.h>
  24
  25 #include <drm/drmP.h>
  26 #include "drm_global.h"
  27 #include "psb_drm.h"
  28 #include "psb_reg.h"
  29 #include "psb_intel_drv.h"
  30 #include "psb_gtt.h"
  31 #include "psb_powermgmt.h"
  32 #include "ttm/ttm_object.h"
  33 #include "psb_ttm_fence_driver.h"
  34 #include "psb_ttm_userobj_api.h"
  35 #include "ttm/ttm_bo_driver.h"
  36 #include "ttm/ttm_lock.h"
  37
  38 /*Append new drm mode definition here, align with libdrm definition*/
  39 #define DRM_MODE_SCALE_NO_SCALE   2
  40
  41 extern struct ttm_bo_driver psb_ttm_bo_driver;
  42
  43 enum {
  44         CHIP_PSB_8108 = 0,
  45         CHIP_PSB_8109 = 1,
  46 };
  47
  48 /*
  49  *Hardware bugfixes
  50  */
  51
  52 #define DRIVER_NAME "pvrsrvkm"
  53 #define DRIVER_DESC "drm driver for the Intel GMA500"
  54 #define DRIVER_AUTHOR "Intel Corporation"
  55 #define OSPM_PROC_ENTRY "ospm"
  56 #define RTPM_PROC_ENTRY "rtpm"
  57 #define BLC_PROC_ENTRY "mrst_blc"
  58 #define DISPLAY_PROC_ENTRY "display_status"
  59
  60 #define PSB_DRM_DRIVER_DATE "2009-03-10"
  61 #define PSB_DRM_DRIVER_MAJOR 8
  62 #define PSB_DRM_DRIVER_MINOR 1
  63 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  64
  65 /*
  66  *TTM driver private offsets.
  67  */
  68
  69 #define DRM_PSB_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  70
  71 #define PSB_OBJECT_HASH_ORDER 13
  72 #define PSB_FILE_OBJECT_HASH_ORDER 12
  73 #define PSB_BO_HASH_ORDER 12
  74
  75 #define PSB_VDC_OFFSET           0x00000000
  76 #define PSB_VDC_SIZE             0x000080000
  77 #define MRST_MMIO_SIZE           0x0000C0000
  78 #define MDFLD_MMIO_SIZE          0x000100000
  79 #define PSB_SGX_SIZE             0x8000
  80 #define PSB_SGX_OFFSET           0x00040000
  81 #define MRST_SGX_OFFSET          0x00080000
  82 #define PSB_MMIO_RESOURCE        0
  83 #define PSB_GATT_RESOURCE        2
  84 #define PSB_GTT_RESOURCE         3
  85 #define PSB_GMCH_CTRL            0x52
  86 #define PSB_BSM                  0x5C
  87 #define _PSB_GMCH_ENABLED        0x4
  88 #define PSB_PGETBL_CTL           0x2020
  89 #define _PSB_PGETBL_ENABLED      0x00000001
  90 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  91 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  92 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  93 #define PSB_NUM_VALIDATE_BUFFERS 2048
  94
  95 #define PSB_MEM_MMU_START       0x00000000
  96 #define PSB_MEM_TT_START        0xE0000000
  97
  98 #define PSB_GL3_CACHE_CTL       0x2100
  99 #define PSB_GL3_CACHE_STAT      0x2108
 100
 101 /*
 102  *Flags for external memory type field.
 103  */
 104
 105 #define MRST_MSVDX_OFFSET       0x90000 /*MSVDX Base offset */
 106 #define PSB_MSVDX_OFFSET        0x50000 /*MSVDX Base offset */
 107 /* MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
 108 #define PSB_MSVDX_SIZE          0x10000
 109
 110 #define LNC_TOPAZ_OFFSET        0xA0000
 111 #define PNW_TOPAZ_OFFSET        0xC0000
 112 #define PNW_GL3_OFFSET          0xB0000
 113 #define LNC_TOPAZ_SIZE          0x10000
 114 #define PNW_TOPAZ_SIZE          0x30000 /* PNW VXE285 has two cores */
 115 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
 116 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
 117 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
 118
 119 /*
 120  *PTE's and PDE's
 121  */
 122
 123 #define PSB_PDE_MASK              0x003FFFFF
 124 #define PSB_PDE_SHIFT             22
 125 #define PSB_PTE_SHIFT             12
 126
 127 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 128 #define PSB_PTE_WO                0x0002        /* Write only */
 129 #define PSB_PTE_RO                0x0004        /* Read only */
 130 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 131
 132 /*
 133  *VDC registers and bits
 134  */
 135 #define PSB_MSVDX_CLOCKGATING     0x2064
 136 #define PSB_TOPAZ_CLOCKGATING     0x2068
 137 #define PSB_HWSTAM                0x2098
 138 #define PSB_INSTPM                0x20C0
 139 #define PSB_INT_IDENTITY_R        0x20A4
 140 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 141 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 142 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 143 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 144 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 145 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 146 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 147 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 148 #define _MDFLD_MIPIA_FLAG         (1<<16)
 149 #define _MDFLD_MIPIC_FLAG         (1<<17)
 150 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 151 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 152 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 153
 154 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 155 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | _MDFLD_PIPEB_EVENT_FLAG | \
 156         _PSB_PIPEA_EVENT_FLAG | _PSB_VSYNC_PIPEA_FLAG | _MDFLD_MIPIA_FLAG | _MDFLD_MIPIC_FLAG)
 157 #define PSB_INT_IDENTITY_R        0x20A4
 158 #define PSB_INT_MASK_R            0x20A8
 159 #define PSB_INT_ENABLE_R          0x20A0
 160
 161 #define _PSB_MMU_ER_MASK      0x0001FF00
 162 #define _PSB_MMU_ER_HOST      (1 << 16)
 163 #define GPIOA                   0x5010
 164 #define GPIOB                   0x5014
 165 #define GPIOC                   0x5018
 166 #define GPIOD                   0x501c
 167 #define GPIOE                   0x5020
 168 #define GPIOF                   0x5024
 169 #define GPIOG                   0x5028
 170 #define GPIOH                   0x502c
 171 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 172 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 173 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 174 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 175 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 176 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 177 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 178 #define GPIO_DATA_DIR_MASK              (1 << 8)
 179 #define GPIO_DATA_DIR_IN                (0 << 9)
 180 #define GPIO_DATA_DIR_OUT               (1 << 9)
 181 #define GPIO_DATA_VAL_MASK              (1 << 10)
 182 #define GPIO_DATA_VAL_OUT               (1 << 11)
 183 #define GPIO_DATA_VAL_IN                (1 << 12)
 184 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 185
 186 #define VCLK_DIVISOR_VGA0   0x6000
 187 #define VCLK_DIVISOR_VGA1   0x6004
 188 #define VCLK_POST_DIV       0x6010
 189
 190 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 191 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 192 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 193 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 194 #define PSB_COMM_USER_IRQ (1024 >> 2)
 195 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 196 #define PSB_COMM_FW (2048 >> 2)
 197
 198 #define PSB_UIRQ_VISTEST               1
 199 #define PSB_UIRQ_OOM_REPLY             2
 200 #define PSB_UIRQ_FIRE_TA_REPLY         3
 201 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 202
 203 #define PSB_2D_SIZE (256*1024*1024)
 204 #define PSB_MAX_RELOC_PAGES 1024
 205
 206 #define PSB_LOW_REG_OFFS 0x0204
 207 #define PSB_HIGH_REG_OFFS 0x0600
 208
 209 #define PSB_NUM_VBLANKS 2
 210
 211
 212 #define PSB_2D_SIZE (256*1024*1024)
 213 #define PSB_MAX_RELOC_PAGES 1024
 214
 215 #define PSB_LOW_REG_OFFS 0x0204
 216 #define PSB_HIGH_REG_OFFS 0x0600
 217
 218 #define PSB_NUM_VBLANKS 2
 219 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 220 #define PSB_LID_DELAY (DRM_HZ / 10)
 221
 222 #define MDFLD_PNW_A0 0x00
 223 #define MDFLD_PNW_B0 0x04
 224 #define MDFLD_PNW_C0 0x08
 225
 226 #define MDFLD_DSR_2D_3D_0 BIT0
 227 #define MDFLD_DSR_2D_3D_2 BIT1
 228 #define MDFLD_DSR_CURSOR_0 BIT2
 229 #define MDFLD_DSR_CURSOR_2 BIT3
 230 #define MDFLD_DSR_OVERLAY_0 BIT4
 231 #define MDFLD_DSR_OVERLAY_2 BIT5
 232 #define MDFLD_DSR_MIPI_CONTROL  BIT6
 233 #define MDFLD_DSR_2D_3D         (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
 234
 235 #define MDFLD_DSR_RR 45
 236 #define MDFLD_DPU_ENABLE BIT31
 237 #define MDFLD_DSR_FULLSCREEN BIT30
 238 #define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
 239
 240 #define PSB_PWR_STATE_ON                1
 241 #define PSB_PWR_STATE_OFF               2
 242
 243 #define PSB_PMPOLICY_NOPM               0
 244 #define PSB_PMPOLICY_CLOCKGATING        1
 245 #define PSB_PMPOLICY_POWERDOWN          2
 246
 247 #define PSB_PMSTATE_POWERUP             0
 248 #define PSB_PMSTATE_CLOCKGATED          1
 249 #define PSB_PMSTATE_POWERDOWN           2
 250 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 251 #define PSB_PCIx_MSI_DATA_LOC           0x98
 252
 253 #define MDFLD_PLANE_MAX_WIDTH           2048
 254 #define MDFLD_PLANE_MAX_HEIGHT          2048
 255
 256 struct opregion_header;
 257 struct opregion_acpi;
 258 struct opregion_swsci;
 259 struct opregion_asle;
 260
 261 struct psb_intel_opregion {
 262         struct opregion_header *header;
 263         struct opregion_acpi *acpi;
 264         struct opregion_swsci *swsci;
 265         struct opregion_asle *asle;
 266         int enabled;
 267 };
 268
 269 /*
 270  *User options.
 271  */
 272
 273 struct drm_psb_uopt {
 274         int pad; /*keep it here in case we use it in future*/
 275 };
 276
 277 /**
 278  *struct psb_context
 279  *
 280  *@buffers:      array of pre-allocated validate buffers.
 281  *@used_buffers: number of buffers in @buffers array currently in use.
 282  *@validate_buffer: buffers validated from user-space.
 283  *@kern_validate_buffers : buffers validated from kernel-space.
 284  *@fence_flags : Fence flags to be used for fence creation.
 285  *
 286  *This structure is used during execbuf validation.
 287  */
 288
 289 struct psb_context {
 290         struct psb_validate_buffer *buffers;
 291         uint32_t used_buffers;
 292         struct list_head validate_list;
 293         struct list_head kern_validate_list;
 294         uint32_t fence_types;
 295         uint32_t val_seq;
 296 };
 297
 298 struct psb_validate_buffer;
 299
 300 /* Currently defined profiles */
 301 enum VAProfile {
 302         VAProfileMPEG2Simple            = 0,
 303         VAProfileMPEG2Main              = 1,
 304         VAProfileMPEG4Simple            = 2,
 305         VAProfileMPEG4AdvancedSimple    = 3,
 306         VAProfileMPEG4Main              = 4,
 307         VAProfileH264Baseline           = 5,
 308         VAProfileH264Main               = 6,
 309         VAProfileH264High               = 7,
 310         VAProfileVC1Simple              = 8,
 311         VAProfileVC1Main                = 9,
 312         VAProfileVC1Advanced            = 10,
 313         VAProfileH263Baseline           = 11,
 314         VAProfileJPEGBaseline           = 12,
 315         VAProfileH264ConstrainedBaseline = 13
 316 };
 317
 318 /* Currently defined entrypoints */
 319 enum VAEntrypoint {
 320         VAEntrypointVLD         = 1,
 321         VAEntrypointIZZ         = 2,
 322         VAEntrypointIDCT        = 3,
 323         VAEntrypointMoComp      = 4,
 324         VAEntrypointDeblocking  = 5,
 325         VAEntrypointEncSlice    = 6,    /* slice level encode */
 326         VAEntrypointEncPicture  = 7     /* pictuer encode, JPEG, etc */
 327 };
 328
 329
 330 struct psb_video_ctx {
 331         struct list_head head;
 332         struct file *filp; /* DRM device file pointer */
 333         int ctx_type; /* profile<<8|entrypoint */
 334         /* todo: more context specific data for multi-context support */
 335 };
 336
 337 #define MODE_SETTING_IN_CRTC    0x1
 338 #define MODE_SETTING_IN_ENCODER 0x2
 339 #define MODE_SETTING_ON_GOING   0x3
 340 #define MODE_SETTING_IN_DSR     0x4
 341 #define MODE_SETTING_ENCODER_DONE 0x8
 342 #define GCT_R10_HEADER_SIZE     16
 343 #define GCT_R10_DISPLAY_DESC_SIZE       28
 344
 345 struct drm_psb_private {
 346         /*
 347          * DSI info.
 348          */
 349         void * dbi_dsr_info;
 350         void * dsi_configs[2];
 351
 352         /*
 353          *TTM Glue.
 354          */
 355
 356         struct drm_global_reference mem_global_ref;
 357         struct ttm_bo_global_ref bo_global_ref;
 358         int has_global;
 359
 360         struct drm_device *dev;
 361         struct ttm_object_device *tdev;
 362         struct ttm_fence_device fdev;
 363         struct ttm_bo_device bdev;
 364         struct ttm_lock ttm_lock;
 365         struct vm_operations_struct *ttm_vm_ops;
 366         int has_fence_device;
 367         int has_bo_device;
 368
 369         unsigned long chipset;
 370
 371         struct drm_psb_dev_info_arg dev_info;
 372         struct drm_psb_uopt uopt;
 373
 374         struct psb_gtt *pg;
 375
 376         /*GTT Memory manager*/
 377         struct psb_gtt_mm *gtt_mm;
 378
 379         struct page *scratch_page;
 380         uint32_t sequence[PSB_NUM_ENGINES];
 381         uint32_t last_sequence[PSB_NUM_ENGINES];
 382         uint32_t last_submitted_seq[PSB_NUM_ENGINES];
 383
 384         struct psb_mmu_driver *mmu;
 385         struct psb_mmu_pd *pf_pd;
 386
 387         uint8_t *sgx_reg;
 388         uint8_t *vdc_reg;
 389         uint32_t gatt_free_offset;
 390
 391         /* IMG video context */
 392         struct list_head video_ctx;
 393
 394
 395
 396         /*
 397          *Fencing / irq.
 398          */
 399
 400         uint32_t vdc_irq_mask;
 401         uint32_t pipestat[PSB_NUM_PIPE];
 402         bool vblanksEnabledForFlips;
 403
 404         spinlock_t irqmask_lock;
 405         spinlock_t sequence_lock;
 406
 407         /*
 408          *Modesetting
 409          */
 410         struct psb_intel_mode_device mode_dev;
 411
 412         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 413         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 414         uint32_t num_pipe;
 415
 416         /*
 417          * CI share buffer
 418          */
 419         unsigned int ci_region_start;
 420         unsigned int ci_region_size;
 421
 422         /*
 423          * RAR share buffer;
 424          */
 425         unsigned int rar_region_start;
 426         unsigned int rar_region_size;
 427
 428         /*
 429          *Memory managers
 430          */
 431
 432         int have_camera;
 433         int have_rar;
 434         int have_tt;
 435         int have_mem_mmu;
 436         struct mutex temp_mem;
 437
 438         /*
 439          *Relocation buffer mapping.
 440          */
 441
 442         spinlock_t reloc_lock;
 443         unsigned int rel_mapped_pages;
 444         wait_queue_head_t rel_mapped_queue;
 445
 446         /*
 447          *SAREA
 448          */
 449         struct drm_psb_sarea *sarea_priv;
 450
 451         /*
 452         *OSPM info
 453         */
 454         uint32_t ospm_base;
 455
 456         /*
 457          * Sizes info
 458          */
 459
 460         struct drm_psb_sizes_arg sizes;
 461
 462         uint32_t fuse_reg_value;
 463
 464         /* pci revision id for B0:D2:F0 */
 465         uint8_t platform_rev_id;
 466
 467         /*
 468          *LVDS info
 469          */
 470         int backlight_duty_cycle;       /* restore backlight to this value */
 471         bool panel_wants_dither;
 472         struct drm_display_mode *panel_fixed_mode;
 473         struct drm_display_mode *lfp_lvds_vbt_mode;
 474         struct drm_display_mode *sdvo_lvds_vbt_mode;
 475
 476         struct bdb_lvds_backlight *lvds_bl; /*LVDS backlight info from VBT*/
 477         struct psb_intel_i2c_chan *lvds_i2c_bus;
 478
 479         /* Feature bits from the VBIOS*/
 480         unsigned int int_tv_support:1;
 481         unsigned int lvds_dither:1;
 482         unsigned int lvds_vbt:1;
 483         unsigned int int_crt_support:1;
 484         unsigned int lvds_use_ssc:1;
 485         int lvds_ssc_freq;
 486         bool is_lvds_on;
 487
 488         unsigned int core_freq;
 489         uint32_t iLVDS_enable;
 490
 491         /*runtime PM state*/
 492         int rpm_enabled;
 493
 494         /*
 495          *Register state
 496          */
 497         uint32_t saveDSPACNTR;
 498         uint32_t saveDSPBCNTR;
 499         uint32_t savePIPEACONF;
 500         uint32_t savePIPEBCONF;
 501         uint32_t savePIPEASRC;
 502         uint32_t savePIPEBSRC;
 503         uint32_t saveFPA0;
 504         uint32_t saveFPA1;
 505         uint32_t saveDPLL_A;
 506         uint32_t saveDPLL_A_MD;
 507         uint32_t saveHTOTAL_A;
 508         uint32_t saveHBLANK_A;
 509         uint32_t saveHSYNC_A;
 510         uint32_t saveVTOTAL_A;
 511         uint32_t saveVBLANK_A;
 512         uint32_t saveVSYNC_A;
 513         uint32_t saveDSPASTRIDE;
 514         uint32_t saveDSPASIZE;
 515         uint32_t saveDSPAPOS;
 516         uint32_t saveDSPABASE;
 517         uint32_t saveDSPASURF;
 518         uint32_t saveFPB0;
 519         uint32_t saveFPB1;
 520         uint32_t saveDPLL_B;
 521         uint32_t saveDPLL_B_MD;
 522         uint32_t saveHTOTAL_B;
 523         uint32_t saveHBLANK_B;
 524         uint32_t saveHSYNC_B;
 525         uint32_t saveVTOTAL_B;
 526         uint32_t saveVBLANK_B;
 527         uint32_t saveVSYNC_B;
 528         uint32_t saveDSPBSTRIDE;
 529         uint32_t saveDSPBSIZE;
 530         uint32_t saveDSPBPOS;
 531         uint32_t saveDSPBBASE;
 532         uint32_t saveDSPBSURF;
 533         uint32_t saveVCLK_DIVISOR_VGA0;
 534         uint32_t saveVCLK_DIVISOR_VGA1;
 535         uint32_t saveVCLK_POST_DIV;
 536         uint32_t saveVGACNTRL;
 537         uint32_t saveADPA;
 538         uint32_t saveLVDS;
 539         uint32_t saveDVOA;
 540         uint32_t saveDVOB;
 541         uint32_t saveDVOC;
 542         uint32_t savePP_ON;
 543         uint32_t savePP_OFF;
 544         uint32_t savePP_CONTROL;
 545         uint32_t savePP_CYCLE;
 546         uint32_t savePFIT_CONTROL;
 547         uint32_t savePaletteA[256];
 548         uint32_t savePaletteB[256];
 549         uint32_t saveBLC_PWM_CTL2;
 550         uint32_t saveBLC_PWM_CTL;
 551         uint32_t saveCLOCKGATING;
 552         uint32_t saveDSPARB;
 553         uint32_t saveDSPATILEOFF;
 554         uint32_t saveDSPBTILEOFF;
 555         uint32_t saveDSPAADDR;
 556         uint32_t saveDSPBADDR;
 557         uint32_t savePFIT_AUTO_RATIOS;
 558         uint32_t savePFIT_PGM_RATIOS;
 559         uint32_t savePP_ON_DELAYS;
 560         uint32_t savePP_OFF_DELAYS;
 561         uint32_t savePP_DIVISOR;
 562         uint32_t saveBSM;
 563         uint32_t saveVBT;
 564         uint32_t saveBCLRPAT_A;
 565         uint32_t saveBCLRPAT_B;
 566         uint32_t saveDSPALINOFF;
 567         uint32_t saveDSPBLINOFF;
 568         uint32_t savePERF_MODE;
 569         uint32_t saveDSPFW1;
 570         uint32_t saveDSPFW2;
 571         uint32_t saveDSPFW3;
 572         uint32_t saveDSPFW4;
 573         uint32_t saveDSPFW5;
 574         uint32_t saveDSPFW6;
 575         uint32_t saveCHICKENBIT;
 576         uint32_t saveDSPACURSOR_CTRL;
 577         uint32_t saveDSPBCURSOR_CTRL;
 578         uint32_t saveDSPACURSOR_BASE;
 579         uint32_t saveDSPBCURSOR_BASE;
 580         uint32_t saveDSPACURSOR_POS;
 581         uint32_t saveDSPBCURSOR_POS;
 582         uint32_t save_palette_a[256];
 583         uint32_t save_palette_b[256];
 584         uint32_t saveOV_OVADD;
 585         uint32_t saveOV_OGAMC0;
 586         uint32_t saveOV_OGAMC1;
 587         uint32_t saveOV_OGAMC2;
 588         uint32_t saveOV_OGAMC3;
 589         uint32_t saveOV_OGAMC4;
 590         uint32_t saveOV_OGAMC5;
 591         uint32_t saveOVC_OVADD;
 592         uint32_t saveOVC_OGAMC0;
 593         uint32_t saveOVC_OGAMC1;
 594         uint32_t saveOVC_OGAMC2;
 595         uint32_t saveOVC_OGAMC3;
 596         uint32_t saveOVC_OGAMC4;
 597         uint32_t saveOVC_OGAMC5;
 598
 599         /*
 600          * extra MDFLD Register state
 601          */
 602         uint32_t saveHDMIPHYMISCCTL;
 603         uint32_t saveHDMIB_CONTROL;
 604         uint32_t saveDSPCCNTR;
 605         uint32_t savePIPECCONF;
 606         uint32_t savePIPECSRC;
 607         uint32_t saveHTOTAL_C;
 608         uint32_t saveHBLANK_C;
 609         uint32_t saveHSYNC_C;
 610         uint32_t saveVTOTAL_C;
 611         uint32_t saveVBLANK_C;
 612         uint32_t saveVSYNC_C;
 613         uint32_t saveDSPCSTRIDE;
 614         uint32_t saveDSPCSIZE;
 615         uint32_t saveDSPCPOS;
 616         uint32_t saveDSPCSURF;
 617         uint32_t saveDSPCLINOFF;
 618         uint32_t saveDSPCTILEOFF;
 619         uint32_t saveDSPCCURSOR_CTRL;
 620         uint32_t saveDSPCCURSOR_BASE;
 621         uint32_t saveDSPCCURSOR_POS;
 622         uint32_t save_palette_c[256];
 623         uint32_t saveOV_OVADD_C;
 624         uint32_t saveOV_OGAMC0_C;
 625         uint32_t saveOV_OGAMC1_C;
 626         uint32_t saveOV_OGAMC2_C;
 627         uint32_t saveOV_OGAMC3_C;
 628         uint32_t saveOV_OGAMC4_C;
 629         uint32_t saveOV_OGAMC5_C;
 630
 631         /* DSI reg save */
 632         uint32_t saveDEVICE_READY_REG;
 633         uint32_t saveINTR_EN_REG;
 634         uint32_t saveDSI_FUNC_PRG_REG;
 635         uint32_t saveHS_TX_TIMEOUT_REG;
 636         uint32_t saveLP_RX_TIMEOUT_REG;
 637         uint32_t saveTURN_AROUND_TIMEOUT_REG;
 638         uint32_t saveDEVICE_RESET_REG;
 639         uint32_t saveDPI_RESOLUTION_REG;
 640         uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
 641         uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
 642         uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
 643         uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
 644         uint32_t saveVERT_SYNC_PAD_COUNT_REG;
 645         uint32_t saveVERT_BACK_PORCH_COUNT_REG;
 646         uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
 647         uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
 648         uint32_t saveINIT_COUNT_REG;
 649         uint32_t saveMAX_RET_PAK_REG;
 650         uint32_t saveVIDEO_FMT_REG;
 651         uint32_t saveEOT_DISABLE_REG;
 652         uint32_t saveLP_BYTECLK_REG;
 653         uint32_t saveHS_LS_DBI_ENABLE_REG;
 654         uint32_t saveTXCLKESC_REG;
 655         uint32_t saveDPHY_PARAM_REG;
 656         uint32_t saveMIPI_CONTROL_REG;
 657         uint32_t saveMIPI;
 658         uint32_t saveMIPI_C;
 659         void (*init_drvIC)(struct drm_device *dev);
 660         void (*dsi_prePowerState)(struct drm_device *dev);
 661         void (*dsi_postPowerState)(struct drm_device *dev);
 662
 663         /* DPST Register Save */
 664         uint32_t saveHISTOGRAM_INT_CONTROL_REG;
 665         uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
 666         uint32_t savePWM_CONTROL_LOGIC;
 667
 668         /* MSI reg save */
 669
 670         uint32_t msi_addr;
 671         uint32_t msi_data;
 672
 673         /*
 674          *Scheduling.
 675          */
 676
 677         struct mutex reset_mutex;
 678         struct mutex cmdbuf_mutex;
 679         /*uint32_t ta_mem_pages;
 680         struct psb_ta_mem *ta_mem;
 681         int force_ta_mem_load;*/
 682         atomic_t val_seq;
 683
 684         /*
 685          *TODO: change this to be per drm-context.
 686          */
 687
 688         struct psb_context context;
 689
 690         /*
 691          * LID-Switch
 692          */
 693         spinlock_t lid_lock;
 694         struct timer_list lid_timer;
 695         struct psb_intel_opregion opregion;
 696         u32 *lid_state;
 697         u32 lid_last_state;
 698
 699         /*
 700          *Watchdog
 701          */
 702
 703         int timer_available;
 704
 705         uint32_t apm_reg;
 706         uint16_t apm_base;
 707
 708         /*
 709          * Used for modifying backlight from
 710          * xrandr -- consider removing and using HAL instead
 711          */
 712         struct drm_property *backlight_property;
 713         uint32_t blc_adj1;
 714         uint32_t blc_adj2;
 715
 716         void * fbdev;
 717 };
 718
 719
 720 struct psb_file_data {  /* TODO: Audit this, remove the indirection and set
 721                            it up properly in open/postclose  ACFIXME */
 722         void *priv;
 723 };
 724
 725 struct psb_fpriv {
 726         struct ttm_object_file *tfile;
 727 };
 728
 729 struct psb_mmu_driver;
 730
 731 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 732 extern int drm_pick_crtcs(struct drm_device *dev);
 733
 734 static inline struct psb_fpriv *psb_fpriv(struct drm_file *file_priv)
 735 {
 736         struct psb_file_data *pvr_file_priv
 737                         = (struct psb_file_data *)file_priv->driver_priv;
 738         return (struct psb_fpriv *) pvr_file_priv->priv;
 739 }
 740
 741 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 742 {
 743         return (struct drm_psb_private *) dev->dev_private;
 744 }
 745
 746 /*
 747  *TTM glue. psb_ttm_glue.c
 748  */
 749
 750 extern int psb_open(struct inode *inode, struct file *filp);
 751 extern int psb_release(struct inode *inode, struct file *filp);
 752 extern int psb_mmap(struct file *filp, struct vm_area_struct *vma);
 753
 754 extern int psb_fence_signaled_ioctl(struct drm_device *dev, void *data,
 755                                     struct drm_file *file_priv);
 756 extern int psb_verify_access(struct ttm_buffer_object *bo,
 757                              struct file *filp);
 758 extern ssize_t psb_ttm_read(struct file *filp, char __user *buf,
 759                             size_t count, loff_t *f_pos);
 760 extern ssize_t psb_ttm_write(struct file *filp, const char __user *buf,
 761                             size_t count, loff_t *f_pos);
 762 extern int psb_fence_finish_ioctl(struct drm_device *dev, void *data,
 763                                   struct drm_file *file_priv);
 764 extern int psb_fence_unref_ioctl(struct drm_device *dev, void *data,
 765                                  struct drm_file *file_priv);
 766 extern int psb_pl_waitidle_ioctl(struct drm_device *dev, void *data,
 767                                  struct drm_file *file_priv);
 768 extern int psb_pl_setstatus_ioctl(struct drm_device *dev, void *data,
 769                                   struct drm_file *file_priv);
 770 extern int psb_pl_synccpu_ioctl(struct drm_device *dev, void *data,
 771                                 struct drm_file *file_priv);
 772 extern int psb_pl_unref_ioctl(struct drm_device *dev, void *data,
 773                               struct drm_file *file_priv);
 774 extern int psb_pl_reference_ioctl(struct drm_device *dev, void *data,
 775                                   struct drm_file *file_priv);
 776 extern int psb_pl_create_ioctl(struct drm_device *dev, void *data,
 777                                struct drm_file *file_priv);
 778 extern int psb_pl_ub_create_ioctl(struct drm_device *dev, void *data,
 779                                struct drm_file *file_priv);
 780 extern int psb_extension_ioctl(struct drm_device *dev, void *data,
 781                                struct drm_file *file_priv);
 782 extern int psb_ttm_global_init(struct drm_psb_private *dev_priv);
 783 extern void psb_ttm_global_release(struct drm_psb_private *dev_priv);
 784 extern int psb_getpageaddrs_ioctl(struct drm_device *dev, void *data,
 785                                 struct drm_file *file_priv);
 786 /*
 787  *MMU stuff.
 788  */
 789
 790 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 791                                         int trap_pagefaults,
 792                                         int invalid_type,
 793                                         struct drm_psb_private *dev_priv);
 794 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 795 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 796                                                  *driver);
 797 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 798                                uint32_t gtt_start, uint32_t gtt_pages);
 799 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 800                                            int trap_pagefaults,
 801                                            int invalid_type);
 802 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 803 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 804 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 805                                         unsigned long address,
 806                                         uint32_t num_pages);
 807 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 808                                        uint32_t start_pfn,
 809                                        unsigned long address,
 810                                        uint32_t num_pages, int type);
 811 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 812                                   unsigned long *pfn);
 813
 814 /*
 815  *Enable / disable MMU for different requestors.
 816  */
 817
 818
 819 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 820 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 821                                 unsigned long address, uint32_t num_pages,
 822                                 uint32_t desired_tile_stride,
 823                                 uint32_t hw_tile_stride, int type);
 824 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 825                                  unsigned long address, uint32_t num_pages,
 826                                  uint32_t desired_tile_stride,
 827                                  uint32_t hw_tile_stride);
 828 /*
 829  *psb_sgx.c
 830  */
 831
 832
 833
 834 extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
 835                             struct drm_file *file_priv);
 836 extern int psb_reg_submit(struct drm_psb_private *dev_priv,
 837                           uint32_t *regs, unsigned int cmds);
 838
 839
 840 extern void psb_fence_or_sync(struct drm_file *file_priv,
 841                               uint32_t engine,
 842                               uint32_t fence_types,
 843                               uint32_t fence_flags,
 844                               struct list_head *list,
 845                               struct psb_ttm_fence_rep *fence_arg,
 846                               struct ttm_fence_object **fence_p);
 847 extern int psb_validate_kernel_buffer(struct psb_context *context,
 848                                       struct ttm_buffer_object *bo,
 849                                       uint32_t fence_class,
 850                                       uint64_t set_flags,
 851                                       uint64_t clr_flags);
 852
 853 /*
 854  *psb_irq.c
 855  */
 856
 857 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 858 extern int psb_irq_enable_dpst(struct drm_device *dev);
 859 extern int psb_irq_disable_dpst(struct drm_device *dev);
 860 extern void psb_irq_preinstall(struct drm_device *dev);
 861 extern int psb_irq_postinstall(struct drm_device *dev);
 862 extern void psb_irq_uninstall(struct drm_device *dev);
 863 extern void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands);
 864 extern int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands);
 865 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 866 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 867
 868 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 869 extern int psb_vblank_wait2(struct drm_device *dev,unsigned int *sequence);
 870 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 871 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 872 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 873 void
 874 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 875
 876 void
 877 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 878
 879 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 880
 881 /*
 882  *psb_fence.c
 883  */
 884
 885 extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
 886
 887 extern int psb_fence_emit_sequence(struct ttm_fence_device *fdev,
 888                                    uint32_t fence_class,
 889                                    uint32_t flags, uint32_t *sequence,
 890                                    unsigned long *timeout_jiffies);
 891 extern void psb_fence_error(struct drm_device *dev,
 892                             uint32_t class,
 893                             uint32_t sequence, uint32_t type, int error);
 894 extern int psb_ttm_fence_device_init(struct ttm_fence_device *fdev);
 895
 896 /* MSVDX/Topaz stuff */
 897 extern int psb_remove_videoctx(struct drm_psb_private *dev_priv, struct file *filp);
 898
 899 extern int lnc_video_frameskip(struct drm_device *dev,
 900                                uint64_t user_pointer);
 901 extern int lnc_video_getparam(struct drm_device *dev, void *data,
 902                               struct drm_file *file_priv);
 903
 904 /*
 905  * psb_opregion.c
 906  */
 907 extern int psb_intel_opregion_init(struct drm_device *dev);
 908
 909 /*
 910  *psb_fb.c
 911  */
 912 extern int psbfb_probed(struct drm_device *dev);
 913 extern int psbfb_remove(struct drm_device *dev,
 914                         struct drm_framebuffer *fb);
 915 extern int psbfb_kms_off_ioctl(struct drm_device *dev, void *data,
 916                                struct drm_file *file_priv);
 917 extern int psbfb_kms_on_ioctl(struct drm_device *dev, void *data,
 918                               struct drm_file *file_priv);
 919 extern void *psbfb_vdc_reg(struct drm_device* dev);
 920
 921 /*
 922  *psb_reset.c
 923  */
 924
 925 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 926 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 927 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 928
 929 /* modesetting */
 930 extern void psb_modeset_init(struct drm_device *dev);
 931 extern void psb_modeset_cleanup(struct drm_device *dev);
 932 extern int psb_fbdev_init(struct drm_device * dev);
 933
 934 /* psb_bl.c */
 935 int psb_backlight_init(struct drm_device *dev);
 936 void psb_backlight_exit(void);
 937 int psb_set_brightness(struct backlight_device *bd);
 938 int psb_get_brightness(struct backlight_device *bd);
 939 struct backlight_device * psb_get_backlight_device(void);
 940
 941 /*
 942  *Debug print bits setting
 943  */
 944 #define PSB_D_GENERAL (1 << 0)
 945 #define PSB_D_INIT    (1 << 1)
 946 #define PSB_D_IRQ     (1 << 2)
 947 #define PSB_D_ENTRY   (1 << 3)
 948 /* debug the get H/V BP/FP count */
 949 #define PSB_D_HV      (1 << 4)
 950 #define PSB_D_DBI_BF  (1 << 5)
 951 #define PSB_D_PM      (1 << 6)
 952 #define PSB_D_RENDER  (1 << 7)
 953 #define PSB_D_REG     (1 << 8)
 954 #define PSB_D_MSVDX   (1 << 9)
 955 #define PSB_D_TOPAZ   (1 << 10)
 956
 957 #ifndef DRM_DEBUG_CODE
 958 /* To enable debug printout, set drm_psb_debug in psb_drv.c
 959  * to any combination of above print flags.
 960  */
 961 /* #define DRM_DEBUG_CODE 2 */
 962 #endif
 963
 964 extern int drm_psb_debug;
 965 extern int drm_psb_no_fb;
 966 extern int drm_psb_disable_vsync;
 967 extern int drm_idle_check_interval;
 968
 969 #define PSB_DEBUG_GENERAL(_fmt, _arg...) \
 970         PSB_DEBUG(PSB_D_GENERAL, _fmt, ##_arg)
 971 #define PSB_DEBUG_INIT(_fmt, _arg...) \
 972         PSB_DEBUG(PSB_D_INIT, _fmt, ##_arg)
 973 #define PSB_DEBUG_IRQ(_fmt, _arg...) \
 974         PSB_DEBUG(PSB_D_IRQ, _fmt, ##_arg)
 975 #define PSB_DEBUG_ENTRY(_fmt, _arg...) \
 976         PSB_DEBUG(PSB_D_ENTRY, _fmt, ##_arg)
 977 #define PSB_DEBUG_HV(_fmt, _arg...) \
 978         PSB_DEBUG(PSB_D_HV, _fmt, ##_arg)
 979 #define PSB_DEBUG_DBI_BF(_fmt, _arg...) \
 980         PSB_DEBUG(PSB_D_DBI_BF, _fmt, ##_arg)
 981 #define PSB_DEBUG_PM(_fmt, _arg...) \
 982         PSB_DEBUG(PSB_D_PM, _fmt, ##_arg)
 983 #define PSB_DEBUG_RENDER(_fmt, _arg...) \
 984         PSB_DEBUG(PSB_D_RENDER, _fmt, ##_arg)
 985 #define PSB_DEBUG_REG(_fmt, _arg...) \
 986         PSB_DEBUG(PSB_D_REG, _fmt, ##_arg)
 987 #define PSB_DEBUG_MSVDX(_fmt, _arg...) \
 988         PSB_DEBUG(PSB_D_MSVDX, _fmt, ##_arg)
 989 #define PSB_DEBUG_TOPAZ(_fmt, _arg...) \
 990         PSB_DEBUG(PSB_D_TOPAZ, _fmt, ##_arg)
 991
 992 #if DRM_DEBUG_CODE
 993 #define PSB_DEBUG(_flag, _fmt, _arg...)                                 \
 994         do {                                                            \
 995                 if (unlikely((_flag) & drm_psb_debug))                  \
 996                         printk(KERN_DEBUG                               \
 997                                "[psb:0x%02x:%s] " _fmt , _flag,         \
 998                                __func__ , ##_arg);                      \
 999         } while (0)
1000 #else
1001 #define PSB_DEBUG(_fmt, _arg...)     do { } while (0)
1002 #endif
1003
1004 /*
1005  *Utilities
1006  */
1007 #define DRM_DRIVER_PRIVATE_T struct drm_psb_private
1008
1009 static inline u32 MRST_MSG_READ32(uint port, uint offset)
1010 {
1011         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
1012         uint32_t ret_val = 0;
1013         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1014         pci_write_config_dword (pci_root, 0xD0, mcr);
1015         pci_read_config_dword (pci_root, 0xD4, &ret_val);
1016         pci_dev_put(pci_root);
1017         return ret_val;
1018 }
1019 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
1020 {
1021         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
1022         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1023         pci_write_config_dword (pci_root, 0xD4, value);
1024         pci_write_config_dword (pci_root, 0xD0, mcr);
1025         pci_dev_put(pci_root);
1026 }
1027 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
1028 {
1029         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
1030         uint32_t ret_val = 0;
1031         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1032         pci_write_config_dword (pci_root, 0xD0, mcr);
1033         pci_read_config_dword (pci_root, 0xD4, &ret_val);
1034         pci_dev_put(pci_root);
1035         return ret_val;
1036 }
1037 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
1038 {
1039         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
1040         struct pci_dev *pci_root = pci_get_bus_and_slot (0, 0);
1041         pci_write_config_dword (pci_root, 0xD4, value);
1042         pci_write_config_dword (pci_root, 0xD0, mcr);
1043         pci_dev_put(pci_root);
1044 }
1045
1046 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
1047 {
1048         struct drm_psb_private *dev_priv = dev->dev_private;
1049         int reg_val = ioread32(dev_priv->vdc_reg + (reg));
1050         PSB_DEBUG_REG("reg = 0x%x. reg_val = 0x%x. \n", reg, reg_val);
1051         return reg_val;
1052 }
1053
1054 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
1055 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
1056                                       uint32_t val)
1057 {
1058         struct drm_psb_private *dev_priv = dev->dev_private;
1059         if ((reg < 0x70084 || reg >0x70088) && (reg < 0xa000 || reg >0xa3ff))
1060                 PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1061
1062         iowrite32((val), dev_priv->vdc_reg + (reg));
1063 }
1064
1065 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
1066
1067 static inline void REGISTER_WRITE16(struct drm_device *dev,
1068                                         uint32_t reg, uint32_t val)
1069 {
1070         struct drm_psb_private *dev_priv = dev->dev_private;
1071
1072         PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1073
1074         iowrite16((val), dev_priv->vdc_reg + (reg));
1075 }
1076
1077 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
1078
1079 static inline void REGISTER_WRITE8(struct drm_device *dev,
1080                                        uint32_t reg, uint32_t val)
1081 {
1082         struct drm_psb_private *dev_priv = dev->dev_private;
1083
1084         PSB_DEBUG_REG("reg = 0x%x, val = 0x%x. \n", reg, val);
1085
1086         iowrite8((val), dev_priv->vdc_reg + (reg));
1087 }
1088
1089 #define REG_WRITE8(reg, val)     REGISTER_WRITE8(dev, (reg), (val))
1090
1091 #define PSB_ALIGN_TO(_val, _align) \
1092   (((_val) + ((_align) - 1)) & ~((_align) - 1))
1093 #define PSB_WVDC32(_val, _offs) \
1094   iowrite32(_val, dev_priv->vdc_reg + (_offs))
1095 #define PSB_RVDC32(_offs) \
1096   ioread32(dev_priv->vdc_reg + (_offs))
1097
1098 /* #define TRAP_SGX_PM_FAULT 1 */
1099 #ifdef TRAP_SGX_PM_FAULT
1100 #define PSB_RSGX32(_offs)                                       \
1101 ({                                                              \
1102     if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {          \
1103         printk(KERN_ERR "access sgx when it's off!! (READ) %s, %d\n", \
1104                __FILE__, __LINE__);                             \
1105         mdelay(1000);                                           \
1106     }                                                           \
1107     ioread32(dev_priv->sgx_reg + (_offs));                      \
1108 })
1109 #else
1110 #define PSB_RSGX32(_offs)                                       \
1111   ioread32(dev_priv->sgx_reg + (_offs))
1112 #endif
1113 #define PSB_WSGX32(_val, _offs) \
1114   iowrite32(_val, dev_priv->sgx_reg + (_offs))
1115
1116 #define MSVDX_REG_DUMP 0
1117 #if MSVDX_REG_DUMP
1118
1119 #define PSB_WMSVDX32(_val, _offs) \
1120   printk("MSVDX: write %08x to reg 0x%08x\n", (unsigned int)(_val), (unsigned int)(_offs));\
1121   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1122 #define PSB_RMSVDX32(_offs) \
1123   ioread32(dev_priv->msvdx_reg + (_offs))
1124
1125 #else
1126
1127 #define PSB_WMSVDX32(_val, _offs) \
1128   iowrite32(_val, dev_priv->msvdx_reg + (_offs))
1129 #define PSB_RMSVDX32(_offs) \
1130   ioread32(dev_priv->msvdx_reg + (_offs))
1131
1132 #endif
1133
1134 #define PSB_ALPL(_val, _base)                   \
1135   (((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT))
1136 #define PSB_ALPLM(_val, _base)                  \
1137   ((((_val) >> (_base ## _ALIGNSHIFT)) << (_base ## _SHIFT)) & (_base ## _MASK))
1138
1139 #endif