2 * linux/arch/arm/mach-integrator/integrator_ap.c
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/sysdev.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
35 #include <mach/hardware.h>
36 #include <mach/platform.h>
37 #include <asm/hardware/arm_timer.h>
39 #include <asm/setup.h>
40 #include <asm/param.h> /* HZ */
41 #include <asm/mach-types.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/flash.h>
47 #include <asm/mach/irq.h>
48 #include <asm/mach/map.h>
49 #include <asm/mach/time.h>
51 #include <plat/fpga-irq.h>
56 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
59 * Setup a VA for the Integrator interrupt controller (for header #0,
62 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
63 #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
64 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
65 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
69 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
70 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
71 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
72 * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
73 * ef000000 Cache flush
74 * f1000000 10000000 Core module registers
75 * f1100000 11000000 System controller registers
76 * f1200000 12000000 EBI registers
77 * f1300000 13000000 Counter/Timer
78 * f1400000 14000000 Interrupt controller
79 * f1600000 16000000 UART 0
80 * f1700000 17000000 UART 1
81 * f1a00000 1a000000 Debug LEDs
82 * f1b00000 1b000000 GPIO
85 static struct map_desc ap_io_desc
[] __initdata
= {
87 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE
),
88 .pfn
= __phys_to_pfn(INTEGRATOR_HDR_BASE
),
92 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE
),
93 .pfn
= __phys_to_pfn(INTEGRATOR_SC_BASE
),
97 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE
),
98 .pfn
= __phys_to_pfn(INTEGRATOR_EBI_BASE
),
102 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE
),
103 .pfn
= __phys_to_pfn(INTEGRATOR_CT_BASE
),
107 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE
),
108 .pfn
= __phys_to_pfn(INTEGRATOR_IC_BASE
),
112 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE
),
113 .pfn
= __phys_to_pfn(INTEGRATOR_UART0_BASE
),
117 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE
),
118 .pfn
= __phys_to_pfn(INTEGRATOR_UART1_BASE
),
122 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE
),
123 .pfn
= __phys_to_pfn(INTEGRATOR_DBG_BASE
),
127 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE
),
128 .pfn
= __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE
),
132 .virtual = PCI_MEMORY_VADDR
,
133 .pfn
= __phys_to_pfn(PHYS_PCI_MEM_BASE
),
137 .virtual = PCI_CONFIG_VADDR
,
138 .pfn
= __phys_to_pfn(PHYS_PCI_CONFIG_BASE
),
142 .virtual = PCI_V3_VADDR
,
143 .pfn
= __phys_to_pfn(PHYS_PCI_V3_BASE
),
147 .virtual = PCI_IO_VADDR
,
148 .pfn
= __phys_to_pfn(PHYS_PCI_IO_BASE
),
154 static void __init
ap_map_io(void)
156 iotable_init(ap_io_desc
, ARRAY_SIZE(ap_io_desc
));
159 #define INTEGRATOR_SC_VALID_INT 0x003fffff
161 static struct fpga_irq_data sc_irq_data
= {
167 static void __init
ap_init_irq(void)
169 /* Disable all interrupts initially. */
170 /* Do the core module ones */
171 writel(-1, VA_CMIC_BASE
+ IRQ_ENABLE_CLEAR
);
173 /* do the header card stuff next */
174 writel(-1, VA_IC_BASE
+ IRQ_ENABLE_CLEAR
);
175 writel(-1, VA_IC_BASE
+ FIQ_ENABLE_CLEAR
);
177 fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT
, &sc_irq_data
);
181 static unsigned long ic_irq_enable
;
183 static int irq_suspend(struct sys_device
*dev
, pm_message_t state
)
185 ic_irq_enable
= readl(VA_IC_BASE
+ IRQ_ENABLE
);
189 static int irq_resume(struct sys_device
*dev
)
191 /* disable all irq sources */
192 writel(-1, VA_CMIC_BASE
+ IRQ_ENABLE_CLEAR
);
193 writel(-1, VA_IC_BASE
+ IRQ_ENABLE_CLEAR
);
194 writel(-1, VA_IC_BASE
+ FIQ_ENABLE_CLEAR
);
196 writel(ic_irq_enable
, VA_IC_BASE
+ IRQ_ENABLE_SET
);
200 #define irq_suspend NULL
201 #define irq_resume NULL
204 static struct sysdev_class irq_class
= {
206 .suspend
= irq_suspend
,
207 .resume
= irq_resume
,
210 static struct sys_device irq_device
= {
215 static int __init
irq_init_sysfs(void)
217 int ret
= sysdev_class_register(&irq_class
);
219 ret
= sysdev_register(&irq_device
);
223 device_initcall(irq_init_sysfs
);
228 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
229 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
230 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
231 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
233 static int ap_flash_init(void)
237 writel(INTEGRATOR_SC_CTRL_nFLVPPEN
| INTEGRATOR_SC_CTRL_nFLWP
, SC_CTRLC
);
239 tmp
= readl(EBI_CSR1
) | INTEGRATOR_EBI_WRITE_ENABLE
;
240 writel(tmp
, EBI_CSR1
);
242 if (!(readl(EBI_CSR1
) & INTEGRATOR_EBI_WRITE_ENABLE
)) {
243 writel(0xa05f, EBI_LOCK
);
244 writel(tmp
, EBI_CSR1
);
250 static void ap_flash_exit(void)
254 writel(INTEGRATOR_SC_CTRL_nFLVPPEN
| INTEGRATOR_SC_CTRL_nFLWP
, SC_CTRLC
);
256 tmp
= readl(EBI_CSR1
) & ~INTEGRATOR_EBI_WRITE_ENABLE
;
257 writel(tmp
, EBI_CSR1
);
259 if (readl(EBI_CSR1
) & INTEGRATOR_EBI_WRITE_ENABLE
) {
260 writel(0xa05f, EBI_LOCK
);
261 writel(tmp
, EBI_CSR1
);
266 static void ap_flash_set_vpp(int on
)
268 void __iomem
*reg
= on
? SC_CTRLS
: SC_CTRLC
;
270 writel(INTEGRATOR_SC_CTRL_nFLVPPEN
, reg
);
273 static struct flash_platform_data ap_flash_data
= {
274 .map_name
= "cfi_probe",
276 .init
= ap_flash_init
,
277 .exit
= ap_flash_exit
,
278 .set_vpp
= ap_flash_set_vpp
,
281 static struct resource cfi_flash_resource
= {
282 .start
= INTEGRATOR_FLASH_BASE
,
283 .end
= INTEGRATOR_FLASH_BASE
+ INTEGRATOR_FLASH_SIZE
- 1,
284 .flags
= IORESOURCE_MEM
,
287 static struct platform_device cfi_flash_device
= {
291 .platform_data
= &ap_flash_data
,
294 .resource
= &cfi_flash_resource
,
297 static void __init
ap_init(void)
299 unsigned long sc_dec
;
302 platform_device_register(&cfi_flash_device
);
304 sc_dec
= readl(VA_SC_BASE
+ INTEGRATOR_SC_DEC_OFFSET
);
305 for (i
= 0; i
< 4; i
++) {
306 struct lm_device
*lmdev
;
308 if ((sc_dec
& (16 << i
)) == 0)
311 lmdev
= kzalloc(sizeof(struct lm_device
), GFP_KERNEL
);
315 lmdev
->resource
.start
= 0xc0000000 + 0x10000000 * i
;
316 lmdev
->resource
.end
= lmdev
->resource
.start
+ 0x0fffffff;
317 lmdev
->resource
.flags
= IORESOURCE_MEM
;
318 lmdev
->irq
= IRQ_AP_EXPINT0
+ i
;
321 lm_device_register(lmdev
);
326 * Where is the timer (VA)?
328 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
329 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
330 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
333 * How long is the timer interval?
335 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
336 #if TIMER_INTERVAL >= 0x100000
337 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
338 #elif TIMER_INTERVAL >= 0x10000
339 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
341 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
344 static unsigned long timer_reload
;
346 static void __iomem
* const clksrc_base
= (void __iomem
*)TIMER2_VA_BASE
;
348 static cycle_t
timersp_read(struct clocksource
*cs
)
350 return ~(readl(clksrc_base
+ TIMER_VALUE
) & 0xffff);
353 static struct clocksource clocksource_timersp
= {
356 .read
= timersp_read
,
357 .mask
= CLOCKSOURCE_MASK(16),
358 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
361 static void integrator_clocksource_init(u32 khz
)
363 struct clocksource
*cs
= &clocksource_timersp
;
364 void __iomem
*base
= clksrc_base
;
365 u32 ctrl
= TIMER_CTRL_ENABLE
;
369 ctrl
= TIMER_CTRL_DIV16
;
372 writel(ctrl
, base
+ TIMER_CTRL
);
373 writel(0xffff, base
+ TIMER_LOAD
);
375 clocksource_register_khz(cs
, khz
);
378 static void __iomem
* const clkevt_base
= (void __iomem
*)TIMER1_VA_BASE
;
381 * IRQ handler for the timer
383 static irqreturn_t
integrator_timer_interrupt(int irq
, void *dev_id
)
385 struct clock_event_device
*evt
= dev_id
;
387 /* clear the interrupt */
388 writel(1, clkevt_base
+ TIMER_INTCLR
);
390 evt
->event_handler(evt
);
395 static void clkevt_set_mode(enum clock_event_mode mode
, struct clock_event_device
*evt
)
397 u32 ctrl
= readl(clkevt_base
+ TIMER_CTRL
) & ~TIMER_CTRL_ENABLE
;
399 BUG_ON(mode
== CLOCK_EVT_MODE_ONESHOT
);
401 if (mode
== CLOCK_EVT_MODE_PERIODIC
) {
402 writel(ctrl
, clkevt_base
+ TIMER_CTRL
);
403 writel(timer_reload
, clkevt_base
+ TIMER_LOAD
);
404 ctrl
|= TIMER_CTRL_PERIODIC
| TIMER_CTRL_ENABLE
;
407 writel(ctrl
, clkevt_base
+ TIMER_CTRL
);
410 static int clkevt_set_next_event(unsigned long next
, struct clock_event_device
*evt
)
412 unsigned long ctrl
= readl(clkevt_base
+ TIMER_CTRL
);
414 writel(ctrl
& ~TIMER_CTRL_ENABLE
, clkevt_base
+ TIMER_CTRL
);
415 writel(next
, clkevt_base
+ TIMER_LOAD
);
416 writel(ctrl
| TIMER_CTRL_ENABLE
, clkevt_base
+ TIMER_CTRL
);
421 static struct clock_event_device integrator_clockevent
= {
424 .features
= CLOCK_EVT_FEAT_PERIODIC
,
425 .set_mode
= clkevt_set_mode
,
426 .set_next_event
= clkevt_set_next_event
,
428 .cpumask
= cpu_all_mask
,
431 static struct irqaction integrator_timer_irq
= {
433 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
,
434 .handler
= integrator_timer_interrupt
,
435 .dev_id
= &integrator_clockevent
,
438 static void integrator_clockevent_init(u32 khz
)
440 struct clock_event_device
*evt
= &integrator_clockevent
;
441 unsigned int ctrl
= 0;
443 if (khz
* 1000 > 0x100000 * HZ
) {
445 ctrl
|= TIMER_CTRL_DIV256
;
446 } else if (khz
* 1000 > 0x10000 * HZ
) {
448 ctrl
|= TIMER_CTRL_DIV16
;
451 timer_reload
= khz
* 1000 / HZ
;
452 writel(ctrl
, clkevt_base
+ TIMER_CTRL
);
454 evt
->irq
= IRQ_TIMERINT1
;
455 evt
->mult
= div_sc(khz
, NSEC_PER_MSEC
, evt
->shift
);
456 evt
->max_delta_ns
= clockevent_delta2ns(0xffff, evt
);
457 evt
->min_delta_ns
= clockevent_delta2ns(0xf, evt
);
459 setup_irq(IRQ_TIMERINT1
, &integrator_timer_irq
);
460 clockevents_register_device(evt
);
466 static void __init
ap_init_timer(void)
468 u32 khz
= TICKS_PER_uSEC
* 1000;
470 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
471 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
472 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
474 integrator_clocksource_init(khz
);
475 integrator_clockevent_init(khz
);
478 static struct sys_timer ap_timer
= {
479 .init
= ap_init_timer
,
482 MACHINE_START(INTEGRATOR
, "ARM-Integrator")
483 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
484 .boot_params
= 0x00000100,
485 .reserve
= integrator_reserve
,
487 .init_early
= integrator_init_early
,
488 .init_irq
= ap_init_irq
,
490 .init_machine
= ap_init
,