2 * Contains common pci routines for ALL ppc platform
3 * (based on pci_32.c and pci_64.c)
5 * Port for PPC64 David Engebretsen, IBM Corp.
6 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
8 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
9 * Rework, based on alpha PCI code.
11 * Common pmac/prep/chrp pci routines. -- Cort
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/string.h>
22 #include <linux/init.h>
23 #include <linux/bootmem.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
31 #include <linux/of_address.h>
33 #include <asm/processor.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/byteorder.h>
38 static DEFINE_SPINLOCK(hose_spinlock
);
41 /* XXX kill that some day ... */
42 static int global_phb_number
; /* Global phb counter */
44 /* ISA Memory physical address */
45 resource_size_t isa_mem_base
;
47 /* Default PCI flags is 0 on ppc32, modified at boot on ppc64 */
48 unsigned int pci_flags
;
50 static struct dma_map_ops
*pci_dma_ops
= &dma_direct_ops
;
52 void set_pci_dma_ops(struct dma_map_ops
*dma_ops
)
54 pci_dma_ops
= dma_ops
;
57 struct dma_map_ops
*get_pci_dma_ops(void)
61 EXPORT_SYMBOL(get_pci_dma_ops
);
63 int pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
65 return dma_set_mask(&dev
->dev
, mask
);
68 int pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
72 rc
= dma_set_mask(&dev
->dev
, mask
);
73 dev
->dev
.coherent_dma_mask
= dev
->dma_mask
;
78 struct pci_controller
*pcibios_alloc_controller(struct device_node
*dev
)
80 struct pci_controller
*phb
;
82 phb
= zalloc_maybe_bootmem(sizeof(struct pci_controller
), GFP_KERNEL
);
85 spin_lock(&hose_spinlock
);
86 phb
->global_number
= global_phb_number
++;
87 list_add_tail(&phb
->list_node
, &hose_list
);
88 spin_unlock(&hose_spinlock
);
90 phb
->is_dynamic
= mem_init_done
;
94 void pcibios_free_controller(struct pci_controller
*phb
)
96 spin_lock(&hose_spinlock
);
97 list_del(&phb
->list_node
);
98 spin_unlock(&hose_spinlock
);
104 static resource_size_t
pcibios_io_size(const struct pci_controller
*hose
)
106 return hose
->io_resource
.end
- hose
->io_resource
.start
+ 1;
109 int pcibios_vaddr_is_ioport(void __iomem
*address
)
112 struct pci_controller
*hose
;
113 resource_size_t size
;
115 spin_lock(&hose_spinlock
);
116 list_for_each_entry(hose
, &hose_list
, list_node
) {
117 size
= pcibios_io_size(hose
);
118 if (address
>= hose
->io_base_virt
&&
119 address
< (hose
->io_base_virt
+ size
)) {
124 spin_unlock(&hose_spinlock
);
128 unsigned long pci_address_to_pio(phys_addr_t address
)
130 struct pci_controller
*hose
;
131 resource_size_t size
;
132 unsigned long ret
= ~0;
134 spin_lock(&hose_spinlock
);
135 list_for_each_entry(hose
, &hose_list
, list_node
) {
136 size
= pcibios_io_size(hose
);
137 if (address
>= hose
->io_base_phys
&&
138 address
< (hose
->io_base_phys
+ size
)) {
140 (unsigned long)hose
->io_base_virt
- _IO_BASE
;
141 ret
= base
+ (address
- hose
->io_base_phys
);
145 spin_unlock(&hose_spinlock
);
149 EXPORT_SYMBOL_GPL(pci_address_to_pio
);
152 * Return the domain number for this bus.
154 int pci_domain_nr(struct pci_bus
*bus
)
156 struct pci_controller
*hose
= pci_bus_to_host(bus
);
158 return hose
->global_number
;
160 EXPORT_SYMBOL(pci_domain_nr
);
162 /* This routine is meant to be used early during boot, when the
163 * PCI bus numbers have not yet been assigned, and you need to
164 * issue PCI config cycles to an OF device.
165 * It could also be used to "fix" RTAS config cycles if you want
166 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
169 struct pci_controller
*pci_find_hose_for_OF_device(struct device_node
*node
)
172 struct pci_controller
*hose
, *tmp
;
173 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
174 if (hose
->dn
== node
)
181 static ssize_t
pci_show_devspec(struct device
*dev
,
182 struct device_attribute
*attr
, char *buf
)
184 struct pci_dev
*pdev
;
185 struct device_node
*np
;
187 pdev
= to_pci_dev(dev
);
188 np
= pci_device_to_OF_node(pdev
);
189 if (np
== NULL
|| np
->full_name
== NULL
)
191 return sprintf(buf
, "%s", np
->full_name
);
193 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
195 /* Add sysfs properties */
196 int pcibios_add_platform_entries(struct pci_dev
*pdev
)
198 return device_create_file(&pdev
->dev
, &dev_attr_devspec
);
201 char __devinit
*pcibios_setup(char *str
)
207 * Reads the interrupt pin to determine if interrupt is use by card.
208 * If the interrupt is used, then gets the interrupt line from the
209 * openfirmware and sets it in the pci_dev and pci_config line.
211 int pci_read_irq_line(struct pci_dev
*pci_dev
)
216 /* The current device-tree that iSeries generates from the HV
217 * PCI informations doesn't contain proper interrupt routing,
218 * and all the fallback would do is print out crap, so we
219 * don't attempt to resolve the interrupts here at all, some
220 * iSeries specific fixup does it.
222 * In the long run, we will hopefully fix the generated device-tree
225 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev
));
228 memset(&oirq
, 0xff, sizeof(oirq
));
230 /* Try to get a mapping from the device-tree */
231 if (of_irq_map_pci(pci_dev
, &oirq
)) {
234 /* If that fails, lets fallback to what is in the config
235 * space and map that through the default controller. We
236 * also set the type to level low since that's what PCI
237 * interrupts are. If your platform does differently, then
238 * either provide a proper interrupt tree or don't use this
241 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_PIN
, &pin
))
245 if (pci_read_config_byte(pci_dev
, PCI_INTERRUPT_LINE
, &line
) ||
246 line
== 0xff || line
== 0) {
249 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
252 virq
= irq_create_mapping(NULL
, line
);
254 set_irq_type(virq
, IRQ_TYPE_LEVEL_LOW
);
256 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
257 oirq
.size
, oirq
.specifier
[0], oirq
.specifier
[1],
258 oirq
.controller
? oirq
.controller
->full_name
:
261 virq
= irq_create_of_mapping(oirq
.controller
, oirq
.specifier
,
264 if (virq
== NO_IRQ
) {
265 pr_debug(" Failed to map !\n");
269 pr_debug(" Mapped to linux irq %d\n", virq
);
275 EXPORT_SYMBOL(pci_read_irq_line
);
278 * Platform support for /proc/bus/pci/X/Y mmap()s,
279 * modelled on the sparc64 implementation by Dave Miller.
284 * Adjust vm_pgoff of VMA such that it is the physical page offset
285 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
287 * Basically, the user finds the base address for his device which he wishes
288 * to mmap. They read the 32-bit value from the config space base register,
289 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
290 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
292 * Returns negative error code on failure, zero on success.
294 static struct resource
*__pci_mmap_make_offset(struct pci_dev
*dev
,
295 resource_size_t
*offset
,
296 enum pci_mmap_state mmap_state
)
298 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
299 unsigned long io_offset
= 0;
303 return NULL
; /* should never happen */
305 /* If memory, add on the PCI bridge address offset */
306 if (mmap_state
== pci_mmap_mem
) {
307 #if 0 /* See comment in pci_resource_to_user() for why this is disabled */
308 *offset
+= hose
->pci_mem_offset
;
310 res_bit
= IORESOURCE_MEM
;
312 io_offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
313 *offset
+= io_offset
;
314 res_bit
= IORESOURCE_IO
;
318 * Check that the offset requested corresponds to one of the
319 * resources of the device.
321 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
322 struct resource
*rp
= &dev
->resource
[i
];
323 int flags
= rp
->flags
;
325 /* treat ROM as memory (should be already) */
326 if (i
== PCI_ROM_RESOURCE
)
327 flags
|= IORESOURCE_MEM
;
329 /* Active and same type? */
330 if ((flags
& res_bit
) == 0)
333 /* In the range of this resource? */
334 if (*offset
< (rp
->start
& PAGE_MASK
) || *offset
> rp
->end
)
337 /* found it! construct the final physical address */
338 if (mmap_state
== pci_mmap_io
)
339 *offset
+= hose
->io_base_phys
- io_offset
;
347 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
350 static pgprot_t
__pci_mmap_set_pgprot(struct pci_dev
*dev
, struct resource
*rp
,
352 enum pci_mmap_state mmap_state
,
355 pgprot_t prot
= protection
;
357 /* Write combine is always 0 on non-memory space mappings. On
358 * memory space, if the user didn't pass 1, we check for a
359 * "prefetchable" resource. This is a bit hackish, but we use
360 * this to workaround the inability of /sysfs to provide a write
363 if (mmap_state
!= pci_mmap_mem
)
365 else if (write_combine
== 0) {
366 if (rp
->flags
& IORESOURCE_PREFETCH
)
370 return pgprot_noncached(prot
);
374 * This one is used by /dev/mem and fbdev who have no clue about the
375 * PCI device, it tries to find the PCI device first and calls the
378 pgprot_t
pci_phys_mem_access_prot(struct file
*file
,
383 struct pci_dev
*pdev
= NULL
;
384 struct resource
*found
= NULL
;
385 resource_size_t offset
= ((resource_size_t
)pfn
) << PAGE_SHIFT
;
388 if (page_is_ram(pfn
))
391 prot
= pgprot_noncached(prot
);
392 for_each_pci_dev(pdev
) {
393 for (i
= 0; i
<= PCI_ROM_RESOURCE
; i
++) {
394 struct resource
*rp
= &pdev
->resource
[i
];
395 int flags
= rp
->flags
;
397 /* Active and same type? */
398 if ((flags
& IORESOURCE_MEM
) == 0)
400 /* In the range of this resource? */
401 if (offset
< (rp
->start
& PAGE_MASK
) ||
411 if (found
->flags
& IORESOURCE_PREFETCH
)
412 prot
= pgprot_noncached_wc(prot
);
416 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
417 (unsigned long long)offset
, pgprot_val(prot
));
423 * Perform the actual remap of the pages for a PCI device mapping, as
424 * appropriate for this architecture. The region in the process to map
425 * is described by vm_start and vm_end members of VMA, the base physical
426 * address is found in vm_pgoff.
427 * The pci device structure is provided so that architectures may make mapping
428 * decisions on a per-device or per-bus basis.
430 * Returns a negative error code on failure, zero on success.
432 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
433 enum pci_mmap_state mmap_state
, int write_combine
)
435 resource_size_t offset
=
436 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
440 rp
= __pci_mmap_make_offset(dev
, &offset
, mmap_state
);
444 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
445 vma
->vm_page_prot
= __pci_mmap_set_pgprot(dev
, rp
,
447 mmap_state
, write_combine
);
449 ret
= remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
450 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
455 /* This provides legacy IO read access on a bus */
456 int pci_legacy_read(struct pci_bus
*bus
, loff_t port
, u32
*val
, size_t size
)
458 unsigned long offset
;
459 struct pci_controller
*hose
= pci_bus_to_host(bus
);
460 struct resource
*rp
= &hose
->io_resource
;
463 /* Check if port can be supported by that bus. We only check
464 * the ranges of the PHB though, not the bus itself as the rules
465 * for forwarding legacy cycles down bridges are not our problem
466 * here. So if the host bridge supports it, we do it.
468 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
471 if (!(rp
->flags
& IORESOURCE_IO
))
473 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
475 addr
= hose
->io_base_virt
+ port
;
479 *((u8
*)val
) = in_8(addr
);
484 *((u16
*)val
) = in_le16(addr
);
489 *((u32
*)val
) = in_le32(addr
);
495 /* This provides legacy IO write access on a bus */
496 int pci_legacy_write(struct pci_bus
*bus
, loff_t port
, u32 val
, size_t size
)
498 unsigned long offset
;
499 struct pci_controller
*hose
= pci_bus_to_host(bus
);
500 struct resource
*rp
= &hose
->io_resource
;
503 /* Check if port can be supported by that bus. We only check
504 * the ranges of the PHB though, not the bus itself as the rules
505 * for forwarding legacy cycles down bridges are not our problem
506 * here. So if the host bridge supports it, we do it.
508 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
511 if (!(rp
->flags
& IORESOURCE_IO
))
513 if (offset
< rp
->start
|| (offset
+ size
) > rp
->end
)
515 addr
= hose
->io_base_virt
+ port
;
517 /* WARNING: The generic code is idiotic. It gets passed a pointer
518 * to what can be a 1, 2 or 4 byte quantity and always reads that
519 * as a u32, which means that we have to correct the location of
520 * the data read within those 32 bits for size 1 and 2
524 out_8(addr
, val
>> 24);
529 out_le16(addr
, val
>> 16);
540 /* This provides legacy IO or memory mmap access on a bus */
541 int pci_mmap_legacy_page_range(struct pci_bus
*bus
,
542 struct vm_area_struct
*vma
,
543 enum pci_mmap_state mmap_state
)
545 struct pci_controller
*hose
= pci_bus_to_host(bus
);
546 resource_size_t offset
=
547 ((resource_size_t
)vma
->vm_pgoff
) << PAGE_SHIFT
;
548 resource_size_t size
= vma
->vm_end
- vma
->vm_start
;
551 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
552 pci_domain_nr(bus
), bus
->number
,
553 mmap_state
== pci_mmap_mem
? "MEM" : "IO",
554 (unsigned long long)offset
,
555 (unsigned long long)(offset
+ size
- 1));
557 if (mmap_state
== pci_mmap_mem
) {
560 * Because X is lame and can fail starting if it gets an error
561 * trying to mmap legacy_mem (instead of just moving on without
562 * legacy memory access) we fake it here by giving it anonymous
563 * memory, effectively behaving just like /dev/zero
565 if ((offset
+ size
) > hose
->isa_mem_size
) {
568 "Process %s (pid:%d) mapped non-existing PCI"
569 "legacy memory for 0%04x:%02x\n",
570 current
->comm
, current
->pid
, pci_domain_nr(bus
),
573 if (vma
->vm_flags
& VM_SHARED
)
574 return shmem_zero_setup(vma
);
577 offset
+= hose
->isa_mem_phys
;
579 unsigned long io_offset
= (unsigned long)hose
->io_base_virt
- \
581 unsigned long roffset
= offset
+ io_offset
;
582 rp
= &hose
->io_resource
;
583 if (!(rp
->flags
& IORESOURCE_IO
))
585 if (roffset
< rp
->start
|| (roffset
+ size
) > rp
->end
)
587 offset
+= hose
->io_base_phys
;
589 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset
);
591 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
592 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
593 return remap_pfn_range(vma
, vma
->vm_start
, vma
->vm_pgoff
,
594 vma
->vm_end
- vma
->vm_start
,
598 void pci_resource_to_user(const struct pci_dev
*dev
, int bar
,
599 const struct resource
*rsrc
,
600 resource_size_t
*start
, resource_size_t
*end
)
602 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
603 resource_size_t offset
= 0;
608 if (rsrc
->flags
& IORESOURCE_IO
)
609 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
611 /* We pass a fully fixed up address to userland for MMIO instead of
612 * a BAR value because X is lame and expects to be able to use that
613 * to pass to /dev/mem !
615 * That means that we'll have potentially 64 bits values where some
616 * userland apps only expect 32 (like X itself since it thinks only
617 * Sparc has 64 bits MMIO) but if we don't do that, we break it on
620 * Hopefully, the sysfs insterface is immune to that gunk. Once X
621 * has been fixed (and the fix spread enough), we can re-enable the
622 * 2 lines below and pass down a BAR value to userland. In that case
623 * we'll also have to re-enable the matching code in
624 * __pci_mmap_make_offset().
629 else if (rsrc
->flags
& IORESOURCE_MEM
)
630 offset
= hose
->pci_mem_offset
;
633 *start
= rsrc
->start
- offset
;
634 *end
= rsrc
->end
- offset
;
638 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
639 * @hose: newly allocated pci_controller to be setup
640 * @dev: device node of the host bridge
641 * @primary: set if primary bus (32 bits only, soon to be deprecated)
643 * This function will parse the "ranges" property of a PCI host bridge device
644 * node and setup the resource mapping of a pci controller based on its
647 * Life would be boring if it wasn't for a few issues that we have to deal
650 * - We can only cope with one IO space range and up to 3 Memory space
651 * ranges. However, some machines (thanks Apple !) tend to split their
652 * space into lots of small contiguous ranges. So we have to coalesce.
654 * - We can only cope with all memory ranges having the same offset
655 * between CPU addresses and PCI addresses. Unfortunately, some bridges
656 * are setup for a large 1:1 mapping along with a small "window" which
657 * maps PCI address 0 to some arbitrary high address of the CPU space in
658 * order to give access to the ISA memory hole.
659 * The way out of here that I've chosen for now is to always set the
660 * offset based on the first resource found, then override it if we
661 * have a different offset and the previous was set by an ISA hole.
663 * - Some busses have IO space not starting at 0, which causes trouble with
664 * the way we do our IO resource renumbering. The code somewhat deals with
665 * it for 64 bits but I would expect problems on 32 bits.
667 * - Some 32 bits platforms such as 4xx can have physical space larger than
668 * 32 bits so we need to use 64 bits values for the parsing
670 void __devinit
pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
671 struct device_node
*dev
,
676 int pna
= of_n_addr_cells(dev
);
678 int memno
= 0, isa_hole
= -1;
680 unsigned long long pci_addr
, cpu_addr
, pci_next
, cpu_next
, size
;
681 unsigned long long isa_mb
= 0;
682 struct resource
*res
;
684 printk(KERN_INFO
"PCI host bridge %s %s ranges:\n",
685 dev
->full_name
, primary
? "(primary)" : "");
687 /* Get ranges property */
688 ranges
= of_get_property(dev
, "ranges", &rlen
);
693 pr_debug("Parsing ranges property...\n");
694 while ((rlen
-= np
* 4) >= 0) {
695 /* Read next ranges element */
696 pci_space
= ranges
[0];
697 pci_addr
= of_read_number(ranges
+ 1, 2);
698 cpu_addr
= of_translate_address(dev
, ranges
+ 3);
699 size
= of_read_number(ranges
+ pna
+ 3, 2);
701 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx "
702 "cpu_addr:0x%016llx size:0x%016llx\n",
703 pci_space
, pci_addr
, cpu_addr
, size
);
707 /* If we failed translation or got a zero-sized region
708 * (some FW try to feed us with non sensical zero sized regions
709 * such as power3 which look like some kind of attempt
710 * at exposing the VGA memory hole)
712 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
715 /* Now consume following elements while they are contiguous */
716 for (; rlen
>= np
* sizeof(u32
);
717 ranges
+= np
, rlen
-= np
* 4) {
718 if (ranges
[0] != pci_space
)
720 pci_next
= of_read_number(ranges
+ 1, 2);
721 cpu_next
= of_translate_address(dev
, ranges
+ 3);
722 if (pci_next
!= pci_addr
+ size
||
723 cpu_next
!= cpu_addr
+ size
)
725 size
+= of_read_number(ranges
+ pna
+ 3, 2);
728 /* Act based on address space type */
730 switch ((pci_space
>> 24) & 0x3) {
731 case 1: /* PCI IO space */
733 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
734 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
);
736 /* We support only one IO range */
737 if (hose
->pci_io_size
) {
739 " \\--> Skipped (too many) !\n");
742 /* On 32 bits, limit I/O space to 16MB */
743 if (size
> 0x01000000)
746 /* 32 bits needs to map IOs here */
747 hose
->io_base_virt
= ioremap(cpu_addr
, size
);
749 /* Expect trouble if pci_addr is not 0 */
752 (unsigned long)hose
->io_base_virt
;
753 /* pci_io_size and io_base_phys always represent IO
754 * space starting at 0 so we factor in pci_addr
756 hose
->pci_io_size
= pci_addr
+ size
;
757 hose
->io_base_phys
= cpu_addr
- pci_addr
;
760 res
= &hose
->io_resource
;
761 res
->flags
= IORESOURCE_IO
;
762 res
->start
= pci_addr
;
764 case 2: /* PCI Memory space */
765 case 3: /* PCI 64 bits Memory space */
767 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
768 cpu_addr
, cpu_addr
+ size
- 1, pci_addr
,
769 (pci_space
& 0x40000000) ? "Prefetch" : "");
771 /* We support only 3 memory ranges */
774 " \\--> Skipped (too many) !\n");
777 /* Handles ISA memory hole space here */
781 if (primary
|| isa_mem_base
== 0)
782 isa_mem_base
= cpu_addr
;
783 hose
->isa_mem_phys
= cpu_addr
;
784 hose
->isa_mem_size
= size
;
787 /* We get the PCI/Mem offset from the first range or
788 * the, current one if the offset came from an ISA
789 * hole. If they don't match, bugger.
792 (isa_hole
>= 0 && pci_addr
!= 0 &&
793 hose
->pci_mem_offset
== isa_mb
))
794 hose
->pci_mem_offset
= cpu_addr
- pci_addr
;
795 else if (pci_addr
!= 0 &&
796 hose
->pci_mem_offset
!= cpu_addr
- pci_addr
) {
798 " \\--> Skipped (offset mismatch) !\n");
803 res
= &hose
->mem_resources
[memno
++];
804 res
->flags
= IORESOURCE_MEM
;
805 if (pci_space
& 0x40000000)
806 res
->flags
|= IORESOURCE_PREFETCH
;
807 res
->start
= cpu_addr
;
811 res
->name
= dev
->full_name
;
812 res
->end
= res
->start
+ size
- 1;
819 /* If there's an ISA hole and the pci_mem_offset is -not- matching
820 * the ISA hole offset, then we need to remove the ISA hole from
821 * the resource list for that brige
823 if (isa_hole
>= 0 && hose
->pci_mem_offset
!= isa_mb
) {
824 unsigned int next
= isa_hole
+ 1;
825 printk(KERN_INFO
" Removing ISA hole at 0x%016llx\n", isa_mb
);
827 memmove(&hose
->mem_resources
[isa_hole
],
828 &hose
->mem_resources
[next
],
829 sizeof(struct resource
) * (memno
- next
));
830 hose
->mem_resources
[--memno
].flags
= 0;
834 /* Decide whether to display the domain number in /proc */
835 int pci_proc_domain(struct pci_bus
*bus
)
837 struct pci_controller
*hose
= pci_bus_to_host(bus
);
839 if (!(pci_flags
& PCI_ENABLE_PROC_DOMAINS
))
841 if (pci_flags
& PCI_COMPAT_DOMAIN_0
)
842 return hose
->global_number
!= 0;
846 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
847 struct resource
*res
)
849 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
850 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
854 if (res
->flags
& IORESOURCE_IO
) {
855 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
857 } else if (res
->flags
& IORESOURCE_MEM
)
858 offset
= hose
->pci_mem_offset
;
860 region
->start
= (res
->start
- offset
) & mask
;
861 region
->end
= (res
->end
- offset
) & mask
;
863 EXPORT_SYMBOL(pcibios_resource_to_bus
);
865 void pcibios_bus_to_resource(struct pci_dev
*dev
, struct resource
*res
,
866 struct pci_bus_region
*region
)
868 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
869 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
873 if (res
->flags
& IORESOURCE_IO
) {
874 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
876 } else if (res
->flags
& IORESOURCE_MEM
)
877 offset
= hose
->pci_mem_offset
;
878 res
->start
= (region
->start
+ offset
) & mask
;
879 res
->end
= (region
->end
+ offset
) & mask
;
881 EXPORT_SYMBOL(pcibios_bus_to_resource
);
883 /* Fixup a bus resource into a linux resource */
884 static void __devinit
fixup_resource(struct resource
*res
, struct pci_dev
*dev
)
886 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
887 resource_size_t offset
= 0, mask
= (resource_size_t
)-1;
889 if (res
->flags
& IORESOURCE_IO
) {
890 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
892 } else if (res
->flags
& IORESOURCE_MEM
)
893 offset
= hose
->pci_mem_offset
;
895 res
->start
= (res
->start
+ offset
) & mask
;
896 res
->end
= (res
->end
+ offset
) & mask
;
899 /* This header fixup will do the resource fixup for all devices as they are
900 * probed, but not for bridge ranges
902 static void __devinit
pcibios_fixup_resources(struct pci_dev
*dev
)
904 struct pci_controller
*hose
= pci_bus_to_host(dev
->bus
);
908 printk(KERN_ERR
"No host bridge for PCI dev %s !\n",
912 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
913 struct resource
*res
= dev
->resource
+ i
;
916 /* On platforms that have PCI_PROBE_ONLY set, we don't
917 * consider 0 as an unassigned BAR value. It's technically
918 * a valid value, but linux doesn't like it... so when we can
919 * re-assign things, we do so, but if we can't, we keep it
920 * around and hope for the best...
922 if (res
->start
== 0 && !(pci_flags
& PCI_PROBE_ONLY
)) {
923 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x]" \
926 (unsigned long long)res
->start
,
927 (unsigned long long)res
->end
,
928 (unsigned int)res
->flags
);
929 res
->end
-= res
->start
;
931 res
->flags
|= IORESOURCE_UNSET
;
935 pr_debug("PCI:%s Resource %d %016llx-%016llx [%x] fixup...\n",
937 (unsigned long long)res
->start
,\
938 (unsigned long long)res
->end
,
939 (unsigned int)res
->flags
);
941 fixup_resource(res
, dev
);
943 pr_debug("PCI:%s %016llx-%016llx\n",
945 (unsigned long long)res
->start
,
946 (unsigned long long)res
->end
);
949 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
951 /* This function tries to figure out if a bridge resource has been initialized
952 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
953 * things go more smoothly when it gets it right. It should covers cases such
954 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
956 static int __devinit
pcibios_uninitialized_bridge_resource(struct pci_bus
*bus
,
957 struct resource
*res
)
959 struct pci_controller
*hose
= pci_bus_to_host(bus
);
960 struct pci_dev
*dev
= bus
->self
;
961 resource_size_t offset
;
965 /* We don't do anything if PCI_PROBE_ONLY is set */
966 if (pci_flags
& PCI_PROBE_ONLY
)
969 /* Job is a bit different between memory and IO */
970 if (res
->flags
& IORESOURCE_MEM
) {
971 /* If the BAR is non-0 (res != pci_mem_offset) then it's
972 * probably been initialized by somebody
974 if (res
->start
!= hose
->pci_mem_offset
)
977 /* The BAR is 0, let's check if memory decoding is enabled on
978 * the bridge. If not, we consider it unassigned
980 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
981 if ((command
& PCI_COMMAND_MEMORY
) == 0)
984 /* Memory decoding is enabled and the BAR is 0. If any of
985 * the bridge resources covers that starting address (0 then
986 * it's good enough for us for memory
988 for (i
= 0; i
< 3; i
++) {
989 if ((hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
) &&
990 hose
->mem_resources
[i
].start
== hose
->pci_mem_offset
)
994 /* Well, it starts at 0 and we know it will collide so we may as
995 * well consider it as unassigned. That covers the Apple case.
999 /* If the BAR is non-0, then we consider it assigned */
1000 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1001 if (((res
->start
- offset
) & 0xfffffffful
) != 0)
1004 /* Here, we are a bit different than memory as typically IO
1005 * space starting at low addresses -is- valid. What we do
1006 * instead if that we consider as unassigned anything that
1007 * doesn't have IO enabled in the PCI command register,
1010 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1011 if (command
& PCI_COMMAND_IO
)
1014 /* It's starting at 0 and IO is disabled in the bridge, consider
1021 /* Fixup resources of a PCI<->PCI bridge */
1022 static void __devinit
pcibios_fixup_bridge(struct pci_bus
*bus
)
1024 struct resource
*res
;
1027 struct pci_dev
*dev
= bus
->self
;
1029 pci_bus_for_each_resource(bus
, res
, i
) {
1030 res
= bus
->resource
[i
];
1035 if (i
>= 3 && bus
->self
->transparent
)
1038 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
1040 (unsigned long long)res
->start
,\
1041 (unsigned long long)res
->end
,
1042 (unsigned int)res
->flags
);
1045 fixup_resource(res
, dev
);
1047 /* Try to detect uninitialized P2P bridge resources,
1048 * and clear them out so they get re-assigned later
1050 if (pcibios_uninitialized_bridge_resource(bus
, res
)) {
1052 pr_debug("PCI:%s (unassigned)\n",
1055 pr_debug("PCI:%s %016llx-%016llx\n",
1057 (unsigned long long)res
->start
,
1058 (unsigned long long)res
->end
);
1063 void __devinit
pcibios_setup_bus_self(struct pci_bus
*bus
)
1065 /* Fix up the bus resources for P2P bridges */
1066 if (bus
->self
!= NULL
)
1067 pcibios_fixup_bridge(bus
);
1070 void __devinit
pcibios_setup_bus_devices(struct pci_bus
*bus
)
1072 struct pci_dev
*dev
;
1074 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1075 bus
->number
, bus
->self
? pci_name(bus
->self
) : "PHB");
1077 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1078 struct dev_archdata
*sd
= &dev
->dev
.archdata
;
1080 /* Setup OF node pointer in archdata */
1081 dev
->dev
.of_node
= pci_device_to_OF_node(dev
);
1083 /* Fixup NUMA node as it may not be setup yet by the generic
1084 * code and is needed by the DMA init
1086 set_dev_node(&dev
->dev
, pcibus_to_node(dev
->bus
));
1088 /* Hook up default DMA ops */
1089 sd
->dma_ops
= pci_dma_ops
;
1090 sd
->dma_data
= (void *)PCI_DRAM_OFFSET
;
1092 /* Read default IRQs and fixup if necessary */
1093 pci_read_irq_line(dev
);
1097 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
1099 /* When called from the generic PCI probe, read PCI<->PCI bridge
1100 * bases. This is -not- called when generating the PCI tree from
1101 * the OF device-tree.
1103 if (bus
->self
!= NULL
)
1104 pci_read_bridge_bases(bus
);
1106 /* Now fixup the bus bus */
1107 pcibios_setup_bus_self(bus
);
1109 /* Now fixup devices on that bus */
1110 pcibios_setup_bus_devices(bus
);
1112 EXPORT_SYMBOL(pcibios_fixup_bus
);
1114 static int skip_isa_ioresource_align(struct pci_dev
*dev
)
1116 if ((pci_flags
& PCI_CAN_SKIP_ISA_ALIGN
) &&
1117 !(dev
->bus
->bridge_ctl
& PCI_BRIDGE_CTL_ISA
))
1123 * We need to avoid collisions with `mirrored' VGA ports
1124 * and other strange ISA hardware, so we always want the
1125 * addresses to be allocated in the 0x000-0x0ff region
1128 * Why? Because some silly external IO cards only decode
1129 * the low 10 bits of the IO address. The 0x00-0xff region
1130 * is reserved for motherboard devices that decode all 16
1131 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1132 * but we want to try to avoid allocating at 0x2900-0x2bff
1133 * which might have be mirrored at 0x0100-0x03ff..
1135 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
1136 resource_size_t size
, resource_size_t align
)
1138 struct pci_dev
*dev
= data
;
1139 resource_size_t start
= res
->start
;
1141 if (res
->flags
& IORESOURCE_IO
) {
1142 if (skip_isa_ioresource_align(dev
))
1145 start
= (start
+ 0x3ff) & ~0x3ff;
1150 EXPORT_SYMBOL(pcibios_align_resource
);
1153 * Reparent resource children of pr that conflict with res
1154 * under res, and make res replace those children.
1156 static int __init
reparent_resources(struct resource
*parent
,
1157 struct resource
*res
)
1159 struct resource
*p
, **pp
;
1160 struct resource
**firstpp
= NULL
;
1162 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
1163 if (p
->end
< res
->start
)
1165 if (res
->end
< p
->start
)
1167 if (p
->start
< res
->start
|| p
->end
> res
->end
)
1168 return -1; /* not completely contained */
1169 if (firstpp
== NULL
)
1172 if (firstpp
== NULL
)
1173 return -1; /* didn't find any conflicting entries? */
1174 res
->parent
= parent
;
1175 res
->child
= *firstpp
;
1179 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
1181 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
1183 (unsigned long long)p
->start
,
1184 (unsigned long long)p
->end
, res
->name
);
1190 * Handle resources of PCI devices. If the world were perfect, we could
1191 * just allocate all the resource regions and do nothing more. It isn't.
1192 * On the other hand, we cannot just re-allocate all devices, as it would
1193 * require us to know lots of host bridge internals. So we attempt to
1194 * keep as much of the original configuration as possible, but tweak it
1195 * when it's found to be wrong.
1197 * Known BIOS problems we have to work around:
1198 * - I/O or memory regions not configured
1199 * - regions configured, but not enabled in the command register
1200 * - bogus I/O addresses above 64K used
1201 * - expansion ROMs left enabled (this may sound harmless, but given
1202 * the fact the PCI specs explicitly allow address decoders to be
1203 * shared between expansion ROMs and other resource regions, it's
1204 * at least dangerous)
1207 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1208 * This gives us fixed barriers on where we can allocate.
1209 * (2) Allocate resources for all enabled devices. If there is
1210 * a collision, just mark the resource as unallocated. Also
1211 * disable expansion ROMs during this step.
1212 * (3) Try to allocate resources for disabled devices. If the
1213 * resources were assigned correctly, everything goes well,
1214 * if they weren't, they won't disturb allocation of other
1216 * (4) Assign new addresses to resources which were either
1217 * not configured at all or misconfigured. If explicitly
1218 * requested by the user, configure expansion ROM address
1222 void pcibios_allocate_bus_resources(struct pci_bus
*bus
)
1226 struct resource
*res
, *pr
;
1228 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1229 pci_domain_nr(bus
), bus
->number
);
1231 pci_bus_for_each_resource(bus
, res
, i
) {
1232 res
= bus
->resource
[i
];
1233 if (!res
|| !res
->flags
1234 || res
->start
> res
->end
|| res
->parent
)
1236 if (bus
->parent
== NULL
)
1237 pr
= (res
->flags
& IORESOURCE_IO
) ?
1238 &ioport_resource
: &iomem_resource
;
1240 /* Don't bother with non-root busses when
1241 * re-assigning all resources. We clear the
1242 * resource flags as if they were colliding
1243 * and as such ensure proper re-allocation
1246 if (pci_flags
& PCI_REASSIGN_ALL_RSRC
)
1247 goto clear_resource
;
1248 pr
= pci_find_parent_resource(bus
->self
, res
);
1250 /* this happens when the generic PCI
1251 * code (wrongly) decides that this
1252 * bridge is transparent -- paulus
1258 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx "
1259 "[0x%x], parent %p (%s)\n",
1260 bus
->self
? pci_name(bus
->self
) : "PHB",
1262 (unsigned long long)res
->start
,
1263 (unsigned long long)res
->end
,
1264 (unsigned int)res
->flags
,
1265 pr
, (pr
&& pr
->name
) ? pr
->name
: "nil");
1267 if (pr
&& !(pr
->flags
& IORESOURCE_UNSET
)) {
1268 if (request_resource(pr
, res
) == 0)
1271 * Must be a conflict with an existing entry.
1272 * Move that entry (or entries) under the
1273 * bridge resource and try again.
1275 if (reparent_resources(pr
, res
) == 0)
1278 printk(KERN_WARNING
"PCI: Cannot allocate resource region "
1279 "%d of PCI bridge %d, will remap\n", i
, bus
->number
);
1281 res
->start
= res
->end
= 0;
1285 list_for_each_entry(b
, &bus
->children
, node
)
1286 pcibios_allocate_bus_resources(b
);
1289 static inline void __devinit
alloc_resource(struct pci_dev
*dev
, int idx
)
1291 struct resource
*pr
, *r
= &dev
->resource
[idx
];
1293 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1295 (unsigned long long)r
->start
,
1296 (unsigned long long)r
->end
,
1297 (unsigned int)r
->flags
);
1299 pr
= pci_find_parent_resource(dev
, r
);
1300 if (!pr
|| (pr
->flags
& IORESOURCE_UNSET
) ||
1301 request_resource(pr
, r
) < 0) {
1302 printk(KERN_WARNING
"PCI: Cannot allocate resource region %d"
1303 " of device %s, will remap\n", idx
, pci_name(dev
));
1305 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1307 (unsigned long long)pr
->start
,
1308 (unsigned long long)pr
->end
,
1309 (unsigned int)pr
->flags
);
1310 /* We'll assign a new address later */
1311 r
->flags
|= IORESOURCE_UNSET
;
1317 static void __init
pcibios_allocate_resources(int pass
)
1319 struct pci_dev
*dev
= NULL
;
1324 for_each_pci_dev(dev
) {
1325 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
1326 for (idx
= 0; idx
<= PCI_ROM_RESOURCE
; idx
++) {
1327 r
= &dev
->resource
[idx
];
1328 if (r
->parent
) /* Already allocated */
1330 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
1331 continue; /* Not assigned at all */
1332 /* We only allocate ROMs on pass 1 just in case they
1333 * have been screwed up by firmware
1335 if (idx
== PCI_ROM_RESOURCE
)
1337 if (r
->flags
& IORESOURCE_IO
)
1338 disabled
= !(command
& PCI_COMMAND_IO
);
1340 disabled
= !(command
& PCI_COMMAND_MEMORY
);
1341 if (pass
== disabled
)
1342 alloc_resource(dev
, idx
);
1346 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
1348 /* Turn the ROM off, leave the resource region,
1349 * but keep it unregistered.
1352 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
1353 if (reg
& PCI_ROM_ADDRESS_ENABLE
) {
1354 pr_debug("PCI: Switching off ROM of %s\n",
1356 r
->flags
&= ~IORESOURCE_ROM_ENABLE
;
1357 pci_write_config_dword(dev
, dev
->rom_base_reg
,
1358 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
1364 static void __init
pcibios_reserve_legacy_regions(struct pci_bus
*bus
)
1366 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1367 resource_size_t offset
;
1368 struct resource
*res
, *pres
;
1371 pr_debug("Reserving legacy ranges for domain %04x\n",
1372 pci_domain_nr(bus
));
1375 if (!(hose
->io_resource
.flags
& IORESOURCE_IO
))
1377 offset
= (unsigned long)hose
->io_base_virt
- _IO_BASE
;
1378 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1379 BUG_ON(res
== NULL
);
1380 res
->name
= "Legacy IO";
1381 res
->flags
= IORESOURCE_IO
;
1382 res
->start
= offset
;
1383 res
->end
= (offset
+ 0xfff) & 0xfffffffful
;
1384 pr_debug("Candidate legacy IO: %pR\n", res
);
1385 if (request_resource(&hose
->io_resource
, res
)) {
1387 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1388 pci_domain_nr(bus
), bus
->number
, res
);
1393 /* Check for memory */
1394 offset
= hose
->pci_mem_offset
;
1395 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset
);
1396 for (i
= 0; i
< 3; i
++) {
1397 pres
= &hose
->mem_resources
[i
];
1398 if (!(pres
->flags
& IORESOURCE_MEM
))
1400 pr_debug("hose mem res: %pR\n", pres
);
1401 if ((pres
->start
- offset
) <= 0xa0000 &&
1402 (pres
->end
- offset
) >= 0xbffff)
1407 res
= kzalloc(sizeof(struct resource
), GFP_KERNEL
);
1408 BUG_ON(res
== NULL
);
1409 res
->name
= "Legacy VGA memory";
1410 res
->flags
= IORESOURCE_MEM
;
1411 res
->start
= 0xa0000 + offset
;
1412 res
->end
= 0xbffff + offset
;
1413 pr_debug("Candidate VGA memory: %pR\n", res
);
1414 if (request_resource(pres
, res
)) {
1416 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1417 pci_domain_nr(bus
), bus
->number
, res
);
1422 void __init
pcibios_resource_survey(void)
1426 /* Allocate and assign resources. If we re-assign everything, then
1427 * we skip the allocate phase
1429 list_for_each_entry(b
, &pci_root_buses
, node
)
1430 pcibios_allocate_bus_resources(b
);
1432 if (!(pci_flags
& PCI_REASSIGN_ALL_RSRC
)) {
1433 pcibios_allocate_resources(0);
1434 pcibios_allocate_resources(1);
1437 /* Before we start assigning unassigned resource, we try to reserve
1438 * the low IO area and the VGA memory area if they intersect the
1439 * bus available resources to avoid allocating things on top of them
1441 if (!(pci_flags
& PCI_PROBE_ONLY
)) {
1442 list_for_each_entry(b
, &pci_root_buses
, node
)
1443 pcibios_reserve_legacy_regions(b
);
1446 /* Now, if the platform didn't decide to blindly trust the firmware,
1447 * we proceed to assigning things that were left unassigned
1449 if (!(pci_flags
& PCI_PROBE_ONLY
)) {
1450 pr_debug("PCI: Assigning unassigned resources...\n");
1451 pci_assign_unassigned_resources();
1455 #ifdef CONFIG_HOTPLUG
1457 /* This is used by the PCI hotplug driver to allocate resource
1458 * of newly plugged busses. We can try to consolidate with the
1459 * rest of the code later, for now, keep it as-is as our main
1460 * resource allocation function doesn't deal with sub-trees yet.
1462 void __devinit
pcibios_claim_one_bus(struct pci_bus
*bus
)
1464 struct pci_dev
*dev
;
1465 struct pci_bus
*child_bus
;
1467 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1470 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++) {
1471 struct resource
*r
= &dev
->resource
[i
];
1473 if (r
->parent
|| !r
->start
|| !r
->flags
)
1476 pr_debug("PCI: Claiming %s: "
1477 "Resource %d: %016llx..%016llx [%x]\n",
1479 (unsigned long long)r
->start
,
1480 (unsigned long long)r
->end
,
1481 (unsigned int)r
->flags
);
1483 pci_claim_resource(dev
, i
);
1487 list_for_each_entry(child_bus
, &bus
->children
, node
)
1488 pcibios_claim_one_bus(child_bus
);
1490 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus
);
1493 /* pcibios_finish_adding_to_bus
1495 * This is to be called by the hotplug code after devices have been
1496 * added to a bus, this include calling it for a PHB that is just
1499 void pcibios_finish_adding_to_bus(struct pci_bus
*bus
)
1501 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1502 pci_domain_nr(bus
), bus
->number
);
1504 /* Allocate bus and devices resources */
1505 pcibios_allocate_bus_resources(bus
);
1506 pcibios_claim_one_bus(bus
);
1508 /* Add new devices to global lists. Register in proc, sysfs. */
1509 pci_bus_add_devices(bus
);
1512 /* eeh_add_device_tree_late(bus); */
1514 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus
);
1516 #endif /* CONFIG_HOTPLUG */
1518 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1520 return pci_enable_resources(dev
, mask
);
1523 void __devinit
pcibios_setup_phb_resources(struct pci_controller
*hose
)
1525 struct pci_bus
*bus
= hose
->bus
;
1526 struct resource
*res
;
1529 /* Hookup PHB IO resource */
1530 bus
->resource
[0] = res
= &hose
->io_resource
;
1533 printk(KERN_WARNING
"PCI: I/O resource not set for host"
1534 " bridge %s (domain %d)\n",
1535 hose
->dn
->full_name
, hose
->global_number
);
1536 /* Workaround for lack of IO resource only on 32-bit */
1537 res
->start
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1538 res
->end
= res
->start
+ IO_SPACE_LIMIT
;
1539 res
->flags
= IORESOURCE_IO
;
1542 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1543 (unsigned long long)res
->start
,
1544 (unsigned long long)res
->end
,
1545 (unsigned long)res
->flags
);
1547 /* Hookup PHB Memory resources */
1548 for (i
= 0; i
< 3; ++i
) {
1549 res
= &hose
->mem_resources
[i
];
1553 printk(KERN_ERR
"PCI: Memory resource 0 not set for "
1554 "host bridge %s (domain %d)\n",
1555 hose
->dn
->full_name
, hose
->global_number
);
1557 /* Workaround for lack of MEM resource only on 32-bit */
1558 res
->start
= hose
->pci_mem_offset
;
1559 res
->end
= (resource_size_t
)-1LL;
1560 res
->flags
= IORESOURCE_MEM
;
1563 bus
->resource
[i
+1] = res
;
1565 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1566 i
, (unsigned long long)res
->start
,
1567 (unsigned long long)res
->end
,
1568 (unsigned long)res
->flags
);
1571 pr_debug("PCI: PHB MEM offset = %016llx\n",
1572 (unsigned long long)hose
->pci_mem_offset
);
1573 pr_debug("PCI: PHB IO offset = %08lx\n",
1574 (unsigned long)hose
->io_base_virt
- _IO_BASE
);
1578 * Null PCI config access functions, for the case when we can't
1581 #define NULL_PCI_OP(rw, size, type) \
1583 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1585 return PCIBIOS_DEVICE_NOT_FOUND; \
1589 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1592 return PCIBIOS_DEVICE_NOT_FOUND
;
1596 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1599 return PCIBIOS_DEVICE_NOT_FOUND
;
1602 static struct pci_ops null_pci_ops
= {
1603 .read
= null_read_config
,
1604 .write
= null_write_config
,
1608 * These functions are used early on before PCI scanning is done
1609 * and all of the pci_dev and pci_bus structures have been created.
1611 static struct pci_bus
*
1612 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1614 static struct pci_bus bus
;
1617 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1621 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1625 #define EARLY_PCI_OP(rw, size, type) \
1626 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1627 int devfn, int offset, type value) \
1629 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1630 devfn, offset, value); \
1633 EARLY_PCI_OP(read
, byte
, u8
*)
1634 EARLY_PCI_OP(read
, word
, u16
*)
1635 EARLY_PCI_OP(read
, dword
, u32
*)
1636 EARLY_PCI_OP(write
, byte
, u8
)
1637 EARLY_PCI_OP(write
, word
, u16
)
1638 EARLY_PCI_OP(write
, dword
, u32
)
1640 int early_find_capability(struct pci_controller
*hose
, int bus
, int devfn
,
1643 return pci_bus_find_capability(fake_pci_bus(hose
, bus
), devfn
, cap
);