?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
tg3: Add EEE support
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / tg3.c
blobf2d96ddd464ec98bfb1d24fd13104d5422d5da48
1 /*
2 * tg3.c: Broadcom Tigon3 ethernet driver.
3 *
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 *
9 * Firmware is:
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
12 *
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
16 */
17
18
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/brcmphy.h>
38 #include <linux/if_vlan.h>
39 #include <linux/ip.h>
40 #include <linux/tcp.h>
41 #include <linux/workqueue.h>
42 #include <linux/prefetch.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/firmware.h>
45
46 #include <net/checksum.h>
47 #include <net/ip.h>
48
49 #include <asm/system.h>
50 #include <asm/io.h>
51 #include <asm/byteorder.h>
52 #include <asm/uaccess.h>
53
54 #ifdef CONFIG_SPARC
55 #include <asm/idprom.h>
56 #include <asm/prom.h>
57 #endif
58
59 #define BAR_0 0
60 #define BAR_2 2
61
62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
63 #define TG3_VLAN_TAG_USED 1
64 #else
65 #define TG3_VLAN_TAG_USED 0
66 #endif
67
68 #include "tg3.h"
69
70 #define DRV_MODULE_NAME "tg3"
71 #define TG3_MAJ_NUM 3
72 #define TG3_MIN_NUM 114
73 #define DRV_MODULE_VERSION \
74 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
75 #define DRV_MODULE_RELDATE "September 30, 2010"
76
77 #define TG3_DEF_MAC_MODE 0
78 #define TG3_DEF_RX_MODE 0
79 #define TG3_DEF_TX_MODE 0
80 #define TG3_DEF_MSG_ENABLE \
81 (NETIF_MSG_DRV | \
82 NETIF_MSG_PROBE | \
83 NETIF_MSG_LINK | \
84 NETIF_MSG_TIMER | \
85 NETIF_MSG_IFDOWN | \
86 NETIF_MSG_IFUP | \
87 NETIF_MSG_RX_ERR | \
88 NETIF_MSG_TX_ERR)
89
90 /* length of time before we decide the hardware is borked,
91 * and dev->tx_timeout() should be called to fix the problem
92 */
93 #define TG3_TX_TIMEOUT (5 * HZ)
94
95 /* hardware minimum and maximum for a single frame's data payload */
96 #define TG3_MIN_MTU 60
97 #define TG3_MAX_MTU(tp) \
98 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
99
100 /* These numbers seem to be hard coded in the NIC firmware somehow.
101 * You can't change the ring sizes, but you can change where you place
102 * them in the NIC onboard memory.
103 */
104 #define TG3_RX_STD_RING_SIZE(tp) \
105 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
107 RX_STD_MAX_SIZE_5717 : 512)
108 #define TG3_DEF_RX_RING_PENDING 200
109 #define TG3_RX_JMB_RING_SIZE(tp) \
110 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
112 1024 : 256)
113 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
114 #define TG3_RSS_INDIR_TBL_SIZE 128
115
116 /* Do not place this n-ring entries value into the tp struct itself,
117 * we really want to expose these constants to GCC so that modulo et
118 * al. operations are done with shifts and masks instead of with
119 * hw multiply/modulo instructions. Another solution would be to
120 * replace things like '% foo' with '& (foo - 1)'.
121 */
122
123 #define TG3_TX_RING_SIZE 512
124 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
125
126 #define TG3_RX_STD_RING_BYTES(tp) \
127 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
128 #define TG3_RX_JMB_RING_BYTES(tp) \
129 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
130 #define TG3_RX_RCB_RING_BYTES(tp) \
131 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
132 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
133 TG3_TX_RING_SIZE)
134 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
135
136 #define TG3_RX_DMA_ALIGN 16
137 #define TG3_RX_HEADROOM ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
138
139 #define TG3_DMA_BYTE_ENAB 64
140
141 #define TG3_RX_STD_DMA_SZ 1536
142 #define TG3_RX_JMB_DMA_SZ 9046
143
144 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
145
146 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
147 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
148
149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
150 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
151
152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
153 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
154
155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
156 * that are at least dword aligned when used in PCIX mode. The driver
157 * works around this bug by double copying the packet. This workaround
158 * is built into the normal double copy length check for efficiency.
159 *
160 * However, the double copy is only necessary on those architectures
161 * where unaligned memory accesses are inefficient. For those architectures
162 * where unaligned memory accesses incur little penalty, we can reintegrate
163 * the 5701 in the normal rx path. Doing so saves a device structure
164 * dereference by hardcoding the double copy threshold in place.
165 */
166 #define TG3_RX_COPY_THRESHOLD 256
167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
168 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
169 #else
170 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
171 #endif
172
173 /* minimum number of free TX descriptors required to wake up TX process */
174 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
175
176 #define TG3_RAW_IP_ALIGN 2
177
178 /* number of ETHTOOL_GSTATS u64's */
179 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
180
181 #define TG3_NUM_TEST 6
182
183 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
184
185 #define FIRMWARE_TG3 "tigon/tg3.bin"
186 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
187 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
188
189 static char version[] __devinitdata =
190 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
191
192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
194 MODULE_LICENSE("GPL");
195 MODULE_VERSION(DRV_MODULE_VERSION);
196 MODULE_FIRMWARE(FIRMWARE_TG3);
197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
199
200 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
201 module_param(tg3_debug, int, 0);
202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
203
204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
260 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
261 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
264 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
277 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
278 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
279 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
280 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
281 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
282 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
283 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
284 {}
285 };
286
287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
288
289 static const struct {
290 const char string[ETH_GSTRING_LEN];
291 } ethtool_stats_keys[TG3_NUM_STATS] = {
292 { "rx_octets" },
293 { "rx_fragments" },
294 { "rx_ucast_packets" },
295 { "rx_mcast_packets" },
296 { "rx_bcast_packets" },
297 { "rx_fcs_errors" },
298 { "rx_align_errors" },
299 { "rx_xon_pause_rcvd" },
300 { "rx_xoff_pause_rcvd" },
301 { "rx_mac_ctrl_rcvd" },
302 { "rx_xoff_entered" },
303 { "rx_frame_too_long_errors" },
304 { "rx_jabbers" },
305 { "rx_undersize_packets" },
306 { "rx_in_length_errors" },
307 { "rx_out_length_errors" },
308 { "rx_64_or_less_octet_packets" },
309 { "rx_65_to_127_octet_packets" },
310 { "rx_128_to_255_octet_packets" },
311 { "rx_256_to_511_octet_packets" },
312 { "rx_512_to_1023_octet_packets" },
313 { "rx_1024_to_1522_octet_packets" },
314 { "rx_1523_to_2047_octet_packets" },
315 { "rx_2048_to_4095_octet_packets" },
316 { "rx_4096_to_8191_octet_packets" },
317 { "rx_8192_to_9022_octet_packets" },
318
319 { "tx_octets" },
320 { "tx_collisions" },
321
322 { "tx_xon_sent" },
323 { "tx_xoff_sent" },
324 { "tx_flow_control" },
325 { "tx_mac_errors" },
326 { "tx_single_collisions" },
327 { "tx_mult_collisions" },
328 { "tx_deferred" },
329 { "tx_excessive_collisions" },
330 { "tx_late_collisions" },
331 { "tx_collide_2times" },
332 { "tx_collide_3times" },
333 { "tx_collide_4times" },
334 { "tx_collide_5times" },
335 { "tx_collide_6times" },
336 { "tx_collide_7times" },
337 { "tx_collide_8times" },
338 { "tx_collide_9times" },
339 { "tx_collide_10times" },
340 { "tx_collide_11times" },
341 { "tx_collide_12times" },
342 { "tx_collide_13times" },
343 { "tx_collide_14times" },
344 { "tx_collide_15times" },
345 { "tx_ucast_packets" },
346 { "tx_mcast_packets" },
347 { "tx_bcast_packets" },
348 { "tx_carrier_sense_errors" },
349 { "tx_discards" },
350 { "tx_errors" },
351
352 { "dma_writeq_full" },
353 { "dma_write_prioq_full" },
354 { "rxbds_empty" },
355 { "rx_discards" },
356 { "rx_errors" },
357 { "rx_threshold_hit" },
358
359 { "dma_readq_full" },
360 { "dma_read_prioq_full" },
361 { "tx_comp_queue_full" },
362
363 { "ring_set_send_prod_index" },
364 { "ring_status_update" },
365 { "nic_irqs" },
366 { "nic_avoided_irqs" },
367 { "nic_tx_threshold_hit" }
368 };
369
370 static const struct {
371 const char string[ETH_GSTRING_LEN];
372 } ethtool_test_keys[TG3_NUM_TEST] = {
373 { "nvram test (online) " },
374 { "link test (online) " },
375 { "register test (offline)" },
376 { "memory test (offline)" },
377 { "loopback test (offline)" },
378 { "interrupt test (offline)" },
379 };
380
381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
382 {
383 writel(val, tp->regs + off);
384 }
385
386 static u32 tg3_read32(struct tg3 *tp, u32 off)
387 {
388 return readl(tp->regs + off);
389 }
390
391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
392 {
393 writel(val, tp->aperegs + off);
394 }
395
396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
397 {
398 return readl(tp->aperegs + off);
399 }
400
401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
402 {
403 unsigned long flags;
404
405 spin_lock_irqsave(&tp->indirect_lock, flags);
406 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
407 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
408 spin_unlock_irqrestore(&tp->indirect_lock, flags);
409 }
410
411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
412 {
413 writel(val, tp->regs + off);
414 readl(tp->regs + off);
415 }
416
417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
418 {
419 unsigned long flags;
420 u32 val;
421
422 spin_lock_irqsave(&tp->indirect_lock, flags);
423 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
424 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
425 spin_unlock_irqrestore(&tp->indirect_lock, flags);
426 return val;
427 }
428
429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
430 {
431 unsigned long flags;
432
433 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
434 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
435 TG3_64BIT_REG_LOW, val);
436 return;
437 }
438 if (off == TG3_RX_STD_PROD_IDX_REG) {
439 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
440 TG3_64BIT_REG_LOW, val);
441 return;
442 }
443
444 spin_lock_irqsave(&tp->indirect_lock, flags);
445 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
446 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
447 spin_unlock_irqrestore(&tp->indirect_lock, flags);
448
449 /* In indirect mode when disabling interrupts, we also need
450 * to clear the interrupt bit in the GRC local ctrl register.
451 */
452 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
453 (val == 0x1)) {
454 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
455 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
456 }
457 }
458
459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
460 {
461 unsigned long flags;
462 u32 val;
463
464 spin_lock_irqsave(&tp->indirect_lock, flags);
465 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
466 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
467 spin_unlock_irqrestore(&tp->indirect_lock, flags);
468 return val;
469 }
470
471 /* usec_wait specifies the wait time in usec when writing to certain registers
472 * where it is unsafe to read back the register without some delay.
473 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
474 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
475 */
476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
477 {
478 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
479 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
480 /* Non-posted methods */
481 tp->write32(tp, off, val);
482 else {
483 /* Posted method */
484 tg3_write32(tp, off, val);
485 if (usec_wait)
486 udelay(usec_wait);
487 tp->read32(tp, off);
488 }
489 /* Wait again after the read for the posted method to guarantee that
490 * the wait time is met.
491 */
492 if (usec_wait)
493 udelay(usec_wait);
494 }
495
496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
497 {
498 tp->write32_mbox(tp, off, val);
499 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
500 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
501 tp->read32_mbox(tp, off);
502 }
503
504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
505 {
506 void __iomem *mbox = tp->regs + off;
507 writel(val, mbox);
508 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
509 writel(val, mbox);
510 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
511 readl(mbox);
512 }
513
514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
515 {
516 return readl(tp->regs + off + GRCMBOX_BASE);
517 }
518
519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
520 {
521 writel(val, tp->regs + off + GRCMBOX_BASE);
522 }
523
524 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
525 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
526 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
527 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
528 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
529
530 #define tw32(reg, val) tp->write32(tp, reg, val)
531 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
532 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
533 #define tr32(reg) tp->read32(tp, reg)
534
535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
536 {
537 unsigned long flags;
538
539 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
540 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
541 return;
542
543 spin_lock_irqsave(&tp->indirect_lock, flags);
544 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
545 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
547
548 /* Always leave this as zero. */
549 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
550 } else {
551 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
552 tw32_f(TG3PCI_MEM_WIN_DATA, val);
553
554 /* Always leave this as zero. */
555 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
556 }
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
558 }
559
560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
561 {
562 unsigned long flags;
563
564 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
565 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
566 *val = 0;
567 return;
568 }
569
570 spin_lock_irqsave(&tp->indirect_lock, flags);
571 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
572 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
573 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
574
575 /* Always leave this as zero. */
576 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
577 } else {
578 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
579 *val = tr32(TG3PCI_MEM_WIN_DATA);
580
581 /* Always leave this as zero. */
582 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
583 }
584 spin_unlock_irqrestore(&tp->indirect_lock, flags);
585 }
586
587 static void tg3_ape_lock_init(struct tg3 *tp)
588 {
589 int i;
590 u32 regbase;
591
592 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
593 regbase = TG3_APE_LOCK_GRANT;
594 else
595 regbase = TG3_APE_PER_LOCK_GRANT;
596
597 /* Make sure the driver hasn't any stale locks. */
598 for (i = 0; i < 8; i++)
599 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
600 }
601
602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
603 {
604 int i, off;
605 int ret = 0;
606 u32 status, req, gnt;
607
608 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
609 return 0;
610
611 switch (locknum) {
612 case TG3_APE_LOCK_GRC:
613 case TG3_APE_LOCK_MEM:
614 break;
615 default:
616 return -EINVAL;
617 }
618
619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
620 req = TG3_APE_LOCK_REQ;
621 gnt = TG3_APE_LOCK_GRANT;
622 } else {
623 req = TG3_APE_PER_LOCK_REQ;
624 gnt = TG3_APE_PER_LOCK_GRANT;
625 }
626
627 off = 4 * locknum;
628
629 tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
630
631 /* Wait for up to 1 millisecond to acquire lock. */
632 for (i = 0; i < 100; i++) {
633 status = tg3_ape_read32(tp, gnt + off);
634 if (status == APE_LOCK_GRANT_DRIVER)
635 break;
636 udelay(10);
637 }
638
639 if (status != APE_LOCK_GRANT_DRIVER) {
640 /* Revoke the lock request. */
641 tg3_ape_write32(tp, gnt + off,
642 APE_LOCK_GRANT_DRIVER);
643
644 ret = -EBUSY;
645 }
646
647 return ret;
648 }
649
650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
651 {
652 u32 gnt;
653
654 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
655 return;
656
657 switch (locknum) {
658 case TG3_APE_LOCK_GRC:
659 case TG3_APE_LOCK_MEM:
660 break;
661 default:
662 return;
663 }
664
665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
666 gnt = TG3_APE_LOCK_GRANT;
667 else
668 gnt = TG3_APE_PER_LOCK_GRANT;
669
670 tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
671 }
672
673 static void tg3_disable_ints(struct tg3 *tp)
674 {
675 int i;
676
677 tw32(TG3PCI_MISC_HOST_CTRL,
678 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
679 for (i = 0; i < tp->irq_max; i++)
680 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
681 }
682
683 static void tg3_enable_ints(struct tg3 *tp)
684 {
685 int i;
686
687 tp->irq_sync = 0;
688 wmb();
689
690 tw32(TG3PCI_MISC_HOST_CTRL,
691 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
692
693 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
694 for (i = 0; i < tp->irq_cnt; i++) {
695 struct tg3_napi *tnapi = &tp->napi[i];
696
697 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
698 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
699 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
700
701 tp->coal_now |= tnapi->coal_now;
702 }
703
704 /* Force an initial interrupt */
705 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
706 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
707 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
708 else
709 tw32(HOSTCC_MODE, tp->coal_now);
710
711 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
712 }
713
714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
715 {
716 struct tg3 *tp = tnapi->tp;
717 struct tg3_hw_status *sblk = tnapi->hw_status;
718 unsigned int work_exists = 0;
719
720 /* check for phy events */
721 if (!(tp->tg3_flags &
722 (TG3_FLAG_USE_LINKCHG_REG |
723 TG3_FLAG_POLL_SERDES))) {
724 if (sblk->status & SD_STATUS_LINK_CHG)
725 work_exists = 1;
726 }
727 /* check for RX/TX work to do */
728 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
729 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
730 work_exists = 1;
731
732 return work_exists;
733 }
734
735 /* tg3_int_reenable
736 * similar to tg3_enable_ints, but it accurately determines whether there
737 * is new work pending and can return without flushing the PIO write
738 * which reenables interrupts
739 */
740 static void tg3_int_reenable(struct tg3_napi *tnapi)
741 {
742 struct tg3 *tp = tnapi->tp;
743
744 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
745 mmiowb();
746
747 /* When doing tagged status, this work check is unnecessary.
748 * The last_tag we write above tells the chip which piece of
749 * work we've completed.
750 */
751 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
752 tg3_has_work(tnapi))
753 tw32(HOSTCC_MODE, tp->coalesce_mode |
754 HOSTCC_MODE_ENABLE | tnapi->coal_now);
755 }
756
757 static void tg3_switch_clocks(struct tg3 *tp)
758 {
759 u32 clock_ctrl;
760 u32 orig_clock_ctrl;
761
762 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
763 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
764 return;
765
766 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
767
768 orig_clock_ctrl = clock_ctrl;
769 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
770 CLOCK_CTRL_CLKRUN_OENABLE |
771 0x1f);
772 tp->pci_clock_ctrl = clock_ctrl;
773
774 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
775 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
776 tw32_wait_f(TG3PCI_CLOCK_CTRL,
777 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
778 }
779 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
780 tw32_wait_f(TG3PCI_CLOCK_CTRL,
781 clock_ctrl |
782 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
783 40);
784 tw32_wait_f(TG3PCI_CLOCK_CTRL,
785 clock_ctrl | (CLOCK_CTRL_ALTCLK),
786 40);
787 }
788 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
789 }
790
791 #define PHY_BUSY_LOOPS 5000
792
793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
794 {
795 u32 frame_val;
796 unsigned int loops;
797 int ret;
798
799 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
800 tw32_f(MAC_MI_MODE,
801 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
802 udelay(80);
803 }
804
805 *val = 0x0;
806
807 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
808 MI_COM_PHY_ADDR_MASK);
809 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
810 MI_COM_REG_ADDR_MASK);
811 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
812
813 tw32_f(MAC_MI_COM, frame_val);
814
815 loops = PHY_BUSY_LOOPS;
816 while (loops != 0) {
817 udelay(10);
818 frame_val = tr32(MAC_MI_COM);
819
820 if ((frame_val & MI_COM_BUSY) == 0) {
821 udelay(5);
822 frame_val = tr32(MAC_MI_COM);
823 break;
824 }
825 loops -= 1;
826 }
827
828 ret = -EBUSY;
829 if (loops != 0) {
830 *val = frame_val & MI_COM_DATA_MASK;
831 ret = 0;
832 }
833
834 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
835 tw32_f(MAC_MI_MODE, tp->mi_mode);
836 udelay(80);
837 }
838
839 return ret;
840 }
841
842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
843 {
844 u32 frame_val;
845 unsigned int loops;
846 int ret;
847
848 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
849 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
850 return 0;
851
852 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
853 tw32_f(MAC_MI_MODE,
854 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
855 udelay(80);
856 }
857
858 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
859 MI_COM_PHY_ADDR_MASK);
860 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
861 MI_COM_REG_ADDR_MASK);
862 frame_val |= (val & MI_COM_DATA_MASK);
863 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
864
865 tw32_f(MAC_MI_COM, frame_val);
866
867 loops = PHY_BUSY_LOOPS;
868 while (loops != 0) {
869 udelay(10);
870 frame_val = tr32(MAC_MI_COM);
871 if ((frame_val & MI_COM_BUSY) == 0) {
872 udelay(5);
873 frame_val = tr32(MAC_MI_COM);
874 break;
875 }
876 loops -= 1;
877 }
878
879 ret = -EBUSY;
880 if (loops != 0)
881 ret = 0;
882
883 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
884 tw32_f(MAC_MI_MODE, tp->mi_mode);
885 udelay(80);
886 }
887
888 return ret;
889 }
890
891 static int tg3_bmcr_reset(struct tg3 *tp)
892 {
893 u32 phy_control;
894 int limit, err;
895
896 /* OK, reset it, and poll the BMCR_RESET bit until it
897 * clears or we time out.
898 */
899 phy_control = BMCR_RESET;
900 err = tg3_writephy(tp, MII_BMCR, phy_control);
901 if (err != 0)
902 return -EBUSY;
903
904 limit = 5000;
905 while (limit--) {
906 err = tg3_readphy(tp, MII_BMCR, &phy_control);
907 if (err != 0)
908 return -EBUSY;
909
910 if ((phy_control & BMCR_RESET) == 0) {
911 udelay(40);
912 break;
913 }
914 udelay(10);
915 }
916 if (limit < 0)
917 return -EBUSY;
918
919 return 0;
920 }
921
922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
923 {
924 struct tg3 *tp = bp->priv;
925 u32 val;
926
927 spin_lock_bh(&tp->lock);
928
929 if (tg3_readphy(tp, reg, &val))
930 val = -EIO;
931
932 spin_unlock_bh(&tp->lock);
933
934 return val;
935 }
936
937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
938 {
939 struct tg3 *tp = bp->priv;
940 u32 ret = 0;
941
942 spin_lock_bh(&tp->lock);
943
944 if (tg3_writephy(tp, reg, val))
945 ret = -EIO;
946
947 spin_unlock_bh(&tp->lock);
948
949 return ret;
950 }
951
952 static int tg3_mdio_reset(struct mii_bus *bp)
953 {
954 return 0;
955 }
956
957 static void tg3_mdio_config_5785(struct tg3 *tp)
958 {
959 u32 val;
960 struct phy_device *phydev;
961
962 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
963 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
964 case PHY_ID_BCM50610:
965 case PHY_ID_BCM50610M:
966 val = MAC_PHYCFG2_50610_LED_MODES;
967 break;
968 case PHY_ID_BCMAC131:
969 val = MAC_PHYCFG2_AC131_LED_MODES;
970 break;
971 case PHY_ID_RTL8211C:
972 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
973 break;
974 case PHY_ID_RTL8201E:
975 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
976 break;
977 default:
978 return;
979 }
980
981 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
982 tw32(MAC_PHYCFG2, val);
983
984 val = tr32(MAC_PHYCFG1);
985 val &= ~(MAC_PHYCFG1_RGMII_INT |
986 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
987 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
988 tw32(MAC_PHYCFG1, val);
989
990 return;
991 }
992
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
994 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
995 MAC_PHYCFG2_FMODE_MASK_MASK |
996 MAC_PHYCFG2_GMODE_MASK_MASK |
997 MAC_PHYCFG2_ACT_MASK_MASK |
998 MAC_PHYCFG2_QUAL_MASK_MASK |
999 MAC_PHYCFG2_INBAND_ENABLE;
1000
1001 tw32(MAC_PHYCFG2, val);
1002
1003 val = tr32(MAC_PHYCFG1);
1004 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011 }
1012 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014 tw32(MAC_PHYCFG1, val);
1015
1016 val = tr32(MAC_EXT_RGMII_MODE);
1017 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018 MAC_RGMII_MODE_RX_QUALITY |
1019 MAC_RGMII_MODE_RX_ACTIVITY |
1020 MAC_RGMII_MODE_RX_ENG_DET |
1021 MAC_RGMII_MODE_TX_ENABLE |
1022 MAC_RGMII_MODE_TX_LOWPWR |
1023 MAC_RGMII_MODE_TX_RESET);
1024 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026 val |= MAC_RGMII_MODE_RX_INT_B |
1027 MAC_RGMII_MODE_RX_QUALITY |
1028 MAC_RGMII_MODE_RX_ACTIVITY |
1029 MAC_RGMII_MODE_RX_ENG_DET;
1030 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031 val |= MAC_RGMII_MODE_TX_ENABLE |
1032 MAC_RGMII_MODE_TX_LOWPWR |
1033 MAC_RGMII_MODE_TX_RESET;
1034 }
1035 tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041 tw32_f(MAC_MI_MODE, tp->mi_mode);
1042 udelay(80);
1043
1044 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051 int i;
1052 u32 reg;
1053 struct phy_device *phydev;
1054
1055 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057 u32 is_serdes;
1058
1059 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063 else
1064 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065 TG3_CPMU_PHY_STRAP_IS_SERDES;
1066 if (is_serdes)
1067 tp->phy_addr += 7;
1068 } else
1069 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071 tg3_mdio_start(tp);
1072
1073 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075 return 0;
1076
1077 tp->mdio_bus = mdiobus_alloc();
1078 if (tp->mdio_bus == NULL)
1079 return -ENOMEM;
1080
1081 tp->mdio_bus->name = "tg3 mdio bus";
1082 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084 tp->mdio_bus->priv = tp;
1085 tp->mdio_bus->parent = &tp->pdev->dev;
1086 tp->mdio_bus->read = &tg3_mdio_read;
1087 tp->mdio_bus->write = &tg3_mdio_write;
1088 tp->mdio_bus->reset = &tg3_mdio_reset;
1089 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090 tp->mdio_bus->irq = &tp->mdio_irq[0];
1091
1092 for (i = 0; i < PHY_MAX_ADDR; i++)
1093 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095 /* The bus registration will look for all the PHYs on the mdio bus.
1096 * Unfortunately, it does not ensure the PHY is powered up before
1097 * accessing the PHY ID registers. A chip reset is the
1098 * quickest way to bring the device back to an operational state..
1099 */
1100 if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101 tg3_bmcr_reset(tp);
1102
1103 i = mdiobus_register(tp->mdio_bus);
1104 if (i) {
1105 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106 mdiobus_free(tp->mdio_bus);
1107 return i;
1108 }
1109
1110 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112 if (!phydev || !phydev->drv) {
1113 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114 mdiobus_unregister(tp->mdio_bus);
1115 mdiobus_free(tp->mdio_bus);
1116 return -ENODEV;
1117 }
1118
1119 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120 case PHY_ID_BCM57780:
1121 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123 break;
1124 case PHY_ID_BCM50610:
1125 case PHY_ID_BCM50610M:
1126 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127 PHY_BRCM_RX_REFCLK_UNUSED |
1128 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136 /* fallthru */
1137 case PHY_ID_RTL8211C:
1138 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139 break;
1140 case PHY_ID_RTL8201E:
1141 case PHY_ID_BCMAC131:
1142 phydev->interface = PHY_INTERFACE_MODE_MII;
1143 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145 break;
1146 }
1147
1148 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151 tg3_mdio_config_5785(tp);
1152
1153 return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160 mdiobus_unregister(tp->mdio_bus);
1161 mdiobus_free(tp->mdio_bus);
1162 }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167 int err;
1168
1169 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170 if (err)
1171 goto done;
1172
1173 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174 if (err)
1175 goto done;
1176
1177 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179 if (err)
1180 goto done;
1181
1182 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185 return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190 int err;
1191
1192 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193 if (err)
1194 goto done;
1195
1196 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197 if (err)
1198 goto done;
1199
1200 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202 if (err)
1203 goto done;
1204
1205 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208 return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214 u32 val;
1215
1216 val = tr32(GRC_RX_CPU_EVENT);
1217 val |= GRC_RX_CPU_DRIVER_EVENT;
1218 tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220 tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228 int i;
1229 unsigned int delay_cnt;
1230 long time_remain;
1231
1232 /* If enough time has passed, no wait is necessary. */
1233 time_remain = (long)(tp->last_event_jiffies + 1 +
1234 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235 (long)jiffies;
1236 if (time_remain < 0)
1237 return;
1238
1239 /* Check if we can shorten the wait time. */
1240 delay_cnt = jiffies_to_usecs(time_remain);
1241 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243 delay_cnt = (delay_cnt >> 3) + 1;
1244
1245 for (i = 0; i < delay_cnt; i++) {
1246 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247 break;
1248 udelay(8);
1249 }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255 u32 reg;
1256 u32 val;
1257
1258 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1260 return;
1261
1262 tg3_wait_for_event_ack(tp);
1263
1264 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268 val = 0;
1269 if (!tg3_readphy(tp, MII_BMCR, &reg))
1270 val = reg << 16;
1271 if (!tg3_readphy(tp, MII_BMSR, &reg))
1272 val |= (reg & 0xffff);
1273 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275 val = 0;
1276 if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277 val = reg << 16;
1278 if (!tg3_readphy(tp, MII_LPA, &reg))
1279 val |= (reg & 0xffff);
1280 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282 val = 0;
1283 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285 val = reg << 16;
1286 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287 val |= (reg & 0xffff);
1288 }
1289 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291 if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292 val = reg << 16;
1293 else
1294 val = 0;
1295 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297 tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302 if (!netif_carrier_ok(tp->dev)) {
1303 netif_info(tp, link, tp->dev, "Link is down\n");
1304 tg3_ump_link_report(tp);
1305 } else if (netif_msg_link(tp)) {
1306 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307 (tp->link_config.active_speed == SPEED_1000 ?
1308 1000 :
1309 (tp->link_config.active_speed == SPEED_100 ?
1310 100 : 10)),
1311 (tp->link_config.active_duplex == DUPLEX_FULL ?
1312 "full" : "half"));
1313
1314 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316 "on" : "off",
1317 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318 "on" : "off");
1319 tg3_ump_link_report(tp);
1320 }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325 u16 miireg;
1326
1327 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328 miireg = ADVERTISE_PAUSE_CAP;
1329 else if (flow_ctrl & FLOW_CTRL_TX)
1330 miireg = ADVERTISE_PAUSE_ASYM;
1331 else if (flow_ctrl & FLOW_CTRL_RX)
1332 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333 else
1334 miireg = 0;
1335
1336 return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341 u16 miireg;
1342
1343 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344 miireg = ADVERTISE_1000XPAUSE;
1345 else if (flow_ctrl & FLOW_CTRL_TX)
1346 miireg = ADVERTISE_1000XPSE_ASYM;
1347 else if (flow_ctrl & FLOW_CTRL_RX)
1348 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349 else
1350 miireg = 0;
1351
1352 return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357 u8 cap = 0;
1358
1359 if (lcladv & ADVERTISE_1000XPAUSE) {
1360 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361 if (rmtadv & LPA_1000XPAUSE)
1362 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364 cap = FLOW_CTRL_RX;
1365 } else {
1366 if (rmtadv & LPA_1000XPAUSE)
1367 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368 }
1369 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371 cap = FLOW_CTRL_TX;
1372 }
1373
1374 return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379 u8 autoneg;
1380 u8 flowctrl = 0;
1381 u32 old_rx_mode = tp->rx_mode;
1382 u32 old_tx_mode = tp->tx_mode;
1383
1384 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386 else
1387 autoneg = tp->link_config.autoneg;
1388
1389 if (autoneg == AUTONEG_ENABLE &&
1390 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393 else
1394 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395 } else
1396 flowctrl = tp->link_config.flowctrl;
1397
1398 tp->link_config.active_flowctrl = flowctrl;
1399
1400 if (flowctrl & FLOW_CTRL_RX)
1401 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402 else
1403 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405 if (old_rx_mode != tp->rx_mode)
1406 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408 if (flowctrl & FLOW_CTRL_TX)
1409 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410 else
1411 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413 if (old_tx_mode != tp->tx_mode)
1414 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419 u8 oldflowctrl, linkmesg = 0;
1420 u32 mac_mode, lcl_adv, rmt_adv;
1421 struct tg3 *tp = netdev_priv(dev);
1422 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424 spin_lock_bh(&tp->lock);
1425
1426 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427 MAC_MODE_HALF_DUPLEX);
1428
1429 oldflowctrl = tp->link_config.active_flowctrl;
1430
1431 if (phydev->link) {
1432 lcl_adv = 0;
1433 rmt_adv = 0;
1434
1435 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436 mac_mode |= MAC_MODE_PORT_MODE_MII;
1437 else if (phydev->speed == SPEED_1000 ||
1438 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440 else
1441 mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443 if (phydev->duplex == DUPLEX_HALF)
1444 mac_mode |= MAC_MODE_HALF_DUPLEX;
1445 else {
1446 lcl_adv = tg3_advert_flowctrl_1000T(
1447 tp->link_config.flowctrl);
1448
1449 if (phydev->pause)
1450 rmt_adv = LPA_PAUSE_CAP;
1451 if (phydev->asym_pause)
1452 rmt_adv |= LPA_PAUSE_ASYM;
1453 }
1454
1455 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456 } else
1457 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459 if (mac_mode != tp->mac_mode) {
1460 tp->mac_mode = mac_mode;
1461 tw32_f(MAC_MODE, tp->mac_mode);
1462 udelay(40);
1463 }
1464
1465 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466 if (phydev->speed == SPEED_10)
1467 tw32(MAC_MI_STAT,
1468 MAC_MI_STAT_10MBPS_MODE |
1469 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470 else
1471 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472 }
1473
1474 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475 tw32(MAC_TX_LENGTHS,
1476 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477 (6 << TX_LENGTHS_IPG_SHIFT) |
1478 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479 else
1480 tw32(MAC_TX_LENGTHS,
1481 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482 (6 << TX_LENGTHS_IPG_SHIFT) |
1483 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487 phydev->speed != tp->link_config.active_speed ||
1488 phydev->duplex != tp->link_config.active_duplex ||
1489 oldflowctrl != tp->link_config.active_flowctrl)
1490 linkmesg = 1;
1491
1492 tp->link_config.active_speed = phydev->speed;
1493 tp->link_config.active_duplex = phydev->duplex;
1494
1495 spin_unlock_bh(&tp->lock);
1496
1497 if (linkmesg)
1498 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503 struct phy_device *phydev;
1504
1505 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506 return 0;
1507
1508 /* Bring the PHY back to a known state. */
1509 tg3_bmcr_reset(tp);
1510
1511 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513 /* Attach the MAC to the PHY. */
1514 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515 phydev->dev_flags, phydev->interface);
1516 if (IS_ERR(phydev)) {
1517 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518 return PTR_ERR(phydev);
1519 }
1520
1521 /* Mask with MAC supported features. */
1522 switch (phydev->interface) {
1523 case PHY_INTERFACE_MODE_GMII:
1524 case PHY_INTERFACE_MODE_RGMII:
1525 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526 phydev->supported &= (PHY_GBIT_FEATURES |
1527 SUPPORTED_Pause |
1528 SUPPORTED_Asym_Pause);
1529 break;
1530 }
1531 /* fallthru */
1532 case PHY_INTERFACE_MODE_MII:
1533 phydev->supported &= (PHY_BASIC_FEATURES |
1534 SUPPORTED_Pause |
1535 SUPPORTED_Asym_Pause);
1536 break;
1537 default:
1538 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539 return -EINVAL;
1540 }
1541
1542 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544 phydev->advertising = phydev->supported;
1545
1546 return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551 struct phy_device *phydev;
1552
1553 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554 return;
1555
1556 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560 phydev->speed = tp->link_config.orig_speed;
1561 phydev->duplex = tp->link_config.orig_duplex;
1562 phydev->autoneg = tp->link_config.orig_autoneg;
1563 phydev->advertising = tp->link_config.orig_advertising;
1564 }
1565
1566 phy_start(phydev);
1567
1568 phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574 return;
1575
1576 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584 }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589 int err;
1590
1591 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592 if (!err)
1593 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595 return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600 int err;
1601
1602 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603 if (!err)
1604 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606 return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611 u32 phytest;
1612
1613 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614 u32 phy;
1615
1616 tg3_writephy(tp, MII_TG3_FET_TEST,
1617 phytest | MII_TG3_FET_SHADOW_EN);
1618 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619 if (enable)
1620 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621 else
1622 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624 }
1625 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626 }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631 u32 reg;
1632
1633 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637 return;
1638
1639 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640 tg3_phy_fet_toggle_apd(tp, enable);
1641 return;
1642 }
1643
1644 reg = MII_TG3_MISC_SHDW_WREN |
1645 MII_TG3_MISC_SHDW_SCR5_SEL |
1646 MII_TG3_MISC_SHDW_SCR5_LPED |
1647 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648 MII_TG3_MISC_SHDW_SCR5_SDTL |
1649 MII_TG3_MISC_SHDW_SCR5_C125OE;
1650 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656 reg = MII_TG3_MISC_SHDW_WREN |
1657 MII_TG3_MISC_SHDW_APD_SEL |
1658 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659 if (enable)
1660 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667 u32 phy;
1668
1669 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671 return;
1672
1673 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674 u32 ephy;
1675
1676 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679 tg3_writephy(tp, MII_TG3_FET_TEST,
1680 ephy | MII_TG3_FET_SHADOW_EN);
1681 if (!tg3_readphy(tp, reg, &phy)) {
1682 if (enable)
1683 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684 else
1685 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686 tg3_writephy(tp, reg, phy);
1687 }
1688 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689 }
1690 } else {
1691 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692 MII_TG3_AUXCTL_SHDWSEL_MISC;
1693 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695 if (enable)
1696 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697 else
1698 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699 phy |= MII_TG3_AUXCTL_MISC_WREN;
1700 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701 }
1702 }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707 u32 val;
1708
1709 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710 return;
1711
1712 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715 (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720 u32 otp, phy;
1721
1722 if (!tp->phy_otp)
1723 return;
1724
1725 otp = tp->phy_otp;
1726
1727 /* Enable SM_DSP clock and tx 6dB coding. */
1728 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730 MII_TG3_AUXCTL_ACTL_TX_6DB;
1731 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755 /* Turn off SM_DSP clock. */
1756 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757 MII_TG3_AUXCTL_ACTL_TX_6DB;
1758 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763 u32 val;
1764
1765 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766 return;
1767
1768 tp->setlpicnt = 0;
1769
1770 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771 current_link_up == 1 &&
1772 (tp->link_config.active_speed == SPEED_1000 ||
1773 (tp->link_config.active_speed == SPEED_100 &&
1774 tp->link_config.active_duplex == DUPLEX_FULL))) {
1775 u32 eeectl;
1776
1777 if (tp->link_config.active_speed == SPEED_1000)
1778 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779 else
1780 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787 val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788 tp->setlpicnt = 2;
1789 }
1790
1791 if (!tp->setlpicnt) {
1792 val = tr32(TG3_CPMU_EEE_MODE);
1793 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794 }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799 int limit = 100;
1800
1801 while (limit--) {
1802 u32 tmp32;
1803
1804 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805 if ((tmp32 & 0x1000) == 0)
1806 break;
1807 }
1808 }
1809 if (limit < 0)
1810 return -EBUSY;
1811
1812 return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817 static const u32 test_pat[4][6] = {
1818 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822 };
1823 int chan;
1824
1825 for (chan = 0; chan < 4; chan++) {
1826 int i;
1827
1828 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829 (chan * 0x2000) | 0x0200);
1830 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832 for (i = 0; i < 6; i++)
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834 test_pat[chan][i]);
1835
1836 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837 if (tg3_wait_macro_done(tp)) {
1838 *resetp = 1;
1839 return -EBUSY;
1840 }
1841
1842 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843 (chan * 0x2000) | 0x0200);
1844 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845 if (tg3_wait_macro_done(tp)) {
1846 *resetp = 1;
1847 return -EBUSY;
1848 }
1849
1850 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851 if (tg3_wait_macro_done(tp)) {
1852 *resetp = 1;
1853 return -EBUSY;
1854 }
1855
1856 for (i = 0; i < 6; i += 2) {
1857 u32 low, high;
1858
1859 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861 tg3_wait_macro_done(tp)) {
1862 *resetp = 1;
1863 return -EBUSY;
1864 }
1865 low &= 0x7fff;
1866 high &= 0x000f;
1867 if (low != test_pat[chan][i] ||
1868 high != test_pat[chan][i+1]) {
1869 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873 return -EBUSY;
1874 }
1875 }
1876 }
1877
1878 return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883 int chan;
1884
1885 for (chan = 0; chan < 4; chan++) {
1886 int i;
1887
1888 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889 (chan * 0x2000) | 0x0200);
1890 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891 for (i = 0; i < 6; i++)
1892 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894 if (tg3_wait_macro_done(tp))
1895 return -EBUSY;
1896 }
1897
1898 return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903 u32 reg32, phy9_orig;
1904 int retries, do_phy_reset, err;
1905
1906 retries = 10;
1907 do_phy_reset = 1;
1908 do {
1909 if (do_phy_reset) {
1910 err = tg3_bmcr_reset(tp);
1911 if (err)
1912 return err;
1913 do_phy_reset = 0;
1914 }
1915
1916 /* Disable transmitter and interrupt. */
1917 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918 continue;
1919
1920 reg32 |= 0x3000;
1921 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923 /* Set full-duplex, 1000 mbps. */
1924 tg3_writephy(tp, MII_BMCR,
1925 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927 /* Set to master mode. */
1928 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929 continue;
1930
1931 tg3_writephy(tp, MII_TG3_CTRL,
1932 (MII_TG3_CTRL_AS_MASTER |
1933 MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935 /* Enable SM_DSP_CLOCK and 6dB. */
1936 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938 /* Block the PHY control access. */
1939 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942 if (!err)
1943 break;
1944 } while (--retries);
1945
1946 err = tg3_phy_reset_chanpat(tp);
1947 if (err)
1948 return err;
1949
1950 tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957 /* Set Extended packet length bit for jumbo frames */
1958 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959 } else {
1960 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961 }
1962
1963 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966 reg32 &= ~0x3000;
1967 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968 } else if (!err)
1969 err = -EBUSY;
1970
1971 return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975 * link unless the FORCE argument is non-zero.
1976 */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979 u32 val, cpmuctrl;
1980 int err;
1981
1982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983 val = tr32(GRC_MISC_CFG);
1984 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985 udelay(40);
1986 }
1987 err = tg3_readphy(tp, MII_BMSR, &val);
1988 err |= tg3_readphy(tp, MII_BMSR, &val);
1989 if (err != 0)
1990 return -EBUSY;
1991
1992 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993 netif_carrier_off(tp->dev);
1994 tg3_link_report(tp);
1995 }
1996
1997 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000 err = tg3_phy_reset_5703_4_5(tp);
2001 if (err)
2002 return err;
2003 goto out;
2004 }
2005
2006 cpmuctrl = 0;
2007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011 tw32(TG3_CPMU_CTRL,
2012 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013 }
2014
2015 err = tg3_bmcr_reset(tp);
2016 if (err)
2017 return err;
2018
2019 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024 }
2025
2026 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030 CPMU_LSPD_1000MB_MACCLK_12_5) {
2031 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032 udelay(40);
2033 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034 }
2035 }
2036
2037 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040 return 0;
2041
2042 tg3_phy_apply_otp(tp);
2043
2044 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045 tg3_phy_toggle_apd(tp, true);
2046 else
2047 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050 if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055 }
2056 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059 }
2060 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071 tg3_writephy(tp, MII_TG3_TEST1,
2072 MII_TG3_TEST1_TRIM_EN | 0x4);
2073 } else
2074 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076 }
2077 /* Set Extended packet length bit (bit 14) on all chips that */
2078 /* support jumbo frames */
2079 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080 /* Cannot do read-modify-write on 5401 */
2081 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083 /* Set bit 14 with read-modify-write to preserve other bits */
2084 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086 tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087 }
2088
2089 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090 * jumbo frames transmission.
2091 */
2092 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096 }
2097
2098 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099 /* adjust output voltage */
2100 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101 }
2102
2103 tg3_phy_toggle_automdix(tp, 1);
2104 tg3_phy_set_wirespeed(tp);
2105 return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110 struct tg3 *tp_peer = tp;
2111
2112 /* The GPIOs do something completely different on 57765. */
2113 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116 return;
2117
2118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121 struct net_device *dev_peer;
2122
2123 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124 /* remove_one() may have been run on the peer. */
2125 if (!dev_peer)
2126 tp_peer = tp;
2127 else
2128 tp_peer = netdev_priv(dev_peer);
2129 }
2130
2131 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138 (GRC_LCLCTRL_GPIO_OE0 |
2139 GRC_LCLCTRL_GPIO_OE1 |
2140 GRC_LCLCTRL_GPIO_OE2 |
2141 GRC_LCLCTRL_GPIO_OUTPUT0 |
2142 GRC_LCLCTRL_GPIO_OUTPUT1),
2143 100);
2144 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148 GRC_LCLCTRL_GPIO_OE1 |
2149 GRC_LCLCTRL_GPIO_OE2 |
2150 GRC_LCLCTRL_GPIO_OUTPUT0 |
2151 GRC_LCLCTRL_GPIO_OUTPUT1 |
2152 tp->grc_local_ctrl;
2153 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160 } else {
2161 u32 no_gpio2;
2162 u32 grc_local_ctrl = 0;
2163
2164 if (tp_peer != tp &&
2165 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166 return;
2167
2168 /* Workaround to prevent overdrawing Amps. */
2169 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170 ASIC_REV_5714) {
2171 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173 grc_local_ctrl, 100);
2174 }
2175
2176 /* On 5753 and variants, GPIO2 cannot be used. */
2177 no_gpio2 = tp->nic_sram_data_cfg &
2178 NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181 GRC_LCLCTRL_GPIO_OE1 |
2182 GRC_LCLCTRL_GPIO_OE2 |
2183 GRC_LCLCTRL_GPIO_OUTPUT1 |
2184 GRC_LCLCTRL_GPIO_OUTPUT2;
2185 if (no_gpio2) {
2186 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187 GRC_LCLCTRL_GPIO_OUTPUT2);
2188 }
2189 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190 grc_local_ctrl, 100);
2191
2192 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195 grc_local_ctrl, 100);
2196
2197 if (!no_gpio2) {
2198 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200 grc_local_ctrl, 100);
2201 }
2202 }
2203 } else {
2204 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206 if (tp_peer != tp &&
2207 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208 return;
2209
2210 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211 (GRC_LCLCTRL_GPIO_OE1 |
2212 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215 GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218 (GRC_LCLCTRL_GPIO_OE1 |
2219 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220 }
2221 }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227 return 1;
2228 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229 if (speed != SPEED_10)
2230 return 1;
2231 } else if (speed == SPEED_10)
2232 return 1;
2233
2234 return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN 0
2240 #define RESET_KIND_INIT 1
2241 #define RESET_KIND_SUSPEND 2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248 u32 val;
2249
2250 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255 sg_dig_ctrl |=
2256 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259 }
2260 return;
2261 }
2262
2263 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264 tg3_bmcr_reset(tp);
2265 val = tr32(GRC_MISC_CFG);
2266 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267 udelay(40);
2268 return;
2269 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270 u32 phytest;
2271 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272 u32 phy;
2273
2274 tg3_writephy(tp, MII_ADVERTISE, 0);
2275 tg3_writephy(tp, MII_BMCR,
2276 BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278 tg3_writephy(tp, MII_TG3_FET_TEST,
2279 phytest | MII_TG3_FET_SHADOW_EN);
2280 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282 tg3_writephy(tp,
2283 MII_TG3_FET_SHDW_AUXMODE4,
2284 phy);
2285 }
2286 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287 }
2288 return;
2289 } else if (do_low_power) {
2290 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297 MII_TG3_AUXCTL_PCTL_VREG_11V);
2298 }
2299
2300 /* The PHY should not be powered down on some chips because
2301 * of bugs.
2302 */
2303 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307 return;
2308
2309 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315 }
2316
2317 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324 int i;
2325
2326 if (tp->nvram_lock_cnt == 0) {
2327 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328 for (i = 0; i < 8000; i++) {
2329 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330 break;
2331 udelay(20);
2332 }
2333 if (i == 8000) {
2334 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335 return -ENODEV;
2336 }
2337 }
2338 tp->nvram_lock_cnt++;
2339 }
2340 return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347 if (tp->nvram_lock_cnt > 0)
2348 tp->nvram_lock_cnt--;
2349 if (tp->nvram_lock_cnt == 0)
2350 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351 }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362 }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373 }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377 u32 offset, u32 *val)
2378 {
2379 u32 tmp;
2380 int i;
2381
2382 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383 return -EINVAL;
2384
2385 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386 EEPROM_ADDR_DEVID_MASK |
2387 EEPROM_ADDR_READ);
2388 tw32(GRC_EEPROM_ADDR,
2389 tmp |
2390 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392 EEPROM_ADDR_ADDR_MASK) |
2393 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395 for (i = 0; i < 1000; i++) {
2396 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398 if (tmp & EEPROM_ADDR_COMPLETE)
2399 break;
2400 msleep(1);
2401 }
2402 if (!(tmp & EEPROM_ADDR_COMPLETE))
2403 return -EBUSY;
2404
2405 tmp = tr32(GRC_EEPROM_DATA);
2406
2407 /*
2408 * The data will always be opposite the native endian
2409 * format. Perform a blind byteswap to compensate.
2410 */
2411 *val = swab32(tmp);
2412
2413 return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420 int i;
2421
2422 tw32(NVRAM_CMD, nvram_cmd);
2423 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424 udelay(10);
2425 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426 udelay(10);
2427 break;
2428 }
2429 }
2430
2431 if (i == NVRAM_CMD_TIMEOUT)
2432 return -EBUSY;
2433
2434 return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443 (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445 addr = ((addr / tp->nvram_pagesize) <<
2446 ATMEL_AT45DB0X1B_PAGE_POS) +
2447 (addr % tp->nvram_pagesize);
2448
2449 return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458 (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461 tp->nvram_pagesize) +
2462 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464 return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468 * the byteswapping settings for all other register accesses.
2469 * tg3 devices are BE devices, so on a BE machine, the data
2470 * returned will be exactly as it is seen in NVRAM. On a LE
2471 * machine, the 32-bit value will be byteswapped.
2472 */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475 int ret;
2476
2477 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480 offset = tg3_nvram_phys_addr(tp, offset);
2481
2482 if (offset > NVRAM_ADDR_MSK)
2483 return -EINVAL;
2484
2485 ret = tg3_nvram_lock(tp);
2486 if (ret)
2487 return ret;
2488
2489 tg3_enable_nvram_access(tp);
2490
2491 tw32(NVRAM_ADDR, offset);
2492 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495 if (ret == 0)
2496 *val = tr32(NVRAM_RDDATA);
2497
2498 tg3_disable_nvram_access(tp);
2499
2500 tg3_nvram_unlock(tp);
2501
2502 return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508 u32 v;
2509 int res = tg3_nvram_read(tp, offset, &v);
2510 if (!res)
2511 *val = cpu_to_be32(v);
2512 return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518 u32 addr_high, addr_low;
2519 int i;
2520
2521 addr_high = ((tp->dev->dev_addr[0] << 8) |
2522 tp->dev->dev_addr[1]);
2523 addr_low = ((tp->dev->dev_addr[2] << 24) |
2524 (tp->dev->dev_addr[3] << 16) |
2525 (tp->dev->dev_addr[4] << 8) |
2526 (tp->dev->dev_addr[5] << 0));
2527 for (i = 0; i < 4; i++) {
2528 if (i == 1 && skip_mac_1)
2529 continue;
2530 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532 }
2533
2534 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536 for (i = 0; i < 12; i++) {
2537 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539 }
2540 }
2541
2542 addr_high = (tp->dev->dev_addr[0] +
2543 tp->dev->dev_addr[1] +
2544 tp->dev->dev_addr[2] +
2545 tp->dev->dev_addr[3] +
2546 tp->dev->dev_addr[4] +
2547 tp->dev->dev_addr[5]) &
2548 TX_BACKOFF_SEED_MASK;
2549 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554 u32 misc_host_ctrl;
2555 bool device_should_wake, do_low_power;
2556
2557 /* Make sure register accesses (indirect or otherwise)
2558 * will function correctly.
2559 */
2560 pci_write_config_dword(tp->pdev,
2561 TG3PCI_MISC_HOST_CTRL,
2562 tp->misc_host_ctrl);
2563
2564 switch (state) {
2565 case PCI_D0:
2566 pci_enable_wake(tp->pdev, state, false);
2567 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569 /* Switch out of Vaux if it is a NIC */
2570 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573 return 0;
2574
2575 case PCI_D1:
2576 case PCI_D2:
2577 case PCI_D3hot:
2578 break;
2579
2580 default:
2581 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582 state);
2583 return -EINVAL;
2584 }
2585
2586 /* Restore the CLKREQ setting. */
2587 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588 u16 lnkctl;
2589
2590 pci_read_config_word(tp->pdev,
2591 tp->pcie_cap + PCI_EXP_LNKCTL,
2592 &lnkctl);
2593 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594 pci_write_config_word(tp->pdev,
2595 tp->pcie_cap + PCI_EXP_LNKCTL,
2596 lnkctl);
2597 }
2598
2599 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600 tw32(TG3PCI_MISC_HOST_CTRL,
2601 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604 device_may_wakeup(&tp->pdev->dev) &&
2605 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608 do_low_power = false;
2609 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611 struct phy_device *phydev;
2612 u32 phyid, advertising;
2613
2614 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618 tp->link_config.orig_speed = phydev->speed;
2619 tp->link_config.orig_duplex = phydev->duplex;
2620 tp->link_config.orig_autoneg = phydev->autoneg;
2621 tp->link_config.orig_advertising = phydev->advertising;
2622
2623 advertising = ADVERTISED_TP |
2624 ADVERTISED_Pause |
2625 ADVERTISED_Autoneg |
2626 ADVERTISED_10baseT_Half;
2627
2628 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629 device_should_wake) {
2630 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631 advertising |=
2632 ADVERTISED_100baseT_Half |
2633 ADVERTISED_100baseT_Full |
2634 ADVERTISED_10baseT_Full;
2635 else
2636 advertising |= ADVERTISED_10baseT_Full;
2637 }
2638
2639 phydev->advertising = advertising;
2640
2641 phy_start_aneg(phydev);
2642
2643 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644 if (phyid != PHY_ID_BCMAC131) {
2645 phyid &= PHY_BCM_OUI_MASK;
2646 if (phyid == PHY_BCM_OUI_1 ||
2647 phyid == PHY_BCM_OUI_2 ||
2648 phyid == PHY_BCM_OUI_3)
2649 do_low_power = true;
2650 }
2651 }
2652 } else {
2653 do_low_power = true;
2654
2655 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657 tp->link_config.orig_speed = tp->link_config.speed;
2658 tp->link_config.orig_duplex = tp->link_config.duplex;
2659 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660 }
2661
2662 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663 tp->link_config.speed = SPEED_10;
2664 tp->link_config.duplex = DUPLEX_HALF;
2665 tp->link_config.autoneg = AUTONEG_ENABLE;
2666 tg3_setup_phy(tp, 0);
2667 }
2668 }
2669
2670 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671 u32 val;
2672
2673 val = tr32(GRC_VCPU_EXT_CTRL);
2674 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676 int i;
2677 u32 val;
2678
2679 for (i = 0; i < 200; i++) {
2680 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682 break;
2683 msleep(1);
2684 }
2685 }
2686 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688 WOL_DRV_STATE_SHUTDOWN |
2689 WOL_DRV_WOL |
2690 WOL_SET_MAGIC_PKT);
2691
2692 if (device_should_wake) {
2693 u32 mac_mode;
2694
2695 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696 if (do_low_power) {
2697 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698 udelay(40);
2699 }
2700
2701 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703 else
2704 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708 ASIC_REV_5700) {
2709 u32 speed = (tp->tg3_flags &
2710 TG3_FLAG_WOL_SPEED_100MB) ?
2711 SPEED_100 : SPEED_10;
2712 if (tg3_5700_link_polarity(tp, speed))
2713 mac_mode |= MAC_MODE_LINK_POLARITY;
2714 else
2715 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716 }
2717 } else {
2718 mac_mode = MAC_MODE_PORT_MODE_TBI;
2719 }
2720
2721 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722 tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2732 mac_mode |= tp->mac_mode &
2733 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2734 if (mac_mode & MAC_MODE_APE_TX_EN)
2735 mac_mode |= MAC_MODE_TDE_ENABLE;
2736 }
2737
2738 tw32_f(MAC_MODE, mac_mode);
2739 udelay(100);
2740
2741 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2742 udelay(10);
2743 }
2744
2745 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2748 u32 base_val;
2749
2750 base_val = tp->pci_clock_ctrl;
2751 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752 CLOCK_CTRL_TXCLK_DISABLE);
2753
2754 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2759 /* do nothing */
2760 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762 u32 newbits1, newbits2;
2763
2764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767 CLOCK_CTRL_TXCLK_DISABLE |
2768 CLOCK_CTRL_ALTCLK);
2769 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771 newbits1 = CLOCK_CTRL_625_CORE;
2772 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2773 } else {
2774 newbits1 = CLOCK_CTRL_ALTCLK;
2775 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776 }
2777
2778 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2779 40);
2780
2781 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2782 40);
2783
2784 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2785 u32 newbits3;
2786
2787 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790 CLOCK_CTRL_TXCLK_DISABLE |
2791 CLOCK_CTRL_44MHZ_CORE);
2792 } else {
2793 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2794 }
2795
2796 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797 tp->pci_clock_ctrl | newbits3, 40);
2798 }
2799 }
2800
2801 if (!(device_should_wake) &&
2802 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803 tg3_power_down_phy(tp, do_low_power);
2804
2805 tg3_frob_aux_power(tp);
2806
2807 /* Workaround for unstable PLL clock */
2808 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810 u32 val = tr32(0x7d00);
2811
2812 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2813 tw32(0x7d00, val);
2814 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2815 int err;
2816
2817 err = tg3_nvram_lock(tp);
2818 tg3_halt_cpu(tp, RX_CPU_BASE);
2819 if (!err)
2820 tg3_nvram_unlock(tp);
2821 }
2822 }
2823
2824 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2825
2826 if (device_should_wake)
2827 pci_enable_wake(tp->pdev, state, true);
2828
2829 /* Finally, set the new power state. */
2830 pci_set_power_state(tp->pdev, state);
2831
2832 return 0;
2833 }
2834
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2836 {
2837 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838 case MII_TG3_AUX_STAT_10HALF:
2839 *speed = SPEED_10;
2840 *duplex = DUPLEX_HALF;
2841 break;
2842
2843 case MII_TG3_AUX_STAT_10FULL:
2844 *speed = SPEED_10;
2845 *duplex = DUPLEX_FULL;
2846 break;
2847
2848 case MII_TG3_AUX_STAT_100HALF:
2849 *speed = SPEED_100;
2850 *duplex = DUPLEX_HALF;
2851 break;
2852
2853 case MII_TG3_AUX_STAT_100FULL:
2854 *speed = SPEED_100;
2855 *duplex = DUPLEX_FULL;
2856 break;
2857
2858 case MII_TG3_AUX_STAT_1000HALF:
2859 *speed = SPEED_1000;
2860 *duplex = DUPLEX_HALF;
2861 break;
2862
2863 case MII_TG3_AUX_STAT_1000FULL:
2864 *speed = SPEED_1000;
2865 *duplex = DUPLEX_FULL;
2866 break;
2867
2868 default:
2869 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2871 SPEED_10;
2872 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2873 DUPLEX_HALF;
2874 break;
2875 }
2876 *speed = SPEED_INVALID;
2877 *duplex = DUPLEX_INVALID;
2878 break;
2879 }
2880 }
2881
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2883 {
2884 u32 new_adv;
2885 int i;
2886
2887 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888 /* Entering low power mode. Disable gigabit and
2889 * 100baseT advertisements.
2890 */
2891 tg3_writephy(tp, MII_TG3_CTRL, 0);
2892
2893 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2897
2898 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899 } else if (tp->link_config.speed == SPEED_INVALID) {
2900 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901 tp->link_config.advertising &=
2902 ~(ADVERTISED_1000baseT_Half |
2903 ADVERTISED_1000baseT_Full);
2904
2905 new_adv = ADVERTISE_CSMA;
2906 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907 new_adv |= ADVERTISE_10HALF;
2908 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909 new_adv |= ADVERTISE_10FULL;
2910 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911 new_adv |= ADVERTISE_100HALF;
2912 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913 new_adv |= ADVERTISE_100FULL;
2914
2915 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2916
2917 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919 if (tp->link_config.advertising &
2920 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2921 new_adv = 0;
2922 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930 MII_TG3_CTRL_ENABLE_AS_MASTER);
2931 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2932 } else {
2933 tg3_writephy(tp, MII_TG3_CTRL, 0);
2934 }
2935 } else {
2936 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937 new_adv |= ADVERTISE_CSMA;
2938
2939 /* Asking for a specific link mode. */
2940 if (tp->link_config.speed == SPEED_1000) {
2941 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2942
2943 if (tp->link_config.duplex == DUPLEX_FULL)
2944 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2945 else
2946 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950 MII_TG3_CTRL_ENABLE_AS_MASTER);
2951 } else {
2952 if (tp->link_config.speed == SPEED_100) {
2953 if (tp->link_config.duplex == DUPLEX_FULL)
2954 new_adv |= ADVERTISE_100FULL;
2955 else
2956 new_adv |= ADVERTISE_100HALF;
2957 } else {
2958 if (tp->link_config.duplex == DUPLEX_FULL)
2959 new_adv |= ADVERTISE_10FULL;
2960 else
2961 new_adv |= ADVERTISE_10HALF;
2962 }
2963 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2964
2965 new_adv = 0;
2966 }
2967
2968 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969 }
2970
2971 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2972 u32 val = 0;
2973
2974 tw32(TG3_CPMU_EEE_MODE,
2975 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2976
2977 /* Enable SM_DSP clock and tx 6dB coding. */
2978 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980 MII_TG3_AUXCTL_ACTL_TX_6DB;
2981 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2982
2983 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985 !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987 val | MII_TG3_DSP_CH34TP2_HIBW01);
2988
2989 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2990 /* Advertise 100-BaseTX EEE ability */
2991 if (tp->link_config.advertising &
2992 (ADVERTISED_100baseT_Half |
2993 ADVERTISED_100baseT_Full))
2994 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2995 /* Advertise 1000-BaseT EEE ability */
2996 if (tp->link_config.advertising &
2997 (ADVERTISED_1000baseT_Half |
2998 ADVERTISED_1000baseT_Full))
2999 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
3000 }
3001 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3002
3003 /* Turn off SM_DSP clock. */
3004 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3005 MII_TG3_AUXCTL_ACTL_TX_6DB;
3006 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3007 }
3008
3009 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3010 tp->link_config.speed != SPEED_INVALID) {
3011 u32 bmcr, orig_bmcr;
3012
3013 tp->link_config.active_speed = tp->link_config.speed;
3014 tp->link_config.active_duplex = tp->link_config.duplex;
3015
3016 bmcr = 0;
3017 switch (tp->link_config.speed) {
3018 default:
3019 case SPEED_10:
3020 break;
3021
3022 case SPEED_100:
3023 bmcr |= BMCR_SPEED100;
3024 break;
3025
3026 case SPEED_1000:
3027 bmcr |= TG3_BMCR_SPEED1000;
3028 break;
3029 }
3030
3031 if (tp->link_config.duplex == DUPLEX_FULL)
3032 bmcr |= BMCR_FULLDPLX;
3033
3034 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3035 (bmcr != orig_bmcr)) {
3036 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3037 for (i = 0; i < 1500; i++) {
3038 u32 tmp;
3039
3040 udelay(10);
3041 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3042 tg3_readphy(tp, MII_BMSR, &tmp))
3043 continue;
3044 if (!(tmp & BMSR_LSTATUS)) {
3045 udelay(40);
3046 break;
3047 }
3048 }
3049 tg3_writephy(tp, MII_BMCR, bmcr);
3050 udelay(40);
3051 }
3052 } else {
3053 tg3_writephy(tp, MII_BMCR,
3054 BMCR_ANENABLE | BMCR_ANRESTART);
3055 }
3056 }
3057
3058 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3059 {
3060 int err;
3061
3062 /* Turn off tap power management. */
3063 /* Set Extended packet length bit */
3064 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3065
3066 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3067 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3068 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3069 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3070 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3071
3072 udelay(40);
3073
3074 return err;
3075 }
3076
3077 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3078 {
3079 u32 adv_reg, all_mask = 0;
3080
3081 if (mask & ADVERTISED_10baseT_Half)
3082 all_mask |= ADVERTISE_10HALF;
3083 if (mask & ADVERTISED_10baseT_Full)
3084 all_mask |= ADVERTISE_10FULL;
3085 if (mask & ADVERTISED_100baseT_Half)
3086 all_mask |= ADVERTISE_100HALF;
3087 if (mask & ADVERTISED_100baseT_Full)
3088 all_mask |= ADVERTISE_100FULL;
3089
3090 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3091 return 0;
3092
3093 if ((adv_reg & all_mask) != all_mask)
3094 return 0;
3095 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3096 u32 tg3_ctrl;
3097
3098 all_mask = 0;
3099 if (mask & ADVERTISED_1000baseT_Half)
3100 all_mask |= ADVERTISE_1000HALF;
3101 if (mask & ADVERTISED_1000baseT_Full)
3102 all_mask |= ADVERTISE_1000FULL;
3103
3104 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3105 return 0;
3106
3107 if ((tg3_ctrl & all_mask) != all_mask)
3108 return 0;
3109 }
3110 return 1;
3111 }
3112
3113 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3114 {
3115 u32 curadv, reqadv;
3116
3117 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3118 return 1;
3119
3120 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3121 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3122
3123 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3124 if (curadv != reqadv)
3125 return 0;
3126
3127 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3128 tg3_readphy(tp, MII_LPA, rmtadv);
3129 } else {
3130 /* Reprogram the advertisement register, even if it
3131 * does not affect the current link. If the link
3132 * gets renegotiated in the future, we can save an
3133 * additional renegotiation cycle by advertising
3134 * it correctly in the first place.
3135 */
3136 if (curadv != reqadv) {
3137 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3138 ADVERTISE_PAUSE_ASYM);
3139 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3140 }
3141 }
3142
3143 return 1;
3144 }
3145
3146 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3147 {
3148 int current_link_up;
3149 u32 bmsr, val;
3150 u32 lcl_adv, rmt_adv;
3151 u16 current_speed;
3152 u8 current_duplex;
3153 int i, err;
3154
3155 tw32(MAC_EVENT, 0);
3156
3157 tw32_f(MAC_STATUS,
3158 (MAC_STATUS_SYNC_CHANGED |
3159 MAC_STATUS_CFG_CHANGED |
3160 MAC_STATUS_MI_COMPLETION |
3161 MAC_STATUS_LNKSTATE_CHANGED));
3162 udelay(40);
3163
3164 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3165 tw32_f(MAC_MI_MODE,
3166 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3167 udelay(80);
3168 }
3169
3170 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3171
3172 /* Some third-party PHYs need to be reset on link going
3173 * down.
3174 */
3175 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3176 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3177 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3178 netif_carrier_ok(tp->dev)) {
3179 tg3_readphy(tp, MII_BMSR, &bmsr);
3180 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3181 !(bmsr & BMSR_LSTATUS))
3182 force_reset = 1;
3183 }
3184 if (force_reset)
3185 tg3_phy_reset(tp);
3186
3187 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3188 tg3_readphy(tp, MII_BMSR, &bmsr);
3189 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3190 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3191 bmsr = 0;
3192
3193 if (!(bmsr & BMSR_LSTATUS)) {
3194 err = tg3_init_5401phy_dsp(tp);
3195 if (err)
3196 return err;
3197
3198 tg3_readphy(tp, MII_BMSR, &bmsr);
3199 for (i = 0; i < 1000; i++) {
3200 udelay(10);
3201 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3202 (bmsr & BMSR_LSTATUS)) {
3203 udelay(40);
3204 break;
3205 }
3206 }
3207
3208 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3209 TG3_PHY_REV_BCM5401_B0 &&
3210 !(bmsr & BMSR_LSTATUS) &&
3211 tp->link_config.active_speed == SPEED_1000) {
3212 err = tg3_phy_reset(tp);
3213 if (!err)
3214 err = tg3_init_5401phy_dsp(tp);
3215 if (err)
3216 return err;
3217 }
3218 }
3219 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3220 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3221 /* 5701 {A0,B0} CRC bug workaround */
3222 tg3_writephy(tp, 0x15, 0x0a75);
3223 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3225 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3226 }
3227
3228 /* Clear pending interrupts... */
3229 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3230 tg3_readphy(tp, MII_TG3_ISTAT, &val);
3231
3232 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3233 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3234 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3235 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3236
3237 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3238 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3239 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3240 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3241 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3242 else
3243 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3244 }
3245
3246 current_link_up = 0;
3247 current_speed = SPEED_INVALID;
3248 current_duplex = DUPLEX_INVALID;
3249
3250 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3251 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3252 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3253 if (!(val & (1 << 10))) {
3254 val |= (1 << 10);
3255 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3256 goto relink;
3257 }
3258 }
3259
3260 bmsr = 0;
3261 for (i = 0; i < 100; i++) {
3262 tg3_readphy(tp, MII_BMSR, &bmsr);
3263 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3264 (bmsr & BMSR_LSTATUS))
3265 break;
3266 udelay(40);
3267 }
3268
3269 if (bmsr & BMSR_LSTATUS) {
3270 u32 aux_stat, bmcr;
3271
3272 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3273 for (i = 0; i < 2000; i++) {
3274 udelay(10);
3275 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3276 aux_stat)
3277 break;
3278 }
3279
3280 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3281 &current_speed,
3282 &current_duplex);
3283
3284 bmcr = 0;
3285 for (i = 0; i < 200; i++) {
3286 tg3_readphy(tp, MII_BMCR, &bmcr);
3287 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3288 continue;
3289 if (bmcr && bmcr != 0x7fff)
3290 break;
3291 udelay(10);
3292 }
3293
3294 lcl_adv = 0;
3295 rmt_adv = 0;
3296
3297 tp->link_config.active_speed = current_speed;
3298 tp->link_config.active_duplex = current_duplex;
3299
3300 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3301 if ((bmcr & BMCR_ANENABLE) &&
3302 tg3_copper_is_advertising_all(tp,
3303 tp->link_config.advertising)) {
3304 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3305 &rmt_adv))
3306 current_link_up = 1;
3307 }
3308 } else {
3309 if (!(bmcr & BMCR_ANENABLE) &&
3310 tp->link_config.speed == current_speed &&
3311 tp->link_config.duplex == current_duplex &&
3312 tp->link_config.flowctrl ==
3313 tp->link_config.active_flowctrl) {
3314 current_link_up = 1;
3315 }
3316 }
3317
3318 if (current_link_up == 1 &&
3319 tp->link_config.active_duplex == DUPLEX_FULL)
3320 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3321 }
3322
3323 relink:
3324 if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3325 tg3_phy_copper_begin(tp);
3326
3327 tg3_readphy(tp, MII_BMSR, &bmsr);
3328 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3329 (bmsr & BMSR_LSTATUS))
3330 current_link_up = 1;
3331 }
3332
3333 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3334 if (current_link_up == 1) {
3335 if (tp->link_config.active_speed == SPEED_100 ||
3336 tp->link_config.active_speed == SPEED_10)
3337 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3338 else
3339 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3340 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3341 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3342 else
3343 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3344
3345 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3346 if (tp->link_config.active_duplex == DUPLEX_HALF)
3347 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3348
3349 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3350 if (current_link_up == 1 &&
3351 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3352 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3353 else
3354 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3355 }
3356
3357 /* ??? Without this setting Netgear GA302T PHY does not
3358 * ??? send/receive packets...
3359 */
3360 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3361 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3362 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3363 tw32_f(MAC_MI_MODE, tp->mi_mode);
3364 udelay(80);
3365 }
3366
3367 tw32_f(MAC_MODE, tp->mac_mode);
3368 udelay(40);
3369
3370 tg3_phy_eee_adjust(tp, current_link_up);
3371
3372 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3373 /* Polled via timer. */
3374 tw32_f(MAC_EVENT, 0);
3375 } else {
3376 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3377 }
3378 udelay(40);
3379
3380 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3381 current_link_up == 1 &&
3382 tp->link_config.active_speed == SPEED_1000 &&
3383 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3384 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3385 udelay(120);
3386 tw32_f(MAC_STATUS,
3387 (MAC_STATUS_SYNC_CHANGED |
3388 MAC_STATUS_CFG_CHANGED));
3389 udelay(40);
3390 tg3_write_mem(tp,
3391 NIC_SRAM_FIRMWARE_MBOX,
3392 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3393 }
3394
3395 /* Prevent send BD corruption. */
3396 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3397 u16 oldlnkctl, newlnkctl;
3398
3399 pci_read_config_word(tp->pdev,
3400 tp->pcie_cap + PCI_EXP_LNKCTL,
3401 &oldlnkctl);
3402 if (tp->link_config.active_speed == SPEED_100 ||
3403 tp->link_config.active_speed == SPEED_10)
3404 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3405 else
3406 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3407 if (newlnkctl != oldlnkctl)
3408 pci_write_config_word(tp->pdev,
3409 tp->pcie_cap + PCI_EXP_LNKCTL,
3410 newlnkctl);
3411 }
3412
3413 if (current_link_up != netif_carrier_ok(tp->dev)) {
3414 if (current_link_up)
3415 netif_carrier_on(tp->dev);
3416 else
3417 netif_carrier_off(tp->dev);
3418 tg3_link_report(tp);
3419 }
3420
3421 return 0;
3422 }
3423
3424 struct tg3_fiber_aneginfo {
3425 int state;
3426 #define ANEG_STATE_UNKNOWN 0
3427 #define ANEG_STATE_AN_ENABLE 1
3428 #define ANEG_STATE_RESTART_INIT 2
3429 #define ANEG_STATE_RESTART 3
3430 #define ANEG_STATE_DISABLE_LINK_OK 4
3431 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3432 #define ANEG_STATE_ABILITY_DETECT 6
3433 #define ANEG_STATE_ACK_DETECT_INIT 7
3434 #define ANEG_STATE_ACK_DETECT 8
3435 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3436 #define ANEG_STATE_COMPLETE_ACK 10
3437 #define ANEG_STATE_IDLE_DETECT_INIT 11
3438 #define ANEG_STATE_IDLE_DETECT 12
3439 #define ANEG_STATE_LINK_OK 13
3440 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3441 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3442
3443 u32 flags;
3444 #define MR_AN_ENABLE 0x00000001
3445 #define MR_RESTART_AN 0x00000002
3446 #define MR_AN_COMPLETE 0x00000004
3447 #define MR_PAGE_RX 0x00000008
3448 #define MR_NP_LOADED 0x00000010
3449 #define MR_TOGGLE_TX 0x00000020
3450 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3451 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3452 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3453 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3454 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3455 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3456 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3457 #define MR_TOGGLE_RX 0x00002000
3458 #define MR_NP_RX 0x00004000
3459
3460 #define MR_LINK_OK 0x80000000
3461
3462 unsigned long link_time, cur_time;
3463
3464 u32 ability_match_cfg;
3465 int ability_match_count;
3466
3467 char ability_match, idle_match, ack_match;
3468
3469 u32 txconfig, rxconfig;
3470 #define ANEG_CFG_NP 0x00000080
3471 #define ANEG_CFG_ACK 0x00000040
3472 #define ANEG_CFG_RF2 0x00000020
3473 #define ANEG_CFG_RF1 0x00000010
3474 #define ANEG_CFG_PS2 0x00000001
3475 #define ANEG_CFG_PS1 0x00008000
3476 #define ANEG_CFG_HD 0x00004000
3477 #define ANEG_CFG_FD 0x00002000
3478 #define ANEG_CFG_INVAL 0x00001f06
3479
3480 };
3481 #define ANEG_OK 0
3482 #define ANEG_DONE 1
3483 #define ANEG_TIMER_ENAB 2
3484 #define ANEG_FAILED -1
3485
3486 #define ANEG_STATE_SETTLE_TIME 10000
3487
3488 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3489 struct tg3_fiber_aneginfo *ap)
3490 {
3491 u16 flowctrl;
3492 unsigned long delta;
3493 u32 rx_cfg_reg;
3494 int ret;
3495
3496 if (ap->state == ANEG_STATE_UNKNOWN) {
3497 ap->rxconfig = 0;
3498 ap->link_time = 0;
3499 ap->cur_time = 0;
3500 ap->ability_match_cfg = 0;
3501 ap->ability_match_count = 0;
3502 ap->ability_match = 0;
3503 ap->idle_match = 0;
3504 ap->ack_match = 0;
3505 }
3506 ap->cur_time++;
3507
3508 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3509 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3510
3511 if (rx_cfg_reg != ap->ability_match_cfg) {
3512 ap->ability_match_cfg = rx_cfg_reg;
3513 ap->ability_match = 0;
3514 ap->ability_match_count = 0;
3515 } else {
3516 if (++ap->ability_match_count > 1) {
3517 ap->ability_match = 1;
3518 ap->ability_match_cfg = rx_cfg_reg;
3519 }
3520 }
3521 if (rx_cfg_reg & ANEG_CFG_ACK)
3522 ap->ack_match = 1;
3523 else
3524 ap->ack_match = 0;
3525
3526 ap->idle_match = 0;
3527 } else {
3528 ap->idle_match = 1;
3529 ap->ability_match_cfg = 0;
3530 ap->ability_match_count = 0;
3531 ap->ability_match = 0;
3532 ap->ack_match = 0;
3533
3534 rx_cfg_reg = 0;
3535 }
3536
3537 ap->rxconfig = rx_cfg_reg;
3538 ret = ANEG_OK;
3539
3540 switch (ap->state) {
3541 case ANEG_STATE_UNKNOWN:
3542 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3543 ap->state = ANEG_STATE_AN_ENABLE;
3544
3545 /* fallthru */
3546 case ANEG_STATE_AN_ENABLE:
3547 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3548 if (ap->flags & MR_AN_ENABLE) {
3549 ap->link_time = 0;
3550 ap->cur_time = 0;
3551 ap->ability_match_cfg = 0;
3552 ap->ability_match_count = 0;
3553 ap->ability_match = 0;
3554 ap->idle_match = 0;
3555 ap->ack_match = 0;
3556
3557 ap->state = ANEG_STATE_RESTART_INIT;
3558 } else {
3559 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3560 }
3561 break;
3562
3563 case ANEG_STATE_RESTART_INIT:
3564 ap->link_time = ap->cur_time;
3565 ap->flags &= ~(MR_NP_LOADED);
3566 ap->txconfig = 0;
3567 tw32(MAC_TX_AUTO_NEG, 0);
3568 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3569 tw32_f(MAC_MODE, tp->mac_mode);
3570 udelay(40);
3571
3572 ret = ANEG_TIMER_ENAB;
3573 ap->state = ANEG_STATE_RESTART;
3574
3575 /* fallthru */
3576 case ANEG_STATE_RESTART:
3577 delta = ap->cur_time - ap->link_time;
3578 if (delta > ANEG_STATE_SETTLE_TIME)
3579 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3580 else
3581 ret = ANEG_TIMER_ENAB;
3582 break;
3583
3584 case ANEG_STATE_DISABLE_LINK_OK:
3585 ret = ANEG_DONE;
3586 break;
3587
3588 case ANEG_STATE_ABILITY_DETECT_INIT:
3589 ap->flags &= ~(MR_TOGGLE_TX);
3590 ap->txconfig = ANEG_CFG_FD;
3591 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3592 if (flowctrl & ADVERTISE_1000XPAUSE)
3593 ap->txconfig |= ANEG_CFG_PS1;
3594 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3595 ap->txconfig |= ANEG_CFG_PS2;
3596 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3597 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3598 tw32_f(MAC_MODE, tp->mac_mode);
3599 udelay(40);
3600
3601 ap->state = ANEG_STATE_ABILITY_DETECT;
3602 break;
3603
3604 case ANEG_STATE_ABILITY_DETECT:
3605 if (ap->ability_match != 0 && ap->rxconfig != 0)
3606 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3607 break;
3608
3609 case ANEG_STATE_ACK_DETECT_INIT:
3610 ap->txconfig |= ANEG_CFG_ACK;
3611 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3612 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3613 tw32_f(MAC_MODE, tp->mac_mode);
3614 udelay(40);
3615
3616 ap->state = ANEG_STATE_ACK_DETECT;
3617
3618 /* fallthru */
3619 case ANEG_STATE_ACK_DETECT:
3620 if (ap->ack_match != 0) {
3621 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3622 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3623 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3624 } else {
3625 ap->state = ANEG_STATE_AN_ENABLE;
3626 }
3627 } else if (ap->ability_match != 0 &&
3628 ap->rxconfig == 0) {
3629 ap->state = ANEG_STATE_AN_ENABLE;
3630 }
3631 break;
3632
3633 case ANEG_STATE_COMPLETE_ACK_INIT:
3634 if (ap->rxconfig & ANEG_CFG_INVAL) {
3635 ret = ANEG_FAILED;
3636 break;
3637 }
3638 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3639 MR_LP_ADV_HALF_DUPLEX |
3640 MR_LP_ADV_SYM_PAUSE |
3641 MR_LP_ADV_ASYM_PAUSE |
3642 MR_LP_ADV_REMOTE_FAULT1 |
3643 MR_LP_ADV_REMOTE_FAULT2 |
3644 MR_LP_ADV_NEXT_PAGE |
3645 MR_TOGGLE_RX |
3646 MR_NP_RX);
3647 if (ap->rxconfig & ANEG_CFG_FD)
3648 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3649 if (ap->rxconfig & ANEG_CFG_HD)
3650 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3651 if (ap->rxconfig & ANEG_CFG_PS1)
3652 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3653 if (ap->rxconfig & ANEG_CFG_PS2)
3654 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3655 if (ap->rxconfig & ANEG_CFG_RF1)
3656 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3657 if (ap->rxconfig & ANEG_CFG_RF2)
3658 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3659 if (ap->rxconfig & ANEG_CFG_NP)
3660 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3661
3662 ap->link_time = ap->cur_time;
3663
3664 ap->flags ^= (MR_TOGGLE_TX);
3665 if (ap->rxconfig & 0x0008)
3666 ap->flags |= MR_TOGGLE_RX;
3667 if (ap->rxconfig & ANEG_CFG_NP)
3668 ap->flags |= MR_NP_RX;
3669 ap->flags |= MR_PAGE_RX;
3670
3671 ap->state = ANEG_STATE_COMPLETE_ACK;
3672 ret = ANEG_TIMER_ENAB;
3673 break;
3674
3675 case ANEG_STATE_COMPLETE_ACK:
3676 if (ap->ability_match != 0 &&
3677 ap->rxconfig == 0) {
3678 ap->state = ANEG_STATE_AN_ENABLE;
3679 break;
3680 }
3681 delta = ap->cur_time - ap->link_time;
3682 if (delta > ANEG_STATE_SETTLE_TIME) {
3683 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3684 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3685 } else {
3686 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3687 !(ap->flags & MR_NP_RX)) {
3688 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3689 } else {
3690 ret = ANEG_FAILED;
3691 }
3692 }
3693 }
3694 break;
3695
3696 case ANEG_STATE_IDLE_DETECT_INIT:
3697 ap->link_time = ap->cur_time;
3698 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3699 tw32_f(MAC_MODE, tp->mac_mode);
3700 udelay(40);
3701
3702 ap->state = ANEG_STATE_IDLE_DETECT;
3703 ret = ANEG_TIMER_ENAB;
3704 break;
3705
3706 case ANEG_STATE_IDLE_DETECT:
3707 if (ap->ability_match != 0 &&
3708 ap->rxconfig == 0) {
3709 ap->state = ANEG_STATE_AN_ENABLE;
3710 break;
3711 }
3712 delta = ap->cur_time - ap->link_time;
3713 if (delta > ANEG_STATE_SETTLE_TIME) {
3714 /* XXX another gem from the Broadcom driver :( */
3715 ap->state = ANEG_STATE_LINK_OK;
3716 }
3717 break;
3718
3719 case ANEG_STATE_LINK_OK:
3720 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3721 ret = ANEG_DONE;
3722 break;
3723
3724 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3725 /* ??? unimplemented */
3726 break;
3727
3728 case ANEG_STATE_NEXT_PAGE_WAIT:
3729 /* ??? unimplemented */
3730 break;
3731
3732 default:
3733 ret = ANEG_FAILED;
3734 break;
3735 }
3736
3737 return ret;
3738 }
3739
3740 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3741 {
3742 int res = 0;
3743 struct tg3_fiber_aneginfo aninfo;
3744 int status = ANEG_FAILED;
3745 unsigned int tick;
3746 u32 tmp;
3747
3748 tw32_f(MAC_TX_AUTO_NEG, 0);
3749
3750 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3751 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3752 udelay(40);
3753
3754 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3755 udelay(40);
3756
3757 memset(&aninfo, 0, sizeof(aninfo));
3758 aninfo.flags |= MR_AN_ENABLE;
3759 aninfo.state = ANEG_STATE_UNKNOWN;
3760 aninfo.cur_time = 0;
3761 tick = 0;
3762 while (++tick < 195000) {
3763 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3764 if (status == ANEG_DONE || status == ANEG_FAILED)
3765 break;
3766
3767 udelay(1);
3768 }
3769
3770 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3771 tw32_f(MAC_MODE, tp->mac_mode);
3772 udelay(40);
3773
3774 *txflags = aninfo.txconfig;
3775 *rxflags = aninfo.flags;
3776
3777 if (status == ANEG_DONE &&
3778 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3779 MR_LP_ADV_FULL_DUPLEX)))
3780 res = 1;
3781
3782 return res;
3783 }
3784
3785 static void tg3_init_bcm8002(struct tg3 *tp)
3786 {
3787 u32 mac_status = tr32(MAC_STATUS);
3788 int i;
3789
3790 /* Reset when initting first time or we have a link. */
3791 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3792 !(mac_status & MAC_STATUS_PCS_SYNCED))
3793 return;
3794
3795 /* Set PLL lock range. */
3796 tg3_writephy(tp, 0x16, 0x8007);
3797
3798 /* SW reset */
3799 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3800
3801 /* Wait for reset to complete. */
3802 /* XXX schedule_timeout() ... */
3803 for (i = 0; i < 500; i++)
3804 udelay(10);
3805
3806 /* Config mode; select PMA/Ch 1 regs. */
3807 tg3_writephy(tp, 0x10, 0x8411);
3808
3809 /* Enable auto-lock and comdet, select txclk for tx. */
3810 tg3_writephy(tp, 0x11, 0x0a10);
3811
3812 tg3_writephy(tp, 0x18, 0x00a0);
3813 tg3_writephy(tp, 0x16, 0x41ff);
3814
3815 /* Assert and deassert POR. */
3816 tg3_writephy(tp, 0x13, 0x0400);
3817 udelay(40);
3818 tg3_writephy(tp, 0x13, 0x0000);
3819
3820 tg3_writephy(tp, 0x11, 0x0a50);
3821 udelay(40);
3822 tg3_writephy(tp, 0x11, 0x0a10);
3823
3824 /* Wait for signal to stabilize */
3825 /* XXX schedule_timeout() ... */
3826 for (i = 0; i < 15000; i++)
3827 udelay(10);
3828
3829 /* Deselect the channel register so we can read the PHYID
3830 * later.
3831 */
3832 tg3_writephy(tp, 0x10, 0x8011);
3833 }
3834
3835 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3836 {
3837 u16 flowctrl;
3838 u32 sg_dig_ctrl, sg_dig_status;
3839 u32 serdes_cfg, expected_sg_dig_ctrl;
3840 int workaround, port_a;
3841 int current_link_up;
3842
3843 serdes_cfg = 0;
3844 expected_sg_dig_ctrl = 0;
3845 workaround = 0;
3846 port_a = 1;
3847 current_link_up = 0;
3848
3849 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3850 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3851 workaround = 1;
3852 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3853 port_a = 0;
3854
3855 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3856 /* preserve bits 20-23 for voltage regulator */
3857 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3858 }
3859
3860 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3861
3862 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3863 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3864 if (workaround) {
3865 u32 val = serdes_cfg;
3866
3867 if (port_a)
3868 val |= 0xc010000;
3869 else
3870 val |= 0x4010000;
3871 tw32_f(MAC_SERDES_CFG, val);
3872 }
3873
3874 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875 }
3876 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3877 tg3_setup_flow_control(tp, 0, 0);
3878 current_link_up = 1;
3879 }
3880 goto out;
3881 }
3882
3883 /* Want auto-negotiation. */
3884 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3885
3886 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3887 if (flowctrl & ADVERTISE_1000XPAUSE)
3888 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3889 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3890 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3891
3892 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3893 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3894 tp->serdes_counter &&
3895 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3896 MAC_STATUS_RCVD_CFG)) ==
3897 MAC_STATUS_PCS_SYNCED)) {
3898 tp->serdes_counter--;
3899 current_link_up = 1;
3900 goto out;
3901 }
3902 restart_autoneg:
3903 if (workaround)
3904 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3905 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3906 udelay(5);
3907 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3908
3909 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3910 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3911 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3912 MAC_STATUS_SIGNAL_DET)) {
3913 sg_dig_status = tr32(SG_DIG_STATUS);
3914 mac_status = tr32(MAC_STATUS);
3915
3916 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3917 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3918 u32 local_adv = 0, remote_adv = 0;
3919
3920 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3921 local_adv |= ADVERTISE_1000XPAUSE;
3922 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3923 local_adv |= ADVERTISE_1000XPSE_ASYM;
3924
3925 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3926 remote_adv |= LPA_1000XPAUSE;
3927 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3928 remote_adv |= LPA_1000XPAUSE_ASYM;
3929
3930 tg3_setup_flow_control(tp, local_adv, remote_adv);
3931 current_link_up = 1;
3932 tp->serdes_counter = 0;
3933 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3934 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3935 if (tp->serdes_counter)
3936 tp->serdes_counter--;
3937 else {
3938 if (workaround) {
3939 u32 val = serdes_cfg;
3940
3941 if (port_a)
3942 val |= 0xc010000;
3943 else
3944 val |= 0x4010000;
3945
3946 tw32_f(MAC_SERDES_CFG, val);
3947 }
3948
3949 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3950 udelay(40);
3951
3952 /* Link parallel detection - link is up */
3953 /* only if we have PCS_SYNC and not */
3954 /* receiving config code words */
3955 mac_status = tr32(MAC_STATUS);
3956 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3957 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3958 tg3_setup_flow_control(tp, 0, 0);
3959 current_link_up = 1;
3960 tp->phy_flags |=
3961 TG3_PHYFLG_PARALLEL_DETECT;
3962 tp->serdes_counter =
3963 SERDES_PARALLEL_DET_TIMEOUT;
3964 } else
3965 goto restart_autoneg;
3966 }
3967 }
3968 } else {
3969 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3970 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3971 }
3972
3973 out:
3974 return current_link_up;
3975 }
3976
3977 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3978 {
3979 int current_link_up = 0;
3980
3981 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3982 goto out;
3983
3984 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3985 u32 txflags, rxflags;
3986 int i;
3987
3988 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3989 u32 local_adv = 0, remote_adv = 0;
3990
3991 if (txflags & ANEG_CFG_PS1)
3992 local_adv |= ADVERTISE_1000XPAUSE;
3993 if (txflags & ANEG_CFG_PS2)
3994 local_adv |= ADVERTISE_1000XPSE_ASYM;
3995
3996 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3997 remote_adv |= LPA_1000XPAUSE;
3998 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3999 remote_adv |= LPA_1000XPAUSE_ASYM;
4000
4001 tg3_setup_flow_control(tp, local_adv, remote_adv);
4002
4003 current_link_up = 1;
4004 }
4005 for (i = 0; i < 30; i++) {
4006 udelay(20);
4007 tw32_f(MAC_STATUS,
4008 (MAC_STATUS_SYNC_CHANGED |
4009 MAC_STATUS_CFG_CHANGED));
4010 udelay(40);
4011 if ((tr32(MAC_STATUS) &
4012 (MAC_STATUS_SYNC_CHANGED |
4013 MAC_STATUS_CFG_CHANGED)) == 0)
4014 break;
4015 }
4016
4017 mac_status = tr32(MAC_STATUS);
4018 if (current_link_up == 0 &&
4019 (mac_status & MAC_STATUS_PCS_SYNCED) &&
4020 !(mac_status & MAC_STATUS_RCVD_CFG))
4021 current_link_up = 1;
4022 } else {
4023 tg3_setup_flow_control(tp, 0, 0);
4024
4025 /* Forcing 1000FD link up. */
4026 current_link_up = 1;
4027
4028 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4029 udelay(40);
4030
4031 tw32_f(MAC_MODE, tp->mac_mode);
4032 udelay(40);
4033 }
4034
4035 out:
4036 return current_link_up;
4037 }
4038
4039 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4040 {
4041 u32 orig_pause_cfg;
4042 u16 orig_active_speed;
4043 u8 orig_active_duplex;
4044 u32 mac_status;
4045 int current_link_up;
4046 int i;
4047
4048 orig_pause_cfg = tp->link_config.active_flowctrl;
4049 orig_active_speed = tp->link_config.active_speed;
4050 orig_active_duplex = tp->link_config.active_duplex;
4051
4052 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4053 netif_carrier_ok(tp->dev) &&
4054 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4055 mac_status = tr32(MAC_STATUS);
4056 mac_status &= (MAC_STATUS_PCS_SYNCED |
4057 MAC_STATUS_SIGNAL_DET |
4058 MAC_STATUS_CFG_CHANGED |
4059 MAC_STATUS_RCVD_CFG);
4060 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4061 MAC_STATUS_SIGNAL_DET)) {
4062 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4063 MAC_STATUS_CFG_CHANGED));
4064 return 0;
4065 }
4066 }
4067
4068 tw32_f(MAC_TX_AUTO_NEG, 0);
4069
4070 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4071 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4072 tw32_f(MAC_MODE, tp->mac_mode);
4073 udelay(40);
4074
4075 if (tp->phy_id == TG3_PHY_ID_BCM8002)
4076 tg3_init_bcm8002(tp);
4077
4078 /* Enable link change event even when serdes polling. */
4079 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4080 udelay(40);
4081
4082 current_link_up = 0;
4083 mac_status = tr32(MAC_STATUS);
4084
4085 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4086 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4087 else
4088 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4089
4090 tp->napi[0].hw_status->status =
4091 (SD_STATUS_UPDATED |
4092 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4093
4094 for (i = 0; i < 100; i++) {
4095 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4096 MAC_STATUS_CFG_CHANGED));
4097 udelay(5);
4098 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4099 MAC_STATUS_CFG_CHANGED |
4100 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4101 break;
4102 }
4103
4104 mac_status = tr32(MAC_STATUS);
4105 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4106 current_link_up = 0;
4107 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4108 tp->serdes_counter == 0) {
4109 tw32_f(MAC_MODE, (tp->mac_mode |
4110 MAC_MODE_SEND_CONFIGS));
4111 udelay(1);
4112 tw32_f(MAC_MODE, tp->mac_mode);
4113 }
4114 }
4115
4116 if (current_link_up == 1) {
4117 tp->link_config.active_speed = SPEED_1000;
4118 tp->link_config.active_duplex = DUPLEX_FULL;
4119 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4120 LED_CTRL_LNKLED_OVERRIDE |
4121 LED_CTRL_1000MBPS_ON));
4122 } else {
4123 tp->link_config.active_speed = SPEED_INVALID;
4124 tp->link_config.active_duplex = DUPLEX_INVALID;
4125 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4126 LED_CTRL_LNKLED_OVERRIDE |
4127 LED_CTRL_TRAFFIC_OVERRIDE));
4128 }
4129
4130 if (current_link_up != netif_carrier_ok(tp->dev)) {
4131 if (current_link_up)
4132 netif_carrier_on(tp->dev);
4133 else
4134 netif_carrier_off(tp->dev);
4135 tg3_link_report(tp);
4136 } else {
4137 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4138 if (orig_pause_cfg != now_pause_cfg ||
4139 orig_active_speed != tp->link_config.active_speed ||
4140 orig_active_duplex != tp->link_config.active_duplex)
4141 tg3_link_report(tp);
4142 }
4143
4144 return 0;
4145 }
4146
4147 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4148 {
4149 int current_link_up, err = 0;
4150 u32 bmsr, bmcr;
4151 u16 current_speed;
4152 u8 current_duplex;
4153 u32 local_adv, remote_adv;
4154
4155 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4156 tw32_f(MAC_MODE, tp->mac_mode);
4157 udelay(40);
4158
4159 tw32(MAC_EVENT, 0);
4160
4161 tw32_f(MAC_STATUS,
4162 (MAC_STATUS_SYNC_CHANGED |
4163 MAC_STATUS_CFG_CHANGED |
4164 MAC_STATUS_MI_COMPLETION |
4165 MAC_STATUS_LNKSTATE_CHANGED));
4166 udelay(40);
4167
4168 if (force_reset)
4169 tg3_phy_reset(tp);
4170
4171 current_link_up = 0;
4172 current_speed = SPEED_INVALID;
4173 current_duplex = DUPLEX_INVALID;
4174
4175 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4177 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4178 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4179 bmsr |= BMSR_LSTATUS;
4180 else
4181 bmsr &= ~BMSR_LSTATUS;
4182 }
4183
4184 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4185
4186 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4187 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4188 /* do nothing, just check for link up at the end */
4189 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4190 u32 adv, new_adv;
4191
4192 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4193 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4194 ADVERTISE_1000XPAUSE |
4195 ADVERTISE_1000XPSE_ASYM |
4196 ADVERTISE_SLCT);
4197
4198 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4199
4200 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4201 new_adv |= ADVERTISE_1000XHALF;
4202 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4203 new_adv |= ADVERTISE_1000XFULL;
4204
4205 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4206 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4207 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4208 tg3_writephy(tp, MII_BMCR, bmcr);
4209
4210 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4211 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4212 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4213
4214 return err;
4215 }
4216 } else {
4217 u32 new_bmcr;
4218
4219 bmcr &= ~BMCR_SPEED1000;
4220 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4221
4222 if (tp->link_config.duplex == DUPLEX_FULL)
4223 new_bmcr |= BMCR_FULLDPLX;
4224
4225 if (new_bmcr != bmcr) {
4226 /* BMCR_SPEED1000 is a reserved bit that needs
4227 * to be set on write.
4228 */
4229 new_bmcr |= BMCR_SPEED1000;
4230
4231 /* Force a linkdown */
4232 if (netif_carrier_ok(tp->dev)) {
4233 u32 adv;
4234
4235 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4236 adv &= ~(ADVERTISE_1000XFULL |
4237 ADVERTISE_1000XHALF |
4238 ADVERTISE_SLCT);
4239 tg3_writephy(tp, MII_ADVERTISE, adv);
4240 tg3_writephy(tp, MII_BMCR, bmcr |
4241 BMCR_ANRESTART |
4242 BMCR_ANENABLE);
4243 udelay(10);
4244 netif_carrier_off(tp->dev);
4245 }
4246 tg3_writephy(tp, MII_BMCR, new_bmcr);
4247 bmcr = new_bmcr;
4248 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4249 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4250 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4251 ASIC_REV_5714) {
4252 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4253 bmsr |= BMSR_LSTATUS;
4254 else
4255 bmsr &= ~BMSR_LSTATUS;
4256 }
4257 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4258 }
4259 }
4260
4261 if (bmsr & BMSR_LSTATUS) {
4262 current_speed = SPEED_1000;
4263 current_link_up = 1;
4264 if (bmcr & BMCR_FULLDPLX)
4265 current_duplex = DUPLEX_FULL;
4266 else
4267 current_duplex = DUPLEX_HALF;
4268
4269 local_adv = 0;
4270 remote_adv = 0;
4271
4272 if (bmcr & BMCR_ANENABLE) {
4273 u32 common;
4274
4275 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4276 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4277 common = local_adv & remote_adv;
4278 if (common & (ADVERTISE_1000XHALF |
4279 ADVERTISE_1000XFULL)) {
4280 if (common & ADVERTISE_1000XFULL)
4281 current_duplex = DUPLEX_FULL;
4282 else
4283 current_duplex = DUPLEX_HALF;
4284 } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4285 /* Link is up via parallel detect */
4286 } else {
4287 current_link_up = 0;
4288 }
4289 }
4290 }
4291
4292 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4293 tg3_setup_flow_control(tp, local_adv, remote_adv);
4294
4295 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4296 if (tp->link_config.active_duplex == DUPLEX_HALF)
4297 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4298
4299 tw32_f(MAC_MODE, tp->mac_mode);
4300 udelay(40);
4301
4302 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4303
4304 tp->link_config.active_speed = current_speed;
4305 tp->link_config.active_duplex = current_duplex;
4306
4307 if (current_link_up != netif_carrier_ok(tp->dev)) {
4308 if (current_link_up)
4309 netif_carrier_on(tp->dev);
4310 else {
4311 netif_carrier_off(tp->dev);
4312 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4313 }
4314 tg3_link_report(tp);
4315 }
4316 return err;
4317 }
4318
4319 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4320 {
4321 if (tp->serdes_counter) {
4322 /* Give autoneg time to complete. */
4323 tp->serdes_counter--;
4324 return;
4325 }
4326
4327 if (!netif_carrier_ok(tp->dev) &&
4328 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4329 u32 bmcr;
4330
4331 tg3_readphy(tp, MII_BMCR, &bmcr);
4332 if (bmcr & BMCR_ANENABLE) {
4333 u32 phy1, phy2;
4334
4335 /* Select shadow register 0x1f */
4336 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4337 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4338
4339 /* Select expansion interrupt status register */
4340 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4341 MII_TG3_DSP_EXP1_INT_STAT);
4342 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4343 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4344
4345 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4346 /* We have signal detect and not receiving
4347 * config code words, link is up by parallel
4348 * detection.
4349 */
4350
4351 bmcr &= ~BMCR_ANENABLE;
4352 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4353 tg3_writephy(tp, MII_BMCR, bmcr);
4354 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4355 }
4356 }
4357 } else if (netif_carrier_ok(tp->dev) &&
4358 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4359 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4360 u32 phy2;
4361
4362 /* Select expansion interrupt status register */
4363 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4364 MII_TG3_DSP_EXP1_INT_STAT);
4365 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4366 if (phy2 & 0x20) {
4367 u32 bmcr;
4368
4369 /* Config code words received, turn on autoneg. */
4370 tg3_readphy(tp, MII_BMCR, &bmcr);
4371 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4372
4373 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4374
4375 }
4376 }
4377 }
4378
4379 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4380 {
4381 int err;
4382
4383 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4384 err = tg3_setup_fiber_phy(tp, force_reset);
4385 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4386 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4387 else
4388 err = tg3_setup_copper_phy(tp, force_reset);
4389
4390 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4391 u32 val, scale;
4392
4393 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4394 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4395 scale = 65;
4396 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4397 scale = 6;
4398 else
4399 scale = 12;
4400
4401 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4402 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4403 tw32(GRC_MISC_CFG, val);
4404 }
4405
4406 if (tp->link_config.active_speed == SPEED_1000 &&
4407 tp->link_config.active_duplex == DUPLEX_HALF)
4408 tw32(MAC_TX_LENGTHS,
4409 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4410 (6 << TX_LENGTHS_IPG_SHIFT) |
4411 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4412 else
4413 tw32(MAC_TX_LENGTHS,
4414 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4415 (6 << TX_LENGTHS_IPG_SHIFT) |
4416 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4417
4418 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4419 if (netif_carrier_ok(tp->dev)) {
4420 tw32(HOSTCC_STAT_COAL_TICKS,
4421 tp->coal.stats_block_coalesce_usecs);
4422 } else {
4423 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4424 }
4425 }
4426
4427 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4428 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4429 if (!netif_carrier_ok(tp->dev))
4430 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4431 tp->pwrmgmt_thresh;
4432 else
4433 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4434 tw32(PCIE_PWR_MGMT_THRESH, val);
4435 }
4436
4437 return err;
4438 }
4439
4440 static inline int tg3_irq_sync(struct tg3 *tp)
4441 {
4442 return tp->irq_sync;
4443 }
4444
4445 /* This is called whenever we suspect that the system chipset is re-
4446 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4447 * is bogus tx completions. We try to recover by setting the
4448 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4449 * in the workqueue.
4450 */
4451 static void tg3_tx_recover(struct tg3 *tp)
4452 {
4453 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4454 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4455
4456 netdev_warn(tp->dev,
4457 "The system may be re-ordering memory-mapped I/O "
4458 "cycles to the network device, attempting to recover. "
4459 "Please report the problem to the driver maintainer "
4460 "and include system chipset information.\n");
4461
4462 spin_lock(&tp->lock);
4463 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4464 spin_unlock(&tp->lock);
4465 }
4466
4467 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4468 {
4469 /* Tell compiler to fetch tx indices from memory. */
4470 barrier();
4471 return tnapi->tx_pending -
4472 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4473 }
4474
4475 /* Tigon3 never reports partial packet sends. So we do not
4476 * need special logic to handle SKBs that have not had all
4477 * of their frags sent yet, like SunGEM does.
4478 */
4479 static void tg3_tx(struct tg3_napi *tnapi)
4480 {
4481 struct tg3 *tp = tnapi->tp;
4482 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4483 u32 sw_idx = tnapi->tx_cons;
4484 struct netdev_queue *txq;
4485 int index = tnapi - tp->napi;
4486
4487 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4488 index--;
4489
4490 txq = netdev_get_tx_queue(tp->dev, index);
4491
4492 while (sw_idx != hw_idx) {
4493 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4494 struct sk_buff *skb = ri->skb;
4495 int i, tx_bug = 0;
4496
4497 if (unlikely(skb == NULL)) {
4498 tg3_tx_recover(tp);
4499 return;
4500 }
4501
4502 pci_unmap_single(tp->pdev,
4503 dma_unmap_addr(ri, mapping),
4504 skb_headlen(skb),
4505 PCI_DMA_TODEVICE);
4506
4507 ri->skb = NULL;
4508
4509 sw_idx = NEXT_TX(sw_idx);
4510
4511 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4512 ri = &tnapi->tx_buffers[sw_idx];
4513 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4514 tx_bug = 1;
4515
4516 pci_unmap_page(tp->pdev,
4517 dma_unmap_addr(ri, mapping),
4518 skb_shinfo(skb)->frags[i].size,
4519 PCI_DMA_TODEVICE);
4520 sw_idx = NEXT_TX(sw_idx);
4521 }
4522
4523 dev_kfree_skb(skb);
4524
4525 if (unlikely(tx_bug)) {
4526 tg3_tx_recover(tp);
4527 return;
4528 }
4529 }
4530
4531 tnapi->tx_cons = sw_idx;
4532
4533 /* Need to make the tx_cons update visible to tg3_start_xmit()
4534 * before checking for netif_queue_stopped(). Without the
4535 * memory barrier, there is a small possibility that tg3_start_xmit()
4536 * will miss it and cause the queue to be stopped forever.
4537 */
4538 smp_mb();
4539
4540 if (unlikely(netif_tx_queue_stopped(txq) &&
4541 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4542 __netif_tx_lock(txq, smp_processor_id());
4543 if (netif_tx_queue_stopped(txq) &&
4544 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4545 netif_tx_wake_queue(txq);
4546 __netif_tx_unlock(txq);
4547 }
4548 }
4549
4550 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4551 {
4552 if (!ri->skb)
4553 return;
4554
4555 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4556 map_sz, PCI_DMA_FROMDEVICE);
4557 dev_kfree_skb_any(ri->skb);
4558 ri->skb = NULL;
4559 }
4560
4561 /* Returns size of skb allocated or < 0 on error.
4562 *
4563 * We only need to fill in the address because the other members
4564 * of the RX descriptor are invariant, see tg3_init_rings.
4565 *
4566 * Note the purposeful assymetry of cpu vs. chip accesses. For
4567 * posting buffers we only dirty the first cache line of the RX
4568 * descriptor (containing the address). Whereas for the RX status
4569 * buffers the cpu only reads the last cacheline of the RX descriptor
4570 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4571 */
4572 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4573 u32 opaque_key, u32 dest_idx_unmasked)
4574 {
4575 struct tg3_rx_buffer_desc *desc;
4576 struct ring_info *map, *src_map;
4577 struct sk_buff *skb;
4578 dma_addr_t mapping;
4579 int skb_size, dest_idx;
4580
4581 src_map = NULL;
4582 switch (opaque_key) {
4583 case RXD_OPAQUE_RING_STD:
4584 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4585 desc = &tpr->rx_std[dest_idx];
4586 map = &tpr->rx_std_buffers[dest_idx];
4587 skb_size = tp->rx_pkt_map_sz;
4588 break;
4589
4590 case RXD_OPAQUE_RING_JUMBO:
4591 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4592 desc = &tpr->rx_jmb[dest_idx].std;
4593 map = &tpr->rx_jmb_buffers[dest_idx];
4594 skb_size = TG3_RX_JMB_MAP_SZ;
4595 break;
4596
4597 default:
4598 return -EINVAL;
4599 }
4600
4601 /* Do not overwrite any of the map or rp information
4602 * until we are sure we can commit to a new buffer.
4603 *
4604 * Callers depend upon this behavior and assume that
4605 * we leave everything unchanged if we fail.
4606 */
4607 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4608 if (skb == NULL)
4609 return -ENOMEM;
4610
4611 skb_reserve(skb, tp->rx_offset);
4612
4613 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4614 PCI_DMA_FROMDEVICE);
4615 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4616 dev_kfree_skb(skb);
4617 return -EIO;
4618 }
4619
4620 map->skb = skb;
4621 dma_unmap_addr_set(map, mapping, mapping);
4622
4623 desc->addr_hi = ((u64)mapping >> 32);
4624 desc->addr_lo = ((u64)mapping & 0xffffffff);
4625
4626 return skb_size;
4627 }
4628
4629 /* We only need to move over in the address because the other
4630 * members of the RX descriptor are invariant. See notes above
4631 * tg3_alloc_rx_skb for full details.
4632 */
4633 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4634 struct tg3_rx_prodring_set *dpr,
4635 u32 opaque_key, int src_idx,
4636 u32 dest_idx_unmasked)
4637 {
4638 struct tg3 *tp = tnapi->tp;
4639 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4640 struct ring_info *src_map, *dest_map;
4641 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4642 int dest_idx;
4643
4644 switch (opaque_key) {
4645 case RXD_OPAQUE_RING_STD:
4646 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4647 dest_desc = &dpr->rx_std[dest_idx];
4648 dest_map = &dpr->rx_std_buffers[dest_idx];
4649 src_desc = &spr->rx_std[src_idx];
4650 src_map = &spr->rx_std_buffers[src_idx];
4651 break;
4652
4653 case RXD_OPAQUE_RING_JUMBO:
4654 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4655 dest_desc = &dpr->rx_jmb[dest_idx].std;
4656 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4657 src_desc = &spr->rx_jmb[src_idx].std;
4658 src_map = &spr->rx_jmb_buffers[src_idx];
4659 break;
4660
4661 default:
4662 return;
4663 }
4664
4665 dest_map->skb = src_map->skb;
4666 dma_unmap_addr_set(dest_map, mapping,
4667 dma_unmap_addr(src_map, mapping));
4668 dest_desc->addr_hi = src_desc->addr_hi;
4669 dest_desc->addr_lo = src_desc->addr_lo;
4670
4671 /* Ensure that the update to the skb happens after the physical
4672 * addresses have been transferred to the new BD location.
4673 */
4674 smp_wmb();
4675
4676 src_map->skb = NULL;
4677 }
4678
4679 /* The RX ring scheme is composed of multiple rings which post fresh
4680 * buffers to the chip, and one special ring the chip uses to report
4681 * status back to the host.
4682 *
4683 * The special ring reports the status of received packets to the
4684 * host. The chip does not write into the original descriptor the
4685 * RX buffer was obtained from. The chip simply takes the original
4686 * descriptor as provided by the host, updates the status and length
4687 * field, then writes this into the next status ring entry.
4688 *
4689 * Each ring the host uses to post buffers to the chip is described
4690 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4691 * it is first placed into the on-chip ram. When the packet's length
4692 * is known, it walks down the TG3_BDINFO entries to select the ring.
4693 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4694 * which is within the range of the new packet's length is chosen.
4695 *
4696 * The "separate ring for rx status" scheme may sound queer, but it makes
4697 * sense from a cache coherency perspective. If only the host writes
4698 * to the buffer post rings, and only the chip writes to the rx status
4699 * rings, then cache lines never move beyond shared-modified state.
4700 * If both the host and chip were to write into the same ring, cache line
4701 * eviction could occur since both entities want it in an exclusive state.
4702 */
4703 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4704 {
4705 struct tg3 *tp = tnapi->tp;
4706 u32 work_mask, rx_std_posted = 0;
4707 u32 std_prod_idx, jmb_prod_idx;
4708 u32 sw_idx = tnapi->rx_rcb_ptr;
4709 u16 hw_idx;
4710 int received;
4711 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4712
4713 hw_idx = *(tnapi->rx_rcb_prod_idx);
4714 /*
4715 * We need to order the read of hw_idx and the read of
4716 * the opaque cookie.
4717 */
4718 rmb();
4719 work_mask = 0;
4720 received = 0;
4721 std_prod_idx = tpr->rx_std_prod_idx;
4722 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4723 while (sw_idx != hw_idx && budget > 0) {
4724 struct ring_info *ri;
4725 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4726 unsigned int len;
4727 struct sk_buff *skb;
4728 dma_addr_t dma_addr;
4729 u32 opaque_key, desc_idx, *post_ptr;
4730 bool hw_vlan __maybe_unused = false;
4731 u16 vtag __maybe_unused = 0;
4732
4733 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4734 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4735 if (opaque_key == RXD_OPAQUE_RING_STD) {
4736 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4737 dma_addr = dma_unmap_addr(ri, mapping);
4738 skb = ri->skb;
4739 post_ptr = &std_prod_idx;
4740 rx_std_posted++;
4741 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4742 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4743 dma_addr = dma_unmap_addr(ri, mapping);
4744 skb = ri->skb;
4745 post_ptr = &jmb_prod_idx;
4746 } else
4747 goto next_pkt_nopost;
4748
4749 work_mask |= opaque_key;
4750
4751 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4752 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4753 drop_it:
4754 tg3_recycle_rx(tnapi, tpr, opaque_key,
4755 desc_idx, *post_ptr);
4756 drop_it_no_recycle:
4757 /* Other statistics kept track of by card. */
4758 tp->net_stats.rx_dropped++;
4759 goto next_pkt;
4760 }
4761
4762 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4763 ETH_FCS_LEN;
4764
4765 if (len > TG3_RX_COPY_THRESH(tp)) {
4766 int skb_size;
4767
4768 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4769 *post_ptr);
4770 if (skb_size < 0)
4771 goto drop_it;
4772
4773 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4774 PCI_DMA_FROMDEVICE);
4775
4776 /* Ensure that the update to the skb happens
4777 * after the usage of the old DMA mapping.
4778 */
4779 smp_wmb();
4780
4781 ri->skb = NULL;
4782
4783 skb_put(skb, len);
4784 } else {
4785 struct sk_buff *copy_skb;
4786
4787 tg3_recycle_rx(tnapi, tpr, opaque_key,
4788 desc_idx, *post_ptr);
4789
4790 copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4791 TG3_RAW_IP_ALIGN);
4792 if (copy_skb == NULL)
4793 goto drop_it_no_recycle;
4794
4795 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4796 skb_put(copy_skb, len);
4797 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4798 skb_copy_from_linear_data(skb, copy_skb->data, len);
4799 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4800
4801 /* We'll reuse the original ring buffer. */
4802 skb = copy_skb;
4803 }
4804
4805 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4806 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4807 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4808 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4809 skb->ip_summed = CHECKSUM_UNNECESSARY;
4810 else
4811 skb_checksum_none_assert(skb);
4812
4813 skb->protocol = eth_type_trans(skb, tp->dev);
4814
4815 if (len > (tp->dev->mtu + ETH_HLEN) &&
4816 skb->protocol != htons(ETH_P_8021Q)) {
4817 dev_kfree_skb(skb);
4818 goto next_pkt;
4819 }
4820
4821 if (desc->type_flags & RXD_FLAG_VLAN &&
4822 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4823 vtag = desc->err_vlan & RXD_VLAN_MASK;
4824 #if TG3_VLAN_TAG_USED
4825 if (tp->vlgrp)
4826 hw_vlan = true;
4827 else
4828 #endif
4829 {
4830 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4831 __skb_push(skb, VLAN_HLEN);
4832
4833 memmove(ve, skb->data + VLAN_HLEN,
4834 ETH_ALEN * 2);
4835 ve->h_vlan_proto = htons(ETH_P_8021Q);
4836 ve->h_vlan_TCI = htons(vtag);
4837 }
4838 }
4839
4840 #if TG3_VLAN_TAG_USED
4841 if (hw_vlan)
4842 vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4843 else
4844 #endif
4845 napi_gro_receive(&tnapi->napi, skb);
4846
4847 received++;
4848 budget--;
4849
4850 next_pkt:
4851 (*post_ptr)++;
4852
4853 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4854 tpr->rx_std_prod_idx = std_prod_idx &
4855 tp->rx_std_ring_mask;
4856 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4857 tpr->rx_std_prod_idx);
4858 work_mask &= ~RXD_OPAQUE_RING_STD;
4859 rx_std_posted = 0;
4860 }
4861 next_pkt_nopost:
4862 sw_idx++;
4863 sw_idx &= tp->rx_ret_ring_mask;
4864
4865 /* Refresh hw_idx to see if there is new work */
4866 if (sw_idx == hw_idx) {
4867 hw_idx = *(tnapi->rx_rcb_prod_idx);
4868 rmb();
4869 }
4870 }
4871
4872 /* ACK the status ring. */
4873 tnapi->rx_rcb_ptr = sw_idx;
4874 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4875
4876 /* Refill RX ring(s). */
4877 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4878 if (work_mask & RXD_OPAQUE_RING_STD) {
4879 tpr->rx_std_prod_idx = std_prod_idx &
4880 tp->rx_std_ring_mask;
4881 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4882 tpr->rx_std_prod_idx);
4883 }
4884 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4885 tpr->rx_jmb_prod_idx = jmb_prod_idx &
4886 tp->rx_jmb_ring_mask;
4887 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4888 tpr->rx_jmb_prod_idx);
4889 }
4890 mmiowb();
4891 } else if (work_mask) {
4892 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4893 * updated before the producer indices can be updated.
4894 */
4895 smp_wmb();
4896
4897 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4898 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4899
4900 if (tnapi != &tp->napi[1])
4901 napi_schedule(&tp->napi[1].napi);
4902 }
4903
4904 return received;
4905 }
4906
4907 static void tg3_poll_link(struct tg3 *tp)
4908 {
4909 /* handle link change and other phy events */
4910 if (!(tp->tg3_flags &
4911 (TG3_FLAG_USE_LINKCHG_REG |
4912 TG3_FLAG_POLL_SERDES))) {
4913 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4914
4915 if (sblk->status & SD_STATUS_LINK_CHG) {
4916 sblk->status = SD_STATUS_UPDATED |
4917 (sblk->status & ~SD_STATUS_LINK_CHG);
4918 spin_lock(&tp->lock);
4919 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4920 tw32_f(MAC_STATUS,
4921 (MAC_STATUS_SYNC_CHANGED |
4922 MAC_STATUS_CFG_CHANGED |
4923 MAC_STATUS_MI_COMPLETION |
4924 MAC_STATUS_LNKSTATE_CHANGED));
4925 udelay(40);
4926 } else
4927 tg3_setup_phy(tp, 0);
4928 spin_unlock(&tp->lock);
4929 }
4930 }
4931 }
4932
4933 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4934 struct tg3_rx_prodring_set *dpr,
4935 struct tg3_rx_prodring_set *spr)
4936 {
4937 u32 si, di, cpycnt, src_prod_idx;
4938 int i, err = 0;
4939
4940 while (1) {
4941 src_prod_idx = spr->rx_std_prod_idx;
4942
4943 /* Make sure updates to the rx_std_buffers[] entries and the
4944 * standard producer index are seen in the correct order.
4945 */
4946 smp_rmb();
4947
4948 if (spr->rx_std_cons_idx == src_prod_idx)
4949 break;
4950
4951 if (spr->rx_std_cons_idx < src_prod_idx)
4952 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4953 else
4954 cpycnt = tp->rx_std_ring_mask + 1 -
4955 spr->rx_std_cons_idx;
4956
4957 cpycnt = min(cpycnt,
4958 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4959
4960 si = spr->rx_std_cons_idx;
4961 di = dpr->rx_std_prod_idx;
4962
4963 for (i = di; i < di + cpycnt; i++) {
4964 if (dpr->rx_std_buffers[i].skb) {
4965 cpycnt = i - di;
4966 err = -ENOSPC;
4967 break;
4968 }
4969 }
4970
4971 if (!cpycnt)
4972 break;
4973
4974 /* Ensure that updates to the rx_std_buffers ring and the
4975 * shadowed hardware producer ring from tg3_recycle_skb() are
4976 * ordered correctly WRT the skb check above.
4977 */
4978 smp_rmb();
4979
4980 memcpy(&dpr->rx_std_buffers[di],
4981 &spr->rx_std_buffers[si],
4982 cpycnt * sizeof(struct ring_info));
4983
4984 for (i = 0; i < cpycnt; i++, di++, si++) {
4985 struct tg3_rx_buffer_desc *sbd, *dbd;
4986 sbd = &spr->rx_std[si];
4987 dbd = &dpr->rx_std[di];
4988 dbd->addr_hi = sbd->addr_hi;
4989 dbd->addr_lo = sbd->addr_lo;
4990 }
4991
4992 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4993 tp->rx_std_ring_mask;
4994 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4995 tp->rx_std_ring_mask;
4996 }
4997
4998 while (1) {
4999 src_prod_idx = spr->rx_jmb_prod_idx;
5000
5001 /* Make sure updates to the rx_jmb_buffers[] entries and
5002 * the jumbo producer index are seen in the correct order.
5003 */
5004 smp_rmb();
5005
5006 if (spr->rx_jmb_cons_idx == src_prod_idx)
5007 break;
5008
5009 if (spr->rx_jmb_cons_idx < src_prod_idx)
5010 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5011 else
5012 cpycnt = tp->rx_jmb_ring_mask + 1 -
5013 spr->rx_jmb_cons_idx;
5014
5015 cpycnt = min(cpycnt,
5016 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5017
5018 si = spr->rx_jmb_cons_idx;
5019 di = dpr->rx_jmb_prod_idx;
5020
5021 for (i = di; i < di + cpycnt; i++) {
5022 if (dpr->rx_jmb_buffers[i].skb) {
5023 cpycnt = i - di;
5024 err = -ENOSPC;
5025 break;
5026 }
5027 }
5028
5029 if (!cpycnt)
5030 break;
5031
5032 /* Ensure that updates to the rx_jmb_buffers ring and the
5033 * shadowed hardware producer ring from tg3_recycle_skb() are
5034 * ordered correctly WRT the skb check above.
5035 */
5036 smp_rmb();
5037
5038 memcpy(&dpr->rx_jmb_buffers[di],
5039 &spr->rx_jmb_buffers[si],
5040 cpycnt * sizeof(struct ring_info));
5041
5042 for (i = 0; i < cpycnt; i++, di++, si++) {
5043 struct tg3_rx_buffer_desc *sbd, *dbd;
5044 sbd = &spr->rx_jmb[si].std;
5045 dbd = &dpr->rx_jmb[di].std;
5046 dbd->addr_hi = sbd->addr_hi;
5047 dbd->addr_lo = sbd->addr_lo;
5048 }
5049
5050 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5051 tp->rx_jmb_ring_mask;
5052 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5053 tp->rx_jmb_ring_mask;
5054 }
5055
5056 return err;
5057 }
5058
5059 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5060 {
5061 struct tg3 *tp = tnapi->tp;
5062
5063 /* run TX completion thread */
5064 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5065 tg3_tx(tnapi);
5066 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5067 return work_done;
5068 }
5069
5070 /* run RX thread, within the bounds set by NAPI.
5071 * All RX "locking" is done by ensuring outside
5072 * code synchronizes with tg3->napi.poll()
5073 */
5074 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5075 work_done += tg3_rx(tnapi, budget - work_done);
5076
5077 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5078 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5079 int i, err = 0;
5080 u32 std_prod_idx = dpr->rx_std_prod_idx;
5081 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5082
5083 for (i = 1; i < tp->irq_cnt; i++)
5084 err |= tg3_rx_prodring_xfer(tp, dpr,
5085 &tp->napi[i].prodring);
5086
5087 wmb();
5088
5089 if (std_prod_idx != dpr->rx_std_prod_idx)
5090 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5091 dpr->rx_std_prod_idx);
5092
5093 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5094 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5095 dpr->rx_jmb_prod_idx);
5096
5097 mmiowb();
5098
5099 if (err)
5100 tw32_f(HOSTCC_MODE, tp->coal_now);
5101 }
5102
5103 return work_done;
5104 }
5105
5106 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5107 {
5108 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5109 struct tg3 *tp = tnapi->tp;
5110 int work_done = 0;
5111 struct tg3_hw_status *sblk = tnapi->hw_status;
5112
5113 while (1) {
5114 work_done = tg3_poll_work(tnapi, work_done, budget);
5115
5116 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5117 goto tx_recovery;
5118
5119 if (unlikely(work_done >= budget))
5120 break;
5121
5122 /* tp->last_tag is used in tg3_int_reenable() below
5123 * to tell the hw how much work has been processed,
5124 * so we must read it before checking for more work.
5125 */
5126 tnapi->last_tag = sblk->status_tag;
5127 tnapi->last_irq_tag = tnapi->last_tag;
5128 rmb();
5129
5130 /* check for RX/TX work to do */
5131 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5132 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5133 napi_complete(napi);
5134 /* Reenable interrupts. */
5135 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5136 mmiowb();
5137 break;
5138 }
5139 }
5140
5141 return work_done;
5142
5143 tx_recovery:
5144 /* work_done is guaranteed to be less than budget. */
5145 napi_complete(napi);
5146 schedule_work(&tp->reset_task);
5147 return work_done;
5148 }
5149
5150 static int tg3_poll(struct napi_struct *napi, int budget)
5151 {
5152 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5153 struct tg3 *tp = tnapi->tp;
5154 int work_done = 0;
5155 struct tg3_hw_status *sblk = tnapi->hw_status;
5156
5157 while (1) {
5158 tg3_poll_link(tp);
5159
5160 work_done = tg3_poll_work(tnapi, work_done, budget);
5161
5162 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5163 goto tx_recovery;
5164
5165 if (unlikely(work_done >= budget))
5166 break;
5167
5168 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5169 /* tp->last_tag is used in tg3_int_reenable() below
5170 * to tell the hw how much work has been processed,
5171 * so we must read it before checking for more work.
5172 */
5173 tnapi->last_tag = sblk->status_tag;
5174 tnapi->last_irq_tag = tnapi->last_tag;
5175 rmb();
5176 } else
5177 sblk->status &= ~SD_STATUS_UPDATED;
5178
5179 if (likely(!tg3_has_work(tnapi))) {
5180 napi_complete(napi);
5181 tg3_int_reenable(tnapi);
5182 break;
5183 }
5184 }
5185
5186 return work_done;
5187
5188 tx_recovery:
5189 /* work_done is guaranteed to be less than budget. */
5190 napi_complete(napi);
5191 schedule_work(&tp->reset_task);
5192 return work_done;
5193 }
5194
5195 static void tg3_napi_disable(struct tg3 *tp)
5196 {
5197 int i;
5198
5199 for (i = tp->irq_cnt - 1; i >= 0; i--)
5200 napi_disable(&tp->napi[i].napi);
5201 }
5202
5203 static void tg3_napi_enable(struct tg3 *tp)
5204 {
5205 int i;
5206
5207 for (i = 0; i < tp->irq_cnt; i++)
5208 napi_enable(&tp->napi[i].napi);
5209 }
5210
5211 static void tg3_napi_init(struct tg3 *tp)
5212 {
5213 int i;
5214
5215 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5216 for (i = 1; i < tp->irq_cnt; i++)
5217 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5218 }
5219
5220 static void tg3_napi_fini(struct tg3 *tp)
5221 {
5222 int i;
5223
5224 for (i = 0; i < tp->irq_cnt; i++)
5225 netif_napi_del(&tp->napi[i].napi);
5226 }
5227
5228 static inline void tg3_netif_stop(struct tg3 *tp)
5229 {
5230 tp->dev->trans_start = jiffies; /* prevent tx timeout */
5231 tg3_napi_disable(tp);
5232 netif_tx_disable(tp->dev);
5233 }
5234
5235 static inline void tg3_netif_start(struct tg3 *tp)
5236 {
5237 /* NOTE: unconditional netif_tx_wake_all_queues is only
5238 * appropriate so long as all callers are assured to
5239 * have free tx slots (such as after tg3_init_hw)
5240 */
5241 netif_tx_wake_all_queues(tp->dev);
5242
5243 tg3_napi_enable(tp);
5244 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5245 tg3_enable_ints(tp);
5246 }
5247
5248 static void tg3_irq_quiesce(struct tg3 *tp)
5249 {
5250 int i;
5251
5252 BUG_ON(tp->irq_sync);
5253
5254 tp->irq_sync = 1;
5255 smp_mb();
5256
5257 for (i = 0; i < tp->irq_cnt; i++)
5258 synchronize_irq(tp->napi[i].irq_vec);
5259 }
5260
5261 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5262 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5263 * with as well. Most of the time, this is not necessary except when
5264 * shutting down the device.
5265 */
5266 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5267 {
5268 spin_lock_bh(&tp->lock);
5269 if (irq_sync)
5270 tg3_irq_quiesce(tp);
5271 }
5272
5273 static inline void tg3_full_unlock(struct tg3 *tp)
5274 {
5275 spin_unlock_bh(&tp->lock);
5276 }
5277
5278 /* One-shot MSI handler - Chip automatically disables interrupt
5279 * after sending MSI so driver doesn't have to do it.
5280 */
5281 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5282 {
5283 struct tg3_napi *tnapi = dev_id;
5284 struct tg3 *tp = tnapi->tp;
5285
5286 prefetch(tnapi->hw_status);
5287 if (tnapi->rx_rcb)
5288 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5289
5290 if (likely(!tg3_irq_sync(tp)))
5291 napi_schedule(&tnapi->napi);
5292
5293 return IRQ_HANDLED;
5294 }
5295
5296 /* MSI ISR - No need to check for interrupt sharing and no need to
5297 * flush status block and interrupt mailbox. PCI ordering rules
5298 * guarantee that MSI will arrive after the status block.
5299 */
5300 static irqreturn_t tg3_msi(int irq, void *dev_id)
5301 {
5302 struct tg3_napi *tnapi = dev_id;
5303 struct tg3 *tp = tnapi->tp;
5304
5305 prefetch(tnapi->hw_status);
5306 if (tnapi->rx_rcb)
5307 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5308 /*
5309 * Writing any value to intr-mbox-0 clears PCI INTA# and
5310 * chip-internal interrupt pending events.
5311 * Writing non-zero to intr-mbox-0 additional tells the
5312 * NIC to stop sending us irqs, engaging "in-intr-handler"
5313 * event coalescing.
5314 */
5315 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5316 if (likely(!tg3_irq_sync(tp)))
5317 napi_schedule(&tnapi->napi);
5318
5319 return IRQ_RETVAL(1);
5320 }
5321
5322 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5323 {
5324 struct tg3_napi *tnapi = dev_id;
5325 struct tg3 *tp = tnapi->tp;
5326 struct tg3_hw_status *sblk = tnapi->hw_status;
5327 unsigned int handled = 1;
5328
5329 /* In INTx mode, it is possible for the interrupt to arrive at
5330 * the CPU before the status block posted prior to the interrupt.
5331 * Reading the PCI State register will confirm whether the
5332 * interrupt is ours and will flush the status block.
5333 */
5334 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5335 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5336 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5337 handled = 0;
5338 goto out;
5339 }
5340 }
5341
5342 /*
5343 * Writing any value to intr-mbox-0 clears PCI INTA# and
5344 * chip-internal interrupt pending events.
5345 * Writing non-zero to intr-mbox-0 additional tells the
5346 * NIC to stop sending us irqs, engaging "in-intr-handler"
5347 * event coalescing.
5348 *
5349 * Flush the mailbox to de-assert the IRQ immediately to prevent
5350 * spurious interrupts. The flush impacts performance but
5351 * excessive spurious interrupts can be worse in some cases.
5352 */
5353 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5354 if (tg3_irq_sync(tp))
5355 goto out;
5356 sblk->status &= ~SD_STATUS_UPDATED;
5357 if (likely(tg3_has_work(tnapi))) {
5358 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5359 napi_schedule(&tnapi->napi);
5360 } else {
5361 /* No work, shared interrupt perhaps? re-enable
5362 * interrupts, and flush that PCI write
5363 */
5364 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5365 0x00000000);
5366 }
5367 out:
5368 return IRQ_RETVAL(handled);
5369 }
5370
5371 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5372 {
5373 struct tg3_napi *tnapi = dev_id;
5374 struct tg3 *tp = tnapi->tp;
5375 struct tg3_hw_status *sblk = tnapi->hw_status;
5376 unsigned int handled = 1;
5377
5378 /* In INTx mode, it is possible for the interrupt to arrive at
5379 * the CPU before the status block posted prior to the interrupt.
5380 * Reading the PCI State register will confirm whether the
5381 * interrupt is ours and will flush the status block.
5382 */
5383 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5384 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5385 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5386 handled = 0;
5387 goto out;
5388 }
5389 }
5390
5391 /*
5392 * writing any value to intr-mbox-0 clears PCI INTA# and
5393 * chip-internal interrupt pending events.
5394 * writing non-zero to intr-mbox-0 additional tells the
5395 * NIC to stop sending us irqs, engaging "in-intr-handler"
5396 * event coalescing.
5397 *
5398 * Flush the mailbox to de-assert the IRQ immediately to prevent
5399 * spurious interrupts. The flush impacts performance but
5400 * excessive spurious interrupts can be worse in some cases.
5401 */
5402 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5403
5404 /*
5405 * In a shared interrupt configuration, sometimes other devices'
5406 * interrupts will scream. We record the current status tag here
5407 * so that the above check can report that the screaming interrupts
5408 * are unhandled. Eventually they will be silenced.
5409 */
5410 tnapi->last_irq_tag = sblk->status_tag;
5411
5412 if (tg3_irq_sync(tp))
5413 goto out;
5414
5415 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5416
5417 napi_schedule(&tnapi->napi);
5418
5419 out:
5420 return IRQ_RETVAL(handled);
5421 }
5422
5423 /* ISR for interrupt test */
5424 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5425 {
5426 struct tg3_napi *tnapi = dev_id;
5427 struct tg3 *tp = tnapi->tp;
5428 struct tg3_hw_status *sblk = tnapi->hw_status;
5429
5430 if ((sblk->status & SD_STATUS_UPDATED) ||
5431 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5432 tg3_disable_ints(tp);
5433 return IRQ_RETVAL(1);
5434 }
5435 return IRQ_RETVAL(0);
5436 }
5437
5438 static int tg3_init_hw(struct tg3 *, int);
5439 static int tg3_halt(struct tg3 *, int, int);
5440
5441 /* Restart hardware after configuration changes, self-test, etc.
5442 * Invoked with tp->lock held.
5443 */
5444 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5445 __releases(tp->lock)
5446 __acquires(tp->lock)
5447 {
5448 int err;
5449
5450 err = tg3_init_hw(tp, reset_phy);
5451 if (err) {
5452 netdev_err(tp->dev,
5453 "Failed to re-initialize device, aborting\n");
5454 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5455 tg3_full_unlock(tp);
5456 del_timer_sync(&tp->timer);
5457 tp->irq_sync = 0;
5458 tg3_napi_enable(tp);
5459 dev_close(tp->dev);
5460 tg3_full_lock(tp, 0);
5461 }
5462 return err;
5463 }
5464
5465 #ifdef CONFIG_NET_POLL_CONTROLLER
5466 static void tg3_poll_controller(struct net_device *dev)
5467 {
5468 int i;
5469 struct tg3 *tp = netdev_priv(dev);
5470
5471 for (i = 0; i < tp->irq_cnt; i++)
5472 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5473 }
5474 #endif
5475
5476 static void tg3_reset_task(struct work_struct *work)
5477 {
5478 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5479 int err;
5480 unsigned int restart_timer;
5481
5482 tg3_full_lock(tp, 0);
5483
5484 if (!netif_running(tp->dev)) {
5485 tg3_full_unlock(tp);
5486 return;
5487 }
5488
5489 tg3_full_unlock(tp);
5490
5491 tg3_phy_stop(tp);
5492
5493 tg3_netif_stop(tp);
5494
5495 tg3_full_lock(tp, 1);
5496
5497 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5498 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5499
5500 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5501 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5502 tp->write32_rx_mbox = tg3_write_flush_reg32;
5503 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5504 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5505 }
5506
5507 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5508 err = tg3_init_hw(tp, 1);
5509 if (err)
5510 goto out;
5511
5512 tg3_netif_start(tp);
5513
5514 if (restart_timer)
5515 mod_timer(&tp->timer, jiffies + 1);
5516
5517 out:
5518 tg3_full_unlock(tp);
5519
5520 if (!err)
5521 tg3_phy_start(tp);
5522 }
5523
5524 static void tg3_dump_short_state(struct tg3 *tp)
5525 {
5526 netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5527 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5528 netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5529 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5530 }
5531
5532 static void tg3_tx_timeout(struct net_device *dev)
5533 {
5534 struct tg3 *tp = netdev_priv(dev);
5535
5536 if (netif_msg_tx_err(tp)) {
5537 netdev_err(dev, "transmit timed out, resetting\n");
5538 tg3_dump_short_state(tp);
5539 }
5540
5541 schedule_work(&tp->reset_task);
5542 }
5543
5544 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5545 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5546 {
5547 u32 base = (u32) mapping & 0xffffffff;
5548
5549 return (base > 0xffffdcc0) && (base + len + 8 < base);
5550 }
5551
5552 /* Test for DMA addresses > 40-bit */
5553 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5554 int len)
5555 {
5556 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5557 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5558 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5559 return 0;
5560 #else
5561 return 0;
5562 #endif
5563 }
5564
5565 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5566
5567 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5568 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5569 struct sk_buff *skb, u32 last_plus_one,
5570 u32 *start, u32 base_flags, u32 mss)
5571 {
5572 struct tg3 *tp = tnapi->tp;
5573 struct sk_buff *new_skb;
5574 dma_addr_t new_addr = 0;
5575 u32 entry = *start;
5576 int i, ret = 0;
5577
5578 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5579 new_skb = skb_copy(skb, GFP_ATOMIC);
5580 else {
5581 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5582
5583 new_skb = skb_copy_expand(skb,
5584 skb_headroom(skb) + more_headroom,
5585 skb_tailroom(skb), GFP_ATOMIC);
5586 }
5587
5588 if (!new_skb) {
5589 ret = -1;
5590 } else {
5591 /* New SKB is guaranteed to be linear. */
5592 entry = *start;
5593 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5594 PCI_DMA_TODEVICE);
5595 /* Make sure the mapping succeeded */
5596 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5597 ret = -1;
5598 dev_kfree_skb(new_skb);
5599 new_skb = NULL;
5600
5601 /* Make sure new skb does not cross any 4G boundaries.
5602 * Drop the packet if it does.
5603 */
5604 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5605 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5606 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5607 PCI_DMA_TODEVICE);
5608 ret = -1;
5609 dev_kfree_skb(new_skb);
5610 new_skb = NULL;
5611 } else {
5612 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5613 base_flags, 1 | (mss << 1));
5614 *start = NEXT_TX(entry);
5615 }
5616 }
5617
5618 /* Now clean up the sw ring entries. */
5619 i = 0;
5620 while (entry != last_plus_one) {
5621 int len;
5622
5623 if (i == 0)
5624 len = skb_headlen(skb);
5625 else
5626 len = skb_shinfo(skb)->frags[i-1].size;
5627
5628 pci_unmap_single(tp->pdev,
5629 dma_unmap_addr(&tnapi->tx_buffers[entry],
5630 mapping),
5631 len, PCI_DMA_TODEVICE);
5632 if (i == 0) {
5633 tnapi->tx_buffers[entry].skb = new_skb;
5634 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5635 new_addr);
5636 } else {
5637 tnapi->tx_buffers[entry].skb = NULL;
5638 }
5639 entry = NEXT_TX(entry);
5640 i++;
5641 }
5642
5643 dev_kfree_skb(skb);
5644
5645 return ret;
5646 }
5647
5648 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5649 dma_addr_t mapping, int len, u32 flags,
5650 u32 mss_and_is_end)
5651 {
5652 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5653 int is_end = (mss_and_is_end & 0x1);
5654 u32 mss = (mss_and_is_end >> 1);
5655 u32 vlan_tag = 0;
5656
5657 if (is_end)
5658 flags |= TXD_FLAG_END;
5659 if (flags & TXD_FLAG_VLAN) {
5660 vlan_tag = flags >> 16;
5661 flags &= 0xffff;
5662 }
5663 vlan_tag |= (mss << TXD_MSS_SHIFT);
5664
5665 txd->addr_hi = ((u64) mapping >> 32);
5666 txd->addr_lo = ((u64) mapping & 0xffffffff);
5667 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5668 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5669 }
5670
5671 /* hard_start_xmit for devices that don't have any bugs and
5672 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5673 */
5674 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5675 struct net_device *dev)
5676 {
5677 struct tg3 *tp = netdev_priv(dev);
5678 u32 len, entry, base_flags, mss;
5679 dma_addr_t mapping;
5680 struct tg3_napi *tnapi;
5681 struct netdev_queue *txq;
5682 unsigned int i, last;
5683
5684 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5685 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5686 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5687 tnapi++;
5688
5689 /* We are running in BH disabled context with netif_tx_lock
5690 * and TX reclaim runs via tp->napi.poll inside of a software
5691 * interrupt. Furthermore, IRQ processing runs lockless so we have
5692 * no IRQ context deadlocks to worry about either. Rejoice!
5693 */
5694 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5695 if (!netif_tx_queue_stopped(txq)) {
5696 netif_tx_stop_queue(txq);
5697
5698 /* This is a hard error, log it. */
5699 netdev_err(dev,
5700 "BUG! Tx Ring full when queue awake!\n");
5701 }
5702 return NETDEV_TX_BUSY;
5703 }
5704
5705 entry = tnapi->tx_prod;
5706 base_flags = 0;
5707 mss = skb_shinfo(skb)->gso_size;
5708 if (mss) {
5709 int tcp_opt_len, ip_tcp_len;
5710 u32 hdrlen;
5711
5712 if (skb_header_cloned(skb) &&
5713 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5714 dev_kfree_skb(skb);
5715 goto out_unlock;
5716 }
5717
5718 if (skb_is_gso_v6(skb)) {
5719 hdrlen = skb_headlen(skb) - ETH_HLEN;
5720 } else {
5721 struct iphdr *iph = ip_hdr(skb);
5722
5723 tcp_opt_len = tcp_optlen(skb);
5724 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5725
5726 iph->check = 0;
5727 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5728 hdrlen = ip_tcp_len + tcp_opt_len;
5729 }
5730
5731 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5732 mss |= (hdrlen & 0xc) << 12;
5733 if (hdrlen & 0x10)
5734 base_flags |= 0x00000010;
5735 base_flags |= (hdrlen & 0x3e0) << 5;
5736 } else
5737 mss |= hdrlen << 9;
5738
5739 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5740 TXD_FLAG_CPU_POST_DMA);
5741
5742 tcp_hdr(skb)->check = 0;
5743
5744 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5745 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5746 }
5747
5748 #if TG3_VLAN_TAG_USED
5749 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5750 base_flags |= (TXD_FLAG_VLAN |
5751 (vlan_tx_tag_get(skb) << 16));
5752 #endif
5753
5754 len = skb_headlen(skb);
5755
5756 /* Queue skb data, a.k.a. the main skb fragment. */
5757 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5758 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5759 dev_kfree_skb(skb);
5760 goto out_unlock;
5761 }
5762
5763 tnapi->tx_buffers[entry].skb = skb;
5764 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5765
5766 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5767 !mss && skb->len > ETH_DATA_LEN)
5768 base_flags |= TXD_FLAG_JMB_PKT;
5769
5770 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5771 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5772
5773 entry = NEXT_TX(entry);
5774
5775 /* Now loop through additional data fragments, and queue them. */
5776 if (skb_shinfo(skb)->nr_frags > 0) {
5777 last = skb_shinfo(skb)->nr_frags - 1;
5778 for (i = 0; i <= last; i++) {
5779 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5780
5781 len = frag->size;
5782 mapping = pci_map_page(tp->pdev,
5783 frag->page,
5784 frag->page_offset,
5785 len, PCI_DMA_TODEVICE);
5786 if (pci_dma_mapping_error(tp->pdev, mapping))
5787 goto dma_error;
5788
5789 tnapi->tx_buffers[entry].skb = NULL;
5790 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5791 mapping);
5792
5793 tg3_set_txd(tnapi, entry, mapping, len,
5794 base_flags, (i == last) | (mss << 1));
5795
5796 entry = NEXT_TX(entry);
5797 }
5798 }
5799
5800 /* Packets are ready, update Tx producer idx local and on card. */
5801 tw32_tx_mbox(tnapi->prodmbox, entry);
5802
5803 tnapi->tx_prod = entry;
5804 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5805 netif_tx_stop_queue(txq);
5806
5807 /* netif_tx_stop_queue() must be done before checking
5808 * checking tx index in tg3_tx_avail() below, because in
5809 * tg3_tx(), we update tx index before checking for
5810 * netif_tx_queue_stopped().
5811 */
5812 smp_mb();
5813 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5814 netif_tx_wake_queue(txq);
5815 }
5816
5817 out_unlock:
5818 mmiowb();
5819
5820 return NETDEV_TX_OK;
5821
5822 dma_error:
5823 last = i;
5824 entry = tnapi->tx_prod;
5825 tnapi->tx_buffers[entry].skb = NULL;
5826 pci_unmap_single(tp->pdev,
5827 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5828 skb_headlen(skb),
5829 PCI_DMA_TODEVICE);
5830 for (i = 0; i <= last; i++) {
5831 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5832 entry = NEXT_TX(entry);
5833
5834 pci_unmap_page(tp->pdev,
5835 dma_unmap_addr(&tnapi->tx_buffers[entry],
5836 mapping),
5837 frag->size, PCI_DMA_TODEVICE);
5838 }
5839
5840 dev_kfree_skb(skb);
5841 return NETDEV_TX_OK;
5842 }
5843
5844 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5845 struct net_device *);
5846
5847 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5848 * TSO header is greater than 80 bytes.
5849 */
5850 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5851 {
5852 struct sk_buff *segs, *nskb;
5853 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5854
5855 /* Estimate the number of fragments in the worst case */
5856 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5857 netif_stop_queue(tp->dev);
5858
5859 /* netif_tx_stop_queue() must be done before checking
5860 * checking tx index in tg3_tx_avail() below, because in
5861 * tg3_tx(), we update tx index before checking for
5862 * netif_tx_queue_stopped().
5863 */
5864 smp_mb();
5865 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5866 return NETDEV_TX_BUSY;
5867
5868 netif_wake_queue(tp->dev);
5869 }
5870
5871 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5872 if (IS_ERR(segs))
5873 goto tg3_tso_bug_end;
5874
5875 do {
5876 nskb = segs;
5877 segs = segs->next;
5878 nskb->next = NULL;
5879 tg3_start_xmit_dma_bug(nskb, tp->dev);
5880 } while (segs);
5881
5882 tg3_tso_bug_end:
5883 dev_kfree_skb(skb);
5884
5885 return NETDEV_TX_OK;
5886 }
5887
5888 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5889 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5890 */
5891 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5892 struct net_device *dev)
5893 {
5894 struct tg3 *tp = netdev_priv(dev);
5895 u32 len, entry, base_flags, mss;
5896 int would_hit_hwbug;
5897 dma_addr_t mapping;
5898 struct tg3_napi *tnapi;
5899 struct netdev_queue *txq;
5900 unsigned int i, last;
5901
5902 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5903 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5904 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5905 tnapi++;
5906
5907 /* We are running in BH disabled context with netif_tx_lock
5908 * and TX reclaim runs via tp->napi.poll inside of a software
5909 * interrupt. Furthermore, IRQ processing runs lockless so we have
5910 * no IRQ context deadlocks to worry about either. Rejoice!
5911 */
5912 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5913 if (!netif_tx_queue_stopped(txq)) {
5914 netif_tx_stop_queue(txq);
5915
5916 /* This is a hard error, log it. */
5917 netdev_err(dev,
5918 "BUG! Tx Ring full when queue awake!\n");
5919 }
5920 return NETDEV_TX_BUSY;
5921 }
5922
5923 entry = tnapi->tx_prod;
5924 base_flags = 0;
5925 if (skb->ip_summed == CHECKSUM_PARTIAL)
5926 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5927
5928 mss = skb_shinfo(skb)->gso_size;
5929 if (mss) {
5930 struct iphdr *iph;
5931 u32 tcp_opt_len, hdr_len;
5932
5933 if (skb_header_cloned(skb) &&
5934 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5935 dev_kfree_skb(skb);
5936 goto out_unlock;
5937 }
5938
5939 iph = ip_hdr(skb);
5940 tcp_opt_len = tcp_optlen(skb);
5941
5942 if (skb_is_gso_v6(skb)) {
5943 hdr_len = skb_headlen(skb) - ETH_HLEN;
5944 } else {
5945 u32 ip_tcp_len;
5946
5947 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5948 hdr_len = ip_tcp_len + tcp_opt_len;
5949
5950 iph->check = 0;
5951 iph->tot_len = htons(mss + hdr_len);
5952 }
5953
5954 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5955 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5956 return tg3_tso_bug(tp, skb);
5957
5958 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5959 TXD_FLAG_CPU_POST_DMA);
5960
5961 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5962 tcp_hdr(skb)->check = 0;
5963 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5964 } else
5965 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5966 iph->daddr, 0,
5967 IPPROTO_TCP,
5968 0);
5969
5970 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5971 mss |= (hdr_len & 0xc) << 12;
5972 if (hdr_len & 0x10)
5973 base_flags |= 0x00000010;
5974 base_flags |= (hdr_len & 0x3e0) << 5;
5975 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5976 mss |= hdr_len << 9;
5977 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5978 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5979 if (tcp_opt_len || iph->ihl > 5) {
5980 int tsflags;
5981
5982 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5983 mss |= (tsflags << 11);
5984 }
5985 } else {
5986 if (tcp_opt_len || iph->ihl > 5) {
5987 int tsflags;
5988
5989 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5990 base_flags |= tsflags << 12;
5991 }
5992 }
5993 }
5994 #if TG3_VLAN_TAG_USED
5995 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5996 base_flags |= (TXD_FLAG_VLAN |
5997 (vlan_tx_tag_get(skb) << 16));
5998 #endif
5999
6000 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
6001 !mss && skb->len > ETH_DATA_LEN)
6002 base_flags |= TXD_FLAG_JMB_PKT;
6003
6004 len = skb_headlen(skb);
6005
6006 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6007 if (pci_dma_mapping_error(tp->pdev, mapping)) {
6008 dev_kfree_skb(skb);
6009 goto out_unlock;
6010 }
6011
6012 tnapi->tx_buffers[entry].skb = skb;
6013 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6014
6015 would_hit_hwbug = 0;
6016
6017 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6018 would_hit_hwbug = 1;
6019
6020 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6021 tg3_4g_overflow_test(mapping, len))
6022 would_hit_hwbug = 1;
6023
6024 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6025 tg3_40bit_overflow_test(tp, mapping, len))
6026 would_hit_hwbug = 1;
6027
6028 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6029 would_hit_hwbug = 1;
6030
6031 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6032 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6033
6034 entry = NEXT_TX(entry);
6035
6036 /* Now loop through additional data fragments, and queue them. */
6037 if (skb_shinfo(skb)->nr_frags > 0) {
6038 last = skb_shinfo(skb)->nr_frags - 1;
6039 for (i = 0; i <= last; i++) {
6040 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6041
6042 len = frag->size;
6043 mapping = pci_map_page(tp->pdev,
6044 frag->page,
6045 frag->page_offset,
6046 len, PCI_DMA_TODEVICE);
6047
6048 tnapi->tx_buffers[entry].skb = NULL;
6049 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6050 mapping);
6051 if (pci_dma_mapping_error(tp->pdev, mapping))
6052 goto dma_error;
6053
6054 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6055 len <= 8)
6056 would_hit_hwbug = 1;
6057
6058 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6059 tg3_4g_overflow_test(mapping, len))
6060 would_hit_hwbug = 1;
6061
6062 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6063 tg3_40bit_overflow_test(tp, mapping, len))
6064 would_hit_hwbug = 1;
6065
6066 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6067 tg3_set_txd(tnapi, entry, mapping, len,
6068 base_flags, (i == last)|(mss << 1));
6069 else
6070 tg3_set_txd(tnapi, entry, mapping, len,
6071 base_flags, (i == last));
6072
6073 entry = NEXT_TX(entry);
6074 }
6075 }
6076
6077 if (would_hit_hwbug) {
6078 u32 last_plus_one = entry;
6079 u32 start;
6080
6081 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6082 start &= (TG3_TX_RING_SIZE - 1);
6083
6084 /* If the workaround fails due to memory/mapping
6085 * failure, silently drop this packet.
6086 */
6087 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6088 &start, base_flags, mss))
6089 goto out_unlock;
6090
6091 entry = start;
6092 }
6093
6094 /* Packets are ready, update Tx producer idx local and on card. */
6095 tw32_tx_mbox(tnapi->prodmbox, entry);
6096
6097 tnapi->tx_prod = entry;
6098 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6099 netif_tx_stop_queue(txq);
6100
6101 /* netif_tx_stop_queue() must be done before checking
6102 * checking tx index in tg3_tx_avail() below, because in
6103 * tg3_tx(), we update tx index before checking for
6104 * netif_tx_queue_stopped().
6105 */
6106 smp_mb();
6107 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6108 netif_tx_wake_queue(txq);
6109 }
6110
6111 out_unlock:
6112 mmiowb();
6113
6114 return NETDEV_TX_OK;
6115
6116 dma_error:
6117 last = i;
6118 entry = tnapi->tx_prod;
6119 tnapi->tx_buffers[entry].skb = NULL;
6120 pci_unmap_single(tp->pdev,
6121 dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6122 skb_headlen(skb),
6123 PCI_DMA_TODEVICE);
6124 for (i = 0; i <= last; i++) {
6125 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6126 entry = NEXT_TX(entry);
6127
6128 pci_unmap_page(tp->pdev,
6129 dma_unmap_addr(&tnapi->tx_buffers[entry],
6130 mapping),
6131 frag->size, PCI_DMA_TODEVICE);
6132 }
6133
6134 dev_kfree_skb(skb);
6135 return NETDEV_TX_OK;
6136 }
6137
6138 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6139 int new_mtu)
6140 {
6141 dev->mtu = new_mtu;
6142
6143 if (new_mtu > ETH_DATA_LEN) {
6144 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6145 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6146 ethtool_op_set_tso(dev, 0);
6147 } else {
6148 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6149 }
6150 } else {
6151 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6152 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6153 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6154 }
6155 }
6156
6157 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6158 {
6159 struct tg3 *tp = netdev_priv(dev);
6160 int err;
6161
6162 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6163 return -EINVAL;
6164
6165 if (!netif_running(dev)) {
6166 /* We'll just catch it later when the
6167 * device is up'd.
6168 */
6169 tg3_set_mtu(dev, tp, new_mtu);
6170 return 0;
6171 }
6172
6173 tg3_phy_stop(tp);
6174
6175 tg3_netif_stop(tp);
6176
6177 tg3_full_lock(tp, 1);
6178
6179 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6180
6181 tg3_set_mtu(dev, tp, new_mtu);
6182
6183 err = tg3_restart_hw(tp, 0);
6184
6185 if (!err)
6186 tg3_netif_start(tp);
6187
6188 tg3_full_unlock(tp);
6189
6190 if (!err)
6191 tg3_phy_start(tp);
6192
6193 return err;
6194 }
6195
6196 static void tg3_rx_prodring_free(struct tg3 *tp,
6197 struct tg3_rx_prodring_set *tpr)
6198 {
6199 int i;
6200
6201 if (tpr != &tp->napi[0].prodring) {
6202 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6203 i = (i + 1) & tp->rx_std_ring_mask)
6204 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6205 tp->rx_pkt_map_sz);
6206
6207 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6208 for (i = tpr->rx_jmb_cons_idx;
6209 i != tpr->rx_jmb_prod_idx;
6210 i = (i + 1) & tp->rx_jmb_ring_mask) {
6211 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6212 TG3_RX_JMB_MAP_SZ);
6213 }
6214 }
6215
6216 return;
6217 }
6218
6219 for (i = 0; i <= tp->rx_std_ring_mask; i++)
6220 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6221 tp->rx_pkt_map_sz);
6222
6223 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6224 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6225 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6226 TG3_RX_JMB_MAP_SZ);
6227 }
6228 }
6229
6230 /* Initialize rx rings for packet processing.
6231 *
6232 * The chip has been shut down and the driver detached from
6233 * the networking, so no interrupts or new tx packets will
6234 * end up in the driver. tp->{tx,}lock are held and thus
6235 * we may not sleep.
6236 */
6237 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6238 struct tg3_rx_prodring_set *tpr)
6239 {
6240 u32 i, rx_pkt_dma_sz;
6241
6242 tpr->rx_std_cons_idx = 0;
6243 tpr->rx_std_prod_idx = 0;
6244 tpr->rx_jmb_cons_idx = 0;
6245 tpr->rx_jmb_prod_idx = 0;
6246
6247 if (tpr != &tp->napi[0].prodring) {
6248 memset(&tpr->rx_std_buffers[0], 0,
6249 TG3_RX_STD_BUFF_RING_SIZE(tp));
6250 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6251 memset(&tpr->rx_jmb_buffers[0], 0,
6252 TG3_RX_JMB_BUFF_RING_SIZE(tp));
6253 goto done;
6254 }
6255
6256 /* Zero out all descriptors. */
6257 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6258
6259 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6260 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6261 tp->dev->mtu > ETH_DATA_LEN)
6262 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6263 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6264
6265 /* Initialize invariants of the rings, we only set this
6266 * stuff once. This works because the card does not
6267 * write into the rx buffer posting rings.
6268 */
6269 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6270 struct tg3_rx_buffer_desc *rxd;
6271
6272 rxd = &tpr->rx_std[i];
6273 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6274 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6275 rxd->opaque = (RXD_OPAQUE_RING_STD |
6276 (i << RXD_OPAQUE_INDEX_SHIFT));
6277 }
6278
6279 /* Now allocate fresh SKBs for each rx ring. */
6280 for (i = 0; i < tp->rx_pending; i++) {
6281 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6282 netdev_warn(tp->dev,
6283 "Using a smaller RX standard ring. Only "
6284 "%d out of %d buffers were allocated "
6285 "successfully\n", i, tp->rx_pending);
6286 if (i == 0)
6287 goto initfail;
6288 tp->rx_pending = i;
6289 break;
6290 }
6291 }
6292
6293 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6294 goto done;
6295
6296 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6297
6298 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6299 goto done;
6300
6301 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6302 struct tg3_rx_buffer_desc *rxd;
6303
6304 rxd = &tpr->rx_jmb[i].std;
6305 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6306 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6307 RXD_FLAG_JUMBO;
6308 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6309 (i << RXD_OPAQUE_INDEX_SHIFT));
6310 }
6311
6312 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6313 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6314 netdev_warn(tp->dev,
6315 "Using a smaller RX jumbo ring. Only %d "
6316 "out of %d buffers were allocated "
6317 "successfully\n", i, tp->rx_jumbo_pending);
6318 if (i == 0)
6319 goto initfail;
6320 tp->rx_jumbo_pending = i;
6321 break;
6322 }
6323 }
6324
6325 done:
6326 return 0;
6327
6328 initfail:
6329 tg3_rx_prodring_free(tp, tpr);
6330 return -ENOMEM;
6331 }
6332
6333 static void tg3_rx_prodring_fini(struct tg3 *tp,
6334 struct tg3_rx_prodring_set *tpr)
6335 {
6336 kfree(tpr->rx_std_buffers);
6337 tpr->rx_std_buffers = NULL;
6338 kfree(tpr->rx_jmb_buffers);
6339 tpr->rx_jmb_buffers = NULL;
6340 if (tpr->rx_std) {
6341 pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6342 tpr->rx_std, tpr->rx_std_mapping);
6343 tpr->rx_std = NULL;
6344 }
6345 if (tpr->rx_jmb) {
6346 pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
6347 tpr->rx_jmb, tpr->rx_jmb_mapping);
6348 tpr->rx_jmb = NULL;
6349 }
6350 }
6351
6352 static int tg3_rx_prodring_init(struct tg3 *tp,
6353 struct tg3_rx_prodring_set *tpr)
6354 {
6355 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6356 GFP_KERNEL);
6357 if (!tpr->rx_std_buffers)
6358 return -ENOMEM;
6359
6360 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6361 &tpr->rx_std_mapping);
6362 if (!tpr->rx_std)
6363 goto err_out;
6364
6365 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6366 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6367 GFP_KERNEL);
6368 if (!tpr->rx_jmb_buffers)
6369 goto err_out;
6370
6371 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6372 TG3_RX_JMB_RING_BYTES(tp),
6373 &tpr->rx_jmb_mapping);
6374 if (!tpr->rx_jmb)
6375 goto err_out;
6376 }
6377
6378 return 0;
6379
6380 err_out:
6381 tg3_rx_prodring_fini(tp, tpr);
6382 return -ENOMEM;
6383 }
6384
6385 /* Free up pending packets in all rx/tx rings.
6386 *
6387 * The chip has been shut down and the driver detached from
6388 * the networking, so no interrupts or new tx packets will
6389 * end up in the driver. tp->{tx,}lock is not held and we are not
6390 * in an interrupt context and thus may sleep.
6391 */
6392 static void tg3_free_rings(struct tg3 *tp)
6393 {
6394 int i, j;
6395
6396 for (j = 0; j < tp->irq_cnt; j++) {
6397 struct tg3_napi *tnapi = &tp->napi[j];
6398
6399 tg3_rx_prodring_free(tp, &tnapi->prodring);
6400
6401 if (!tnapi->tx_buffers)
6402 continue;
6403
6404 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6405 struct ring_info *txp;
6406 struct sk_buff *skb;
6407 unsigned int k;
6408
6409 txp = &tnapi->tx_buffers[i];
6410 skb = txp->skb;
6411
6412 if (skb == NULL) {
6413 i++;
6414 continue;
6415 }
6416
6417 pci_unmap_single(tp->pdev,
6418 dma_unmap_addr(txp, mapping),
6419 skb_headlen(skb),
6420 PCI_DMA_TODEVICE);
6421 txp->skb = NULL;
6422
6423 i++;
6424
6425 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6426 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6427 pci_unmap_page(tp->pdev,
6428 dma_unmap_addr(txp, mapping),
6429 skb_shinfo(skb)->frags[k].size,
6430 PCI_DMA_TODEVICE);
6431 i++;
6432 }
6433
6434 dev_kfree_skb_any(skb);
6435 }
6436 }
6437 }
6438
6439 /* Initialize tx/rx rings for packet processing.
6440 *
6441 * The chip has been shut down and the driver detached from
6442 * the networking, so no interrupts or new tx packets will
6443 * end up in the driver. tp->{tx,}lock are held and thus
6444 * we may not sleep.
6445 */
6446 static int tg3_init_rings(struct tg3 *tp)
6447 {
6448 int i;
6449
6450 /* Free up all the SKBs. */
6451 tg3_free_rings(tp);
6452
6453 for (i = 0; i < tp->irq_cnt; i++) {
6454 struct tg3_napi *tnapi = &tp->napi[i];
6455
6456 tnapi->last_tag = 0;
6457 tnapi->last_irq_tag = 0;
6458 tnapi->hw_status->status = 0;
6459 tnapi->hw_status->status_tag = 0;
6460 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6461
6462 tnapi->tx_prod = 0;
6463 tnapi->tx_cons = 0;
6464 if (tnapi->tx_ring)
6465 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6466
6467 tnapi->rx_rcb_ptr = 0;
6468 if (tnapi->rx_rcb)
6469 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6470
6471 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6472 tg3_free_rings(tp);
6473 return -ENOMEM;
6474 }
6475 }
6476
6477 return 0;
6478 }
6479
6480 /*
6481 * Must not be invoked with interrupt sources disabled and
6482 * the hardware shutdown down.
6483 */
6484 static void tg3_free_consistent(struct tg3 *tp)
6485 {
6486 int i;
6487
6488 for (i = 0; i < tp->irq_cnt; i++) {
6489 struct tg3_napi *tnapi = &tp->napi[i];
6490
6491 if (tnapi->tx_ring) {
6492 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6493 tnapi->tx_ring, tnapi->tx_desc_mapping);
6494 tnapi->tx_ring = NULL;
6495 }
6496
6497 kfree(tnapi->tx_buffers);
6498 tnapi->tx_buffers = NULL;
6499
6500 if (tnapi->rx_rcb) {
6501 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6502 tnapi->rx_rcb,
6503 tnapi->rx_rcb_mapping);
6504 tnapi->rx_rcb = NULL;
6505 }
6506
6507 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6508
6509 if (tnapi->hw_status) {
6510 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6511 tnapi->hw_status,
6512 tnapi->status_mapping);
6513 tnapi->hw_status = NULL;
6514 }
6515 }
6516
6517 if (tp->hw_stats) {
6518 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6519 tp->hw_stats, tp->stats_mapping);
6520 tp->hw_stats = NULL;
6521 }
6522 }
6523
6524 /*
6525 * Must not be invoked with interrupt sources disabled and
6526 * the hardware shutdown down. Can sleep.
6527 */
6528 static int tg3_alloc_consistent(struct tg3 *tp)
6529 {
6530 int i;
6531
6532 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6533 sizeof(struct tg3_hw_stats),
6534 &tp->stats_mapping);
6535 if (!tp->hw_stats)
6536 goto err_out;
6537
6538 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6539
6540 for (i = 0; i < tp->irq_cnt; i++) {
6541 struct tg3_napi *tnapi = &tp->napi[i];
6542 struct tg3_hw_status *sblk;
6543
6544 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6545 TG3_HW_STATUS_SIZE,
6546 &tnapi->status_mapping);
6547 if (!tnapi->hw_status)
6548 goto err_out;
6549
6550 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6551 sblk = tnapi->hw_status;
6552
6553 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6554 goto err_out;
6555
6556 /* If multivector TSS is enabled, vector 0 does not handle
6557 * tx interrupts. Don't allocate any resources for it.
6558 */
6559 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6560 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6561 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6562 TG3_TX_RING_SIZE,
6563 GFP_KERNEL);
6564 if (!tnapi->tx_buffers)
6565 goto err_out;
6566
6567 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6568 TG3_TX_RING_BYTES,
6569 &tnapi->tx_desc_mapping);
6570 if (!tnapi->tx_ring)
6571 goto err_out;
6572 }
6573
6574 /*
6575 * When RSS is enabled, the status block format changes
6576 * slightly. The "rx_jumbo_consumer", "reserved",
6577 * and "rx_mini_consumer" members get mapped to the
6578 * other three rx return ring producer indexes.
6579 */
6580 switch (i) {
6581 default:
6582 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6583 break;
6584 case 2:
6585 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6586 break;
6587 case 3:
6588 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6589 break;
6590 case 4:
6591 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6592 break;
6593 }
6594
6595 /*
6596 * If multivector RSS is enabled, vector 0 does not handle
6597 * rx or tx interrupts. Don't allocate any resources for it.
6598 */
6599 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6600 continue;
6601
6602 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6603 TG3_RX_RCB_RING_BYTES(tp),
6604 &tnapi->rx_rcb_mapping);
6605 if (!tnapi->rx_rcb)
6606 goto err_out;
6607
6608 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6609 }
6610
6611 return 0;
6612
6613 err_out:
6614 tg3_free_consistent(tp);
6615 return -ENOMEM;
6616 }
6617
6618 #define MAX_WAIT_CNT 1000
6619
6620 /* To stop a block, clear the enable bit and poll till it
6621 * clears. tp->lock is held.
6622 */
6623 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6624 {
6625 unsigned int i;
6626 u32 val;
6627
6628 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6629 switch (ofs) {
6630 case RCVLSC_MODE:
6631 case DMAC_MODE:
6632 case MBFREE_MODE:
6633 case BUFMGR_MODE:
6634 case MEMARB_MODE:
6635 /* We can't enable/disable these bits of the
6636 * 5705/5750, just say success.
6637 */
6638 return 0;
6639
6640 default:
6641 break;
6642 }
6643 }
6644
6645 val = tr32(ofs);
6646 val &= ~enable_bit;
6647 tw32_f(ofs, val);
6648
6649 for (i = 0; i < MAX_WAIT_CNT; i++) {
6650 udelay(100);
6651 val = tr32(ofs);
6652 if ((val & enable_bit) == 0)
6653 break;
6654 }
6655
6656 if (i == MAX_WAIT_CNT && !silent) {
6657 dev_err(&tp->pdev->dev,
6658 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6659 ofs, enable_bit);
6660 return -ENODEV;
6661 }
6662
6663 return 0;
6664 }
6665
6666 /* tp->lock is held. */
6667 static int tg3_abort_hw(struct tg3 *tp, int silent)
6668 {
6669 int i, err;
6670
6671 tg3_disable_ints(tp);
6672
6673 tp->rx_mode &= ~RX_MODE_ENABLE;
6674 tw32_f(MAC_RX_MODE, tp->rx_mode);
6675 udelay(10);
6676
6677 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6678 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6679 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6680 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6681 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6682 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6683
6684 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6685 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6686 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6687 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6688 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6689 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6690 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6691
6692 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6693 tw32_f(MAC_MODE, tp->mac_mode);
6694 udelay(40);
6695
6696 tp->tx_mode &= ~TX_MODE_ENABLE;
6697 tw32_f(MAC_TX_MODE, tp->tx_mode);
6698
6699 for (i = 0; i < MAX_WAIT_CNT; i++) {
6700 udelay(100);
6701 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6702 break;
6703 }
6704 if (i >= MAX_WAIT_CNT) {
6705 dev_err(&tp->pdev->dev,
6706 "%s timed out, TX_MODE_ENABLE will not clear "
6707 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6708 err |= -ENODEV;
6709 }
6710
6711 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6712 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6713 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6714
6715 tw32(FTQ_RESET, 0xffffffff);
6716 tw32(FTQ_RESET, 0x00000000);
6717
6718 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6719 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6720
6721 for (i = 0; i < tp->irq_cnt; i++) {
6722 struct tg3_napi *tnapi = &tp->napi[i];
6723 if (tnapi->hw_status)
6724 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6725 }
6726 if (tp->hw_stats)
6727 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6728
6729 return err;
6730 }
6731
6732 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6733 {
6734 int i;
6735 u32 apedata;
6736
6737 /* NCSI does not support APE events */
6738 if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6739 return;
6740
6741 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6742 if (apedata != APE_SEG_SIG_MAGIC)
6743 return;
6744
6745 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6746 if (!(apedata & APE_FW_STATUS_READY))
6747 return;
6748
6749 /* Wait for up to 1 millisecond for APE to service previous event. */
6750 for (i = 0; i < 10; i++) {
6751 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6752 return;
6753
6754 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6755
6756 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6757 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6758 event | APE_EVENT_STATUS_EVENT_PENDING);
6759
6760 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6761
6762 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6763 break;
6764
6765 udelay(100);
6766 }
6767
6768 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6769 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6770 }
6771
6772 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6773 {
6774 u32 event;
6775 u32 apedata;
6776
6777 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6778 return;
6779
6780 switch (kind) {
6781 case RESET_KIND_INIT:
6782 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6783 APE_HOST_SEG_SIG_MAGIC);
6784 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6785 APE_HOST_SEG_LEN_MAGIC);
6786 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6787 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6788 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6789 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6790 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6791 APE_HOST_BEHAV_NO_PHYLOCK);
6792 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6793 TG3_APE_HOST_DRVR_STATE_START);
6794
6795 event = APE_EVENT_STATUS_STATE_START;
6796 break;
6797 case RESET_KIND_SHUTDOWN:
6798 /* With the interface we are currently using,
6799 * APE does not track driver state. Wiping
6800 * out the HOST SEGMENT SIGNATURE forces
6801 * the APE to assume OS absent status.
6802 */
6803 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6804
6805 if (device_may_wakeup(&tp->pdev->dev) &&
6806 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6807 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6808 TG3_APE_HOST_WOL_SPEED_AUTO);
6809 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6810 } else
6811 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6812
6813 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6814
6815 event = APE_EVENT_STATUS_STATE_UNLOAD;
6816 break;
6817 case RESET_KIND_SUSPEND:
6818 event = APE_EVENT_STATUS_STATE_SUSPEND;
6819 break;
6820 default:
6821 return;
6822 }
6823
6824 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6825
6826 tg3_ape_send_event(tp, event);
6827 }
6828
6829 /* tp->lock is held. */
6830 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6831 {
6832 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6833 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6834
6835 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6836 switch (kind) {
6837 case RESET_KIND_INIT:
6838 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6839 DRV_STATE_START);
6840 break;
6841
6842 case RESET_KIND_SHUTDOWN:
6843 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6844 DRV_STATE_UNLOAD);
6845 break;
6846
6847 case RESET_KIND_SUSPEND:
6848 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6849 DRV_STATE_SUSPEND);
6850 break;
6851
6852 default:
6853 break;
6854 }
6855 }
6856
6857 if (kind == RESET_KIND_INIT ||
6858 kind == RESET_KIND_SUSPEND)
6859 tg3_ape_driver_state_change(tp, kind);
6860 }
6861
6862 /* tp->lock is held. */
6863 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6864 {
6865 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6866 switch (kind) {
6867 case RESET_KIND_INIT:
6868 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6869 DRV_STATE_START_DONE);
6870 break;
6871
6872 case RESET_KIND_SHUTDOWN:
6873 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6874 DRV_STATE_UNLOAD_DONE);
6875 break;
6876
6877 default:
6878 break;
6879 }
6880 }
6881
6882 if (kind == RESET_KIND_SHUTDOWN)
6883 tg3_ape_driver_state_change(tp, kind);
6884 }
6885
6886 /* tp->lock is held. */
6887 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6888 {
6889 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6890 switch (kind) {
6891 case RESET_KIND_INIT:
6892 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6893 DRV_STATE_START);
6894 break;
6895
6896 case RESET_KIND_SHUTDOWN:
6897 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6898 DRV_STATE_UNLOAD);
6899 break;
6900
6901 case RESET_KIND_SUSPEND:
6902 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6903 DRV_STATE_SUSPEND);
6904 break;
6905
6906 default:
6907 break;
6908 }
6909 }
6910 }
6911
6912 static int tg3_poll_fw(struct tg3 *tp)
6913 {
6914 int i;
6915 u32 val;
6916
6917 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6918 /* Wait up to 20ms for init done. */
6919 for (i = 0; i < 200; i++) {
6920 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6921 return 0;
6922 udelay(100);
6923 }
6924 return -ENODEV;
6925 }
6926
6927 /* Wait for firmware initialization to complete. */
6928 for (i = 0; i < 100000; i++) {
6929 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6930 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6931 break;
6932 udelay(10);
6933 }
6934
6935 /* Chip might not be fitted with firmware. Some Sun onboard
6936 * parts are configured like that. So don't signal the timeout
6937 * of the above loop as an error, but do report the lack of
6938 * running firmware once.
6939 */
6940 if (i >= 100000 &&
6941 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6942 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6943
6944 netdev_info(tp->dev, "No firmware running\n");
6945 }
6946
6947 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6948 /* The 57765 A0 needs a little more
6949 * time to do some important work.
6950 */
6951 mdelay(10);
6952 }
6953
6954 return 0;
6955 }
6956
6957 /* Save PCI command register before chip reset */
6958 static void tg3_save_pci_state(struct tg3 *tp)
6959 {
6960 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6961 }
6962
6963 /* Restore PCI state after chip reset */
6964 static void tg3_restore_pci_state(struct tg3 *tp)
6965 {
6966 u32 val;
6967
6968 /* Re-enable indirect register accesses. */
6969 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6970 tp->misc_host_ctrl);
6971
6972 /* Set MAX PCI retry to zero. */
6973 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6974 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6975 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6976 val |= PCISTATE_RETRY_SAME_DMA;
6977 /* Allow reads and writes to the APE register and memory space. */
6978 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6979 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6980 PCISTATE_ALLOW_APE_SHMEM_WR |
6981 PCISTATE_ALLOW_APE_PSPACE_WR;
6982 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6983
6984 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6985
6986 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6987 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6988 pcie_set_readrq(tp->pdev, 4096);
6989 else {
6990 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6991 tp->pci_cacheline_sz);
6992 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6993 tp->pci_lat_timer);
6994 }
6995 }
6996
6997 /* Make sure PCI-X relaxed ordering bit is clear. */
6998 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6999 u16 pcix_cmd;
7000
7001 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7002 &pcix_cmd);
7003 pcix_cmd &= ~PCI_X_CMD_ERO;
7004 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7005 pcix_cmd);
7006 }
7007
7008 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7009
7010 /* Chip reset on 5780 will reset MSI enable bit,
7011 * so need to restore it.
7012 */
7013 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7014 u16 ctrl;
7015
7016 pci_read_config_word(tp->pdev,
7017 tp->msi_cap + PCI_MSI_FLAGS,
7018 &ctrl);
7019 pci_write_config_word(tp->pdev,
7020 tp->msi_cap + PCI_MSI_FLAGS,
7021 ctrl | PCI_MSI_FLAGS_ENABLE);
7022 val = tr32(MSGINT_MODE);
7023 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7024 }
7025 }
7026 }
7027
7028 static void tg3_stop_fw(struct tg3 *);
7029
7030 /* tp->lock is held. */
7031 static int tg3_chip_reset(struct tg3 *tp)
7032 {
7033 u32 val;
7034 void (*write_op)(struct tg3 *, u32, u32);
7035 int i, err;
7036
7037 tg3_nvram_lock(tp);
7038
7039 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7040
7041 /* No matching tg3_nvram_unlock() after this because
7042 * chip reset below will undo the nvram lock.
7043 */
7044 tp->nvram_lock_cnt = 0;
7045
7046 /* GRC_MISC_CFG core clock reset will clear the memory
7047 * enable bit in PCI register 4 and the MSI enable bit
7048 * on some chips, so we save relevant registers here.
7049 */
7050 tg3_save_pci_state(tp);
7051
7052 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7053 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7054 tw32(GRC_FASTBOOT_PC, 0);
7055
7056 /*
7057 * We must avoid the readl() that normally takes place.
7058 * It locks machines, causes machine checks, and other
7059 * fun things. So, temporarily disable the 5701
7060 * hardware workaround, while we do the reset.
7061 */
7062 write_op = tp->write32;
7063 if (write_op == tg3_write_flush_reg32)
7064 tp->write32 = tg3_write32;
7065
7066 /* Prevent the irq handler from reading or writing PCI registers
7067 * during chip reset when the memory enable bit in the PCI command
7068 * register may be cleared. The chip does not generate interrupt
7069 * at this time, but the irq handler may still be called due to irq
7070 * sharing or irqpoll.
7071 */
7072 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7073 for (i = 0; i < tp->irq_cnt; i++) {
7074 struct tg3_napi *tnapi = &tp->napi[i];
7075 if (tnapi->hw_status) {
7076 tnapi->hw_status->status = 0;
7077 tnapi->hw_status->status_tag = 0;
7078 }
7079 tnapi->last_tag = 0;
7080 tnapi->last_irq_tag = 0;
7081 }
7082 smp_mb();
7083
7084 for (i = 0; i < tp->irq_cnt; i++)
7085 synchronize_irq(tp->napi[i].irq_vec);
7086
7087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7088 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7089 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7090 }
7091
7092 /* do the reset */
7093 val = GRC_MISC_CFG_CORECLK_RESET;
7094
7095 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7096 /* Force PCIe 1.0a mode */
7097 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7098 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7099 tr32(TG3_PCIE_PHY_TSTCTL) ==
7100 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7101 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7102
7103 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7104 tw32(GRC_MISC_CFG, (1 << 29));
7105 val |= (1 << 29);
7106 }
7107 }
7108
7109 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7110 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7111 tw32(GRC_VCPU_EXT_CTRL,
7112 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7113 }
7114
7115 /* Manage gphy power for all CPMU absent PCIe devices. */
7116 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7117 !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7118 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7119
7120 tw32(GRC_MISC_CFG, val);
7121
7122 /* restore 5701 hardware bug workaround write method */
7123 tp->write32 = write_op;
7124
7125 /* Unfortunately, we have to delay before the PCI read back.
7126 * Some 575X chips even will not respond to a PCI cfg access
7127 * when the reset command is given to the chip.
7128 *
7129 * How do these hardware designers expect things to work
7130 * properly if the PCI write is posted for a long period
7131 * of time? It is always necessary to have some method by
7132 * which a register read back can occur to push the write
7133 * out which does the reset.
7134 *
7135 * For most tg3 variants the trick below was working.
7136 * Ho hum...
7137 */
7138 udelay(120);
7139
7140 /* Flush PCI posted writes. The normal MMIO registers
7141 * are inaccessible at this time so this is the only
7142 * way to make this reliably (actually, this is no longer
7143 * the case, see above). I tried to use indirect
7144 * register read/write but this upset some 5701 variants.
7145 */
7146 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7147
7148 udelay(120);
7149
7150 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7151 u16 val16;
7152
7153 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7154 int i;
7155 u32 cfg_val;
7156
7157 /* Wait for link training to complete. */
7158 for (i = 0; i < 5000; i++)
7159 udelay(100);
7160
7161 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7162 pci_write_config_dword(tp->pdev, 0xc4,
7163 cfg_val | (1 << 15));
7164 }
7165
7166 /* Clear the "no snoop" and "relaxed ordering" bits. */
7167 pci_read_config_word(tp->pdev,
7168 tp->pcie_cap + PCI_EXP_DEVCTL,
7169 &val16);
7170 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7171 PCI_EXP_DEVCTL_NOSNOOP_EN);
7172 /*
7173 * Older PCIe devices only support the 128 byte
7174 * MPS setting. Enforce the restriction.
7175 */
7176 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7177 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7178 pci_write_config_word(tp->pdev,
7179 tp->pcie_cap + PCI_EXP_DEVCTL,
7180 val16);
7181
7182 pcie_set_readrq(tp->pdev, 4096);
7183
7184 /* Clear error status */
7185 pci_write_config_word(tp->pdev,
7186 tp->pcie_cap + PCI_EXP_DEVSTA,
7187 PCI_EXP_DEVSTA_CED |
7188 PCI_EXP_DEVSTA_NFED |
7189 PCI_EXP_DEVSTA_FED |
7190 PCI_EXP_DEVSTA_URD);
7191 }
7192
7193 tg3_restore_pci_state(tp);
7194
7195 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7196
7197 val = 0;
7198 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7199 val = tr32(MEMARB_MODE);
7200 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7201
7202 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7203 tg3_stop_fw(tp);
7204 tw32(0x5000, 0x400);
7205 }
7206
7207 tw32(GRC_MODE, tp->grc_mode);
7208
7209 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7210 val = tr32(0xc4);
7211
7212 tw32(0xc4, val | (1 << 15));
7213 }
7214
7215 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7216 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7217 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7218 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7219 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7220 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7221 }
7222
7223 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7224 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7225 tw32_f(MAC_MODE, tp->mac_mode);
7226 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7227 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7228 tw32_f(MAC_MODE, tp->mac_mode);
7229 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7230 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7231 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7232 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7233 tw32_f(MAC_MODE, tp->mac_mode);
7234 } else
7235 tw32_f(MAC_MODE, 0);
7236 udelay(40);
7237
7238 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7239
7240 err = tg3_poll_fw(tp);
7241 if (err)
7242 return err;
7243
7244 tg3_mdio_start(tp);
7245
7246 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7247 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7248 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7249 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7250 val = tr32(0x7c00);
7251
7252 tw32(0x7c00, val | (1 << 25));
7253 }
7254
7255 /* Reprobe ASF enable state. */
7256 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7257 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7258 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7259 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7260 u32 nic_cfg;
7261
7262 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7263 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7264 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7265 tp->last_event_jiffies = jiffies;
7266 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7267 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7268 }
7269 }
7270
7271 return 0;
7272 }
7273
7274 /* tp->lock is held. */
7275 static void tg3_stop_fw(struct tg3 *tp)
7276 {
7277 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7278 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7279 /* Wait for RX cpu to ACK the previous event. */
7280 tg3_wait_for_event_ack(tp);
7281
7282 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7283
7284 tg3_generate_fw_event(tp);
7285
7286 /* Wait for RX cpu to ACK this event. */
7287 tg3_wait_for_event_ack(tp);
7288 }
7289 }
7290
7291 /* tp->lock is held. */
7292 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7293 {
7294 int err;
7295
7296 tg3_stop_fw(tp);
7297
7298 tg3_write_sig_pre_reset(tp, kind);
7299
7300 tg3_abort_hw(tp, silent);
7301 err = tg3_chip_reset(tp);
7302
7303 __tg3_set_mac_addr(tp, 0);
7304
7305 tg3_write_sig_legacy(tp, kind);
7306 tg3_write_sig_post_reset(tp, kind);
7307
7308 if (err)
7309 return err;
7310
7311 return 0;
7312 }
7313
7314 #define RX_CPU_SCRATCH_BASE 0x30000
7315 #define RX_CPU_SCRATCH_SIZE 0x04000
7316 #define TX_CPU_SCRATCH_BASE 0x34000
7317 #define TX_CPU_SCRATCH_SIZE 0x04000
7318
7319 /* tp->lock is held. */
7320 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7321 {
7322 int i;
7323
7324 BUG_ON(offset == TX_CPU_BASE &&
7325 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7326
7327 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7328 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7329
7330 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7331 return 0;
7332 }
7333 if (offset == RX_CPU_BASE) {
7334 for (i = 0; i < 10000; i++) {
7335 tw32(offset + CPU_STATE, 0xffffffff);
7336 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7337 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7338 break;
7339 }
7340
7341 tw32(offset + CPU_STATE, 0xffffffff);
7342 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7343 udelay(10);
7344 } else {
7345 for (i = 0; i < 10000; i++) {
7346 tw32(offset + CPU_STATE, 0xffffffff);
7347 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7348 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7349 break;
7350 }
7351 }
7352
7353 if (i >= 10000) {
7354 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7355 __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7356 return -ENODEV;
7357 }
7358
7359 /* Clear firmware's nvram arbitration. */
7360 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7361 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7362 return 0;
7363 }
7364
7365 struct fw_info {
7366 unsigned int fw_base;
7367 unsigned int fw_len;
7368 const __be32 *fw_data;
7369 };
7370
7371 /* tp->lock is held. */
7372 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7373 int cpu_scratch_size, struct fw_info *info)
7374 {
7375 int err, lock_err, i;
7376 void (*write_op)(struct tg3 *, u32, u32);
7377
7378 if (cpu_base == TX_CPU_BASE &&
7379 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7380 netdev_err(tp->dev,
7381 "%s: Trying to load TX cpu firmware which is 5705\n",
7382 __func__);
7383 return -EINVAL;
7384 }
7385
7386 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7387 write_op = tg3_write_mem;
7388 else
7389 write_op = tg3_write_indirect_reg32;
7390
7391 /* It is possible that bootcode is still loading at this point.
7392 * Get the nvram lock first before halting the cpu.
7393 */
7394 lock_err = tg3_nvram_lock(tp);
7395 err = tg3_halt_cpu(tp, cpu_base);
7396 if (!lock_err)
7397 tg3_nvram_unlock(tp);
7398 if (err)
7399 goto out;
7400
7401 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7402 write_op(tp, cpu_scratch_base + i, 0);
7403 tw32(cpu_base + CPU_STATE, 0xffffffff);
7404 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7405 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7406 write_op(tp, (cpu_scratch_base +
7407 (info->fw_base & 0xffff) +
7408 (i * sizeof(u32))),
7409 be32_to_cpu(info->fw_data[i]));
7410
7411 err = 0;
7412
7413 out:
7414 return err;
7415 }
7416
7417 /* tp->lock is held. */
7418 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7419 {
7420 struct fw_info info;
7421 const __be32 *fw_data;
7422 int err, i;
7423
7424 fw_data = (void *)tp->fw->data;
7425
7426 /* Firmware blob starts with version numbers, followed by
7427 start address and length. We are setting complete length.
7428 length = end_address_of_bss - start_address_of_text.
7429 Remainder is the blob to be loaded contiguously
7430 from start address. */
7431
7432 info.fw_base = be32_to_cpu(fw_data[1]);
7433 info.fw_len = tp->fw->size - 12;
7434 info.fw_data = &fw_data[3];
7435
7436 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7437 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7438 &info);
7439 if (err)
7440 return err;
7441
7442 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7443 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7444 &info);
7445 if (err)
7446 return err;
7447
7448 /* Now startup only the RX cpu. */
7449 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7450 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7451
7452 for (i = 0; i < 5; i++) {
7453 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7454 break;
7455 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7456 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7457 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7458 udelay(1000);
7459 }
7460 if (i >= 5) {
7461 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7462 "should be %08x\n", __func__,
7463 tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7464 return -ENODEV;
7465 }
7466 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7467 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7468
7469 return 0;
7470 }
7471
7472 /* 5705 needs a special version of the TSO firmware. */
7473
7474 /* tp->lock is held. */
7475 static int tg3_load_tso_firmware(struct tg3 *tp)
7476 {
7477 struct fw_info info;
7478 const __be32 *fw_data;
7479 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7480 int err, i;
7481
7482 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7483 return 0;
7484
7485 fw_data = (void *)tp->fw->data;
7486
7487 /* Firmware blob starts with version numbers, followed by
7488 start address and length. We are setting complete length.
7489 length = end_address_of_bss - start_address_of_text.
7490 Remainder is the blob to be loaded contiguously
7491 from start address. */
7492
7493 info.fw_base = be32_to_cpu(fw_data[1]);
7494 cpu_scratch_size = tp->fw_len;
7495 info.fw_len = tp->fw->size - 12;
7496 info.fw_data = &fw_data[3];
7497
7498 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7499 cpu_base = RX_CPU_BASE;
7500 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7501 } else {
7502 cpu_base = TX_CPU_BASE;
7503 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7504 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7505 }
7506
7507 err = tg3_load_firmware_cpu(tp, cpu_base,
7508 cpu_scratch_base, cpu_scratch_size,
7509 &info);
7510 if (err)
7511 return err;
7512
7513 /* Now startup the cpu. */
7514 tw32(cpu_base + CPU_STATE, 0xffffffff);
7515 tw32_f(cpu_base + CPU_PC, info.fw_base);
7516
7517 for (i = 0; i < 5; i++) {
7518 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7519 break;
7520 tw32(cpu_base + CPU_STATE, 0xffffffff);
7521 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7522 tw32_f(cpu_base + CPU_PC, info.fw_base);
7523 udelay(1000);
7524 }
7525 if (i >= 5) {
7526 netdev_err(tp->dev,
7527 "%s fails to set CPU PC, is %08x should be %08x\n",
7528 __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7529 return -ENODEV;
7530 }
7531 tw32(cpu_base + CPU_STATE, 0xffffffff);
7532 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7533 return 0;
7534 }
7535
7536
7537 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7538 {
7539 struct tg3 *tp = netdev_priv(dev);
7540 struct sockaddr *addr = p;
7541 int err = 0, skip_mac_1 = 0;
7542
7543 if (!is_valid_ether_addr(addr->sa_data))
7544 return -EINVAL;
7545
7546 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7547
7548 if (!netif_running(dev))
7549 return 0;
7550
7551 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7552 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7553
7554 addr0_high = tr32(MAC_ADDR_0_HIGH);
7555 addr0_low = tr32(MAC_ADDR_0_LOW);
7556 addr1_high = tr32(MAC_ADDR_1_HIGH);
7557 addr1_low = tr32(MAC_ADDR_1_LOW);
7558
7559 /* Skip MAC addr 1 if ASF is using it. */
7560 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7561 !(addr1_high == 0 && addr1_low == 0))
7562 skip_mac_1 = 1;
7563 }
7564 spin_lock_bh(&tp->lock);
7565 __tg3_set_mac_addr(tp, skip_mac_1);
7566 spin_unlock_bh(&tp->lock);
7567
7568 return err;
7569 }
7570
7571 /* tp->lock is held. */
7572 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7573 dma_addr_t mapping, u32 maxlen_flags,
7574 u32 nic_addr)
7575 {
7576 tg3_write_mem(tp,
7577 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7578 ((u64) mapping >> 32));
7579 tg3_write_mem(tp,
7580 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7581 ((u64) mapping & 0xffffffff));
7582 tg3_write_mem(tp,
7583 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7584 maxlen_flags);
7585
7586 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7587 tg3_write_mem(tp,
7588 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7589 nic_addr);
7590 }
7591
7592 static void __tg3_set_rx_mode(struct net_device *);
7593 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7594 {
7595 int i;
7596
7597 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7598 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7599 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7600 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7601 } else {
7602 tw32(HOSTCC_TXCOL_TICKS, 0);
7603 tw32(HOSTCC_TXMAX_FRAMES, 0);
7604 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7605 }
7606
7607 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7608 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7609 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7610 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7611 } else {
7612 tw32(HOSTCC_RXCOL_TICKS, 0);
7613 tw32(HOSTCC_RXMAX_FRAMES, 0);
7614 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7615 }
7616
7617 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7618 u32 val = ec->stats_block_coalesce_usecs;
7619
7620 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7621 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7622
7623 if (!netif_carrier_ok(tp->dev))
7624 val = 0;
7625
7626 tw32(HOSTCC_STAT_COAL_TICKS, val);
7627 }
7628
7629 for (i = 0; i < tp->irq_cnt - 1; i++) {
7630 u32 reg;
7631
7632 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7633 tw32(reg, ec->rx_coalesce_usecs);
7634 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7635 tw32(reg, ec->rx_max_coalesced_frames);
7636 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7637 tw32(reg, ec->rx_max_coalesced_frames_irq);
7638
7639 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7640 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7641 tw32(reg, ec->tx_coalesce_usecs);
7642 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7643 tw32(reg, ec->tx_max_coalesced_frames);
7644 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7645 tw32(reg, ec->tx_max_coalesced_frames_irq);
7646 }
7647 }
7648
7649 for (; i < tp->irq_max - 1; i++) {
7650 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7651 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7652 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7653
7654 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7655 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7656 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7657 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7658 }
7659 }
7660 }
7661
7662 /* tp->lock is held. */
7663 static void tg3_rings_reset(struct tg3 *tp)
7664 {
7665 int i;
7666 u32 stblk, txrcb, rxrcb, limit;
7667 struct tg3_napi *tnapi = &tp->napi[0];
7668
7669 /* Disable all transmit rings but the first. */
7670 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7671 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7672 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7673 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7674 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7675 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7676 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7677 else
7678 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7679
7680 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7681 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7682 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7683 BDINFO_FLAGS_DISABLED);
7684
7685
7686 /* Disable all receive return rings but the first. */
7687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7688 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7689 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7690 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7691 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7692 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7693 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7694 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7695 else
7696 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7697
7698 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7699 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7700 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7701 BDINFO_FLAGS_DISABLED);
7702
7703 /* Disable interrupts */
7704 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7705
7706 /* Zero mailbox registers. */
7707 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7708 for (i = 1; i < tp->irq_max; i++) {
7709 tp->napi[i].tx_prod = 0;
7710 tp->napi[i].tx_cons = 0;
7711 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7712 tw32_mailbox(tp->napi[i].prodmbox, 0);
7713 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7714 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7715 }
7716 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7717 tw32_mailbox(tp->napi[0].prodmbox, 0);
7718 } else {
7719 tp->napi[0].tx_prod = 0;
7720 tp->napi[0].tx_cons = 0;
7721 tw32_mailbox(tp->napi[0].prodmbox, 0);
7722 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7723 }
7724
7725 /* Make sure the NIC-based send BD rings are disabled. */
7726 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7727 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7728 for (i = 0; i < 16; i++)
7729 tw32_tx_mbox(mbox + i * 8, 0);
7730 }
7731
7732 txrcb = NIC_SRAM_SEND_RCB;
7733 rxrcb = NIC_SRAM_RCV_RET_RCB;
7734
7735 /* Clear status block in ram. */
7736 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7737
7738 /* Set status block DMA address */
7739 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7740 ((u64) tnapi->status_mapping >> 32));
7741 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7742 ((u64) tnapi->status_mapping & 0xffffffff));
7743
7744 if (tnapi->tx_ring) {
7745 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7746 (TG3_TX_RING_SIZE <<
7747 BDINFO_FLAGS_MAXLEN_SHIFT),
7748 NIC_SRAM_TX_BUFFER_DESC);
7749 txrcb += TG3_BDINFO_SIZE;
7750 }
7751
7752 if (tnapi->rx_rcb) {
7753 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7754 (tp->rx_ret_ring_mask + 1) <<
7755 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7756 rxrcb += TG3_BDINFO_SIZE;
7757 }
7758
7759 stblk = HOSTCC_STATBLCK_RING1;
7760
7761 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7762 u64 mapping = (u64)tnapi->status_mapping;
7763 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7764 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7765
7766 /* Clear status block in ram. */
7767 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7768
7769 if (tnapi->tx_ring) {
7770 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7771 (TG3_TX_RING_SIZE <<
7772 BDINFO_FLAGS_MAXLEN_SHIFT),
7773 NIC_SRAM_TX_BUFFER_DESC);
7774 txrcb += TG3_BDINFO_SIZE;
7775 }
7776
7777 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7778 ((tp->rx_ret_ring_mask + 1) <<
7779 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7780
7781 stblk += 8;
7782 rxrcb += TG3_BDINFO_SIZE;
7783 }
7784 }
7785
7786 /* tp->lock is held. */
7787 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7788 {
7789 u32 val, rdmac_mode;
7790 int i, err, limit;
7791 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7792
7793 tg3_disable_ints(tp);
7794
7795 tg3_stop_fw(tp);
7796
7797 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7798
7799 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7800 tg3_abort_hw(tp, 1);
7801
7802 if (reset_phy)
7803 tg3_phy_reset(tp);
7804
7805 err = tg3_chip_reset(tp);
7806 if (err)
7807 return err;
7808
7809 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7810
7811 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7812 val = tr32(TG3_CPMU_CTRL);
7813 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7814 tw32(TG3_CPMU_CTRL, val);
7815
7816 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7817 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7818 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7819 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7820
7821 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7822 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7823 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7824 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7825
7826 val = tr32(TG3_CPMU_HST_ACC);
7827 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7828 val |= CPMU_HST_ACC_MACCLK_6_25;
7829 tw32(TG3_CPMU_HST_ACC, val);
7830 }
7831
7832 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7833 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7834 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7835 PCIE_PWR_MGMT_L1_THRESH_4MS;
7836 tw32(PCIE_PWR_MGMT_THRESH, val);
7837
7838 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7839 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7840
7841 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7842
7843 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7844 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7845 }
7846
7847 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7848 u32 grc_mode = tr32(GRC_MODE);
7849
7850 /* Access the lower 1K of PL PCIE block registers. */
7851 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7852 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7853
7854 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7855 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7856 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7857
7858 tw32(GRC_MODE, grc_mode);
7859 }
7860
7861 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7862 u32 grc_mode = tr32(GRC_MODE);
7863
7864 /* Access the lower 1K of PL PCIE block registers. */
7865 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7866 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7867
7868 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7869 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7870 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7871
7872 tw32(GRC_MODE, grc_mode);
7873
7874 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7875 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7876 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7877 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7878 }
7879
7880 /* Enable MAC control of LPI */
7881 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7882 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7883 TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7884 TG3_CPMU_EEE_LNKIDL_UART_IDL);
7885
7886 tw32_f(TG3_CPMU_EEE_CTRL,
7887 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7888
7889 tw32_f(TG3_CPMU_EEE_MODE,
7890 TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7891 TG3_CPMU_EEEMD_LPI_IN_TX |
7892 TG3_CPMU_EEEMD_LPI_IN_RX |
7893 TG3_CPMU_EEEMD_EEE_ENABLE);
7894 }
7895
7896 /* This works around an issue with Athlon chipsets on
7897 * B3 tigon3 silicon. This bit has no effect on any
7898 * other revision. But do not set this on PCI Express
7899 * chips and don't even touch the clocks if the CPMU is present.
7900 */
7901 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7902 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7903 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7904 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7905 }
7906
7907 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7908 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7909 val = tr32(TG3PCI_PCISTATE);
7910 val |= PCISTATE_RETRY_SAME_DMA;
7911 tw32(TG3PCI_PCISTATE, val);
7912 }
7913
7914 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7915 /* Allow reads and writes to the
7916 * APE register and memory space.
7917 */
7918 val = tr32(TG3PCI_PCISTATE);
7919 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7920 PCISTATE_ALLOW_APE_SHMEM_WR |
7921 PCISTATE_ALLOW_APE_PSPACE_WR;
7922 tw32(TG3PCI_PCISTATE, val);
7923 }
7924
7925 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7926 /* Enable some hw fixes. */
7927 val = tr32(TG3PCI_MSI_DATA);
7928 val |= (1 << 26) | (1 << 28) | (1 << 29);
7929 tw32(TG3PCI_MSI_DATA, val);
7930 }
7931
7932 /* Descriptor ring init may make accesses to the
7933 * NIC SRAM area to setup the TX descriptors, so we
7934 * can only do this after the hardware has been
7935 * successfully reset.
7936 */
7937 err = tg3_init_rings(tp);
7938 if (err)
7939 return err;
7940
7941 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7942 val = tr32(TG3PCI_DMA_RW_CTRL) &
7943 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7944 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7945 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7946 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7947 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7948 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7949 /* This value is determined during the probe time DMA
7950 * engine test, tg3_test_dma.
7951 */
7952 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7953 }
7954
7955 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7956 GRC_MODE_4X_NIC_SEND_RINGS |
7957 GRC_MODE_NO_TX_PHDR_CSUM |
7958 GRC_MODE_NO_RX_PHDR_CSUM);
7959 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7960
7961 /* Pseudo-header checksum is done by hardware logic and not
7962 * the offload processers, so make the chip do the pseudo-
7963 * header checksums on receive. For transmit it is more
7964 * convenient to do the pseudo-header checksum in software
7965 * as Linux does that on transmit for us in all cases.
7966 */
7967 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7968
7969 tw32(GRC_MODE,
7970 tp->grc_mode |
7971 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7972
7973 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7974 val = tr32(GRC_MISC_CFG);
7975 val &= ~0xff;
7976 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7977 tw32(GRC_MISC_CFG, val);
7978
7979 /* Initialize MBUF/DESC pool. */
7980 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7981 /* Do nothing. */
7982 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7983 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7984 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7985 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7986 else
7987 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7988 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7989 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7990 } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7991 int fw_len;
7992
7993 fw_len = tp->fw_len;
7994 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7995 tw32(BUFMGR_MB_POOL_ADDR,
7996 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7997 tw32(BUFMGR_MB_POOL_SIZE,
7998 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7999 }
8000
8001 if (tp->dev->mtu <= ETH_DATA_LEN) {
8002 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8003 tp->bufmgr_config.mbuf_read_dma_low_water);
8004 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8005 tp->bufmgr_config.mbuf_mac_rx_low_water);
8006 tw32(BUFMGR_MB_HIGH_WATER,
8007 tp->bufmgr_config.mbuf_high_water);
8008 } else {
8009 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8010 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8011 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8012 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8013 tw32(BUFMGR_MB_HIGH_WATER,
8014 tp->bufmgr_config.mbuf_high_water_jumbo);
8015 }
8016 tw32(BUFMGR_DMA_LOW_WATER,
8017 tp->bufmgr_config.dma_low_water);
8018 tw32(BUFMGR_DMA_HIGH_WATER,
8019 tp->bufmgr_config.dma_high_water);
8020
8021 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8022 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8023 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8024 tw32(BUFMGR_MODE, val);
8025 for (i = 0; i < 2000; i++) {
8026 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8027 break;
8028 udelay(10);
8029 }
8030 if (i >= 2000) {
8031 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8032 return -ENODEV;
8033 }
8034
8035 /* Setup replenish threshold. */
8036 val = tp->rx_pending / 8;
8037 if (val == 0)
8038 val = 1;
8039 else if (val > tp->rx_std_max_post)
8040 val = tp->rx_std_max_post;
8041 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8042 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8043 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8044
8045 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8046 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8047 }
8048
8049 tw32(RCVBDI_STD_THRESH, val);
8050
8051 /* Initialize TG3_BDINFO's at:
8052 * RCVDBDI_STD_BD: standard eth size rx ring
8053 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
8054 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
8055 *
8056 * like so:
8057 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
8058 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
8059 * ring attribute flags
8060 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
8061 *
8062 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8063 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8064 *
8065 * The size of each ring is fixed in the firmware, but the location is
8066 * configurable.
8067 */
8068 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8069 ((u64) tpr->rx_std_mapping >> 32));
8070 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8071 ((u64) tpr->rx_std_mapping & 0xffffffff));
8072 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8073 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8074 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8075 NIC_SRAM_RX_BUFFER_DESC);
8076
8077 /* Disable the mini ring */
8078 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8079 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8080 BDINFO_FLAGS_DISABLED);
8081
8082 /* Program the jumbo buffer descriptor ring control
8083 * blocks on those devices that have them.
8084 */
8085 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8086 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8087 /* Setup replenish threshold. */
8088 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8089
8090 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8091 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8092 ((u64) tpr->rx_jmb_mapping >> 32));
8093 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8094 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8095 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8096 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8097 BDINFO_FLAGS_USE_EXT_RECV);
8098 if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8099 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8100 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8101 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8102 } else {
8103 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8104 BDINFO_FLAGS_DISABLED);
8105 }
8106
8107 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8108 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8109 val = RX_STD_MAX_SIZE_5705;
8110 else
8111 val = RX_STD_MAX_SIZE_5717;
8112 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8113 val |= (TG3_RX_STD_DMA_SZ << 2);
8114 } else
8115 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8116 } else
8117 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8118
8119 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8120
8121 tpr->rx_std_prod_idx = tp->rx_pending;
8122 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8123
8124 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8125 tp->rx_jumbo_pending : 0;
8126 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8127
8128 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8129 tw32(STD_REPLENISH_LWM, 32);
8130 tw32(JMB_REPLENISH_LWM, 16);
8131 }
8132
8133 tg3_rings_reset(tp);
8134
8135 /* Initialize MAC address and backoff seed. */
8136 __tg3_set_mac_addr(tp, 0);
8137
8138 /* MTU + ethernet header + FCS + optional VLAN tag */
8139 tw32(MAC_RX_MTU_SIZE,
8140 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8141
8142 /* The slot time is changed by tg3_setup_phy if we
8143 * run at gigabit with half duplex.
8144 */
8145 tw32(MAC_TX_LENGTHS,
8146 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8147 (6 << TX_LENGTHS_IPG_SHIFT) |
8148 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8149
8150 /* Receive rules. */
8151 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8152 tw32(RCVLPC_CONFIG, 0x0181);
8153
8154 /* Calculate RDMAC_MODE setting early, we need it to determine
8155 * the RCVLPC_STATE_ENABLE mask.
8156 */
8157 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8158 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8159 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8160 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8161 RDMAC_MODE_LNGREAD_ENAB);
8162
8163 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8164 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8165 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8166
8167 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8168 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8169 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8170 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8171 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8172 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8173
8174 /* If statement applies to 5705 and 5750 PCI devices only */
8175 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8176 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8177 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8178 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8179 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8180 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8181 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8182 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8183 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8184 }
8185 }
8186
8187 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8188 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8189
8190 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8191 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8192
8193 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8194 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8195 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8196 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8197
8198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8199 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8200 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8201 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8202 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8203 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8204 tw32(TG3_RDMA_RSRVCTRL_REG,
8205 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8206 }
8207
8208 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8209 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8210 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8211 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8212 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8213 }
8214
8215 /* Receive/send statistics. */
8216 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8217 val = tr32(RCVLPC_STATS_ENABLE);
8218 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8219 tw32(RCVLPC_STATS_ENABLE, val);
8220 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8221 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8222 val = tr32(RCVLPC_STATS_ENABLE);
8223 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8224 tw32(RCVLPC_STATS_ENABLE, val);
8225 } else {
8226 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8227 }
8228 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8229 tw32(SNDDATAI_STATSENAB, 0xffffff);
8230 tw32(SNDDATAI_STATSCTRL,
8231 (SNDDATAI_SCTRL_ENABLE |
8232 SNDDATAI_SCTRL_FASTUPD));
8233
8234 /* Setup host coalescing engine. */
8235 tw32(HOSTCC_MODE, 0);
8236 for (i = 0; i < 2000; i++) {
8237 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8238 break;
8239 udelay(10);
8240 }
8241
8242 __tg3_set_coalesce(tp, &tp->coal);
8243
8244 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8245 /* Status/statistics block address. See tg3_timer,
8246 * the tg3_periodic_fetch_stats call there, and
8247 * tg3_get_stats to see how this works for 5705/5750 chips.
8248 */
8249 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8250 ((u64) tp->stats_mapping >> 32));
8251 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8252 ((u64) tp->stats_mapping & 0xffffffff));
8253 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8254
8255 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8256
8257 /* Clear statistics and status block memory areas */
8258 for (i = NIC_SRAM_STATS_BLK;
8259 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8260 i += sizeof(u32)) {
8261 tg3_write_mem(tp, i, 0);
8262 udelay(40);
8263 }
8264 }
8265
8266 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8267
8268 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8269 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8270 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8271 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8272
8273 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8274 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8275 /* reset to prevent losing 1st rx packet intermittently */
8276 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8277 udelay(10);
8278 }
8279
8280 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8281 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8282 else
8283 tp->mac_mode = 0;
8284 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8285 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8286 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8287 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8288 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8289 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8290 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8291 udelay(40);
8292
8293 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8294 * If TG3_FLG2_IS_NIC is zero, we should read the
8295 * register to preserve the GPIO settings for LOMs. The GPIOs,
8296 * whether used as inputs or outputs, are set by boot code after
8297 * reset.
8298 */
8299 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8300 u32 gpio_mask;
8301
8302 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8303 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8304 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8305
8306 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8307 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8308 GRC_LCLCTRL_GPIO_OUTPUT3;
8309
8310 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8311 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8312
8313 tp->grc_local_ctrl &= ~gpio_mask;
8314 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8315
8316 /* GPIO1 must be driven high for eeprom write protect */
8317 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8318 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8319 GRC_LCLCTRL_GPIO_OUTPUT1);
8320 }
8321 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8322 udelay(100);
8323
8324 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8325 val = tr32(MSGINT_MODE);
8326 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8327 tw32(MSGINT_MODE, val);
8328 }
8329
8330 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8331 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8332 udelay(40);
8333 }
8334
8335 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8336 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8337 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8338 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8339 WDMAC_MODE_LNGREAD_ENAB);
8340
8341 /* If statement applies to 5705 and 5750 PCI devices only */
8342 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8343 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8344 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8345 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8346 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8347 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8348 /* nothing */
8349 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8350 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8351 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8352 val |= WDMAC_MODE_RX_ACCEL;
8353 }
8354 }
8355
8356 /* Enable host coalescing bug fix */
8357 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8358 val |= WDMAC_MODE_STATUS_TAG_FIX;
8359
8360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8361 val |= WDMAC_MODE_BURST_ALL_DATA;
8362
8363 tw32_f(WDMAC_MODE, val);
8364 udelay(40);
8365
8366 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8367 u16 pcix_cmd;
8368
8369 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8370 &pcix_cmd);
8371 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8372 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8373 pcix_cmd |= PCI_X_CMD_READ_2K;
8374 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8375 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8376 pcix_cmd |= PCI_X_CMD_READ_2K;
8377 }
8378 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8379 pcix_cmd);
8380 }
8381
8382 tw32_f(RDMAC_MODE, rdmac_mode);
8383 udelay(40);
8384
8385 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8386 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8387 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8388
8389 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8390 tw32(SNDDATAC_MODE,
8391 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8392 else
8393 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8394
8395 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8396 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8397 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8398 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8399 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8400 val |= RCVDBDI_MODE_LRG_RING_SZ;
8401 tw32(RCVDBDI_MODE, val);
8402 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8403 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8404 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8405 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8406 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8407 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8408 tw32(SNDBDI_MODE, val);
8409 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8410
8411 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8412 err = tg3_load_5701_a0_firmware_fix(tp);
8413 if (err)
8414 return err;
8415 }
8416
8417 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8418 err = tg3_load_tso_firmware(tp);
8419 if (err)
8420 return err;
8421 }
8422
8423 tp->tx_mode = TX_MODE_ENABLE;
8424 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8426 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8427 tw32_f(MAC_TX_MODE, tp->tx_mode);
8428 udelay(100);
8429
8430 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8431 u32 reg = MAC_RSS_INDIR_TBL_0;
8432 u8 *ent = (u8 *)&val;
8433
8434 /* Setup the indirection table */
8435 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8436 int idx = i % sizeof(val);
8437
8438 ent[idx] = i % (tp->irq_cnt - 1);
8439 if (idx == sizeof(val) - 1) {
8440 tw32(reg, val);
8441 reg += 4;
8442 }
8443 }
8444
8445 /* Setup the "secret" hash key. */
8446 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8447 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8448 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8449 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8450 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8451 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8452 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8453 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8454 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8455 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8456 }
8457
8458 tp->rx_mode = RX_MODE_ENABLE;
8459 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8460 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8461
8462 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8463 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8464 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8465 RX_MODE_RSS_IPV6_HASH_EN |
8466 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8467 RX_MODE_RSS_IPV4_HASH_EN |
8468 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8469
8470 tw32_f(MAC_RX_MODE, tp->rx_mode);
8471 udelay(10);
8472
8473 tw32(MAC_LED_CTRL, tp->led_ctrl);
8474
8475 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8476 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8477 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8478 udelay(10);
8479 }
8480 tw32_f(MAC_RX_MODE, tp->rx_mode);
8481 udelay(10);
8482
8483 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8484 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8485 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8486 /* Set drive transmission level to 1.2V */
8487 /* only if the signal pre-emphasis bit is not set */
8488 val = tr32(MAC_SERDES_CFG);
8489 val &= 0xfffff000;
8490 val |= 0x880;
8491 tw32(MAC_SERDES_CFG, val);
8492 }
8493 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8494 tw32(MAC_SERDES_CFG, 0x616000);
8495 }
8496
8497 /* Prevent chip from dropping frames when flow control
8498 * is enabled.
8499 */
8500 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8501 val = 1;
8502 else
8503 val = 2;
8504 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8505
8506 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8507 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8508 /* Use hardware link auto-negotiation */
8509 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8510 }
8511
8512 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8513 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8514 u32 tmp;
8515
8516 tmp = tr32(SERDES_RX_CTRL);
8517 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8518 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8519 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8520 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8521 }
8522
8523 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8524 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8525 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8526 tp->link_config.speed = tp->link_config.orig_speed;
8527 tp->link_config.duplex = tp->link_config.orig_duplex;
8528 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8529 }
8530
8531 err = tg3_setup_phy(tp, 0);
8532 if (err)
8533 return err;
8534
8535 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8536 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8537 u32 tmp;
8538
8539 /* Clear CRC stats. */
8540 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8541 tg3_writephy(tp, MII_TG3_TEST1,
8542 tmp | MII_TG3_TEST1_CRC_EN);
8543 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8544 }
8545 }
8546 }
8547
8548 __tg3_set_rx_mode(tp->dev);
8549
8550 /* Initialize receive rules. */
8551 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8552 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8553 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8554 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8555
8556 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8557 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8558 limit = 8;
8559 else
8560 limit = 16;
8561 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8562 limit -= 4;
8563 switch (limit) {
8564 case 16:
8565 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8566 case 15:
8567 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8568 case 14:
8569 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8570 case 13:
8571 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8572 case 12:
8573 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8574 case 11:
8575 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8576 case 10:
8577 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8578 case 9:
8579 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8580 case 8:
8581 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8582 case 7:
8583 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8584 case 6:
8585 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8586 case 5:
8587 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8588 case 4:
8589 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8590 case 3:
8591 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8592 case 2:
8593 case 1:
8594
8595 default:
8596 break;
8597 }
8598
8599 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8600 /* Write our heartbeat update interval to APE. */
8601 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8602 APE_HOST_HEARTBEAT_INT_DISABLE);
8603
8604 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8605
8606 return 0;
8607 }
8608
8609 /* Called at device open time to get the chip ready for
8610 * packet processing. Invoked with tp->lock held.
8611 */
8612 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8613 {
8614 tg3_switch_clocks(tp);
8615
8616 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8617
8618 return tg3_reset_hw(tp, reset_phy);
8619 }
8620
8621 #define TG3_STAT_ADD32(PSTAT, REG) \
8622 do { u32 __val = tr32(REG); \
8623 (PSTAT)->low += __val; \
8624 if ((PSTAT)->low < __val) \
8625 (PSTAT)->high += 1; \
8626 } while (0)
8627
8628 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8629 {
8630 struct tg3_hw_stats *sp = tp->hw_stats;
8631
8632 if (!netif_carrier_ok(tp->dev))
8633 return;
8634
8635 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8636 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8637 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8638 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8639 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8640 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8641 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8642 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8643 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8644 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8645 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8646 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8647 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8648
8649 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8650 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8651 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8652 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8653 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8654 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8655 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8656 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8657 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8658 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8659 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8660 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8661 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8662 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8663
8664 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8665 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8666 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8667 }
8668
8669 static void tg3_timer(unsigned long __opaque)
8670 {
8671 struct tg3 *tp = (struct tg3 *) __opaque;
8672
8673 if (tp->irq_sync)
8674 goto restart_timer;
8675
8676 spin_lock(&tp->lock);
8677
8678 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8679 /* All of this garbage is because when using non-tagged
8680 * IRQ status the mailbox/status_block protocol the chip
8681 * uses with the cpu is race prone.
8682 */
8683 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8684 tw32(GRC_LOCAL_CTRL,
8685 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8686 } else {
8687 tw32(HOSTCC_MODE, tp->coalesce_mode |
8688 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8689 }
8690
8691 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8692 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8693 spin_unlock(&tp->lock);
8694 schedule_work(&tp->reset_task);
8695 return;
8696 }
8697 }
8698
8699 /* This part only runs once per second. */
8700 if (!--tp->timer_counter) {
8701 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8702 tg3_periodic_fetch_stats(tp);
8703
8704 if (tp->setlpicnt && !--tp->setlpicnt) {
8705 u32 val = tr32(TG3_CPMU_EEE_MODE);
8706 tw32(TG3_CPMU_EEE_MODE,
8707 val | TG3_CPMU_EEEMD_LPI_ENABLE);
8708 }
8709
8710 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8711 u32 mac_stat;
8712 int phy_event;
8713
8714 mac_stat = tr32(MAC_STATUS);
8715
8716 phy_event = 0;
8717 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8718 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8719 phy_event = 1;
8720 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8721 phy_event = 1;
8722
8723 if (phy_event)
8724 tg3_setup_phy(tp, 0);
8725 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8726 u32 mac_stat = tr32(MAC_STATUS);
8727 int need_setup = 0;
8728
8729 if (netif_carrier_ok(tp->dev) &&
8730 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8731 need_setup = 1;
8732 }
8733 if (!netif_carrier_ok(tp->dev) &&
8734 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8735 MAC_STATUS_SIGNAL_DET))) {
8736 need_setup = 1;
8737 }
8738 if (need_setup) {
8739 if (!tp->serdes_counter) {
8740 tw32_f(MAC_MODE,
8741 (tp->mac_mode &
8742 ~MAC_MODE_PORT_MODE_MASK));
8743 udelay(40);
8744 tw32_f(MAC_MODE, tp->mac_mode);
8745 udelay(40);
8746 }
8747 tg3_setup_phy(tp, 0);
8748 }
8749 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8751 tg3_serdes_parallel_detect(tp);
8752 }
8753
8754 tp->timer_counter = tp->timer_multiplier;
8755 }
8756
8757 /* Heartbeat is only sent once every 2 seconds.
8758 *
8759 * The heartbeat is to tell the ASF firmware that the host
8760 * driver is still alive. In the event that the OS crashes,
8761 * ASF needs to reset the hardware to free up the FIFO space
8762 * that may be filled with rx packets destined for the host.
8763 * If the FIFO is full, ASF will no longer function properly.
8764 *
8765 * Unintended resets have been reported on real time kernels
8766 * where the timer doesn't run on time. Netpoll will also have
8767 * same problem.
8768 *
8769 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8770 * to check the ring condition when the heartbeat is expiring
8771 * before doing the reset. This will prevent most unintended
8772 * resets.
8773 */
8774 if (!--tp->asf_counter) {
8775 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8776 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8777 tg3_wait_for_event_ack(tp);
8778
8779 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8780 FWCMD_NICDRV_ALIVE3);
8781 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8782 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8783 TG3_FW_UPDATE_TIMEOUT_SEC);
8784
8785 tg3_generate_fw_event(tp);
8786 }
8787 tp->asf_counter = tp->asf_multiplier;
8788 }
8789
8790 spin_unlock(&tp->lock);
8791
8792 restart_timer:
8793 tp->timer.expires = jiffies + tp->timer_offset;
8794 add_timer(&tp->timer);
8795 }
8796
8797 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8798 {
8799 irq_handler_t fn;
8800 unsigned long flags;
8801 char *name;
8802 struct tg3_napi *tnapi = &tp->napi[irq_num];
8803
8804 if (tp->irq_cnt == 1)
8805 name = tp->dev->name;
8806 else {
8807 name = &tnapi->irq_lbl[0];
8808 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8809 name[IFNAMSIZ-1] = 0;
8810 }
8811
8812 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8813 fn = tg3_msi;
8814 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8815 fn = tg3_msi_1shot;
8816 flags = IRQF_SAMPLE_RANDOM;
8817 } else {
8818 fn = tg3_interrupt;
8819 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8820 fn = tg3_interrupt_tagged;
8821 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8822 }
8823
8824 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8825 }
8826
8827 static int tg3_test_interrupt(struct tg3 *tp)
8828 {
8829 struct tg3_napi *tnapi = &tp->napi[0];
8830 struct net_device *dev = tp->dev;
8831 int err, i, intr_ok = 0;
8832 u32 val;
8833
8834 if (!netif_running(dev))
8835 return -ENODEV;
8836
8837 tg3_disable_ints(tp);
8838
8839 free_irq(tnapi->irq_vec, tnapi);
8840
8841 /*
8842 * Turn off MSI one shot mode. Otherwise this test has no
8843 * observable way to know whether the interrupt was delivered.
8844 */
8845 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8846 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8847 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8848 tw32(MSGINT_MODE, val);
8849 }
8850
8851 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8852 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8853 if (err)
8854 return err;
8855
8856 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8857 tg3_enable_ints(tp);
8858
8859 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8860 tnapi->coal_now);
8861
8862 for (i = 0; i < 5; i++) {
8863 u32 int_mbox, misc_host_ctrl;
8864
8865 int_mbox = tr32_mailbox(tnapi->int_mbox);
8866 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8867
8868 if ((int_mbox != 0) ||
8869 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8870 intr_ok = 1;
8871 break;
8872 }
8873
8874 msleep(10);
8875 }
8876
8877 tg3_disable_ints(tp);
8878
8879 free_irq(tnapi->irq_vec, tnapi);
8880
8881 err = tg3_request_irq(tp, 0);
8882
8883 if (err)
8884 return err;
8885
8886 if (intr_ok) {
8887 /* Reenable MSI one shot mode. */
8888 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8889 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8890 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8891 tw32(MSGINT_MODE, val);
8892 }
8893 return 0;
8894 }
8895
8896 return -EIO;
8897 }
8898
8899 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8900 * successfully restored
8901 */
8902 static int tg3_test_msi(struct tg3 *tp)
8903 {
8904 int err;
8905 u16 pci_cmd;
8906
8907 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8908 return 0;
8909
8910 /* Turn off SERR reporting in case MSI terminates with Master
8911 * Abort.
8912 */
8913 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8914 pci_write_config_word(tp->pdev, PCI_COMMAND,
8915 pci_cmd & ~PCI_COMMAND_SERR);
8916
8917 err = tg3_test_interrupt(tp);
8918
8919 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8920
8921 if (!err)
8922 return 0;
8923
8924 /* other failures */
8925 if (err != -EIO)
8926 return err;
8927
8928 /* MSI test failed, go back to INTx mode */
8929 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8930 "to INTx mode. Please report this failure to the PCI "
8931 "maintainer and include system chipset information\n");
8932
8933 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8934
8935 pci_disable_msi(tp->pdev);
8936
8937 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8938 tp->napi[0].irq_vec = tp->pdev->irq;
8939
8940 err = tg3_request_irq(tp, 0);
8941 if (err)
8942 return err;
8943
8944 /* Need to reset the chip because the MSI cycle may have terminated
8945 * with Master Abort.
8946 */
8947 tg3_full_lock(tp, 1);
8948
8949 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8950 err = tg3_init_hw(tp, 1);
8951
8952 tg3_full_unlock(tp);
8953
8954 if (err)
8955 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8956
8957 return err;
8958 }
8959
8960 static int tg3_request_firmware(struct tg3 *tp)
8961 {
8962 const __be32 *fw_data;
8963
8964 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8965 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8966 tp->fw_needed);
8967 return -ENOENT;
8968 }
8969
8970 fw_data = (void *)tp->fw->data;
8971
8972 /* Firmware blob starts with version numbers, followed by
8973 * start address and _full_ length including BSS sections
8974 * (which must be longer than the actual data, of course
8975 */
8976
8977 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8978 if (tp->fw_len < (tp->fw->size - 12)) {
8979 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8980 tp->fw_len, tp->fw_needed);
8981 release_firmware(tp->fw);
8982 tp->fw = NULL;
8983 return -EINVAL;
8984 }
8985
8986 /* We no longer need firmware; we have it. */
8987 tp->fw_needed = NULL;
8988 return 0;
8989 }
8990
8991 static bool tg3_enable_msix(struct tg3 *tp)
8992 {
8993 int i, rc, cpus = num_online_cpus();
8994 struct msix_entry msix_ent[tp->irq_max];
8995
8996 if (cpus == 1)
8997 /* Just fallback to the simpler MSI mode. */
8998 return false;
8999
9000 /*
9001 * We want as many rx rings enabled as there are cpus.
9002 * The first MSIX vector only deals with link interrupts, etc,
9003 * so we add one to the number of vectors we are requesting.
9004 */
9005 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9006
9007 for (i = 0; i < tp->irq_max; i++) {
9008 msix_ent[i].entry = i;
9009 msix_ent[i].vector = 0;
9010 }
9011
9012 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9013 if (rc < 0) {
9014 return false;
9015 } else if (rc != 0) {
9016 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9017 return false;
9018 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9019 tp->irq_cnt, rc);
9020 tp->irq_cnt = rc;
9021 }
9022
9023 for (i = 0; i < tp->irq_max; i++)
9024 tp->napi[i].irq_vec = msix_ent[i].vector;
9025
9026 netif_set_real_num_tx_queues(tp->dev, 1);
9027 rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9028 if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9029 pci_disable_msix(tp->pdev);
9030 return false;
9031 }
9032 if (tp->irq_cnt > 1)
9033 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9034
9035 return true;
9036 }
9037
9038 static void tg3_ints_init(struct tg3 *tp)
9039 {
9040 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9041 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9042 /* All MSI supporting chips should support tagged
9043 * status. Assert that this is the case.
9044 */
9045 netdev_warn(tp->dev,
9046 "MSI without TAGGED_STATUS? Not using MSI\n");
9047 goto defcfg;
9048 }
9049
9050 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9051 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9052 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9053 pci_enable_msi(tp->pdev) == 0)
9054 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9055
9056 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9057 u32 msi_mode = tr32(MSGINT_MODE);
9058 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9059 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9060 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9061 }
9062 defcfg:
9063 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9064 tp->irq_cnt = 1;
9065 tp->napi[0].irq_vec = tp->pdev->irq;
9066 netif_set_real_num_tx_queues(tp->dev, 1);
9067 netif_set_real_num_rx_queues(tp->dev, 1);
9068 }
9069 }
9070
9071 static void tg3_ints_fini(struct tg3 *tp)
9072 {
9073 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9074 pci_disable_msix(tp->pdev);
9075 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9076 pci_disable_msi(tp->pdev);
9077 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9078 tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9079 }
9080
9081 static int tg3_open(struct net_device *dev)
9082 {
9083 struct tg3 *tp = netdev_priv(dev);
9084 int i, err;
9085
9086 if (tp->fw_needed) {
9087 err = tg3_request_firmware(tp);
9088 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9089 if (err)
9090 return err;
9091 } else if (err) {
9092 netdev_warn(tp->dev, "TSO capability disabled\n");
9093 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9094 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9095 netdev_notice(tp->dev, "TSO capability restored\n");
9096 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9097 }
9098 }
9099
9100 netif_carrier_off(tp->dev);
9101
9102 err = tg3_set_power_state(tp, PCI_D0);
9103 if (err)
9104 return err;
9105
9106 tg3_full_lock(tp, 0);
9107
9108 tg3_disable_ints(tp);
9109 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9110
9111 tg3_full_unlock(tp);
9112
9113 /*
9114 * Setup interrupts first so we know how
9115 * many NAPI resources to allocate
9116 */
9117 tg3_ints_init(tp);
9118
9119 /* The placement of this call is tied
9120 * to the setup and use of Host TX descriptors.
9121 */
9122 err = tg3_alloc_consistent(tp);
9123 if (err)
9124 goto err_out1;
9125
9126 tg3_napi_init(tp);
9127
9128 tg3_napi_enable(tp);
9129
9130 for (i = 0; i < tp->irq_cnt; i++) {
9131 struct tg3_napi *tnapi = &tp->napi[i];
9132 err = tg3_request_irq(tp, i);
9133 if (err) {
9134 for (i--; i >= 0; i--)
9135 free_irq(tnapi->irq_vec, tnapi);
9136 break;
9137 }
9138 }
9139
9140 if (err)
9141 goto err_out2;
9142
9143 tg3_full_lock(tp, 0);
9144
9145 err = tg3_init_hw(tp, 1);
9146 if (err) {
9147 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9148 tg3_free_rings(tp);
9149 } else {
9150 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9151 tp->timer_offset = HZ;
9152 else
9153 tp->timer_offset = HZ / 10;
9154
9155 BUG_ON(tp->timer_offset > HZ);
9156 tp->timer_counter = tp->timer_multiplier =
9157 (HZ / tp->timer_offset);
9158 tp->asf_counter = tp->asf_multiplier =
9159 ((HZ / tp->timer_offset) * 2);
9160
9161 init_timer(&tp->timer);
9162 tp->timer.expires = jiffies + tp->timer_offset;
9163 tp->timer.data = (unsigned long) tp;
9164 tp->timer.function = tg3_timer;
9165 }
9166
9167 tg3_full_unlock(tp);
9168
9169 if (err)
9170 goto err_out3;
9171
9172 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9173 err = tg3_test_msi(tp);
9174
9175 if (err) {
9176 tg3_full_lock(tp, 0);
9177 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9178 tg3_free_rings(tp);
9179 tg3_full_unlock(tp);
9180
9181 goto err_out2;
9182 }
9183
9184 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9185 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9186 u32 val = tr32(PCIE_TRANSACTION_CFG);
9187
9188 tw32(PCIE_TRANSACTION_CFG,
9189 val | PCIE_TRANS_CFG_1SHOT_MSI);
9190 }
9191 }
9192
9193 tg3_phy_start(tp);
9194
9195 tg3_full_lock(tp, 0);
9196
9197 add_timer(&tp->timer);
9198 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9199 tg3_enable_ints(tp);
9200
9201 tg3_full_unlock(tp);
9202
9203 netif_tx_start_all_queues(dev);
9204
9205 return 0;
9206
9207 err_out3:
9208 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9209 struct tg3_napi *tnapi = &tp->napi[i];
9210 free_irq(tnapi->irq_vec, tnapi);
9211 }
9212
9213 err_out2:
9214 tg3_napi_disable(tp);
9215 tg3_napi_fini(tp);
9216 tg3_free_consistent(tp);
9217
9218 err_out1:
9219 tg3_ints_fini(tp);
9220 return err;
9221 }
9222
9223 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9224 struct rtnl_link_stats64 *);
9225 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9226
9227 static int tg3_close(struct net_device *dev)
9228 {
9229 int i;
9230 struct tg3 *tp = netdev_priv(dev);
9231
9232 tg3_napi_disable(tp);
9233 cancel_work_sync(&tp->reset_task);
9234
9235 netif_tx_stop_all_queues(dev);
9236
9237 del_timer_sync(&tp->timer);
9238
9239 tg3_phy_stop(tp);
9240
9241 tg3_full_lock(tp, 1);
9242
9243 tg3_disable_ints(tp);
9244
9245 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9246 tg3_free_rings(tp);
9247 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9248
9249 tg3_full_unlock(tp);
9250
9251 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9252 struct tg3_napi *tnapi = &tp->napi[i];
9253 free_irq(tnapi->irq_vec, tnapi);
9254 }
9255
9256 tg3_ints_fini(tp);
9257
9258 tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9259
9260 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9261 sizeof(tp->estats_prev));
9262
9263 tg3_napi_fini(tp);
9264
9265 tg3_free_consistent(tp);
9266
9267 tg3_set_power_state(tp, PCI_D3hot);
9268
9269 netif_carrier_off(tp->dev);
9270
9271 return 0;
9272 }
9273
9274 static inline u64 get_stat64(tg3_stat64_t *val)
9275 {
9276 return ((u64)val->high << 32) | ((u64)val->low);
9277 }
9278
9279 static u64 calc_crc_errors(struct tg3 *tp)
9280 {
9281 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9282
9283 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9284 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9285 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9286 u32 val;
9287
9288 spin_lock_bh(&tp->lock);
9289 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9290 tg3_writephy(tp, MII_TG3_TEST1,
9291 val | MII_TG3_TEST1_CRC_EN);
9292 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9293 } else
9294 val = 0;
9295 spin_unlock_bh(&tp->lock);
9296
9297 tp->phy_crc_errors += val;
9298
9299 return tp->phy_crc_errors;
9300 }
9301
9302 return get_stat64(&hw_stats->rx_fcs_errors);
9303 }
9304
9305 #define ESTAT_ADD(member) \
9306 estats->member = old_estats->member + \
9307 get_stat64(&hw_stats->member)
9308
9309 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9310 {
9311 struct tg3_ethtool_stats *estats = &tp->estats;
9312 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9313 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9314
9315 if (!hw_stats)
9316 return old_estats;
9317
9318 ESTAT_ADD(rx_octets);
9319 ESTAT_ADD(rx_fragments);
9320 ESTAT_ADD(rx_ucast_packets);
9321 ESTAT_ADD(rx_mcast_packets);
9322 ESTAT_ADD(rx_bcast_packets);
9323 ESTAT_ADD(rx_fcs_errors);
9324 ESTAT_ADD(rx_align_errors);
9325 ESTAT_ADD(rx_xon_pause_rcvd);
9326 ESTAT_ADD(rx_xoff_pause_rcvd);
9327 ESTAT_ADD(rx_mac_ctrl_rcvd);
9328 ESTAT_ADD(rx_xoff_entered);
9329 ESTAT_ADD(rx_frame_too_long_errors);
9330 ESTAT_ADD(rx_jabbers);
9331 ESTAT_ADD(rx_undersize_packets);
9332 ESTAT_ADD(rx_in_length_errors);
9333 ESTAT_ADD(rx_out_length_errors);
9334 ESTAT_ADD(rx_64_or_less_octet_packets);
9335 ESTAT_ADD(rx_65_to_127_octet_packets);
9336 ESTAT_ADD(rx_128_to_255_octet_packets);
9337 ESTAT_ADD(rx_256_to_511_octet_packets);
9338 ESTAT_ADD(rx_512_to_1023_octet_packets);
9339 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9340 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9341 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9342 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9343 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9344
9345 ESTAT_ADD(tx_octets);
9346 ESTAT_ADD(tx_collisions);
9347 ESTAT_ADD(tx_xon_sent);
9348 ESTAT_ADD(tx_xoff_sent);
9349 ESTAT_ADD(tx_flow_control);
9350 ESTAT_ADD(tx_mac_errors);
9351 ESTAT_ADD(tx_single_collisions);
9352 ESTAT_ADD(tx_mult_collisions);
9353 ESTAT_ADD(tx_deferred);
9354 ESTAT_ADD(tx_excessive_collisions);
9355 ESTAT_ADD(tx_late_collisions);
9356 ESTAT_ADD(tx_collide_2times);
9357 ESTAT_ADD(tx_collide_3times);
9358 ESTAT_ADD(tx_collide_4times);
9359 ESTAT_ADD(tx_collide_5times);
9360 ESTAT_ADD(tx_collide_6times);
9361 ESTAT_ADD(tx_collide_7times);
9362 ESTAT_ADD(tx_collide_8times);
9363 ESTAT_ADD(tx_collide_9times);
9364 ESTAT_ADD(tx_collide_10times);
9365 ESTAT_ADD(tx_collide_11times);
9366 ESTAT_ADD(tx_collide_12times);
9367 ESTAT_ADD(tx_collide_13times);
9368 ESTAT_ADD(tx_collide_14times);
9369 ESTAT_ADD(tx_collide_15times);
9370 ESTAT_ADD(tx_ucast_packets);
9371 ESTAT_ADD(tx_mcast_packets);
9372 ESTAT_ADD(tx_bcast_packets);
9373 ESTAT_ADD(tx_carrier_sense_errors);
9374 ESTAT_ADD(tx_discards);
9375 ESTAT_ADD(tx_errors);
9376
9377 ESTAT_ADD(dma_writeq_full);
9378 ESTAT_ADD(dma_write_prioq_full);
9379 ESTAT_ADD(rxbds_empty);
9380 ESTAT_ADD(rx_discards);
9381 ESTAT_ADD(rx_errors);
9382 ESTAT_ADD(rx_threshold_hit);
9383
9384 ESTAT_ADD(dma_readq_full);
9385 ESTAT_ADD(dma_read_prioq_full);
9386 ESTAT_ADD(tx_comp_queue_full);
9387
9388 ESTAT_ADD(ring_set_send_prod_index);
9389 ESTAT_ADD(ring_status_update);
9390 ESTAT_ADD(nic_irqs);
9391 ESTAT_ADD(nic_avoided_irqs);
9392 ESTAT_ADD(nic_tx_threshold_hit);
9393
9394 return estats;
9395 }
9396
9397 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9398 struct rtnl_link_stats64 *stats)
9399 {
9400 struct tg3 *tp = netdev_priv(dev);
9401 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9402 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9403
9404 if (!hw_stats)
9405 return old_stats;
9406
9407 stats->rx_packets = old_stats->rx_packets +
9408 get_stat64(&hw_stats->rx_ucast_packets) +
9409 get_stat64(&hw_stats->rx_mcast_packets) +
9410 get_stat64(&hw_stats->rx_bcast_packets);
9411
9412 stats->tx_packets = old_stats->tx_packets +
9413 get_stat64(&hw_stats->tx_ucast_packets) +
9414 get_stat64(&hw_stats->tx_mcast_packets) +
9415 get_stat64(&hw_stats->tx_bcast_packets);
9416
9417 stats->rx_bytes = old_stats->rx_bytes +
9418 get_stat64(&hw_stats->rx_octets);
9419 stats->tx_bytes = old_stats->tx_bytes +
9420 get_stat64(&hw_stats->tx_octets);
9421
9422 stats->rx_errors = old_stats->rx_errors +
9423 get_stat64(&hw_stats->rx_errors);
9424 stats->tx_errors = old_stats->tx_errors +
9425 get_stat64(&hw_stats->tx_errors) +
9426 get_stat64(&hw_stats->tx_mac_errors) +
9427 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9428 get_stat64(&hw_stats->tx_discards);
9429
9430 stats->multicast = old_stats->multicast +
9431 get_stat64(&hw_stats->rx_mcast_packets);
9432 stats->collisions = old_stats->collisions +
9433 get_stat64(&hw_stats->tx_collisions);
9434
9435 stats->rx_length_errors = old_stats->rx_length_errors +
9436 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9437 get_stat64(&hw_stats->rx_undersize_packets);
9438
9439 stats->rx_over_errors = old_stats->rx_over_errors +
9440 get_stat64(&hw_stats->rxbds_empty);
9441 stats->rx_frame_errors = old_stats->rx_frame_errors +
9442 get_stat64(&hw_stats->rx_align_errors);
9443 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9444 get_stat64(&hw_stats->tx_discards);
9445 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9446 get_stat64(&hw_stats->tx_carrier_sense_errors);
9447
9448 stats->rx_crc_errors = old_stats->rx_crc_errors +
9449 calc_crc_errors(tp);
9450
9451 stats->rx_missed_errors = old_stats->rx_missed_errors +
9452 get_stat64(&hw_stats->rx_discards);
9453
9454 return stats;
9455 }
9456
9457 static inline u32 calc_crc(unsigned char *buf, int len)
9458 {
9459 u32 reg;
9460 u32 tmp;
9461 int j, k;
9462
9463 reg = 0xffffffff;
9464
9465 for (j = 0; j < len; j++) {
9466 reg ^= buf[j];
9467
9468 for (k = 0; k < 8; k++) {
9469 tmp = reg & 0x01;
9470
9471 reg >>= 1;
9472
9473 if (tmp)
9474 reg ^= 0xedb88320;
9475 }
9476 }
9477
9478 return ~reg;
9479 }
9480
9481 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9482 {
9483 /* accept or reject all multicast frames */
9484 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9485 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9486 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9487 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9488 }
9489
9490 static void __tg3_set_rx_mode(struct net_device *dev)
9491 {
9492 struct tg3 *tp = netdev_priv(dev);
9493 u32 rx_mode;
9494
9495 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9496 RX_MODE_KEEP_VLAN_TAG);
9497
9498 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9499 * flag clear.
9500 */
9501 #if TG3_VLAN_TAG_USED
9502 if (!tp->vlgrp &&
9503 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9504 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9505 #else
9506 /* By definition, VLAN is disabled always in this
9507 * case.
9508 */
9509 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9510 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9511 #endif
9512
9513 if (dev->flags & IFF_PROMISC) {
9514 /* Promiscuous mode. */
9515 rx_mode |= RX_MODE_PROMISC;
9516 } else if (dev->flags & IFF_ALLMULTI) {
9517 /* Accept all multicast. */
9518 tg3_set_multi(tp, 1);
9519 } else if (netdev_mc_empty(dev)) {
9520 /* Reject all multicast. */
9521 tg3_set_multi(tp, 0);
9522 } else {
9523 /* Accept one or more multicast(s). */
9524 struct netdev_hw_addr *ha;
9525 u32 mc_filter[4] = { 0, };
9526 u32 regidx;
9527 u32 bit;
9528 u32 crc;
9529
9530 netdev_for_each_mc_addr(ha, dev) {
9531 crc = calc_crc(ha->addr, ETH_ALEN);
9532 bit = ~crc & 0x7f;
9533 regidx = (bit & 0x60) >> 5;
9534 bit &= 0x1f;
9535 mc_filter[regidx] |= (1 << bit);
9536 }
9537
9538 tw32(MAC_HASH_REG_0, mc_filter[0]);
9539 tw32(MAC_HASH_REG_1, mc_filter[1]);
9540 tw32(MAC_HASH_REG_2, mc_filter[2]);
9541 tw32(MAC_HASH_REG_3, mc_filter[3]);
9542 }
9543
9544 if (rx_mode != tp->rx_mode) {
9545 tp->rx_mode = rx_mode;
9546 tw32_f(MAC_RX_MODE, rx_mode);
9547 udelay(10);
9548 }
9549 }
9550
9551 static void tg3_set_rx_mode(struct net_device *dev)
9552 {
9553 struct tg3 *tp = netdev_priv(dev);
9554
9555 if (!netif_running(dev))
9556 return;
9557
9558 tg3_full_lock(tp, 0);
9559 __tg3_set_rx_mode(dev);
9560 tg3_full_unlock(tp);
9561 }
9562
9563 #define TG3_REGDUMP_LEN (32 * 1024)
9564
9565 static int tg3_get_regs_len(struct net_device *dev)
9566 {
9567 return TG3_REGDUMP_LEN;
9568 }
9569
9570 static void tg3_get_regs(struct net_device *dev,
9571 struct ethtool_regs *regs, void *_p)
9572 {
9573 u32 *p = _p;
9574 struct tg3 *tp = netdev_priv(dev);
9575 u8 *orig_p = _p;
9576 int i;
9577
9578 regs->version = 0;
9579
9580 memset(p, 0, TG3_REGDUMP_LEN);
9581
9582 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9583 return;
9584
9585 tg3_full_lock(tp, 0);
9586
9587 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9588 #define GET_REG32_LOOP(base, len) \
9589 do { p = (u32 *)(orig_p + (base)); \
9590 for (i = 0; i < len; i += 4) \
9591 __GET_REG32((base) + i); \
9592 } while (0)
9593 #define GET_REG32_1(reg) \
9594 do { p = (u32 *)(orig_p + (reg)); \
9595 __GET_REG32((reg)); \
9596 } while (0)
9597
9598 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9599 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9600 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9601 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9602 GET_REG32_1(SNDDATAC_MODE);
9603 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9604 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9605 GET_REG32_1(SNDBDC_MODE);
9606 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9607 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9608 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9609 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9610 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9611 GET_REG32_1(RCVDCC_MODE);
9612 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9613 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9614 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9615 GET_REG32_1(MBFREE_MODE);
9616 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9617 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9618 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9619 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9620 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9621 GET_REG32_1(RX_CPU_MODE);
9622 GET_REG32_1(RX_CPU_STATE);
9623 GET_REG32_1(RX_CPU_PGMCTR);
9624 GET_REG32_1(RX_CPU_HWBKPT);
9625 GET_REG32_1(TX_CPU_MODE);
9626 GET_REG32_1(TX_CPU_STATE);
9627 GET_REG32_1(TX_CPU_PGMCTR);
9628 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9629 GET_REG32_LOOP(FTQ_RESET, 0x120);
9630 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9631 GET_REG32_1(DMAC_MODE);
9632 GET_REG32_LOOP(GRC_MODE, 0x4c);
9633 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9634 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9635
9636 #undef __GET_REG32
9637 #undef GET_REG32_LOOP
9638 #undef GET_REG32_1
9639
9640 tg3_full_unlock(tp);
9641 }
9642
9643 static int tg3_get_eeprom_len(struct net_device *dev)
9644 {
9645 struct tg3 *tp = netdev_priv(dev);
9646
9647 return tp->nvram_size;
9648 }
9649
9650 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9651 {
9652 struct tg3 *tp = netdev_priv(dev);
9653 int ret;
9654 u8 *pd;
9655 u32 i, offset, len, b_offset, b_count;
9656 __be32 val;
9657
9658 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9659 return -EINVAL;
9660
9661 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9662 return -EAGAIN;
9663
9664 offset = eeprom->offset;
9665 len = eeprom->len;
9666 eeprom->len = 0;
9667
9668 eeprom->magic = TG3_EEPROM_MAGIC;
9669
9670 if (offset & 3) {
9671 /* adjustments to start on required 4 byte boundary */
9672 b_offset = offset & 3;
9673 b_count = 4 - b_offset;
9674 if (b_count > len) {
9675 /* i.e. offset=1 len=2 */
9676 b_count = len;
9677 }
9678 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9679 if (ret)
9680 return ret;
9681 memcpy(data, ((char *)&val) + b_offset, b_count);
9682 len -= b_count;
9683 offset += b_count;
9684 eeprom->len += b_count;
9685 }
9686
9687 /* read bytes upto the last 4 byte boundary */
9688 pd = &data[eeprom->len];
9689 for (i = 0; i < (len - (len & 3)); i += 4) {
9690 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9691 if (ret) {
9692 eeprom->len += i;
9693 return ret;
9694 }
9695 memcpy(pd + i, &val, 4);
9696 }
9697 eeprom->len += i;
9698
9699 if (len & 3) {
9700 /* read last bytes not ending on 4 byte boundary */
9701 pd = &data[eeprom->len];
9702 b_count = len & 3;
9703 b_offset = offset + len - b_count;
9704 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9705 if (ret)
9706 return ret;
9707 memcpy(pd, &val, b_count);
9708 eeprom->len += b_count;
9709 }
9710 return 0;
9711 }
9712
9713 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9714
9715 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9716 {
9717 struct tg3 *tp = netdev_priv(dev);
9718 int ret;
9719 u32 offset, len, b_offset, odd_len;
9720 u8 *buf;
9721 __be32 start, end;
9722
9723 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9724 return -EAGAIN;
9725
9726 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9727 eeprom->magic != TG3_EEPROM_MAGIC)
9728 return -EINVAL;
9729
9730 offset = eeprom->offset;
9731 len = eeprom->len;
9732
9733 if ((b_offset = (offset & 3))) {
9734 /* adjustments to start on required 4 byte boundary */
9735 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9736 if (ret)
9737 return ret;
9738 len += b_offset;
9739 offset &= ~3;
9740 if (len < 4)
9741 len = 4;
9742 }
9743
9744 odd_len = 0;
9745 if (len & 3) {
9746 /* adjustments to end on required 4 byte boundary */
9747 odd_len = 1;
9748 len = (len + 3) & ~3;
9749 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9750 if (ret)
9751 return ret;
9752 }
9753
9754 buf = data;
9755 if (b_offset || odd_len) {
9756 buf = kmalloc(len, GFP_KERNEL);
9757 if (!buf)
9758 return -ENOMEM;
9759 if (b_offset)
9760 memcpy(buf, &start, 4);
9761 if (odd_len)
9762 memcpy(buf+len-4, &end, 4);
9763 memcpy(buf + b_offset, data, eeprom->len);
9764 }
9765
9766 ret = tg3_nvram_write_block(tp, offset, len, buf);
9767
9768 if (buf != data)
9769 kfree(buf);
9770
9771 return ret;
9772 }
9773
9774 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9775 {
9776 struct tg3 *tp = netdev_priv(dev);
9777
9778 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9779 struct phy_device *phydev;
9780 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9781 return -EAGAIN;
9782 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9783 return phy_ethtool_gset(phydev, cmd);
9784 }
9785
9786 cmd->supported = (SUPPORTED_Autoneg);
9787
9788 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9789 cmd->supported |= (SUPPORTED_1000baseT_Half |
9790 SUPPORTED_1000baseT_Full);
9791
9792 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9793 cmd->supported |= (SUPPORTED_100baseT_Half |
9794 SUPPORTED_100baseT_Full |
9795 SUPPORTED_10baseT_Half |
9796 SUPPORTED_10baseT_Full |
9797 SUPPORTED_TP);
9798 cmd->port = PORT_TP;
9799 } else {
9800 cmd->supported |= SUPPORTED_FIBRE;
9801 cmd->port = PORT_FIBRE;
9802 }
9803
9804 cmd->advertising = tp->link_config.advertising;
9805 if (netif_running(dev)) {
9806 cmd->speed = tp->link_config.active_speed;
9807 cmd->duplex = tp->link_config.active_duplex;
9808 }
9809 cmd->phy_address = tp->phy_addr;
9810 cmd->transceiver = XCVR_INTERNAL;
9811 cmd->autoneg = tp->link_config.autoneg;
9812 cmd->maxtxpkt = 0;
9813 cmd->maxrxpkt = 0;
9814 return 0;
9815 }
9816
9817 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9818 {
9819 struct tg3 *tp = netdev_priv(dev);
9820
9821 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9822 struct phy_device *phydev;
9823 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9824 return -EAGAIN;
9825 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9826 return phy_ethtool_sset(phydev, cmd);
9827 }
9828
9829 if (cmd->autoneg != AUTONEG_ENABLE &&
9830 cmd->autoneg != AUTONEG_DISABLE)
9831 return -EINVAL;
9832
9833 if (cmd->autoneg == AUTONEG_DISABLE &&
9834 cmd->duplex != DUPLEX_FULL &&
9835 cmd->duplex != DUPLEX_HALF)
9836 return -EINVAL;
9837
9838 if (cmd->autoneg == AUTONEG_ENABLE) {
9839 u32 mask = ADVERTISED_Autoneg |
9840 ADVERTISED_Pause |
9841 ADVERTISED_Asym_Pause;
9842
9843 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9844 mask |= ADVERTISED_1000baseT_Half |
9845 ADVERTISED_1000baseT_Full;
9846
9847 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9848 mask |= ADVERTISED_100baseT_Half |
9849 ADVERTISED_100baseT_Full |
9850 ADVERTISED_10baseT_Half |
9851 ADVERTISED_10baseT_Full |
9852 ADVERTISED_TP;
9853 else
9854 mask |= ADVERTISED_FIBRE;
9855
9856 if (cmd->advertising & ~mask)
9857 return -EINVAL;
9858
9859 mask &= (ADVERTISED_1000baseT_Half |
9860 ADVERTISED_1000baseT_Full |
9861 ADVERTISED_100baseT_Half |
9862 ADVERTISED_100baseT_Full |
9863 ADVERTISED_10baseT_Half |
9864 ADVERTISED_10baseT_Full);
9865
9866 cmd->advertising &= mask;
9867 } else {
9868 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9869 if (cmd->speed != SPEED_1000)
9870 return -EINVAL;
9871
9872 if (cmd->duplex != DUPLEX_FULL)
9873 return -EINVAL;
9874 } else {
9875 if (cmd->speed != SPEED_100 &&
9876 cmd->speed != SPEED_10)
9877 return -EINVAL;
9878 }
9879 }
9880
9881 tg3_full_lock(tp, 0);
9882
9883 tp->link_config.autoneg = cmd->autoneg;
9884 if (cmd->autoneg == AUTONEG_ENABLE) {
9885 tp->link_config.advertising = (cmd->advertising |
9886 ADVERTISED_Autoneg);
9887 tp->link_config.speed = SPEED_INVALID;
9888 tp->link_config.duplex = DUPLEX_INVALID;
9889 } else {
9890 tp->link_config.advertising = 0;
9891 tp->link_config.speed = cmd->speed;
9892 tp->link_config.duplex = cmd->duplex;
9893 }
9894
9895 tp->link_config.orig_speed = tp->link_config.speed;
9896 tp->link_config.orig_duplex = tp->link_config.duplex;
9897 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9898
9899 if (netif_running(dev))
9900 tg3_setup_phy(tp, 1);
9901
9902 tg3_full_unlock(tp);
9903
9904 return 0;
9905 }
9906
9907 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9908 {
9909 struct tg3 *tp = netdev_priv(dev);
9910
9911 strcpy(info->driver, DRV_MODULE_NAME);
9912 strcpy(info->version, DRV_MODULE_VERSION);
9913 strcpy(info->fw_version, tp->fw_ver);
9914 strcpy(info->bus_info, pci_name(tp->pdev));
9915 }
9916
9917 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9918 {
9919 struct tg3 *tp = netdev_priv(dev);
9920
9921 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9922 device_can_wakeup(&tp->pdev->dev))
9923 wol->supported = WAKE_MAGIC;
9924 else
9925 wol->supported = 0;
9926 wol->wolopts = 0;
9927 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9928 device_can_wakeup(&tp->pdev->dev))
9929 wol->wolopts = WAKE_MAGIC;
9930 memset(&wol->sopass, 0, sizeof(wol->sopass));
9931 }
9932
9933 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9934 {
9935 struct tg3 *tp = netdev_priv(dev);
9936 struct device *dp = &tp->pdev->dev;
9937
9938 if (wol->wolopts & ~WAKE_MAGIC)
9939 return -EINVAL;
9940 if ((wol->wolopts & WAKE_MAGIC) &&
9941 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9942 return -EINVAL;
9943
9944 spin_lock_bh(&tp->lock);
9945 if (wol->wolopts & WAKE_MAGIC) {
9946 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9947 device_set_wakeup_enable(dp, true);
9948 } else {
9949 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9950 device_set_wakeup_enable(dp, false);
9951 }
9952 spin_unlock_bh(&tp->lock);
9953
9954 return 0;
9955 }
9956
9957 static u32 tg3_get_msglevel(struct net_device *dev)
9958 {
9959 struct tg3 *tp = netdev_priv(dev);
9960 return tp->msg_enable;
9961 }
9962
9963 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9964 {
9965 struct tg3 *tp = netdev_priv(dev);
9966 tp->msg_enable = value;
9967 }
9968
9969 static int tg3_set_tso(struct net_device *dev, u32 value)
9970 {
9971 struct tg3 *tp = netdev_priv(dev);
9972
9973 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9974 if (value)
9975 return -EINVAL;
9976 return 0;
9977 }
9978 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9979 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9980 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9981 if (value) {
9982 dev->features |= NETIF_F_TSO6;
9983 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9985 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9986 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9987 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9989 dev->features |= NETIF_F_TSO_ECN;
9990 } else
9991 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9992 }
9993 return ethtool_op_set_tso(dev, value);
9994 }
9995
9996 static int tg3_nway_reset(struct net_device *dev)
9997 {
9998 struct tg3 *tp = netdev_priv(dev);
9999 int r;
10000
10001 if (!netif_running(dev))
10002 return -EAGAIN;
10003
10004 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10005 return -EINVAL;
10006
10007 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10008 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10009 return -EAGAIN;
10010 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10011 } else {
10012 u32 bmcr;
10013
10014 spin_lock_bh(&tp->lock);
10015 r = -EINVAL;
10016 tg3_readphy(tp, MII_BMCR, &bmcr);
10017 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10018 ((bmcr & BMCR_ANENABLE) ||
10019 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10020 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10021 BMCR_ANENABLE);
10022 r = 0;
10023 }
10024 spin_unlock_bh(&tp->lock);
10025 }
10026
10027 return r;
10028 }
10029
10030 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10031 {
10032 struct tg3 *tp = netdev_priv(dev);
10033
10034 ering->rx_max_pending = tp->rx_std_ring_mask;
10035 ering->rx_mini_max_pending = 0;
10036 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10037 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10038 else
10039 ering->rx_jumbo_max_pending = 0;
10040
10041 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10042
10043 ering->rx_pending = tp->rx_pending;
10044 ering->rx_mini_pending = 0;
10045 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10046 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10047 else
10048 ering->rx_jumbo_pending = 0;
10049
10050 ering->tx_pending = tp->napi[0].tx_pending;
10051 }
10052
10053 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10054 {
10055 struct tg3 *tp = netdev_priv(dev);
10056 int i, irq_sync = 0, err = 0;
10057
10058 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10059 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10060 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10061 (ering->tx_pending <= MAX_SKB_FRAGS) ||
10062 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10063 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10064 return -EINVAL;
10065
10066 if (netif_running(dev)) {
10067 tg3_phy_stop(tp);
10068 tg3_netif_stop(tp);
10069 irq_sync = 1;
10070 }
10071
10072 tg3_full_lock(tp, irq_sync);
10073
10074 tp->rx_pending = ering->rx_pending;
10075
10076 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10077 tp->rx_pending > 63)
10078 tp->rx_pending = 63;
10079 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10080
10081 for (i = 0; i < tp->irq_max; i++)
10082 tp->napi[i].tx_pending = ering->tx_pending;
10083
10084 if (netif_running(dev)) {
10085 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10086 err = tg3_restart_hw(tp, 1);
10087 if (!err)
10088 tg3_netif_start(tp);
10089 }
10090
10091 tg3_full_unlock(tp);
10092
10093 if (irq_sync && !err)
10094 tg3_phy_start(tp);
10095
10096 return err;
10097 }
10098
10099 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10100 {
10101 struct tg3 *tp = netdev_priv(dev);
10102
10103 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10104
10105 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10106 epause->rx_pause = 1;
10107 else
10108 epause->rx_pause = 0;
10109
10110 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10111 epause->tx_pause = 1;
10112 else
10113 epause->tx_pause = 0;
10114 }
10115
10116 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10117 {
10118 struct tg3 *tp = netdev_priv(dev);
10119 int err = 0;
10120
10121 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10122 u32 newadv;
10123 struct phy_device *phydev;
10124
10125 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10126
10127 if (!(phydev->supported & SUPPORTED_Pause) ||
10128 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10129 (epause->rx_pause != epause->tx_pause)))
10130 return -EINVAL;
10131
10132 tp->link_config.flowctrl = 0;
10133 if (epause->rx_pause) {
10134 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10135
10136 if (epause->tx_pause) {
10137 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10138 newadv = ADVERTISED_Pause;
10139 } else
10140 newadv = ADVERTISED_Pause |
10141 ADVERTISED_Asym_Pause;
10142 } else if (epause->tx_pause) {
10143 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10144 newadv = ADVERTISED_Asym_Pause;
10145 } else
10146 newadv = 0;
10147
10148 if (epause->autoneg)
10149 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10150 else
10151 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10152
10153 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10154 u32 oldadv = phydev->advertising &
10155 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10156 if (oldadv != newadv) {
10157 phydev->advertising &=
10158 ~(ADVERTISED_Pause |
10159 ADVERTISED_Asym_Pause);
10160 phydev->advertising |= newadv;
10161 if (phydev->autoneg) {
10162 /*
10163 * Always renegotiate the link to
10164 * inform our link partner of our
10165 * flow control settings, even if the
10166 * flow control is forced. Let
10167 * tg3_adjust_link() do the final
10168 * flow control setup.
10169 */
10170 return phy_start_aneg(phydev);
10171 }
10172 }
10173
10174 if (!epause->autoneg)
10175 tg3_setup_flow_control(tp, 0, 0);
10176 } else {
10177 tp->link_config.orig_advertising &=
10178 ~(ADVERTISED_Pause |
10179 ADVERTISED_Asym_Pause);
10180 tp->link_config.orig_advertising |= newadv;
10181 }
10182 } else {
10183 int irq_sync = 0;
10184
10185 if (netif_running(dev)) {
10186 tg3_netif_stop(tp);
10187 irq_sync = 1;
10188 }
10189
10190 tg3_full_lock(tp, irq_sync);
10191
10192 if (epause->autoneg)
10193 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10194 else
10195 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10196 if (epause->rx_pause)
10197 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10198 else
10199 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10200 if (epause->tx_pause)
10201 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10202 else
10203 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10204
10205 if (netif_running(dev)) {
10206 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10207 err = tg3_restart_hw(tp, 1);
10208 if (!err)
10209 tg3_netif_start(tp);
10210 }
10211
10212 tg3_full_unlock(tp);
10213 }
10214
10215 return err;
10216 }
10217
10218 static u32 tg3_get_rx_csum(struct net_device *dev)
10219 {
10220 struct tg3 *tp = netdev_priv(dev);
10221 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10222 }
10223
10224 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10225 {
10226 struct tg3 *tp = netdev_priv(dev);
10227
10228 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10229 if (data != 0)
10230 return -EINVAL;
10231 return 0;
10232 }
10233
10234 spin_lock_bh(&tp->lock);
10235 if (data)
10236 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10237 else
10238 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10239 spin_unlock_bh(&tp->lock);
10240
10241 return 0;
10242 }
10243
10244 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10245 {
10246 struct tg3 *tp = netdev_priv(dev);
10247
10248 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10249 if (data != 0)
10250 return -EINVAL;
10251 return 0;
10252 }
10253
10254 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10255 ethtool_op_set_tx_ipv6_csum(dev, data);
10256 else
10257 ethtool_op_set_tx_csum(dev, data);
10258
10259 return 0;
10260 }
10261
10262 static int tg3_get_sset_count(struct net_device *dev, int sset)
10263 {
10264 switch (sset) {
10265 case ETH_SS_TEST:
10266 return TG3_NUM_TEST;
10267 case ETH_SS_STATS:
10268 return TG3_NUM_STATS;
10269 default:
10270 return -EOPNOTSUPP;
10271 }
10272 }
10273
10274 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10275 {
10276 switch (stringset) {
10277 case ETH_SS_STATS:
10278 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10279 break;
10280 case ETH_SS_TEST:
10281 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10282 break;
10283 default:
10284 WARN_ON(1); /* we need a WARN() */
10285 break;
10286 }
10287 }
10288
10289 static int tg3_phys_id(struct net_device *dev, u32 data)
10290 {
10291 struct tg3 *tp = netdev_priv(dev);
10292 int i;
10293
10294 if (!netif_running(tp->dev))
10295 return -EAGAIN;
10296
10297 if (data == 0)
10298 data = UINT_MAX / 2;
10299
10300 for (i = 0; i < (data * 2); i++) {
10301 if ((i % 2) == 0)
10302 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10303 LED_CTRL_1000MBPS_ON |
10304 LED_CTRL_100MBPS_ON |
10305 LED_CTRL_10MBPS_ON |
10306 LED_CTRL_TRAFFIC_OVERRIDE |
10307 LED_CTRL_TRAFFIC_BLINK |
10308 LED_CTRL_TRAFFIC_LED);
10309
10310 else
10311 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10312 LED_CTRL_TRAFFIC_OVERRIDE);
10313
10314 if (msleep_interruptible(500))
10315 break;
10316 }
10317 tw32(MAC_LED_CTRL, tp->led_ctrl);
10318 return 0;
10319 }
10320
10321 static void tg3_get_ethtool_stats(struct net_device *dev,
10322 struct ethtool_stats *estats, u64 *tmp_stats)
10323 {
10324 struct tg3 *tp = netdev_priv(dev);
10325 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10326 }
10327
10328 #define NVRAM_TEST_SIZE 0x100
10329 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10330 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10331 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10332 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10333 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10334
10335 static int tg3_test_nvram(struct tg3 *tp)
10336 {
10337 u32 csum, magic;
10338 __be32 *buf;
10339 int i, j, k, err = 0, size;
10340
10341 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10342 return 0;
10343
10344 if (tg3_nvram_read(tp, 0, &magic) != 0)
10345 return -EIO;
10346
10347 if (magic == TG3_EEPROM_MAGIC)
10348 size = NVRAM_TEST_SIZE;
10349 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10350 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10351 TG3_EEPROM_SB_FORMAT_1) {
10352 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10353 case TG3_EEPROM_SB_REVISION_0:
10354 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10355 break;
10356 case TG3_EEPROM_SB_REVISION_2:
10357 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10358 break;
10359 case TG3_EEPROM_SB_REVISION_3:
10360 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10361 break;
10362 default:
10363 return 0;
10364 }
10365 } else
10366 return 0;
10367 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10368 size = NVRAM_SELFBOOT_HW_SIZE;
10369 else
10370 return -EIO;
10371
10372 buf = kmalloc(size, GFP_KERNEL);
10373 if (buf == NULL)
10374 return -ENOMEM;
10375
10376 err = -EIO;
10377 for (i = 0, j = 0; i < size; i += 4, j++) {
10378 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10379 if (err)
10380 break;
10381 }
10382 if (i < size)
10383 goto out;
10384
10385 /* Selfboot format */
10386 magic = be32_to_cpu(buf[0]);
10387 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10388 TG3_EEPROM_MAGIC_FW) {
10389 u8 *buf8 = (u8 *) buf, csum8 = 0;
10390
10391 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10392 TG3_EEPROM_SB_REVISION_2) {
10393 /* For rev 2, the csum doesn't include the MBA. */
10394 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10395 csum8 += buf8[i];
10396 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10397 csum8 += buf8[i];
10398 } else {
10399 for (i = 0; i < size; i++)
10400 csum8 += buf8[i];
10401 }
10402
10403 if (csum8 == 0) {
10404 err = 0;
10405 goto out;
10406 }
10407
10408 err = -EIO;
10409 goto out;
10410 }
10411
10412 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10413 TG3_EEPROM_MAGIC_HW) {
10414 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10415 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10416 u8 *buf8 = (u8 *) buf;
10417
10418 /* Separate the parity bits and the data bytes. */
10419 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10420 if ((i == 0) || (i == 8)) {
10421 int l;
10422 u8 msk;
10423
10424 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10425 parity[k++] = buf8[i] & msk;
10426 i++;
10427 } else if (i == 16) {
10428 int l;
10429 u8 msk;
10430
10431 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10432 parity[k++] = buf8[i] & msk;
10433 i++;
10434
10435 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10436 parity[k++] = buf8[i] & msk;
10437 i++;
10438 }
10439 data[j++] = buf8[i];
10440 }
10441
10442 err = -EIO;
10443 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10444 u8 hw8 = hweight8(data[i]);
10445
10446 if ((hw8 & 0x1) && parity[i])
10447 goto out;
10448 else if (!(hw8 & 0x1) && !parity[i])
10449 goto out;
10450 }
10451 err = 0;
10452 goto out;
10453 }
10454
10455 /* Bootstrap checksum at offset 0x10 */
10456 csum = calc_crc((unsigned char *) buf, 0x10);
10457 if (csum != be32_to_cpu(buf[0x10/4]))
10458 goto out;
10459
10460 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10461 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10462 if (csum != be32_to_cpu(buf[0xfc/4]))
10463 goto out;
10464
10465 err = 0;
10466
10467 out:
10468 kfree(buf);
10469 return err;
10470 }
10471
10472 #define TG3_SERDES_TIMEOUT_SEC 2
10473 #define TG3_COPPER_TIMEOUT_SEC 6
10474
10475 static int tg3_test_link(struct tg3 *tp)
10476 {
10477 int i, max;
10478
10479 if (!netif_running(tp->dev))
10480 return -ENODEV;
10481
10482 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10483 max = TG3_SERDES_TIMEOUT_SEC;
10484 else
10485 max = TG3_COPPER_TIMEOUT_SEC;
10486
10487 for (i = 0; i < max; i++) {
10488 if (netif_carrier_ok(tp->dev))
10489 return 0;
10490
10491 if (msleep_interruptible(1000))
10492 break;
10493 }
10494
10495 return -EIO;
10496 }
10497
10498 /* Only test the commonly used registers */
10499 static int tg3_test_registers(struct tg3 *tp)
10500 {
10501 int i, is_5705, is_5750;
10502 u32 offset, read_mask, write_mask, val, save_val, read_val;
10503 static struct {
10504 u16 offset;
10505 u16 flags;
10506 #define TG3_FL_5705 0x1
10507 #define TG3_FL_NOT_5705 0x2
10508 #define TG3_FL_NOT_5788 0x4
10509 #define TG3_FL_NOT_5750 0x8
10510 u32 read_mask;
10511 u32 write_mask;
10512 } reg_tbl[] = {
10513 /* MAC Control Registers */
10514 { MAC_MODE, TG3_FL_NOT_5705,
10515 0x00000000, 0x00ef6f8c },
10516 { MAC_MODE, TG3_FL_5705,
10517 0x00000000, 0x01ef6b8c },
10518 { MAC_STATUS, TG3_FL_NOT_5705,
10519 0x03800107, 0x00000000 },
10520 { MAC_STATUS, TG3_FL_5705,
10521 0x03800100, 0x00000000 },
10522 { MAC_ADDR_0_HIGH, 0x0000,
10523 0x00000000, 0x0000ffff },
10524 { MAC_ADDR_0_LOW, 0x0000,
10525 0x00000000, 0xffffffff },
10526 { MAC_RX_MTU_SIZE, 0x0000,
10527 0x00000000, 0x0000ffff },
10528 { MAC_TX_MODE, 0x0000,
10529 0x00000000, 0x00000070 },
10530 { MAC_TX_LENGTHS, 0x0000,
10531 0x00000000, 0x00003fff },
10532 { MAC_RX_MODE, TG3_FL_NOT_5705,
10533 0x00000000, 0x000007fc },
10534 { MAC_RX_MODE, TG3_FL_5705,
10535 0x00000000, 0x000007dc },
10536 { MAC_HASH_REG_0, 0x0000,
10537 0x00000000, 0xffffffff },
10538 { MAC_HASH_REG_1, 0x0000,
10539 0x00000000, 0xffffffff },
10540 { MAC_HASH_REG_2, 0x0000,
10541 0x00000000, 0xffffffff },
10542 { MAC_HASH_REG_3, 0x0000,
10543 0x00000000, 0xffffffff },
10544
10545 /* Receive Data and Receive BD Initiator Control Registers. */
10546 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10547 0x00000000, 0xffffffff },
10548 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10549 0x00000000, 0xffffffff },
10550 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10551 0x00000000, 0x00000003 },
10552 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10553 0x00000000, 0xffffffff },
10554 { RCVDBDI_STD_BD+0, 0x0000,
10555 0x00000000, 0xffffffff },
10556 { RCVDBDI_STD_BD+4, 0x0000,
10557 0x00000000, 0xffffffff },
10558 { RCVDBDI_STD_BD+8, 0x0000,
10559 0x00000000, 0xffff0002 },
10560 { RCVDBDI_STD_BD+0xc, 0x0000,
10561 0x00000000, 0xffffffff },
10562
10563 /* Receive BD Initiator Control Registers. */
10564 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10565 0x00000000, 0xffffffff },
10566 { RCVBDI_STD_THRESH, TG3_FL_5705,
10567 0x00000000, 0x000003ff },
10568 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10569 0x00000000, 0xffffffff },
10570
10571 /* Host Coalescing Control Registers. */
10572 { HOSTCC_MODE, TG3_FL_NOT_5705,
10573 0x00000000, 0x00000004 },
10574 { HOSTCC_MODE, TG3_FL_5705,
10575 0x00000000, 0x000000f6 },
10576 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10577 0x00000000, 0xffffffff },
10578 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10579 0x00000000, 0x000003ff },
10580 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10581 0x00000000, 0xffffffff },
10582 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10583 0x00000000, 0x000003ff },
10584 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10585 0x00000000, 0xffffffff },
10586 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10587 0x00000000, 0x000000ff },
10588 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10589 0x00000000, 0xffffffff },
10590 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10591 0x00000000, 0x000000ff },
10592 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10593 0x00000000, 0xffffffff },
10594 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10595 0x00000000, 0xffffffff },
10596 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10597 0x00000000, 0xffffffff },
10598 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10599 0x00000000, 0x000000ff },
10600 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10601 0x00000000, 0xffffffff },
10602 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10603 0x00000000, 0x000000ff },
10604 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10605 0x00000000, 0xffffffff },
10606 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10607 0x00000000, 0xffffffff },
10608 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10609 0x00000000, 0xffffffff },
10610 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10611 0x00000000, 0xffffffff },
10612 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10613 0x00000000, 0xffffffff },
10614 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10615 0xffffffff, 0x00000000 },
10616 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10617 0xffffffff, 0x00000000 },
10618
10619 /* Buffer Manager Control Registers. */
10620 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10621 0x00000000, 0x007fff80 },
10622 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10623 0x00000000, 0x007fffff },
10624 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10625 0x00000000, 0x0000003f },
10626 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10627 0x00000000, 0x000001ff },
10628 { BUFMGR_MB_HIGH_WATER, 0x0000,
10629 0x00000000, 0x000001ff },
10630 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10631 0xffffffff, 0x00000000 },
10632 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10633 0xffffffff, 0x00000000 },
10634
10635 /* Mailbox Registers */
10636 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10637 0x00000000, 0x000001ff },
10638 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10639 0x00000000, 0x000001ff },
10640 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10641 0x00000000, 0x000007ff },
10642 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10643 0x00000000, 0x000001ff },
10644
10645 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10646 };
10647
10648 is_5705 = is_5750 = 0;
10649 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10650 is_5705 = 1;
10651 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10652 is_5750 = 1;
10653 }
10654
10655 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10656 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10657 continue;
10658
10659 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10660 continue;
10661
10662 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10663 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10664 continue;
10665
10666 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10667 continue;
10668
10669 offset = (u32) reg_tbl[i].offset;
10670 read_mask = reg_tbl[i].read_mask;
10671 write_mask = reg_tbl[i].write_mask;
10672
10673 /* Save the original register content */
10674 save_val = tr32(offset);
10675
10676 /* Determine the read-only value. */
10677 read_val = save_val & read_mask;
10678
10679 /* Write zero to the register, then make sure the read-only bits
10680 * are not changed and the read/write bits are all zeros.
10681 */
10682 tw32(offset, 0);
10683
10684 val = tr32(offset);
10685
10686 /* Test the read-only and read/write bits. */
10687 if (((val & read_mask) != read_val) || (val & write_mask))
10688 goto out;
10689
10690 /* Write ones to all the bits defined by RdMask and WrMask, then
10691 * make sure the read-only bits are not changed and the
10692 * read/write bits are all ones.
10693 */
10694 tw32(offset, read_mask | write_mask);
10695
10696 val = tr32(offset);
10697
10698 /* Test the read-only bits. */
10699 if ((val & read_mask) != read_val)
10700 goto out;
10701
10702 /* Test the read/write bits. */
10703 if ((val & write_mask) != write_mask)
10704 goto out;
10705
10706 tw32(offset, save_val);
10707 }
10708
10709 return 0;
10710
10711 out:
10712 if (netif_msg_hw(tp))
10713 netdev_err(tp->dev,
10714 "Register test failed at offset %x\n", offset);
10715 tw32(offset, save_val);
10716 return -EIO;
10717 }
10718
10719 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10720 {
10721 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10722 int i;
10723 u32 j;
10724
10725 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10726 for (j = 0; j < len; j += 4) {
10727 u32 val;
10728
10729 tg3_write_mem(tp, offset + j, test_pattern[i]);
10730 tg3_read_mem(tp, offset + j, &val);
10731 if (val != test_pattern[i])
10732 return -EIO;
10733 }
10734 }
10735 return 0;
10736 }
10737
10738 static int tg3_test_memory(struct tg3 *tp)
10739 {
10740 static struct mem_entry {
10741 u32 offset;
10742 u32 len;
10743 } mem_tbl_570x[] = {
10744 { 0x00000000, 0x00b50},
10745 { 0x00002000, 0x1c000},
10746 { 0xffffffff, 0x00000}
10747 }, mem_tbl_5705[] = {
10748 { 0x00000100, 0x0000c},
10749 { 0x00000200, 0x00008},
10750 { 0x00004000, 0x00800},
10751 { 0x00006000, 0x01000},
10752 { 0x00008000, 0x02000},
10753 { 0x00010000, 0x0e000},
10754 { 0xffffffff, 0x00000}
10755 }, mem_tbl_5755[] = {
10756 { 0x00000200, 0x00008},
10757 { 0x00004000, 0x00800},
10758 { 0x00006000, 0x00800},
10759 { 0x00008000, 0x02000},
10760 { 0x00010000, 0x0c000},
10761 { 0xffffffff, 0x00000}
10762 }, mem_tbl_5906[] = {
10763 { 0x00000200, 0x00008},
10764 { 0x00004000, 0x00400},
10765 { 0x00006000, 0x00400},
10766 { 0x00008000, 0x01000},
10767 { 0x00010000, 0x01000},
10768 { 0xffffffff, 0x00000}
10769 }, mem_tbl_5717[] = {
10770 { 0x00000200, 0x00008},
10771 { 0x00010000, 0x0a000},
10772 { 0x00020000, 0x13c00},
10773 { 0xffffffff, 0x00000}
10774 }, mem_tbl_57765[] = {
10775 { 0x00000200, 0x00008},
10776 { 0x00004000, 0x00800},
10777 { 0x00006000, 0x09800},
10778 { 0x00010000, 0x0a000},
10779 { 0xffffffff, 0x00000}
10780 };
10781 struct mem_entry *mem_tbl;
10782 int err = 0;
10783 int i;
10784
10785 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10786 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10787 mem_tbl = mem_tbl_5717;
10788 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10789 mem_tbl = mem_tbl_57765;
10790 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10791 mem_tbl = mem_tbl_5755;
10792 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10793 mem_tbl = mem_tbl_5906;
10794 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10795 mem_tbl = mem_tbl_5705;
10796 else
10797 mem_tbl = mem_tbl_570x;
10798
10799 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10800 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10801 if (err)
10802 break;
10803 }
10804
10805 return err;
10806 }
10807
10808 #define TG3_MAC_LOOPBACK 0
10809 #define TG3_PHY_LOOPBACK 1
10810
10811 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10812 {
10813 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10814 u32 desc_idx, coal_now;
10815 struct sk_buff *skb, *rx_skb;
10816 u8 *tx_data;
10817 dma_addr_t map;
10818 int num_pkts, tx_len, rx_len, i, err;
10819 struct tg3_rx_buffer_desc *desc;
10820 struct tg3_napi *tnapi, *rnapi;
10821 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10822
10823 tnapi = &tp->napi[0];
10824 rnapi = &tp->napi[0];
10825 if (tp->irq_cnt > 1) {
10826 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10827 rnapi = &tp->napi[1];
10828 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10829 tnapi = &tp->napi[1];
10830 }
10831 coal_now = tnapi->coal_now | rnapi->coal_now;
10832
10833 if (loopback_mode == TG3_MAC_LOOPBACK) {
10834 /* HW errata - mac loopback fails in some cases on 5780.
10835 * Normal traffic and PHY loopback are not affected by
10836 * errata.
10837 */
10838 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10839 return 0;
10840
10841 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10842 MAC_MODE_PORT_INT_LPBACK;
10843 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10844 mac_mode |= MAC_MODE_LINK_POLARITY;
10845 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10846 mac_mode |= MAC_MODE_PORT_MODE_MII;
10847 else
10848 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10849 tw32(MAC_MODE, mac_mode);
10850 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10851 u32 val;
10852
10853 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10854 tg3_phy_fet_toggle_apd(tp, false);
10855 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10856 } else
10857 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10858
10859 tg3_phy_toggle_automdix(tp, 0);
10860
10861 tg3_writephy(tp, MII_BMCR, val);
10862 udelay(40);
10863
10864 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10865 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10866 tg3_writephy(tp, MII_TG3_FET_PTEST,
10867 MII_TG3_FET_PTEST_FRC_TX_LINK |
10868 MII_TG3_FET_PTEST_FRC_TX_LOCK);
10869 /* The write needs to be flushed for the AC131 */
10870 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10871 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10872 mac_mode |= MAC_MODE_PORT_MODE_MII;
10873 } else
10874 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10875
10876 /* reset to prevent losing 1st rx packet intermittently */
10877 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10878 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10879 udelay(10);
10880 tw32_f(MAC_RX_MODE, tp->rx_mode);
10881 }
10882 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10883 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10884 if (masked_phy_id == TG3_PHY_ID_BCM5401)
10885 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10886 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10887 mac_mode |= MAC_MODE_LINK_POLARITY;
10888 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10889 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10890 }
10891 tw32(MAC_MODE, mac_mode);
10892 } else {
10893 return -EINVAL;
10894 }
10895
10896 err = -EIO;
10897
10898 tx_len = 1514;
10899 skb = netdev_alloc_skb(tp->dev, tx_len);
10900 if (!skb)
10901 return -ENOMEM;
10902
10903 tx_data = skb_put(skb, tx_len);
10904 memcpy(tx_data, tp->dev->dev_addr, 6);
10905 memset(tx_data + 6, 0x0, 8);
10906
10907 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10908
10909 for (i = 14; i < tx_len; i++)
10910 tx_data[i] = (u8) (i & 0xff);
10911
10912 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10913 if (pci_dma_mapping_error(tp->pdev, map)) {
10914 dev_kfree_skb(skb);
10915 return -EIO;
10916 }
10917
10918 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10919 rnapi->coal_now);
10920
10921 udelay(10);
10922
10923 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10924
10925 num_pkts = 0;
10926
10927 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10928
10929 tnapi->tx_prod++;
10930 num_pkts++;
10931
10932 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10933 tr32_mailbox(tnapi->prodmbox);
10934
10935 udelay(10);
10936
10937 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10938 for (i = 0; i < 35; i++) {
10939 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10940 coal_now);
10941
10942 udelay(10);
10943
10944 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10945 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10946 if ((tx_idx == tnapi->tx_prod) &&
10947 (rx_idx == (rx_start_idx + num_pkts)))
10948 break;
10949 }
10950
10951 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10952 dev_kfree_skb(skb);
10953
10954 if (tx_idx != tnapi->tx_prod)
10955 goto out;
10956
10957 if (rx_idx != rx_start_idx + num_pkts)
10958 goto out;
10959
10960 desc = &rnapi->rx_rcb[rx_start_idx];
10961 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10962 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10963 if (opaque_key != RXD_OPAQUE_RING_STD)
10964 goto out;
10965
10966 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10967 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10968 goto out;
10969
10970 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10971 if (rx_len != tx_len)
10972 goto out;
10973
10974 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10975
10976 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10977 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10978
10979 for (i = 14; i < tx_len; i++) {
10980 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10981 goto out;
10982 }
10983 err = 0;
10984
10985 /* tg3_free_rings will unmap and free the rx_skb */
10986 out:
10987 return err;
10988 }
10989
10990 #define TG3_MAC_LOOPBACK_FAILED 1
10991 #define TG3_PHY_LOOPBACK_FAILED 2
10992 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10993 TG3_PHY_LOOPBACK_FAILED)
10994
10995 static int tg3_test_loopback(struct tg3 *tp)
10996 {
10997 int err = 0;
10998 u32 cpmuctrl = 0;
10999
11000 if (!netif_running(tp->dev))
11001 return TG3_LOOPBACK_FAILED;
11002
11003 err = tg3_reset_hw(tp, 1);
11004 if (err)
11005 return TG3_LOOPBACK_FAILED;
11006
11007 /* Turn off gphy autopowerdown. */
11008 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11009 tg3_phy_toggle_apd(tp, false);
11010
11011 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11012 int i;
11013 u32 status;
11014
11015 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11016
11017 /* Wait for up to 40 microseconds to acquire lock. */
11018 for (i = 0; i < 4; i++) {
11019 status = tr32(TG3_CPMU_MUTEX_GNT);
11020 if (status == CPMU_MUTEX_GNT_DRIVER)
11021 break;
11022 udelay(10);
11023 }
11024
11025 if (status != CPMU_MUTEX_GNT_DRIVER)
11026 return TG3_LOOPBACK_FAILED;
11027
11028 /* Turn off link-based power management. */
11029 cpmuctrl = tr32(TG3_CPMU_CTRL);
11030 tw32(TG3_CPMU_CTRL,
11031 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11032 CPMU_CTRL_LINK_AWARE_MODE));
11033 }
11034
11035 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11036 err |= TG3_MAC_LOOPBACK_FAILED;
11037
11038 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11039 tw32(TG3_CPMU_CTRL, cpmuctrl);
11040
11041 /* Release the mutex */
11042 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11043 }
11044
11045 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11046 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11047 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11048 err |= TG3_PHY_LOOPBACK_FAILED;
11049 }
11050
11051 /* Re-enable gphy autopowerdown. */
11052 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11053 tg3_phy_toggle_apd(tp, true);
11054
11055 return err;
11056 }
11057
11058 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11059 u64 *data)
11060 {
11061 struct tg3 *tp = netdev_priv(dev);
11062
11063 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11064 tg3_set_power_state(tp, PCI_D0);
11065
11066 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11067
11068 if (tg3_test_nvram(tp) != 0) {
11069 etest->flags |= ETH_TEST_FL_FAILED;
11070 data[0] = 1;
11071 }
11072 if (tg3_test_link(tp) != 0) {
11073 etest->flags |= ETH_TEST_FL_FAILED;
11074 data[1] = 1;
11075 }
11076 if (etest->flags & ETH_TEST_FL_OFFLINE) {
11077 int err, err2 = 0, irq_sync = 0;
11078
11079 if (netif_running(dev)) {
11080 tg3_phy_stop(tp);
11081 tg3_netif_stop(tp);
11082 irq_sync = 1;
11083 }
11084
11085 tg3_full_lock(tp, irq_sync);
11086
11087 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11088 err = tg3_nvram_lock(tp);
11089 tg3_halt_cpu(tp, RX_CPU_BASE);
11090 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11091 tg3_halt_cpu(tp, TX_CPU_BASE);
11092 if (!err)
11093 tg3_nvram_unlock(tp);
11094
11095 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11096 tg3_phy_reset(tp);
11097
11098 if (tg3_test_registers(tp) != 0) {
11099 etest->flags |= ETH_TEST_FL_FAILED;
11100 data[2] = 1;
11101 }
11102 if (tg3_test_memory(tp) != 0) {
11103 etest->flags |= ETH_TEST_FL_FAILED;
11104 data[3] = 1;
11105 }
11106 if ((data[4] = tg3_test_loopback(tp)) != 0)
11107 etest->flags |= ETH_TEST_FL_FAILED;
11108
11109 tg3_full_unlock(tp);
11110
11111 if (tg3_test_interrupt(tp) != 0) {
11112 etest->flags |= ETH_TEST_FL_FAILED;
11113 data[5] = 1;
11114 }
11115
11116 tg3_full_lock(tp, 0);
11117
11118 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11119 if (netif_running(dev)) {
11120 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11121 err2 = tg3_restart_hw(tp, 1);
11122 if (!err2)
11123 tg3_netif_start(tp);
11124 }
11125
11126 tg3_full_unlock(tp);
11127
11128 if (irq_sync && !err2)
11129 tg3_phy_start(tp);
11130 }
11131 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11132 tg3_set_power_state(tp, PCI_D3hot);
11133
11134 }
11135
11136 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11137 {
11138 struct mii_ioctl_data *data = if_mii(ifr);
11139 struct tg3 *tp = netdev_priv(dev);
11140 int err;
11141
11142 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11143 struct phy_device *phydev;
11144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11145 return -EAGAIN;
11146 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11147 return phy_mii_ioctl(phydev, ifr, cmd);
11148 }
11149
11150 switch (cmd) {
11151 case SIOCGMIIPHY:
11152 data->phy_id = tp->phy_addr;
11153
11154 /* fallthru */
11155 case SIOCGMIIREG: {
11156 u32 mii_regval;
11157
11158 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11159 break; /* We have no PHY */
11160
11161 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11162 return -EAGAIN;
11163
11164 spin_lock_bh(&tp->lock);
11165 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11166 spin_unlock_bh(&tp->lock);
11167
11168 data->val_out = mii_regval;
11169
11170 return err;
11171 }
11172
11173 case SIOCSMIIREG:
11174 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11175 break; /* We have no PHY */
11176
11177 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11178 return -EAGAIN;
11179
11180 spin_lock_bh(&tp->lock);
11181 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11182 spin_unlock_bh(&tp->lock);
11183
11184 return err;
11185
11186 default:
11187 /* do nothing */
11188 break;
11189 }
11190 return -EOPNOTSUPP;
11191 }
11192
11193 #if TG3_VLAN_TAG_USED
11194 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11195 {
11196 struct tg3 *tp = netdev_priv(dev);
11197
11198 if (!netif_running(dev)) {
11199 tp->vlgrp = grp;
11200 return;
11201 }
11202
11203 tg3_netif_stop(tp);
11204
11205 tg3_full_lock(tp, 0);
11206
11207 tp->vlgrp = grp;
11208
11209 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11210 __tg3_set_rx_mode(dev);
11211
11212 tg3_netif_start(tp);
11213
11214 tg3_full_unlock(tp);
11215 }
11216 #endif
11217
11218 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11219 {
11220 struct tg3 *tp = netdev_priv(dev);
11221
11222 memcpy(ec, &tp->coal, sizeof(*ec));
11223 return 0;
11224 }
11225
11226 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11227 {
11228 struct tg3 *tp = netdev_priv(dev);
11229 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11230 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11231
11232 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11233 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11234 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11235 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11236 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11237 }
11238
11239 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11240 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11241 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11242 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11243 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11244 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11245 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11246 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11247 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11248 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11249 return -EINVAL;
11250
11251 /* No rx interrupts will be generated if both are zero */
11252 if ((ec->rx_coalesce_usecs == 0) &&
11253 (ec->rx_max_coalesced_frames == 0))
11254 return -EINVAL;
11255
11256 /* No tx interrupts will be generated if both are zero */
11257 if ((ec->tx_coalesce_usecs == 0) &&
11258 (ec->tx_max_coalesced_frames == 0))
11259 return -EINVAL;
11260
11261 /* Only copy relevant parameters, ignore all others. */
11262 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11263 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11264 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11265 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11266 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11267 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11268 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11269 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11270 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11271
11272 if (netif_running(dev)) {
11273 tg3_full_lock(tp, 0);
11274 __tg3_set_coalesce(tp, &tp->coal);
11275 tg3_full_unlock(tp);
11276 }
11277 return 0;
11278 }
11279
11280 static const struct ethtool_ops tg3_ethtool_ops = {
11281 .get_settings = tg3_get_settings,
11282 .set_settings = tg3_set_settings,
11283 .get_drvinfo = tg3_get_drvinfo,
11284 .get_regs_len = tg3_get_regs_len,
11285 .get_regs = tg3_get_regs,
11286 .get_wol = tg3_get_wol,
11287 .set_wol = tg3_set_wol,
11288 .get_msglevel = tg3_get_msglevel,
11289 .set_msglevel = tg3_set_msglevel,
11290 .nway_reset = tg3_nway_reset,
11291 .get_link = ethtool_op_get_link,
11292 .get_eeprom_len = tg3_get_eeprom_len,
11293 .get_eeprom = tg3_get_eeprom,
11294 .set_eeprom = tg3_set_eeprom,
11295 .get_ringparam = tg3_get_ringparam,
11296 .set_ringparam = tg3_set_ringparam,
11297 .get_pauseparam = tg3_get_pauseparam,
11298 .set_pauseparam = tg3_set_pauseparam,
11299 .get_rx_csum = tg3_get_rx_csum,
11300 .set_rx_csum = tg3_set_rx_csum,
11301 .set_tx_csum = tg3_set_tx_csum,
11302 .set_sg = ethtool_op_set_sg,
11303 .set_tso = tg3_set_tso,
11304 .self_test = tg3_self_test,
11305 .get_strings = tg3_get_strings,
11306 .phys_id = tg3_phys_id,
11307 .get_ethtool_stats = tg3_get_ethtool_stats,
11308 .get_coalesce = tg3_get_coalesce,
11309 .set_coalesce = tg3_set_coalesce,
11310 .get_sset_count = tg3_get_sset_count,
11311 };
11312
11313 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11314 {
11315 u32 cursize, val, magic;
11316
11317 tp->nvram_size = EEPROM_CHIP_SIZE;
11318
11319 if (tg3_nvram_read(tp, 0, &magic) != 0)
11320 return;
11321
11322 if ((magic != TG3_EEPROM_MAGIC) &&
11323 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11324 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11325 return;
11326
11327 /*
11328 * Size the chip by reading offsets at increasing powers of two.
11329 * When we encounter our validation signature, we know the addressing
11330 * has wrapped around, and thus have our chip size.
11331 */
11332 cursize = 0x10;
11333
11334 while (cursize < tp->nvram_size) {
11335 if (tg3_nvram_read(tp, cursize, &val) != 0)
11336 return;
11337
11338 if (val == magic)
11339 break;
11340
11341 cursize <<= 1;
11342 }
11343
11344 tp->nvram_size = cursize;
11345 }
11346
11347 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11348 {
11349 u32 val;
11350
11351 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11352 tg3_nvram_read(tp, 0, &val) != 0)
11353 return;
11354
11355 /* Selfboot format */
11356 if (val != TG3_EEPROM_MAGIC) {
11357 tg3_get_eeprom_size(tp);
11358 return;
11359 }
11360
11361 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11362 if (val != 0) {
11363 /* This is confusing. We want to operate on the
11364 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11365 * call will read from NVRAM and byteswap the data
11366 * according to the byteswapping settings for all
11367 * other register accesses. This ensures the data we
11368 * want will always reside in the lower 16-bits.
11369 * However, the data in NVRAM is in LE format, which
11370 * means the data from the NVRAM read will always be
11371 * opposite the endianness of the CPU. The 16-bit
11372 * byteswap then brings the data to CPU endianness.
11373 */
11374 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11375 return;
11376 }
11377 }
11378 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11379 }
11380
11381 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11382 {
11383 u32 nvcfg1;
11384
11385 nvcfg1 = tr32(NVRAM_CFG1);
11386 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11387 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11388 } else {
11389 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11390 tw32(NVRAM_CFG1, nvcfg1);
11391 }
11392
11393 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11394 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11395 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11396 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11397 tp->nvram_jedecnum = JEDEC_ATMEL;
11398 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11399 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11400 break;
11401 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11402 tp->nvram_jedecnum = JEDEC_ATMEL;
11403 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11404 break;
11405 case FLASH_VENDOR_ATMEL_EEPROM:
11406 tp->nvram_jedecnum = JEDEC_ATMEL;
11407 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11408 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11409 break;
11410 case FLASH_VENDOR_ST:
11411 tp->nvram_jedecnum = JEDEC_ST;
11412 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11413 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11414 break;
11415 case FLASH_VENDOR_SAIFUN:
11416 tp->nvram_jedecnum = JEDEC_SAIFUN;
11417 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11418 break;
11419 case FLASH_VENDOR_SST_SMALL:
11420 case FLASH_VENDOR_SST_LARGE:
11421 tp->nvram_jedecnum = JEDEC_SST;
11422 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11423 break;
11424 }
11425 } else {
11426 tp->nvram_jedecnum = JEDEC_ATMEL;
11427 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11428 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11429 }
11430 }
11431
11432 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11433 {
11434 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11435 case FLASH_5752PAGE_SIZE_256:
11436 tp->nvram_pagesize = 256;
11437 break;
11438 case FLASH_5752PAGE_SIZE_512:
11439 tp->nvram_pagesize = 512;
11440 break;
11441 case FLASH_5752PAGE_SIZE_1K:
11442 tp->nvram_pagesize = 1024;
11443 break;
11444 case FLASH_5752PAGE_SIZE_2K:
11445 tp->nvram_pagesize = 2048;
11446 break;
11447 case FLASH_5752PAGE_SIZE_4K:
11448 tp->nvram_pagesize = 4096;
11449 break;
11450 case FLASH_5752PAGE_SIZE_264:
11451 tp->nvram_pagesize = 264;
11452 break;
11453 case FLASH_5752PAGE_SIZE_528:
11454 tp->nvram_pagesize = 528;
11455 break;
11456 }
11457 }
11458
11459 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11460 {
11461 u32 nvcfg1;
11462
11463 nvcfg1 = tr32(NVRAM_CFG1);
11464
11465 /* NVRAM protection for TPM */
11466 if (nvcfg1 & (1 << 27))
11467 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11468
11469 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11470 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11471 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11472 tp->nvram_jedecnum = JEDEC_ATMEL;
11473 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11474 break;
11475 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11476 tp->nvram_jedecnum = JEDEC_ATMEL;
11477 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11478 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11479 break;
11480 case FLASH_5752VENDOR_ST_M45PE10:
11481 case FLASH_5752VENDOR_ST_M45PE20:
11482 case FLASH_5752VENDOR_ST_M45PE40:
11483 tp->nvram_jedecnum = JEDEC_ST;
11484 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11485 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11486 break;
11487 }
11488
11489 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11490 tg3_nvram_get_pagesize(tp, nvcfg1);
11491 } else {
11492 /* For eeprom, set pagesize to maximum eeprom size */
11493 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11494
11495 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11496 tw32(NVRAM_CFG1, nvcfg1);
11497 }
11498 }
11499
11500 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11501 {
11502 u32 nvcfg1, protect = 0;
11503
11504 nvcfg1 = tr32(NVRAM_CFG1);
11505
11506 /* NVRAM protection for TPM */
11507 if (nvcfg1 & (1 << 27)) {
11508 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11509 protect = 1;
11510 }
11511
11512 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11513 switch (nvcfg1) {
11514 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11515 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11516 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11517 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11518 tp->nvram_jedecnum = JEDEC_ATMEL;
11519 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11520 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11521 tp->nvram_pagesize = 264;
11522 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11523 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11524 tp->nvram_size = (protect ? 0x3e200 :
11525 TG3_NVRAM_SIZE_512KB);
11526 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11527 tp->nvram_size = (protect ? 0x1f200 :
11528 TG3_NVRAM_SIZE_256KB);
11529 else
11530 tp->nvram_size = (protect ? 0x1f200 :
11531 TG3_NVRAM_SIZE_128KB);
11532 break;
11533 case FLASH_5752VENDOR_ST_M45PE10:
11534 case FLASH_5752VENDOR_ST_M45PE20:
11535 case FLASH_5752VENDOR_ST_M45PE40:
11536 tp->nvram_jedecnum = JEDEC_ST;
11537 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11538 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11539 tp->nvram_pagesize = 256;
11540 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11541 tp->nvram_size = (protect ?
11542 TG3_NVRAM_SIZE_64KB :
11543 TG3_NVRAM_SIZE_128KB);
11544 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11545 tp->nvram_size = (protect ?
11546 TG3_NVRAM_SIZE_64KB :
11547 TG3_NVRAM_SIZE_256KB);
11548 else
11549 tp->nvram_size = (protect ?
11550 TG3_NVRAM_SIZE_128KB :
11551 TG3_NVRAM_SIZE_512KB);
11552 break;
11553 }
11554 }
11555
11556 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11557 {
11558 u32 nvcfg1;
11559
11560 nvcfg1 = tr32(NVRAM_CFG1);
11561
11562 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11563 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11564 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11565 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11566 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11567 tp->nvram_jedecnum = JEDEC_ATMEL;
11568 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11569 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11570
11571 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11572 tw32(NVRAM_CFG1, nvcfg1);
11573 break;
11574 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11575 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11576 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11577 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11578 tp->nvram_jedecnum = JEDEC_ATMEL;
11579 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11580 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11581 tp->nvram_pagesize = 264;
11582 break;
11583 case FLASH_5752VENDOR_ST_M45PE10:
11584 case FLASH_5752VENDOR_ST_M45PE20:
11585 case FLASH_5752VENDOR_ST_M45PE40:
11586 tp->nvram_jedecnum = JEDEC_ST;
11587 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11588 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11589 tp->nvram_pagesize = 256;
11590 break;
11591 }
11592 }
11593
11594 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11595 {
11596 u32 nvcfg1, protect = 0;
11597
11598 nvcfg1 = tr32(NVRAM_CFG1);
11599
11600 /* NVRAM protection for TPM */
11601 if (nvcfg1 & (1 << 27)) {
11602 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11603 protect = 1;
11604 }
11605
11606 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11607 switch (nvcfg1) {
11608 case FLASH_5761VENDOR_ATMEL_ADB021D:
11609 case FLASH_5761VENDOR_ATMEL_ADB041D:
11610 case FLASH_5761VENDOR_ATMEL_ADB081D:
11611 case FLASH_5761VENDOR_ATMEL_ADB161D:
11612 case FLASH_5761VENDOR_ATMEL_MDB021D:
11613 case FLASH_5761VENDOR_ATMEL_MDB041D:
11614 case FLASH_5761VENDOR_ATMEL_MDB081D:
11615 case FLASH_5761VENDOR_ATMEL_MDB161D:
11616 tp->nvram_jedecnum = JEDEC_ATMEL;
11617 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11618 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11619 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11620 tp->nvram_pagesize = 256;
11621 break;
11622 case FLASH_5761VENDOR_ST_A_M45PE20:
11623 case FLASH_5761VENDOR_ST_A_M45PE40:
11624 case FLASH_5761VENDOR_ST_A_M45PE80:
11625 case FLASH_5761VENDOR_ST_A_M45PE16:
11626 case FLASH_5761VENDOR_ST_M_M45PE20:
11627 case FLASH_5761VENDOR_ST_M_M45PE40:
11628 case FLASH_5761VENDOR_ST_M_M45PE80:
11629 case FLASH_5761VENDOR_ST_M_M45PE16:
11630 tp->nvram_jedecnum = JEDEC_ST;
11631 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11632 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11633 tp->nvram_pagesize = 256;
11634 break;
11635 }
11636
11637 if (protect) {
11638 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11639 } else {
11640 switch (nvcfg1) {
11641 case FLASH_5761VENDOR_ATMEL_ADB161D:
11642 case FLASH_5761VENDOR_ATMEL_MDB161D:
11643 case FLASH_5761VENDOR_ST_A_M45PE16:
11644 case FLASH_5761VENDOR_ST_M_M45PE16:
11645 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11646 break;
11647 case FLASH_5761VENDOR_ATMEL_ADB081D:
11648 case FLASH_5761VENDOR_ATMEL_MDB081D:
11649 case FLASH_5761VENDOR_ST_A_M45PE80:
11650 case FLASH_5761VENDOR_ST_M_M45PE80:
11651 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11652 break;
11653 case FLASH_5761VENDOR_ATMEL_ADB041D:
11654 case FLASH_5761VENDOR_ATMEL_MDB041D:
11655 case FLASH_5761VENDOR_ST_A_M45PE40:
11656 case FLASH_5761VENDOR_ST_M_M45PE40:
11657 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11658 break;
11659 case FLASH_5761VENDOR_ATMEL_ADB021D:
11660 case FLASH_5761VENDOR_ATMEL_MDB021D:
11661 case FLASH_5761VENDOR_ST_A_M45PE20:
11662 case FLASH_5761VENDOR_ST_M_M45PE20:
11663 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11664 break;
11665 }
11666 }
11667 }
11668
11669 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11670 {
11671 tp->nvram_jedecnum = JEDEC_ATMEL;
11672 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11673 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11674 }
11675
11676 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11677 {
11678 u32 nvcfg1;
11679
11680 nvcfg1 = tr32(NVRAM_CFG1);
11681
11682 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11683 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11684 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11685 tp->nvram_jedecnum = JEDEC_ATMEL;
11686 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11687 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11688
11689 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11690 tw32(NVRAM_CFG1, nvcfg1);
11691 return;
11692 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11693 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11694 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11695 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11696 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11697 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11698 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11699 tp->nvram_jedecnum = JEDEC_ATMEL;
11700 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11701 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11702
11703 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11704 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11705 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11706 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11707 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11708 break;
11709 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11710 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11711 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11712 break;
11713 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11714 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11715 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11716 break;
11717 }
11718 break;
11719 case FLASH_5752VENDOR_ST_M45PE10:
11720 case FLASH_5752VENDOR_ST_M45PE20:
11721 case FLASH_5752VENDOR_ST_M45PE40:
11722 tp->nvram_jedecnum = JEDEC_ST;
11723 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11724 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11725
11726 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11727 case FLASH_5752VENDOR_ST_M45PE10:
11728 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11729 break;
11730 case FLASH_5752VENDOR_ST_M45PE20:
11731 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11732 break;
11733 case FLASH_5752VENDOR_ST_M45PE40:
11734 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11735 break;
11736 }
11737 break;
11738 default:
11739 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11740 return;
11741 }
11742
11743 tg3_nvram_get_pagesize(tp, nvcfg1);
11744 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11745 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11746 }
11747
11748
11749 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11750 {
11751 u32 nvcfg1;
11752
11753 nvcfg1 = tr32(NVRAM_CFG1);
11754
11755 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11756 case FLASH_5717VENDOR_ATMEL_EEPROM:
11757 case FLASH_5717VENDOR_MICRO_EEPROM:
11758 tp->nvram_jedecnum = JEDEC_ATMEL;
11759 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11760 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11761
11762 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11763 tw32(NVRAM_CFG1, nvcfg1);
11764 return;
11765 case FLASH_5717VENDOR_ATMEL_MDB011D:
11766 case FLASH_5717VENDOR_ATMEL_ADB011B:
11767 case FLASH_5717VENDOR_ATMEL_ADB011D:
11768 case FLASH_5717VENDOR_ATMEL_MDB021D:
11769 case FLASH_5717VENDOR_ATMEL_ADB021B:
11770 case FLASH_5717VENDOR_ATMEL_ADB021D:
11771 case FLASH_5717VENDOR_ATMEL_45USPT:
11772 tp->nvram_jedecnum = JEDEC_ATMEL;
11773 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11774 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11775
11776 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11777 case FLASH_5717VENDOR_ATMEL_MDB021D:
11778 case FLASH_5717VENDOR_ATMEL_ADB021B:
11779 case FLASH_5717VENDOR_ATMEL_ADB021D:
11780 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11781 break;
11782 default:
11783 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11784 break;
11785 }
11786 break;
11787 case FLASH_5717VENDOR_ST_M_M25PE10:
11788 case FLASH_5717VENDOR_ST_A_M25PE10:
11789 case FLASH_5717VENDOR_ST_M_M45PE10:
11790 case FLASH_5717VENDOR_ST_A_M45PE10:
11791 case FLASH_5717VENDOR_ST_M_M25PE20:
11792 case FLASH_5717VENDOR_ST_A_M25PE20:
11793 case FLASH_5717VENDOR_ST_M_M45PE20:
11794 case FLASH_5717VENDOR_ST_A_M45PE20:
11795 case FLASH_5717VENDOR_ST_25USPT:
11796 case FLASH_5717VENDOR_ST_45USPT:
11797 tp->nvram_jedecnum = JEDEC_ST;
11798 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11799 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11800
11801 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11802 case FLASH_5717VENDOR_ST_M_M25PE20:
11803 case FLASH_5717VENDOR_ST_A_M25PE20:
11804 case FLASH_5717VENDOR_ST_M_M45PE20:
11805 case FLASH_5717VENDOR_ST_A_M45PE20:
11806 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11807 break;
11808 default:
11809 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11810 break;
11811 }
11812 break;
11813 default:
11814 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11815 return;
11816 }
11817
11818 tg3_nvram_get_pagesize(tp, nvcfg1);
11819 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11820 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11821 }
11822
11823 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11824 static void __devinit tg3_nvram_init(struct tg3 *tp)
11825 {
11826 tw32_f(GRC_EEPROM_ADDR,
11827 (EEPROM_ADDR_FSM_RESET |
11828 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11829 EEPROM_ADDR_CLKPERD_SHIFT)));
11830
11831 msleep(1);
11832
11833 /* Enable seeprom accesses. */
11834 tw32_f(GRC_LOCAL_CTRL,
11835 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11836 udelay(100);
11837
11838 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11839 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11840 tp->tg3_flags |= TG3_FLAG_NVRAM;
11841
11842 if (tg3_nvram_lock(tp)) {
11843 netdev_warn(tp->dev,
11844 "Cannot get nvram lock, %s failed\n",
11845 __func__);
11846 return;
11847 }
11848 tg3_enable_nvram_access(tp);
11849
11850 tp->nvram_size = 0;
11851
11852 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11853 tg3_get_5752_nvram_info(tp);
11854 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11855 tg3_get_5755_nvram_info(tp);
11856 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11858 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11859 tg3_get_5787_nvram_info(tp);
11860 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11861 tg3_get_5761_nvram_info(tp);
11862 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11863 tg3_get_5906_nvram_info(tp);
11864 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11865 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11866 tg3_get_57780_nvram_info(tp);
11867 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11868 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11869 tg3_get_5717_nvram_info(tp);
11870 else
11871 tg3_get_nvram_info(tp);
11872
11873 if (tp->nvram_size == 0)
11874 tg3_get_nvram_size(tp);
11875
11876 tg3_disable_nvram_access(tp);
11877 tg3_nvram_unlock(tp);
11878
11879 } else {
11880 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11881
11882 tg3_get_eeprom_size(tp);
11883 }
11884 }
11885
11886 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11887 u32 offset, u32 len, u8 *buf)
11888 {
11889 int i, j, rc = 0;
11890 u32 val;
11891
11892 for (i = 0; i < len; i += 4) {
11893 u32 addr;
11894 __be32 data;
11895
11896 addr = offset + i;
11897
11898 memcpy(&data, buf + i, 4);
11899
11900 /*
11901 * The SEEPROM interface expects the data to always be opposite
11902 * the native endian format. We accomplish this by reversing
11903 * all the operations that would have been performed on the
11904 * data from a call to tg3_nvram_read_be32().
11905 */
11906 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11907
11908 val = tr32(GRC_EEPROM_ADDR);
11909 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11910
11911 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11912 EEPROM_ADDR_READ);
11913 tw32(GRC_EEPROM_ADDR, val |
11914 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11915 (addr & EEPROM_ADDR_ADDR_MASK) |
11916 EEPROM_ADDR_START |
11917 EEPROM_ADDR_WRITE);
11918
11919 for (j = 0; j < 1000; j++) {
11920 val = tr32(GRC_EEPROM_ADDR);
11921
11922 if (val & EEPROM_ADDR_COMPLETE)
11923 break;
11924 msleep(1);
11925 }
11926 if (!(val & EEPROM_ADDR_COMPLETE)) {
11927 rc = -EBUSY;
11928 break;
11929 }
11930 }
11931
11932 return rc;
11933 }
11934
11935 /* offset and length are dword aligned */
11936 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11937 u8 *buf)
11938 {
11939 int ret = 0;
11940 u32 pagesize = tp->nvram_pagesize;
11941 u32 pagemask = pagesize - 1;
11942 u32 nvram_cmd;
11943 u8 *tmp;
11944
11945 tmp = kmalloc(pagesize, GFP_KERNEL);
11946 if (tmp == NULL)
11947 return -ENOMEM;
11948
11949 while (len) {
11950 int j;
11951 u32 phy_addr, page_off, size;
11952
11953 phy_addr = offset & ~pagemask;
11954
11955 for (j = 0; j < pagesize; j += 4) {
11956 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11957 (__be32 *) (tmp + j));
11958 if (ret)
11959 break;
11960 }
11961 if (ret)
11962 break;
11963
11964 page_off = offset & pagemask;
11965 size = pagesize;
11966 if (len < size)
11967 size = len;
11968
11969 len -= size;
11970
11971 memcpy(tmp + page_off, buf, size);
11972
11973 offset = offset + (pagesize - page_off);
11974
11975 tg3_enable_nvram_access(tp);
11976
11977 /*
11978 * Before we can erase the flash page, we need
11979 * to issue a special "write enable" command.
11980 */
11981 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11982
11983 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11984 break;
11985
11986 /* Erase the target page */
11987 tw32(NVRAM_ADDR, phy_addr);
11988
11989 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11990 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11991
11992 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11993 break;
11994
11995 /* Issue another write enable to start the write. */
11996 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11997
11998 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11999 break;
12000
12001 for (j = 0; j < pagesize; j += 4) {
12002 __be32 data;
12003
12004 data = *((__be32 *) (tmp + j));
12005
12006 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12007
12008 tw32(NVRAM_ADDR, phy_addr + j);
12009
12010 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12011 NVRAM_CMD_WR;
12012
12013 if (j == 0)
12014 nvram_cmd |= NVRAM_CMD_FIRST;
12015 else if (j == (pagesize - 4))
12016 nvram_cmd |= NVRAM_CMD_LAST;
12017
12018 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12019 break;
12020 }
12021 if (ret)
12022 break;
12023 }
12024
12025 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12026 tg3_nvram_exec_cmd(tp, nvram_cmd);
12027
12028 kfree(tmp);
12029
12030 return ret;
12031 }
12032
12033 /* offset and length are dword aligned */
12034 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12035 u8 *buf)
12036 {
12037 int i, ret = 0;
12038
12039 for (i = 0; i < len; i += 4, offset += 4) {
12040 u32 page_off, phy_addr, nvram_cmd;
12041 __be32 data;
12042
12043 memcpy(&data, buf + i, 4);
12044 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12045
12046 page_off = offset % tp->nvram_pagesize;
12047
12048 phy_addr = tg3_nvram_phys_addr(tp, offset);
12049
12050 tw32(NVRAM_ADDR, phy_addr);
12051
12052 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12053
12054 if (page_off == 0 || i == 0)
12055 nvram_cmd |= NVRAM_CMD_FIRST;
12056 if (page_off == (tp->nvram_pagesize - 4))
12057 nvram_cmd |= NVRAM_CMD_LAST;
12058
12059 if (i == (len - 4))
12060 nvram_cmd |= NVRAM_CMD_LAST;
12061
12062 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12063 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12064 (tp->nvram_jedecnum == JEDEC_ST) &&
12065 (nvram_cmd & NVRAM_CMD_FIRST)) {
12066
12067 if ((ret = tg3_nvram_exec_cmd(tp,
12068 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12069 NVRAM_CMD_DONE)))
12070
12071 break;
12072 }
12073 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12074 /* We always do complete word writes to eeprom. */
12075 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12076 }
12077
12078 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12079 break;
12080 }
12081 return ret;
12082 }
12083
12084 /* offset and length are dword aligned */
12085 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12086 {
12087 int ret;
12088
12089 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12090 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12091 ~GRC_LCLCTRL_GPIO_OUTPUT1);
12092 udelay(40);
12093 }
12094
12095 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12096 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12097 } else {
12098 u32 grc_mode;
12099
12100 ret = tg3_nvram_lock(tp);
12101 if (ret)
12102 return ret;
12103
12104 tg3_enable_nvram_access(tp);
12105 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12106 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12107 tw32(NVRAM_WRITE1, 0x406);
12108
12109 grc_mode = tr32(GRC_MODE);
12110 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12111
12112 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12113 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12114
12115 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12116 buf);
12117 } else {
12118 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12119 buf);
12120 }
12121
12122 grc_mode = tr32(GRC_MODE);
12123 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12124
12125 tg3_disable_nvram_access(tp);
12126 tg3_nvram_unlock(tp);
12127 }
12128
12129 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12130 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12131 udelay(40);
12132 }
12133
12134 return ret;
12135 }
12136
12137 struct subsys_tbl_ent {
12138 u16 subsys_vendor, subsys_devid;
12139 u32 phy_id;
12140 };
12141
12142 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12143 /* Broadcom boards. */
12144 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12145 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12146 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12147 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12148 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12149 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12150 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12151 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12152 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12153 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12154 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12155 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12156 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12157 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12158 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12159 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12160 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12161 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12162 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12163 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12164 { TG3PCI_SUBVENDOR_ID_BROADCOM,
12165 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12166
12167 /* 3com boards. */
12168 { TG3PCI_SUBVENDOR_ID_3COM,
12169 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12170 { TG3PCI_SUBVENDOR_ID_3COM,
12171 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12172 { TG3PCI_SUBVENDOR_ID_3COM,
12173 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12174 { TG3PCI_SUBVENDOR_ID_3COM,
12175 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12176 { TG3PCI_SUBVENDOR_ID_3COM,
12177 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12178
12179 /* DELL boards. */
12180 { TG3PCI_SUBVENDOR_ID_DELL,
12181 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12182 { TG3PCI_SUBVENDOR_ID_DELL,
12183 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12184 { TG3PCI_SUBVENDOR_ID_DELL,
12185 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12186 { TG3PCI_SUBVENDOR_ID_DELL,
12187 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12188
12189 /* Compaq boards. */
12190 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12191 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12192 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12193 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12194 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12195 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12196 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12197 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12198 { TG3PCI_SUBVENDOR_ID_COMPAQ,
12199 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12200
12201 /* IBM boards. */
12202 { TG3PCI_SUBVENDOR_ID_IBM,
12203 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12204 };
12205
12206 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12207 {
12208 int i;
12209
12210 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12211 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12212 tp->pdev->subsystem_vendor) &&
12213 (subsys_id_to_phy_id[i].subsys_devid ==
12214 tp->pdev->subsystem_device))
12215 return &subsys_id_to_phy_id[i];
12216 }
12217 return NULL;
12218 }
12219
12220 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12221 {
12222 u32 val;
12223 u16 pmcsr;
12224
12225 /* On some early chips the SRAM cannot be accessed in D3hot state,
12226 * so need make sure we're in D0.
12227 */
12228 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12229 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12230 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12231 msleep(1);
12232
12233 /* Make sure register accesses (indirect or otherwise)
12234 * will function correctly.
12235 */
12236 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12237 tp->misc_host_ctrl);
12238
12239 /* The memory arbiter has to be enabled in order for SRAM accesses
12240 * to succeed. Normally on powerup the tg3 chip firmware will make
12241 * sure it is enabled, but other entities such as system netboot
12242 * code might disable it.
12243 */
12244 val = tr32(MEMARB_MODE);
12245 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12246
12247 tp->phy_id = TG3_PHY_ID_INVALID;
12248 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12249
12250 /* Assume an onboard device and WOL capable by default. */
12251 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12252
12253 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12254 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12255 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12256 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12257 }
12258 val = tr32(VCPU_CFGSHDW);
12259 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12260 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12261 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12262 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12263 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12264 goto done;
12265 }
12266
12267 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12268 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12269 u32 nic_cfg, led_cfg;
12270 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12271 int eeprom_phy_serdes = 0;
12272
12273 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12274 tp->nic_sram_data_cfg = nic_cfg;
12275
12276 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12277 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12278 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12279 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12280 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12281 (ver > 0) && (ver < 0x100))
12282 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12283
12284 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12285 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12286
12287 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12288 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12289 eeprom_phy_serdes = 1;
12290
12291 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12292 if (nic_phy_id != 0) {
12293 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12294 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12295
12296 eeprom_phy_id = (id1 >> 16) << 10;
12297 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12298 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12299 } else
12300 eeprom_phy_id = 0;
12301
12302 tp->phy_id = eeprom_phy_id;
12303 if (eeprom_phy_serdes) {
12304 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12305 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12306 else
12307 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12308 }
12309
12310 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12311 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12312 SHASTA_EXT_LED_MODE_MASK);
12313 else
12314 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12315
12316 switch (led_cfg) {
12317 default:
12318 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12319 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12320 break;
12321
12322 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12323 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12324 break;
12325
12326 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12327 tp->led_ctrl = LED_CTRL_MODE_MAC;
12328
12329 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12330 * read on some older 5700/5701 bootcode.
12331 */
12332 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12333 ASIC_REV_5700 ||
12334 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12335 ASIC_REV_5701)
12336 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12337
12338 break;
12339
12340 case SHASTA_EXT_LED_SHARED:
12341 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12342 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12343 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12344 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12345 LED_CTRL_MODE_PHY_2);
12346 break;
12347
12348 case SHASTA_EXT_LED_MAC:
12349 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12350 break;
12351
12352 case SHASTA_EXT_LED_COMBO:
12353 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12354 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12355 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12356 LED_CTRL_MODE_PHY_2);
12357 break;
12358
12359 }
12360
12361 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12362 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12363 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12364 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12365
12366 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12367 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12368
12369 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12370 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12371 if ((tp->pdev->subsystem_vendor ==
12372 PCI_VENDOR_ID_ARIMA) &&
12373 (tp->pdev->subsystem_device == 0x205a ||
12374 tp->pdev->subsystem_device == 0x2063))
12375 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12376 } else {
12377 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12378 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12379 }
12380
12381 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12382 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12383 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12384 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12385 }
12386
12387 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12388 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12389 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12390
12391 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12392 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12393 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12394
12395 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12396 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12397 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12398
12399 if (cfg2 & (1 << 17))
12400 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12401
12402 /* serdes signal pre-emphasis in register 0x590 set by */
12403 /* bootcode if bit 18 is set */
12404 if (cfg2 & (1 << 18))
12405 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12406
12407 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12408 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12409 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12410 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12411
12412 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12413 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12414 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12415 u32 cfg3;
12416
12417 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12418 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12419 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12420 }
12421
12422 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12423 tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12424 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12425 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12426 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12427 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12428 }
12429 done:
12430 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12431 device_set_wakeup_enable(&tp->pdev->dev,
12432 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12433 }
12434
12435 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12436 {
12437 int i;
12438 u32 val;
12439
12440 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12441 tw32(OTP_CTRL, cmd);
12442
12443 /* Wait for up to 1 ms for command to execute. */
12444 for (i = 0; i < 100; i++) {
12445 val = tr32(OTP_STATUS);
12446 if (val & OTP_STATUS_CMD_DONE)
12447 break;
12448 udelay(10);
12449 }
12450
12451 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12452 }
12453
12454 /* Read the gphy configuration from the OTP region of the chip. The gphy
12455 * configuration is a 32-bit value that straddles the alignment boundary.
12456 * We do two 32-bit reads and then shift and merge the results.
12457 */
12458 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12459 {
12460 u32 bhalf_otp, thalf_otp;
12461
12462 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12463
12464 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12465 return 0;
12466
12467 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12468
12469 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12470 return 0;
12471
12472 thalf_otp = tr32(OTP_READ_DATA);
12473
12474 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12475
12476 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12477 return 0;
12478
12479 bhalf_otp = tr32(OTP_READ_DATA);
12480
12481 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12482 }
12483
12484 static int __devinit tg3_phy_probe(struct tg3 *tp)
12485 {
12486 u32 hw_phy_id_1, hw_phy_id_2;
12487 u32 hw_phy_id, hw_phy_id_masked;
12488 int err;
12489
12490 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12491 return tg3_phy_init(tp);
12492
12493 /* Reading the PHY ID register can conflict with ASF
12494 * firmware access to the PHY hardware.
12495 */
12496 err = 0;
12497 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12498 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12499 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12500 } else {
12501 /* Now read the physical PHY_ID from the chip and verify
12502 * that it is sane. If it doesn't look good, we fall back
12503 * to either the hard-coded table based PHY_ID and failing
12504 * that the value found in the eeprom area.
12505 */
12506 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12507 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12508
12509 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12510 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12511 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12512
12513 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12514 }
12515
12516 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12517 tp->phy_id = hw_phy_id;
12518 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12519 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12520 else
12521 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12522 } else {
12523 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12524 /* Do nothing, phy ID already set up in
12525 * tg3_get_eeprom_hw_cfg().
12526 */
12527 } else {
12528 struct subsys_tbl_ent *p;
12529
12530 /* No eeprom signature? Try the hardcoded
12531 * subsys device table.
12532 */
12533 p = tg3_lookup_by_subsys(tp);
12534 if (!p)
12535 return -ENODEV;
12536
12537 tp->phy_id = p->phy_id;
12538 if (!tp->phy_id ||
12539 tp->phy_id == TG3_PHY_ID_BCM8002)
12540 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12541 }
12542 }
12543
12544 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12545 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12546 tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
12547 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12548
12549 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12550 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12551 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12552 u32 bmsr, adv_reg, tg3_ctrl, mask;
12553
12554 tg3_readphy(tp, MII_BMSR, &bmsr);
12555 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12556 (bmsr & BMSR_LSTATUS))
12557 goto skip_phy_reset;
12558
12559 err = tg3_phy_reset(tp);
12560 if (err)
12561 return err;
12562
12563 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12564 ADVERTISE_100HALF | ADVERTISE_100FULL |
12565 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12566 tg3_ctrl = 0;
12567 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12568 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12569 MII_TG3_CTRL_ADV_1000_FULL);
12570 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12571 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12572 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12573 MII_TG3_CTRL_ENABLE_AS_MASTER);
12574 }
12575
12576 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12577 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12578 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12579 if (!tg3_copper_is_advertising_all(tp, mask)) {
12580 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12581
12582 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12583 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12584
12585 tg3_writephy(tp, MII_BMCR,
12586 BMCR_ANENABLE | BMCR_ANRESTART);
12587 }
12588 tg3_phy_set_wirespeed(tp);
12589
12590 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12591 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12592 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12593 }
12594
12595 skip_phy_reset:
12596 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12597 err = tg3_init_5401phy_dsp(tp);
12598 if (err)
12599 return err;
12600
12601 err = tg3_init_5401phy_dsp(tp);
12602 }
12603
12604 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12605 tp->link_config.advertising =
12606 (ADVERTISED_1000baseT_Half |
12607 ADVERTISED_1000baseT_Full |
12608 ADVERTISED_Autoneg |
12609 ADVERTISED_FIBRE);
12610 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12611 tp->link_config.advertising &=
12612 ~(ADVERTISED_1000baseT_Half |
12613 ADVERTISED_1000baseT_Full);
12614
12615 return err;
12616 }
12617
12618 static void __devinit tg3_read_vpd(struct tg3 *tp)
12619 {
12620 u8 *vpd_data;
12621 unsigned int block_end, rosize, len;
12622 int j, i = 0;
12623 u32 magic;
12624
12625 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12626 tg3_nvram_read(tp, 0x0, &magic))
12627 goto out_no_vpd;
12628
12629 vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12630 if (!vpd_data)
12631 goto out_no_vpd;
12632
12633 if (magic == TG3_EEPROM_MAGIC) {
12634 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12635 u32 tmp;
12636
12637 /* The data is in little-endian format in NVRAM.
12638 * Use the big-endian read routines to preserve
12639 * the byte order as it exists in NVRAM.
12640 */
12641 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12642 goto out_not_found;
12643
12644 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12645 }
12646 } else {
12647 ssize_t cnt;
12648 unsigned int pos = 0;
12649
12650 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12651 cnt = pci_read_vpd(tp->pdev, pos,
12652 TG3_NVM_VPD_LEN - pos,
12653 &vpd_data[pos]);
12654 if (cnt == -ETIMEDOUT || -EINTR)
12655 cnt = 0;
12656 else if (cnt < 0)
12657 goto out_not_found;
12658 }
12659 if (pos != TG3_NVM_VPD_LEN)
12660 goto out_not_found;
12661 }
12662
12663 i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12664 PCI_VPD_LRDT_RO_DATA);
12665 if (i < 0)
12666 goto out_not_found;
12667
12668 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12669 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12670 i += PCI_VPD_LRDT_TAG_SIZE;
12671
12672 if (block_end > TG3_NVM_VPD_LEN)
12673 goto out_not_found;
12674
12675 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12676 PCI_VPD_RO_KEYWORD_MFR_ID);
12677 if (j > 0) {
12678 len = pci_vpd_info_field_size(&vpd_data[j]);
12679
12680 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12681 if (j + len > block_end || len != 4 ||
12682 memcmp(&vpd_data[j], "1028", 4))
12683 goto partno;
12684
12685 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12686 PCI_VPD_RO_KEYWORD_VENDOR0);
12687 if (j < 0)
12688 goto partno;
12689
12690 len = pci_vpd_info_field_size(&vpd_data[j]);
12691
12692 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12693 if (j + len > block_end)
12694 goto partno;
12695
12696 memcpy(tp->fw_ver, &vpd_data[j], len);
12697 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12698 }
12699
12700 partno:
12701 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12702 PCI_VPD_RO_KEYWORD_PARTNO);
12703 if (i < 0)
12704 goto out_not_found;
12705
12706 len = pci_vpd_info_field_size(&vpd_data[i]);
12707
12708 i += PCI_VPD_INFO_FLD_HDR_SIZE;
12709 if (len > TG3_BPN_SIZE ||
12710 (len + i) > TG3_NVM_VPD_LEN)
12711 goto out_not_found;
12712
12713 memcpy(tp->board_part_number, &vpd_data[i], len);
12714
12715 out_not_found:
12716 kfree(vpd_data);
12717 if (tp->board_part_number[0])
12718 return;
12719
12720 out_no_vpd:
12721 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12722 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12723 strcpy(tp->board_part_number, "BCM5717");
12724 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12725 strcpy(tp->board_part_number, "BCM5718");
12726 else
12727 goto nomatch;
12728 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12729 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12730 strcpy(tp->board_part_number, "BCM57780");
12731 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12732 strcpy(tp->board_part_number, "BCM57760");
12733 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12734 strcpy(tp->board_part_number, "BCM57790");
12735 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12736 strcpy(tp->board_part_number, "BCM57788");
12737 else
12738 goto nomatch;
12739 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12740 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12741 strcpy(tp->board_part_number, "BCM57761");
12742 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12743 strcpy(tp->board_part_number, "BCM57765");
12744 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12745 strcpy(tp->board_part_number, "BCM57781");
12746 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12747 strcpy(tp->board_part_number, "BCM57785");
12748 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12749 strcpy(tp->board_part_number, "BCM57791");
12750 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12751 strcpy(tp->board_part_number, "BCM57795");
12752 else
12753 goto nomatch;
12754 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12755 strcpy(tp->board_part_number, "BCM95906");
12756 } else {
12757 nomatch:
12758 strcpy(tp->board_part_number, "none");
12759 }
12760 }
12761
12762 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12763 {
12764 u32 val;
12765
12766 if (tg3_nvram_read(tp, offset, &val) ||
12767 (val & 0xfc000000) != 0x0c000000 ||
12768 tg3_nvram_read(tp, offset + 4, &val) ||
12769 val != 0)
12770 return 0;
12771
12772 return 1;
12773 }
12774
12775 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12776 {
12777 u32 val, offset, start, ver_offset;
12778 int i, dst_off;
12779 bool newver = false;
12780
12781 if (tg3_nvram_read(tp, 0xc, &offset) ||
12782 tg3_nvram_read(tp, 0x4, &start))
12783 return;
12784
12785 offset = tg3_nvram_logical_addr(tp, offset);
12786
12787 if (tg3_nvram_read(tp, offset, &val))
12788 return;
12789
12790 if ((val & 0xfc000000) == 0x0c000000) {
12791 if (tg3_nvram_read(tp, offset + 4, &val))
12792 return;
12793
12794 if (val == 0)
12795 newver = true;
12796 }
12797
12798 dst_off = strlen(tp->fw_ver);
12799
12800 if (newver) {
12801 if (TG3_VER_SIZE - dst_off < 16 ||
12802 tg3_nvram_read(tp, offset + 8, &ver_offset))
12803 return;
12804
12805 offset = offset + ver_offset - start;
12806 for (i = 0; i < 16; i += 4) {
12807 __be32 v;
12808 if (tg3_nvram_read_be32(tp, offset + i, &v))
12809 return;
12810
12811 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12812 }
12813 } else {
12814 u32 major, minor;
12815
12816 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12817 return;
12818
12819 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12820 TG3_NVM_BCVER_MAJSFT;
12821 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12822 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12823 "v%d.%02d", major, minor);
12824 }
12825 }
12826
12827 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12828 {
12829 u32 val, major, minor;
12830
12831 /* Use native endian representation */
12832 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12833 return;
12834
12835 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12836 TG3_NVM_HWSB_CFG1_MAJSFT;
12837 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12838 TG3_NVM_HWSB_CFG1_MINSFT;
12839
12840 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12841 }
12842
12843 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12844 {
12845 u32 offset, major, minor, build;
12846
12847 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12848
12849 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12850 return;
12851
12852 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12853 case TG3_EEPROM_SB_REVISION_0:
12854 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12855 break;
12856 case TG3_EEPROM_SB_REVISION_2:
12857 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12858 break;
12859 case TG3_EEPROM_SB_REVISION_3:
12860 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12861 break;
12862 case TG3_EEPROM_SB_REVISION_4:
12863 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12864 break;
12865 case TG3_EEPROM_SB_REVISION_5:
12866 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12867 break;
12868 case TG3_EEPROM_SB_REVISION_6:
12869 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12870 break;
12871 default:
12872 return;
12873 }
12874
12875 if (tg3_nvram_read(tp, offset, &val))
12876 return;
12877
12878 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12879 TG3_EEPROM_SB_EDH_BLD_SHFT;
12880 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12881 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12882 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12883
12884 if (minor > 99 || build > 26)
12885 return;
12886
12887 offset = strlen(tp->fw_ver);
12888 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12889 " v%d.%02d", major, minor);
12890
12891 if (build > 0) {
12892 offset = strlen(tp->fw_ver);
12893 if (offset < TG3_VER_SIZE - 1)
12894 tp->fw_ver[offset] = 'a' + build - 1;
12895 }
12896 }
12897
12898 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12899 {
12900 u32 val, offset, start;
12901 int i, vlen;
12902
12903 for (offset = TG3_NVM_DIR_START;
12904 offset < TG3_NVM_DIR_END;
12905 offset += TG3_NVM_DIRENT_SIZE) {
12906 if (tg3_nvram_read(tp, offset, &val))
12907 return;
12908
12909 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12910 break;
12911 }
12912
12913 if (offset == TG3_NVM_DIR_END)
12914 return;
12915
12916 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12917 start = 0x08000000;
12918 else if (tg3_nvram_read(tp, offset - 4, &start))
12919 return;
12920
12921 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12922 !tg3_fw_img_is_valid(tp, offset) ||
12923 tg3_nvram_read(tp, offset + 8, &val))
12924 return;
12925
12926 offset += val - start;
12927
12928 vlen = strlen(tp->fw_ver);
12929
12930 tp->fw_ver[vlen++] = ',';
12931 tp->fw_ver[vlen++] = ' ';
12932
12933 for (i = 0; i < 4; i++) {
12934 __be32 v;
12935 if (tg3_nvram_read_be32(tp, offset, &v))
12936 return;
12937
12938 offset += sizeof(v);
12939
12940 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12941 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12942 break;
12943 }
12944
12945 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12946 vlen += sizeof(v);
12947 }
12948 }
12949
12950 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12951 {
12952 int vlen;
12953 u32 apedata;
12954 char *fwtype;
12955
12956 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12957 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12958 return;
12959
12960 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12961 if (apedata != APE_SEG_SIG_MAGIC)
12962 return;
12963
12964 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12965 if (!(apedata & APE_FW_STATUS_READY))
12966 return;
12967
12968 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12969
12970 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12971 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12972 fwtype = "NCSI";
12973 } else {
12974 fwtype = "DASH";
12975 }
12976
12977 vlen = strlen(tp->fw_ver);
12978
12979 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12980 fwtype,
12981 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12982 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12983 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12984 (apedata & APE_FW_VERSION_BLDMSK));
12985 }
12986
12987 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12988 {
12989 u32 val;
12990 bool vpd_vers = false;
12991
12992 if (tp->fw_ver[0] != 0)
12993 vpd_vers = true;
12994
12995 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12996 strcat(tp->fw_ver, "sb");
12997 return;
12998 }
12999
13000 if (tg3_nvram_read(tp, 0, &val))
13001 return;
13002
13003 if (val == TG3_EEPROM_MAGIC)
13004 tg3_read_bc_ver(tp);
13005 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13006 tg3_read_sb_ver(tp, val);
13007 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13008 tg3_read_hwsb_ver(tp);
13009 else
13010 return;
13011
13012 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13013 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13014 goto done;
13015
13016 tg3_read_mgmtfw_ver(tp);
13017
13018 done:
13019 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13020 }
13021
13022 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13023
13024 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13025 {
13026 #if TG3_VLAN_TAG_USED
13027 dev->vlan_features |= flags;
13028 #endif
13029 }
13030
13031 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13032 {
13033 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13034 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13035 return 4096;
13036 else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13037 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13038 return 1024;
13039 else
13040 return 512;
13041 }
13042
13043 static int __devinit tg3_get_invariants(struct tg3 *tp)
13044 {
13045 static struct pci_device_id write_reorder_chipsets[] = {
13046 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13047 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13048 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13049 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13050 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
13051 PCI_DEVICE_ID_VIA_8385_0) },
13052 { },
13053 };
13054 u32 misc_ctrl_reg;
13055 u32 pci_state_reg, grc_misc_cfg;
13056 u32 val;
13057 u16 pci_cmd;
13058 int err;
13059
13060 /* Force memory write invalidate off. If we leave it on,
13061 * then on 5700_BX chips we have to enable a workaround.
13062 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13063 * to match the cacheline size. The Broadcom driver have this
13064 * workaround but turns MWI off all the times so never uses
13065 * it. This seems to suggest that the workaround is insufficient.
13066 */
13067 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13068 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13069 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13070
13071 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13072 * has the register indirect write enable bit set before
13073 * we try to access any of the MMIO registers. It is also
13074 * critical that the PCI-X hw workaround situation is decided
13075 * before that as well.
13076 */
13077 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13078 &misc_ctrl_reg);
13079
13080 tp->pci_chip_rev_id = (misc_ctrl_reg >>
13081 MISC_HOST_CTRL_CHIPREV_SHIFT);
13082 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13083 u32 prod_id_asic_rev;
13084
13085 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13086 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13087 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13088 pci_read_config_dword(tp->pdev,
13089 TG3PCI_GEN2_PRODID_ASICREV,
13090 &prod_id_asic_rev);
13091 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13092 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13093 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13094 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13095 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13096 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13097 pci_read_config_dword(tp->pdev,
13098 TG3PCI_GEN15_PRODID_ASICREV,
13099 &prod_id_asic_rev);
13100 else
13101 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13102 &prod_id_asic_rev);
13103
13104 tp->pci_chip_rev_id = prod_id_asic_rev;
13105 }
13106
13107 /* Wrong chip ID in 5752 A0. This code can be removed later
13108 * as A0 is not in production.
13109 */
13110 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13111 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13112
13113 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13114 * we need to disable memory and use config. cycles
13115 * only to access all registers. The 5702/03 chips
13116 * can mistakenly decode the special cycles from the
13117 * ICH chipsets as memory write cycles, causing corruption
13118 * of register and memory space. Only certain ICH bridges
13119 * will drive special cycles with non-zero data during the
13120 * address phase which can fall within the 5703's address
13121 * range. This is not an ICH bug as the PCI spec allows
13122 * non-zero address during special cycles. However, only
13123 * these ICH bridges are known to drive non-zero addresses
13124 * during special cycles.
13125 *
13126 * Since special cycles do not cross PCI bridges, we only
13127 * enable this workaround if the 5703 is on the secondary
13128 * bus of these ICH bridges.
13129 */
13130 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13131 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13132 static struct tg3_dev_id {
13133 u32 vendor;
13134 u32 device;
13135 u32 rev;
13136 } ich_chipsets[] = {
13137 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13138 PCI_ANY_ID },
13139 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13140 PCI_ANY_ID },
13141 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13142 0xa },
13143 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13144 PCI_ANY_ID },
13145 { },
13146 };
13147 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13148 struct pci_dev *bridge = NULL;
13149
13150 while (pci_id->vendor != 0) {
13151 bridge = pci_get_device(pci_id->vendor, pci_id->device,
13152 bridge);
13153 if (!bridge) {
13154 pci_id++;
13155 continue;
13156 }
13157 if (pci_id->rev != PCI_ANY_ID) {
13158 if (bridge->revision > pci_id->rev)
13159 continue;
13160 }
13161 if (bridge->subordinate &&
13162 (bridge->subordinate->number ==
13163 tp->pdev->bus->number)) {
13164
13165 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13166 pci_dev_put(bridge);
13167 break;
13168 }
13169 }
13170 }
13171
13172 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13173 static struct tg3_dev_id {
13174 u32 vendor;
13175 u32 device;
13176 } bridge_chipsets[] = {
13177 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13178 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13179 { },
13180 };
13181 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13182 struct pci_dev *bridge = NULL;
13183
13184 while (pci_id->vendor != 0) {
13185 bridge = pci_get_device(pci_id->vendor,
13186 pci_id->device,
13187 bridge);
13188 if (!bridge) {
13189 pci_id++;
13190 continue;
13191 }
13192 if (bridge->subordinate &&
13193 (bridge->subordinate->number <=
13194 tp->pdev->bus->number) &&
13195 (bridge->subordinate->subordinate >=
13196 tp->pdev->bus->number)) {
13197 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13198 pci_dev_put(bridge);
13199 break;
13200 }
13201 }
13202 }
13203
13204 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13205 * DMA addresses > 40-bit. This bridge may have other additional
13206 * 57xx devices behind it in some 4-port NIC designs for example.
13207 * Any tg3 device found behind the bridge will also need the 40-bit
13208 * DMA workaround.
13209 */
13210 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13211 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13212 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13213 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13214 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13215 } else {
13216 struct pci_dev *bridge = NULL;
13217
13218 do {
13219 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13220 PCI_DEVICE_ID_SERVERWORKS_EPB,
13221 bridge);
13222 if (bridge && bridge->subordinate &&
13223 (bridge->subordinate->number <=
13224 tp->pdev->bus->number) &&
13225 (bridge->subordinate->subordinate >=
13226 tp->pdev->bus->number)) {
13227 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13228 pci_dev_put(bridge);
13229 break;
13230 }
13231 } while (bridge);
13232 }
13233
13234 /* Initialize misc host control in PCI block. */
13235 tp->misc_host_ctrl |= (misc_ctrl_reg &
13236 MISC_HOST_CTRL_CHIPREV);
13237 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13238 tp->misc_host_ctrl);
13239
13240 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13241 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13242 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13243 tp->pdev_peer = tg3_find_peer(tp);
13244
13245 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13246 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13247 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13248 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13249
13250 /* Intentionally exclude ASIC_REV_5906 */
13251 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13252 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13253 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13254 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13255 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13256 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13257 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13258 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13259
13260 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13261 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13262 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13263 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13264 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13265 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13266
13267 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13268 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13269 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13270
13271 /* 5700 B0 chips do not support checksumming correctly due
13272 * to hardware bugs.
13273 */
13274 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13275 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13276 else {
13277 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13278
13279 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13280 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13281 features |= NETIF_F_IPV6_CSUM;
13282 tp->dev->features |= features;
13283 vlan_features_add(tp->dev, features);
13284 }
13285
13286 /* Determine TSO capabilities */
13287 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13288 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13289 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13290 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13291 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13292 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13293 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13294 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13295 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13296 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13297 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13298 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13299 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13300 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13301 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13302 tp->fw_needed = FIRMWARE_TG3TSO5;
13303 else
13304 tp->fw_needed = FIRMWARE_TG3TSO;
13305 }
13306
13307 tp->irq_max = 1;
13308
13309 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13310 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13311 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13312 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13313 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13314 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13315 tp->pdev_peer == tp->pdev))
13316 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13317
13318 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13319 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13320 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13321 }
13322
13323 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13324 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13325 tp->irq_max = TG3_IRQ_MAX_VECS;
13326 }
13327 }
13328
13329 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13330 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13331 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13332 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13333 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13334 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13335 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13336 }
13337
13338 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13339 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13340
13341 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13342 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13343 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13344 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13345
13346 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13347 &pci_state_reg);
13348
13349 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13350 if (tp->pcie_cap != 0) {
13351 u16 lnkctl;
13352
13353 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13354
13355 pcie_set_readrq(tp->pdev, 4096);
13356
13357 pci_read_config_word(tp->pdev,
13358 tp->pcie_cap + PCI_EXP_LNKCTL,
13359 &lnkctl);
13360 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13361 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13362 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13363 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13364 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13365 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13366 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13367 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13368 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13369 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13370 }
13371 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13372 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13373 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13374 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13375 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13376 if (!tp->pcix_cap) {
13377 dev_err(&tp->pdev->dev,
13378 "Cannot find PCI-X capability, aborting\n");
13379 return -EIO;
13380 }
13381
13382 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13383 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13384 }
13385
13386 /* If we have an AMD 762 or VIA K8T800 chipset, write
13387 * reordering to the mailbox registers done by the host
13388 * controller can cause major troubles. We read back from
13389 * every mailbox register write to force the writes to be
13390 * posted to the chip in order.
13391 */
13392 if (pci_dev_present(write_reorder_chipsets) &&
13393 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13394 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13395
13396 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13397 &tp->pci_cacheline_sz);
13398 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13399 &tp->pci_lat_timer);
13400 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13401 tp->pci_lat_timer < 64) {
13402 tp->pci_lat_timer = 64;
13403 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13404 tp->pci_lat_timer);
13405 }
13406
13407 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13408 /* 5700 BX chips need to have their TX producer index
13409 * mailboxes written twice to workaround a bug.
13410 */
13411 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13412
13413 /* If we are in PCI-X mode, enable register write workaround.
13414 *
13415 * The workaround is to use indirect register accesses
13416 * for all chip writes not to mailbox registers.
13417 */
13418 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13419 u32 pm_reg;
13420
13421 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13422
13423 /* The chip can have it's power management PCI config
13424 * space registers clobbered due to this bug.
13425 * So explicitly force the chip into D0 here.
13426 */
13427 pci_read_config_dword(tp->pdev,
13428 tp->pm_cap + PCI_PM_CTRL,
13429 &pm_reg);
13430 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13431 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13432 pci_write_config_dword(tp->pdev,
13433 tp->pm_cap + PCI_PM_CTRL,
13434 pm_reg);
13435
13436 /* Also, force SERR#/PERR# in PCI command. */
13437 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13438 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13439 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13440 }
13441 }
13442
13443 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13444 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13445 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13446 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13447
13448 /* Chip-specific fixup from Broadcom driver */
13449 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13450 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13451 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13452 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13453 }
13454
13455 /* Default fast path register access methods */
13456 tp->read32 = tg3_read32;
13457 tp->write32 = tg3_write32;
13458 tp->read32_mbox = tg3_read32;
13459 tp->write32_mbox = tg3_write32;
13460 tp->write32_tx_mbox = tg3_write32;
13461 tp->write32_rx_mbox = tg3_write32;
13462
13463 /* Various workaround register access methods */
13464 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13465 tp->write32 = tg3_write_indirect_reg32;
13466 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13467 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13468 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13469 /*
13470 * Back to back register writes can cause problems on these
13471 * chips, the workaround is to read back all reg writes
13472 * except those to mailbox regs.
13473 *
13474 * See tg3_write_indirect_reg32().
13475 */
13476 tp->write32 = tg3_write_flush_reg32;
13477 }
13478
13479 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13480 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13481 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13482 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13483 tp->write32_rx_mbox = tg3_write_flush_reg32;
13484 }
13485
13486 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13487 tp->read32 = tg3_read_indirect_reg32;
13488 tp->write32 = tg3_write_indirect_reg32;
13489 tp->read32_mbox = tg3_read_indirect_mbox;
13490 tp->write32_mbox = tg3_write_indirect_mbox;
13491 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13492 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13493
13494 iounmap(tp->regs);
13495 tp->regs = NULL;
13496
13497 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13498 pci_cmd &= ~PCI_COMMAND_MEMORY;
13499 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13500 }
13501 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13502 tp->read32_mbox = tg3_read32_mbox_5906;
13503 tp->write32_mbox = tg3_write32_mbox_5906;
13504 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13505 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13506 }
13507
13508 if (tp->write32 == tg3_write_indirect_reg32 ||
13509 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13510 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13511 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13512 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13513
13514 /* Get eeprom hw config before calling tg3_set_power_state().
13515 * In particular, the TG3_FLG2_IS_NIC flag must be
13516 * determined before calling tg3_set_power_state() so that
13517 * we know whether or not to switch out of Vaux power.
13518 * When the flag is set, it means that GPIO1 is used for eeprom
13519 * write protect and also implies that it is a LOM where GPIOs
13520 * are not used to switch power.
13521 */
13522 tg3_get_eeprom_hw_cfg(tp);
13523
13524 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13525 /* Allow reads and writes to the
13526 * APE register and memory space.
13527 */
13528 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13529 PCISTATE_ALLOW_APE_SHMEM_WR |
13530 PCISTATE_ALLOW_APE_PSPACE_WR;
13531 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13532 pci_state_reg);
13533 }
13534
13535 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13536 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13537 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13538 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13539 (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13540 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13541
13542 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13543 * GPIO1 driven high will bring 5700's external PHY out of reset.
13544 * It is also used as eeprom write protect on LOMs.
13545 */
13546 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13547 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13548 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13549 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13550 GRC_LCLCTRL_GPIO_OUTPUT1);
13551 /* Unused GPIO3 must be driven as output on 5752 because there
13552 * are no pull-up resistors on unused GPIO pins.
13553 */
13554 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13555 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13556
13557 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13558 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13559 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13560 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13561
13562 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13563 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13564 /* Turn off the debug UART. */
13565 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13566 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13567 /* Keep VMain power. */
13568 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13569 GRC_LCLCTRL_GPIO_OUTPUT0;
13570 }
13571
13572 /* Force the chip into D0. */
13573 err = tg3_set_power_state(tp, PCI_D0);
13574 if (err) {
13575 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13576 return err;
13577 }
13578
13579 /* Derive initial jumbo mode from MTU assigned in
13580 * ether_setup() via the alloc_etherdev() call
13581 */
13582 if (tp->dev->mtu > ETH_DATA_LEN &&
13583 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13584 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13585
13586 /* Determine WakeOnLan speed to use. */
13587 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13588 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13589 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13590 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13591 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13592 } else {
13593 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13594 }
13595
13596 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13597 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13598
13599 /* A few boards don't want Ethernet@WireSpeed phy feature */
13600 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13601 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13602 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13603 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13604 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13605 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13606 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13607
13608 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13609 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13610 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13611 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13612 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13613
13614 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13615 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13616 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13617 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13618 !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13621 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13623 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13624 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13625 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13626 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13627 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13628 } else
13629 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13630 }
13631
13632 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13633 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13634 tp->phy_otp = tg3_read_otp_phycfg(tp);
13635 if (tp->phy_otp == 0)
13636 tp->phy_otp = TG3_OTP_DEFAULT;
13637 }
13638
13639 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13640 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13641 else
13642 tp->mi_mode = MAC_MI_MODE_BASE;
13643
13644 tp->coalesce_mode = 0;
13645 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13646 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13647 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13648
13649 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13651 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13652
13653 err = tg3_mdio_init(tp);
13654 if (err)
13655 return err;
13656
13657 /* Initialize data/descriptor byte/word swapping. */
13658 val = tr32(GRC_MODE);
13659 val &= GRC_MODE_HOST_STACKUP;
13660 tw32(GRC_MODE, val | tp->grc_mode);
13661
13662 tg3_switch_clocks(tp);
13663
13664 /* Clear this out for sanity. */
13665 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13666
13667 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13668 &pci_state_reg);
13669 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13670 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13671 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13672
13673 if (chiprevid == CHIPREV_ID_5701_A0 ||
13674 chiprevid == CHIPREV_ID_5701_B0 ||
13675 chiprevid == CHIPREV_ID_5701_B2 ||
13676 chiprevid == CHIPREV_ID_5701_B5) {
13677 void __iomem *sram_base;
13678
13679 /* Write some dummy words into the SRAM status block
13680 * area, see if it reads back correctly. If the return
13681 * value is bad, force enable the PCIX workaround.
13682 */
13683 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13684
13685 writel(0x00000000, sram_base);
13686 writel(0x00000000, sram_base + 4);
13687 writel(0xffffffff, sram_base + 4);
13688 if (readl(sram_base) != 0x00000000)
13689 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13690 }
13691 }
13692
13693 udelay(50);
13694 tg3_nvram_init(tp);
13695
13696 grc_misc_cfg = tr32(GRC_MISC_CFG);
13697 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13698
13699 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13700 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13701 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13702 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13703
13704 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13705 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13706 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13707 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13708 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13709 HOSTCC_MODE_CLRTICK_TXBD);
13710
13711 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13712 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13713 tp->misc_host_ctrl);
13714 }
13715
13716 /* Preserve the APE MAC_MODE bits */
13717 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13718 tp->mac_mode = tr32(MAC_MODE) |
13719 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13720 else
13721 tp->mac_mode = TG3_DEF_MAC_MODE;
13722
13723 /* these are limited to 10/100 only */
13724 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13725 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13726 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13727 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13728 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13729 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13730 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13731 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13732 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13733 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13734 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13735 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13736 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13737 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13738 (tp->phy_flags & TG3_PHYFLG_IS_FET))
13739 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13740
13741 err = tg3_phy_probe(tp);
13742 if (err) {
13743 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13744 /* ... but do not return immediately ... */
13745 tg3_mdio_fini(tp);
13746 }
13747
13748 tg3_read_vpd(tp);
13749 tg3_read_fw_ver(tp);
13750
13751 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13752 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13753 } else {
13754 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13755 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13756 else
13757 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13758 }
13759
13760 /* 5700 {AX,BX} chips have a broken status block link
13761 * change bit implementation, so we must use the
13762 * status register in those cases.
13763 */
13764 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13765 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13766 else
13767 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13768
13769 /* The led_ctrl is set during tg3_phy_probe, here we might
13770 * have to force the link status polling mechanism based
13771 * upon subsystem IDs.
13772 */
13773 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13774 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13775 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13776 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13777 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13778 }
13779
13780 /* For all SERDES we poll the MAC status register. */
13781 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13782 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13783 else
13784 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13785
13786 tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13787 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13788 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13789 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13790 tp->rx_offset -= NET_IP_ALIGN;
13791 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13792 tp->rx_copy_thresh = ~(u16)0;
13793 #endif
13794 }
13795
13796 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13797 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13798 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13799
13800 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13801
13802 /* Increment the rx prod index on the rx std ring by at most
13803 * 8 for these chips to workaround hw errata.
13804 */
13805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13807 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13808 tp->rx_std_max_post = 8;
13809
13810 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13811 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13812 PCIE_PWR_MGMT_L1_THRESH_MSK;
13813
13814 return err;
13815 }
13816
13817 #ifdef CONFIG_SPARC
13818 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13819 {
13820 struct net_device *dev = tp->dev;
13821 struct pci_dev *pdev = tp->pdev;
13822 struct device_node *dp = pci_device_to_OF_node(pdev);
13823 const unsigned char *addr;
13824 int len;
13825
13826 addr = of_get_property(dp, "local-mac-address", &len);
13827 if (addr && len == 6) {
13828 memcpy(dev->dev_addr, addr, 6);
13829 memcpy(dev->perm_addr, dev->dev_addr, 6);
13830 return 0;
13831 }
13832 return -ENODEV;
13833 }
13834
13835 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13836 {
13837 struct net_device *dev = tp->dev;
13838
13839 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13840 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13841 return 0;
13842 }
13843 #endif
13844
13845 static int __devinit tg3_get_device_address(struct tg3 *tp)
13846 {
13847 struct net_device *dev = tp->dev;
13848 u32 hi, lo, mac_offset;
13849 int addr_ok = 0;
13850
13851 #ifdef CONFIG_SPARC
13852 if (!tg3_get_macaddr_sparc(tp))
13853 return 0;
13854 #endif
13855
13856 mac_offset = 0x7c;
13857 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13858 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13859 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13860 mac_offset = 0xcc;
13861 if (tg3_nvram_lock(tp))
13862 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13863 else
13864 tg3_nvram_unlock(tp);
13865 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13866 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13867 if (PCI_FUNC(tp->pdev->devfn) & 1)
13868 mac_offset = 0xcc;
13869 if (PCI_FUNC(tp->pdev->devfn) > 1)
13870 mac_offset += 0x18c;
13871 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13872 mac_offset = 0x10;
13873
13874 /* First try to get it from MAC address mailbox. */
13875 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13876 if ((hi >> 16) == 0x484b) {
13877 dev->dev_addr[0] = (hi >> 8) & 0xff;
13878 dev->dev_addr[1] = (hi >> 0) & 0xff;
13879
13880 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13881 dev->dev_addr[2] = (lo >> 24) & 0xff;
13882 dev->dev_addr[3] = (lo >> 16) & 0xff;
13883 dev->dev_addr[4] = (lo >> 8) & 0xff;
13884 dev->dev_addr[5] = (lo >> 0) & 0xff;
13885
13886 /* Some old bootcode may report a 0 MAC address in SRAM */
13887 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13888 }
13889 if (!addr_ok) {
13890 /* Next, try NVRAM. */
13891 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13892 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13893 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13894 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13895 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13896 }
13897 /* Finally just fetch it out of the MAC control regs. */
13898 else {
13899 hi = tr32(MAC_ADDR_0_HIGH);
13900 lo = tr32(MAC_ADDR_0_LOW);
13901
13902 dev->dev_addr[5] = lo & 0xff;
13903 dev->dev_addr[4] = (lo >> 8) & 0xff;
13904 dev->dev_addr[3] = (lo >> 16) & 0xff;
13905 dev->dev_addr[2] = (lo >> 24) & 0xff;
13906 dev->dev_addr[1] = hi & 0xff;
13907 dev->dev_addr[0] = (hi >> 8) & 0xff;
13908 }
13909 }
13910
13911 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13912 #ifdef CONFIG_SPARC
13913 if (!tg3_get_default_macaddr_sparc(tp))
13914 return 0;
13915 #endif
13916 return -EINVAL;
13917 }
13918 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13919 return 0;
13920 }
13921
13922 #define BOUNDARY_SINGLE_CACHELINE 1
13923 #define BOUNDARY_MULTI_CACHELINE 2
13924
13925 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13926 {
13927 int cacheline_size;
13928 u8 byte;
13929 int goal;
13930
13931 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13932 if (byte == 0)
13933 cacheline_size = 1024;
13934 else
13935 cacheline_size = (int) byte * 4;
13936
13937 /* On 5703 and later chips, the boundary bits have no
13938 * effect.
13939 */
13940 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13941 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13942 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13943 goto out;
13944
13945 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13946 goal = BOUNDARY_MULTI_CACHELINE;
13947 #else
13948 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13949 goal = BOUNDARY_SINGLE_CACHELINE;
13950 #else
13951 goal = 0;
13952 #endif
13953 #endif
13954
13955 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13956 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13957 goto out;
13958 }
13959
13960 if (!goal)
13961 goto out;
13962
13963 /* PCI controllers on most RISC systems tend to disconnect
13964 * when a device tries to burst across a cache-line boundary.
13965 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13966 *
13967 * Unfortunately, for PCI-E there are only limited
13968 * write-side controls for this, and thus for reads
13969 * we will still get the disconnects. We'll also waste
13970 * these PCI cycles for both read and write for chips
13971 * other than 5700 and 5701 which do not implement the
13972 * boundary bits.
13973 */
13974 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13975 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13976 switch (cacheline_size) {
13977 case 16:
13978 case 32:
13979 case 64:
13980 case 128:
13981 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13982 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13983 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13984 } else {
13985 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13986 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13987 }
13988 break;
13989
13990 case 256:
13991 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13992 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13993 break;
13994
13995 default:
13996 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13997 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13998 break;
13999 }
14000 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14001 switch (cacheline_size) {
14002 case 16:
14003 case 32:
14004 case 64:
14005 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14006 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14007 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14008 break;
14009 }
14010 /* fallthrough */
14011 case 128:
14012 default:
14013 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14014 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14015 break;
14016 }
14017 } else {
14018 switch (cacheline_size) {
14019 case 16:
14020 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14021 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14022 DMA_RWCTRL_WRITE_BNDRY_16);
14023 break;
14024 }
14025 /* fallthrough */
14026 case 32:
14027 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14028 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14029 DMA_RWCTRL_WRITE_BNDRY_32);
14030 break;
14031 }
14032 /* fallthrough */
14033 case 64:
14034 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14035 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14036 DMA_RWCTRL_WRITE_BNDRY_64);
14037 break;
14038 }
14039 /* fallthrough */
14040 case 128:
14041 if (goal == BOUNDARY_SINGLE_CACHELINE) {
14042 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14043 DMA_RWCTRL_WRITE_BNDRY_128);
14044 break;
14045 }
14046 /* fallthrough */
14047 case 256:
14048 val |= (DMA_RWCTRL_READ_BNDRY_256 |
14049 DMA_RWCTRL_WRITE_BNDRY_256);
14050 break;
14051 case 512:
14052 val |= (DMA_RWCTRL_READ_BNDRY_512 |
14053 DMA_RWCTRL_WRITE_BNDRY_512);
14054 break;
14055 case 1024:
14056 default:
14057 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14058 DMA_RWCTRL_WRITE_BNDRY_1024);
14059 break;
14060 }
14061 }
14062
14063 out:
14064 return val;
14065 }
14066
14067 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14068 {
14069 struct tg3_internal_buffer_desc test_desc;
14070 u32 sram_dma_descs;
14071 int i, ret;
14072
14073 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14074
14075 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14076 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14077 tw32(RDMAC_STATUS, 0);
14078 tw32(WDMAC_STATUS, 0);
14079
14080 tw32(BUFMGR_MODE, 0);
14081 tw32(FTQ_RESET, 0);
14082
14083 test_desc.addr_hi = ((u64) buf_dma) >> 32;
14084 test_desc.addr_lo = buf_dma & 0xffffffff;
14085 test_desc.nic_mbuf = 0x00002100;
14086 test_desc.len = size;
14087
14088 /*
14089 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14090 * the *second* time the tg3 driver was getting loaded after an
14091 * initial scan.
14092 *
14093 * Broadcom tells me:
14094 * ...the DMA engine is connected to the GRC block and a DMA
14095 * reset may affect the GRC block in some unpredictable way...
14096 * The behavior of resets to individual blocks has not been tested.
14097 *
14098 * Broadcom noted the GRC reset will also reset all sub-components.
14099 */
14100 if (to_device) {
14101 test_desc.cqid_sqid = (13 << 8) | 2;
14102
14103 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14104 udelay(40);
14105 } else {
14106 test_desc.cqid_sqid = (16 << 8) | 7;
14107
14108 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14109 udelay(40);
14110 }
14111 test_desc.flags = 0x00000005;
14112
14113 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14114 u32 val;
14115
14116 val = *(((u32 *)&test_desc) + i);
14117 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14118 sram_dma_descs + (i * sizeof(u32)));
14119 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14120 }
14121 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14122
14123 if (to_device)
14124 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14125 else
14126 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14127
14128 ret = -ENODEV;
14129 for (i = 0; i < 40; i++) {
14130 u32 val;
14131
14132 if (to_device)
14133 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14134 else
14135 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14136 if ((val & 0xffff) == sram_dma_descs) {
14137 ret = 0;
14138 break;
14139 }
14140
14141 udelay(100);
14142 }
14143
14144 return ret;
14145 }
14146
14147 #define TEST_BUFFER_SIZE 0x2000
14148
14149 static int __devinit tg3_test_dma(struct tg3 *tp)
14150 {
14151 dma_addr_t buf_dma;
14152 u32 *buf, saved_dma_rwctrl;
14153 int ret = 0;
14154
14155 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14156 if (!buf) {
14157 ret = -ENOMEM;
14158 goto out_nofree;
14159 }
14160
14161 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14162 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14163
14164 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14165
14166 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14167 goto out;
14168
14169 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14170 /* DMA read watermark not used on PCIE */
14171 tp->dma_rwctrl |= 0x00180000;
14172 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14174 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14175 tp->dma_rwctrl |= 0x003f0000;
14176 else
14177 tp->dma_rwctrl |= 0x003f000f;
14178 } else {
14179 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14180 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14181 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14182 u32 read_water = 0x7;
14183
14184 /* If the 5704 is behind the EPB bridge, we can
14185 * do the less restrictive ONE_DMA workaround for
14186 * better performance.
14187 */
14188 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14189 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14190 tp->dma_rwctrl |= 0x8000;
14191 else if (ccval == 0x6 || ccval == 0x7)
14192 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14193
14194 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14195 read_water = 4;
14196 /* Set bit 23 to enable PCIX hw bug fix */
14197 tp->dma_rwctrl |=
14198 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14199 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14200 (1 << 23);
14201 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14202 /* 5780 always in PCIX mode */
14203 tp->dma_rwctrl |= 0x00144000;
14204 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14205 /* 5714 always in PCIX mode */
14206 tp->dma_rwctrl |= 0x00148000;
14207 } else {
14208 tp->dma_rwctrl |= 0x001b000f;
14209 }
14210 }
14211
14212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14213 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14214 tp->dma_rwctrl &= 0xfffffff0;
14215
14216 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14217 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14218 /* Remove this if it causes problems for some boards. */
14219 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14220
14221 /* On 5700/5701 chips, we need to set this bit.
14222 * Otherwise the chip will issue cacheline transactions
14223 * to streamable DMA memory with not all the byte
14224 * enables turned on. This is an error on several
14225 * RISC PCI controllers, in particular sparc64.
14226 *
14227 * On 5703/5704 chips, this bit has been reassigned
14228 * a different meaning. In particular, it is used
14229 * on those chips to enable a PCI-X workaround.
14230 */
14231 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14232 }
14233
14234 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14235
14236 #if 0
14237 /* Unneeded, already done by tg3_get_invariants. */
14238 tg3_switch_clocks(tp);
14239 #endif
14240
14241 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14242 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14243 goto out;
14244
14245 /* It is best to perform DMA test with maximum write burst size
14246 * to expose the 5700/5701 write DMA bug.
14247 */
14248 saved_dma_rwctrl = tp->dma_rwctrl;
14249 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14250 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14251
14252 while (1) {
14253 u32 *p = buf, i;
14254
14255 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14256 p[i] = i;
14257
14258 /* Send the buffer to the chip. */
14259 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14260 if (ret) {
14261 dev_err(&tp->pdev->dev,
14262 "%s: Buffer write failed. err = %d\n",
14263 __func__, ret);
14264 break;
14265 }
14266
14267 #if 0
14268 /* validate data reached card RAM correctly. */
14269 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14270 u32 val;
14271 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14272 if (le32_to_cpu(val) != p[i]) {
14273 dev_err(&tp->pdev->dev,
14274 "%s: Buffer corrupted on device! "
14275 "(%d != %d)\n", __func__, val, i);
14276 /* ret = -ENODEV here? */
14277 }
14278 p[i] = 0;
14279 }
14280 #endif
14281 /* Now read it back. */
14282 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14283 if (ret) {
14284 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14285 "err = %d\n", __func__, ret);
14286 break;
14287 }
14288
14289 /* Verify it. */
14290 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14291 if (p[i] == i)
14292 continue;
14293
14294 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14295 DMA_RWCTRL_WRITE_BNDRY_16) {
14296 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14297 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14298 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14299 break;
14300 } else {
14301 dev_err(&tp->pdev->dev,
14302 "%s: Buffer corrupted on read back! "
14303 "(%d != %d)\n", __func__, p[i], i);
14304 ret = -ENODEV;
14305 goto out;
14306 }
14307 }
14308
14309 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14310 /* Success. */
14311 ret = 0;
14312 break;
14313 }
14314 }
14315 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14316 DMA_RWCTRL_WRITE_BNDRY_16) {
14317 static struct pci_device_id dma_wait_state_chipsets[] = {
14318 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14319 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14320 { },
14321 };
14322
14323 /* DMA test passed without adjusting DMA boundary,
14324 * now look for chipsets that are known to expose the
14325 * DMA bug without failing the test.
14326 */
14327 if (pci_dev_present(dma_wait_state_chipsets)) {
14328 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14329 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14330 } else {
14331 /* Safe to use the calculated DMA boundary. */
14332 tp->dma_rwctrl = saved_dma_rwctrl;
14333 }
14334
14335 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14336 }
14337
14338 out:
14339 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14340 out_nofree:
14341 return ret;
14342 }
14343
14344 static void __devinit tg3_init_link_config(struct tg3 *tp)
14345 {
14346 tp->link_config.advertising =
14347 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14348 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14349 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14350 ADVERTISED_Autoneg | ADVERTISED_MII);
14351 tp->link_config.speed = SPEED_INVALID;
14352 tp->link_config.duplex = DUPLEX_INVALID;
14353 tp->link_config.autoneg = AUTONEG_ENABLE;
14354 tp->link_config.active_speed = SPEED_INVALID;
14355 tp->link_config.active_duplex = DUPLEX_INVALID;
14356 tp->link_config.orig_speed = SPEED_INVALID;
14357 tp->link_config.orig_duplex = DUPLEX_INVALID;
14358 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14359 }
14360
14361 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14362 {
14363 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14364 tp->bufmgr_config.mbuf_read_dma_low_water =
14365 DEFAULT_MB_RDMA_LOW_WATER_5705;
14366 tp->bufmgr_config.mbuf_mac_rx_low_water =
14367 DEFAULT_MB_MACRX_LOW_WATER_57765;
14368 tp->bufmgr_config.mbuf_high_water =
14369 DEFAULT_MB_HIGH_WATER_57765;
14370
14371 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14372 DEFAULT_MB_RDMA_LOW_WATER_5705;
14373 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14374 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14375 tp->bufmgr_config.mbuf_high_water_jumbo =
14376 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14377 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14378 tp->bufmgr_config.mbuf_read_dma_low_water =
14379 DEFAULT_MB_RDMA_LOW_WATER_5705;
14380 tp->bufmgr_config.mbuf_mac_rx_low_water =
14381 DEFAULT_MB_MACRX_LOW_WATER_5705;
14382 tp->bufmgr_config.mbuf_high_water =
14383 DEFAULT_MB_HIGH_WATER_5705;
14384 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14385 tp->bufmgr_config.mbuf_mac_rx_low_water =
14386 DEFAULT_MB_MACRX_LOW_WATER_5906;
14387 tp->bufmgr_config.mbuf_high_water =
14388 DEFAULT_MB_HIGH_WATER_5906;
14389 }
14390
14391 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14392 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14393 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14394 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14395 tp->bufmgr_config.mbuf_high_water_jumbo =
14396 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14397 } else {
14398 tp->bufmgr_config.mbuf_read_dma_low_water =
14399 DEFAULT_MB_RDMA_LOW_WATER;
14400 tp->bufmgr_config.mbuf_mac_rx_low_water =
14401 DEFAULT_MB_MACRX_LOW_WATER;
14402 tp->bufmgr_config.mbuf_high_water =
14403 DEFAULT_MB_HIGH_WATER;
14404
14405 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14406 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14407 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14408 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14409 tp->bufmgr_config.mbuf_high_water_jumbo =
14410 DEFAULT_MB_HIGH_WATER_JUMBO;
14411 }
14412
14413 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14414 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14415 }
14416
14417 static char * __devinit tg3_phy_string(struct tg3 *tp)
14418 {
14419 switch (tp->phy_id & TG3_PHY_ID_MASK) {
14420 case TG3_PHY_ID_BCM5400: return "5400";
14421 case TG3_PHY_ID_BCM5401: return "5401";
14422 case TG3_PHY_ID_BCM5411: return "5411";
14423 case TG3_PHY_ID_BCM5701: return "5701";
14424 case TG3_PHY_ID_BCM5703: return "5703";
14425 case TG3_PHY_ID_BCM5704: return "5704";
14426 case TG3_PHY_ID_BCM5705: return "5705";
14427 case TG3_PHY_ID_BCM5750: return "5750";
14428 case TG3_PHY_ID_BCM5752: return "5752";
14429 case TG3_PHY_ID_BCM5714: return "5714";
14430 case TG3_PHY_ID_BCM5780: return "5780";
14431 case TG3_PHY_ID_BCM5755: return "5755";
14432 case TG3_PHY_ID_BCM5787: return "5787";
14433 case TG3_PHY_ID_BCM5784: return "5784";
14434 case TG3_PHY_ID_BCM5756: return "5722/5756";
14435 case TG3_PHY_ID_BCM5906: return "5906";
14436 case TG3_PHY_ID_BCM5761: return "5761";
14437 case TG3_PHY_ID_BCM5718C: return "5718C";
14438 case TG3_PHY_ID_BCM5718S: return "5718S";
14439 case TG3_PHY_ID_BCM57765: return "57765";
14440 case TG3_PHY_ID_BCM5719C: return "5719C";
14441 case TG3_PHY_ID_BCM8002: return "8002/serdes";
14442 case 0: return "serdes";
14443 default: return "unknown";
14444 }
14445 }
14446
14447 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14448 {
14449 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14450 strcpy(str, "PCI Express");
14451 return str;
14452 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14453 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14454
14455 strcpy(str, "PCIX:");
14456
14457 if ((clock_ctrl == 7) ||
14458 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14459 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14460 strcat(str, "133MHz");
14461 else if (clock_ctrl == 0)
14462 strcat(str, "33MHz");
14463 else if (clock_ctrl == 2)
14464 strcat(str, "50MHz");
14465 else if (clock_ctrl == 4)
14466 strcat(str, "66MHz");
14467 else if (clock_ctrl == 6)
14468 strcat(str, "100MHz");
14469 } else {
14470 strcpy(str, "PCI:");
14471 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14472 strcat(str, "66MHz");
14473 else
14474 strcat(str, "33MHz");
14475 }
14476 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14477 strcat(str, ":32-bit");
14478 else
14479 strcat(str, ":64-bit");
14480 return str;
14481 }
14482
14483 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14484 {
14485 struct pci_dev *peer;
14486 unsigned int func, devnr = tp->pdev->devfn & ~7;
14487
14488 for (func = 0; func < 8; func++) {
14489 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14490 if (peer && peer != tp->pdev)
14491 break;
14492 pci_dev_put(peer);
14493 }
14494 /* 5704 can be configured in single-port mode, set peer to
14495 * tp->pdev in that case.
14496 */
14497 if (!peer) {
14498 peer = tp->pdev;
14499 return peer;
14500 }
14501
14502 /*
14503 * We don't need to keep the refcount elevated; there's no way
14504 * to remove one half of this device without removing the other
14505 */
14506 pci_dev_put(peer);
14507
14508 return peer;
14509 }
14510
14511 static void __devinit tg3_init_coal(struct tg3 *tp)
14512 {
14513 struct ethtool_coalesce *ec = &tp->coal;
14514
14515 memset(ec, 0, sizeof(*ec));
14516 ec->cmd = ETHTOOL_GCOALESCE;
14517 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14518 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14519 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14520 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14521 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14522 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14523 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14524 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14525 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14526
14527 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14528 HOSTCC_MODE_CLRTICK_TXBD)) {
14529 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14530 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14531 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14532 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14533 }
14534
14535 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14536 ec->rx_coalesce_usecs_irq = 0;
14537 ec->tx_coalesce_usecs_irq = 0;
14538 ec->stats_block_coalesce_usecs = 0;
14539 }
14540 }
14541
14542 static const struct net_device_ops tg3_netdev_ops = {
14543 .ndo_open = tg3_open,
14544 .ndo_stop = tg3_close,
14545 .ndo_start_xmit = tg3_start_xmit,
14546 .ndo_get_stats64 = tg3_get_stats64,
14547 .ndo_validate_addr = eth_validate_addr,
14548 .ndo_set_multicast_list = tg3_set_rx_mode,
14549 .ndo_set_mac_address = tg3_set_mac_addr,
14550 .ndo_do_ioctl = tg3_ioctl,
14551 .ndo_tx_timeout = tg3_tx_timeout,
14552 .ndo_change_mtu = tg3_change_mtu,
14553 #if TG3_VLAN_TAG_USED
14554 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14555 #endif
14556 #ifdef CONFIG_NET_POLL_CONTROLLER
14557 .ndo_poll_controller = tg3_poll_controller,
14558 #endif
14559 };
14560
14561 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14562 .ndo_open = tg3_open,
14563 .ndo_stop = tg3_close,
14564 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14565 .ndo_get_stats64 = tg3_get_stats64,
14566 .ndo_validate_addr = eth_validate_addr,
14567 .ndo_set_multicast_list = tg3_set_rx_mode,
14568 .ndo_set_mac_address = tg3_set_mac_addr,
14569 .ndo_do_ioctl = tg3_ioctl,
14570 .ndo_tx_timeout = tg3_tx_timeout,
14571 .ndo_change_mtu = tg3_change_mtu,
14572 #if TG3_VLAN_TAG_USED
14573 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14574 #endif
14575 #ifdef CONFIG_NET_POLL_CONTROLLER
14576 .ndo_poll_controller = tg3_poll_controller,
14577 #endif
14578 };
14579
14580 static int __devinit tg3_init_one(struct pci_dev *pdev,
14581 const struct pci_device_id *ent)
14582 {
14583 struct net_device *dev;
14584 struct tg3 *tp;
14585 int i, err, pm_cap;
14586 u32 sndmbx, rcvmbx, intmbx;
14587 char str[40];
14588 u64 dma_mask, persist_dma_mask;
14589
14590 printk_once(KERN_INFO "%s\n", version);
14591
14592 err = pci_enable_device(pdev);
14593 if (err) {
14594 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14595 return err;
14596 }
14597
14598 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14599 if (err) {
14600 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14601 goto err_out_disable_pdev;
14602 }
14603
14604 pci_set_master(pdev);
14605
14606 /* Find power-management capability. */
14607 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14608 if (pm_cap == 0) {
14609 dev_err(&pdev->dev,
14610 "Cannot find Power Management capability, aborting\n");
14611 err = -EIO;
14612 goto err_out_free_res;
14613 }
14614
14615 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14616 if (!dev) {
14617 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14618 err = -ENOMEM;
14619 goto err_out_free_res;
14620 }
14621
14622 SET_NETDEV_DEV(dev, &pdev->dev);
14623
14624 #if TG3_VLAN_TAG_USED
14625 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14626 #endif
14627
14628 tp = netdev_priv(dev);
14629 tp->pdev = pdev;
14630 tp->dev = dev;
14631 tp->pm_cap = pm_cap;
14632 tp->rx_mode = TG3_DEF_RX_MODE;
14633 tp->tx_mode = TG3_DEF_TX_MODE;
14634
14635 if (tg3_debug > 0)
14636 tp->msg_enable = tg3_debug;
14637 else
14638 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14639
14640 /* The word/byte swap controls here control register access byte
14641 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14642 * setting below.
14643 */
14644 tp->misc_host_ctrl =
14645 MISC_HOST_CTRL_MASK_PCI_INT |
14646 MISC_HOST_CTRL_WORD_SWAP |
14647 MISC_HOST_CTRL_INDIR_ACCESS |
14648 MISC_HOST_CTRL_PCISTATE_RW;
14649
14650 /* The NONFRM (non-frame) byte/word swap controls take effect
14651 * on descriptor entries, anything which isn't packet data.
14652 *
14653 * The StrongARM chips on the board (one for tx, one for rx)
14654 * are running in big-endian mode.
14655 */
14656 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14657 GRC_MODE_WSWAP_NONFRM_DATA);
14658 #ifdef __BIG_ENDIAN
14659 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14660 #endif
14661 spin_lock_init(&tp->lock);
14662 spin_lock_init(&tp->indirect_lock);
14663 INIT_WORK(&tp->reset_task, tg3_reset_task);
14664
14665 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14666 if (!tp->regs) {
14667 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14668 err = -ENOMEM;
14669 goto err_out_free_dev;
14670 }
14671
14672 tg3_init_link_config(tp);
14673
14674 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14675 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14676
14677 dev->ethtool_ops = &tg3_ethtool_ops;
14678 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14679 dev->irq = pdev->irq;
14680
14681 err = tg3_get_invariants(tp);
14682 if (err) {
14683 dev_err(&pdev->dev,
14684 "Problem fetching invariants of chip, aborting\n");
14685 goto err_out_iounmap;
14686 }
14687
14688 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14689 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14690 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14691 dev->netdev_ops = &tg3_netdev_ops;
14692 else
14693 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14694
14695
14696 /* The EPB bridge inside 5714, 5715, and 5780 and any
14697 * device behind the EPB cannot support DMA addresses > 40-bit.
14698 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14699 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14700 * do DMA address check in tg3_start_xmit().
14701 */
14702 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14703 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14704 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14705 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14706 #ifdef CONFIG_HIGHMEM
14707 dma_mask = DMA_BIT_MASK(64);
14708 #endif
14709 } else
14710 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14711
14712 /* Configure DMA attributes. */
14713 if (dma_mask > DMA_BIT_MASK(32)) {
14714 err = pci_set_dma_mask(pdev, dma_mask);
14715 if (!err) {
14716 dev->features |= NETIF_F_HIGHDMA;
14717 err = pci_set_consistent_dma_mask(pdev,
14718 persist_dma_mask);
14719 if (err < 0) {
14720 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14721 "DMA for consistent allocations\n");
14722 goto err_out_iounmap;
14723 }
14724 }
14725 }
14726 if (err || dma_mask == DMA_BIT_MASK(32)) {
14727 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14728 if (err) {
14729 dev_err(&pdev->dev,
14730 "No usable DMA configuration, aborting\n");
14731 goto err_out_iounmap;
14732 }
14733 }
14734
14735 tg3_init_bufmgr_config(tp);
14736
14737 /* Selectively allow TSO based on operating conditions */
14738 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14739 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14740 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14741 else {
14742 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14743 tp->fw_needed = NULL;
14744 }
14745
14746 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14747 tp->fw_needed = FIRMWARE_TG3;
14748
14749 /* TSO is on by default on chips that support hardware TSO.
14750 * Firmware TSO on older chips gives lower performance, so it
14751 * is off by default, but can be enabled using ethtool.
14752 */
14753 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14754 (dev->features & NETIF_F_IP_CSUM)) {
14755 dev->features |= NETIF_F_TSO;
14756 vlan_features_add(dev, NETIF_F_TSO);
14757 }
14758 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14759 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14760 if (dev->features & NETIF_F_IPV6_CSUM) {
14761 dev->features |= NETIF_F_TSO6;
14762 vlan_features_add(dev, NETIF_F_TSO6);
14763 }
14764 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14765 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14766 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14767 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14768 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14769 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14770 dev->features |= NETIF_F_TSO_ECN;
14771 vlan_features_add(dev, NETIF_F_TSO_ECN);
14772 }
14773 }
14774
14775 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14776 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14777 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14778 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14779 tp->rx_pending = 63;
14780 }
14781
14782 err = tg3_get_device_address(tp);
14783 if (err) {
14784 dev_err(&pdev->dev,
14785 "Could not obtain valid ethernet address, aborting\n");
14786 goto err_out_iounmap;
14787 }
14788
14789 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14790 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14791 if (!tp->aperegs) {
14792 dev_err(&pdev->dev,
14793 "Cannot map APE registers, aborting\n");
14794 err = -ENOMEM;
14795 goto err_out_iounmap;
14796 }
14797
14798 tg3_ape_lock_init(tp);
14799
14800 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14801 tg3_read_dash_ver(tp);
14802 }
14803
14804 /*
14805 * Reset chip in case UNDI or EFI driver did not shutdown
14806 * DMA self test will enable WDMAC and we'll see (spurious)
14807 * pending DMA on the PCI bus at that point.
14808 */
14809 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14810 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14811 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14812 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14813 }
14814
14815 err = tg3_test_dma(tp);
14816 if (err) {
14817 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14818 goto err_out_apeunmap;
14819 }
14820
14821 /* flow control autonegotiation is default behavior */
14822 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14823 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14824
14825 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14826 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14827 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14828 for (i = 0; i < tp->irq_max; i++) {
14829 struct tg3_napi *tnapi = &tp->napi[i];
14830
14831 tnapi->tp = tp;
14832 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14833
14834 tnapi->int_mbox = intmbx;
14835 if (i < 4)
14836 intmbx += 0x8;
14837 else
14838 intmbx += 0x4;
14839
14840 tnapi->consmbox = rcvmbx;
14841 tnapi->prodmbox = sndmbx;
14842
14843 if (i)
14844 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14845 else
14846 tnapi->coal_now = HOSTCC_MODE_NOW;
14847
14848 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14849 break;
14850
14851 /*
14852 * If we support MSIX, we'll be using RSS. If we're using
14853 * RSS, the first vector only handles link interrupts and the
14854 * remaining vectors handle rx and tx interrupts. Reuse the
14855 * mailbox values for the next iteration. The values we setup
14856 * above are still useful for the single vectored mode.
14857 */
14858 if (!i)
14859 continue;
14860
14861 rcvmbx += 0x8;
14862
14863 if (sndmbx & 0x4)
14864 sndmbx -= 0x4;
14865 else
14866 sndmbx += 0xc;
14867 }
14868
14869 tg3_init_coal(tp);
14870
14871 pci_set_drvdata(pdev, dev);
14872
14873 err = register_netdev(dev);
14874 if (err) {
14875 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14876 goto err_out_apeunmap;
14877 }
14878
14879 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14880 tp->board_part_number,
14881 tp->pci_chip_rev_id,
14882 tg3_bus_string(tp, str),
14883 dev->dev_addr);
14884
14885 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14886 struct phy_device *phydev;
14887 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14888 netdev_info(dev,
14889 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14890 phydev->drv->name, dev_name(&phydev->dev));
14891 } else {
14892 char *ethtype;
14893
14894 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14895 ethtype = "10/100Base-TX";
14896 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14897 ethtype = "1000Base-SX";
14898 else
14899 ethtype = "10/100/1000Base-T";
14900
14901 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14902 "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14903 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14904 }
14905
14906 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14907 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14908 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14909 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14910 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14911 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14912 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14913 tp->dma_rwctrl,
14914 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14915 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14916
14917 return 0;
14918
14919 err_out_apeunmap:
14920 if (tp->aperegs) {
14921 iounmap(tp->aperegs);
14922 tp->aperegs = NULL;
14923 }
14924
14925 err_out_iounmap:
14926 if (tp->regs) {
14927 iounmap(tp->regs);
14928 tp->regs = NULL;
14929 }
14930
14931 err_out_free_dev:
14932 free_netdev(dev);
14933
14934 err_out_free_res:
14935 pci_release_regions(pdev);
14936
14937 err_out_disable_pdev:
14938 pci_disable_device(pdev);
14939 pci_set_drvdata(pdev, NULL);
14940 return err;
14941 }
14942
14943 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14944 {
14945 struct net_device *dev = pci_get_drvdata(pdev);
14946
14947 if (dev) {
14948 struct tg3 *tp = netdev_priv(dev);
14949
14950 if (tp->fw)
14951 release_firmware(tp->fw);
14952
14953 flush_scheduled_work();
14954
14955 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14956 tg3_phy_fini(tp);
14957 tg3_mdio_fini(tp);
14958 }
14959
14960 unregister_netdev(dev);
14961 if (tp->aperegs) {
14962 iounmap(tp->aperegs);
14963 tp->aperegs = NULL;
14964 }
14965 if (tp->regs) {
14966 iounmap(tp->regs);
14967 tp->regs = NULL;
14968 }
14969 free_netdev(dev);
14970 pci_release_regions(pdev);
14971 pci_disable_device(pdev);
14972 pci_set_drvdata(pdev, NULL);
14973 }
14974 }
14975
14976 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14977 {
14978 struct net_device *dev = pci_get_drvdata(pdev);
14979 struct tg3 *tp = netdev_priv(dev);
14980 pci_power_t target_state;
14981 int err;
14982
14983 /* PCI register 4 needs to be saved whether netif_running() or not.
14984 * MSI address and data need to be saved if using MSI and
14985 * netif_running().
14986 */
14987 pci_save_state(pdev);
14988
14989 if (!netif_running(dev))
14990 return 0;
14991
14992 flush_scheduled_work();
14993 tg3_phy_stop(tp);
14994 tg3_netif_stop(tp);
14995
14996 del_timer_sync(&tp->timer);
14997
14998 tg3_full_lock(tp, 1);
14999 tg3_disable_ints(tp);
15000 tg3_full_unlock(tp);
15001
15002 netif_device_detach(dev);
15003
15004 tg3_full_lock(tp, 0);
15005 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15006 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15007 tg3_full_unlock(tp);
15008
15009 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
15010
15011 err = tg3_set_power_state(tp, target_state);
15012 if (err) {
15013 int err2;
15014
15015 tg3_full_lock(tp, 0);
15016
15017 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15018 err2 = tg3_restart_hw(tp, 1);
15019 if (err2)
15020 goto out;
15021
15022 tp->timer.expires = jiffies + tp->timer_offset;
15023 add_timer(&tp->timer);
15024
15025 netif_device_attach(dev);
15026 tg3_netif_start(tp);
15027
15028 out:
15029 tg3_full_unlock(tp);
15030
15031 if (!err2)
15032 tg3_phy_start(tp);
15033 }
15034
15035 return err;
15036 }
15037
15038 static int tg3_resume(struct pci_dev *pdev)
15039 {
15040 struct net_device *dev = pci_get_drvdata(pdev);
15041 struct tg3 *tp = netdev_priv(dev);
15042 int err;
15043
15044 pci_restore_state(tp->pdev);
15045
15046 if (!netif_running(dev))
15047 return 0;
15048
15049 err = tg3_set_power_state(tp, PCI_D0);
15050 if (err)
15051 return err;
15052
15053 netif_device_attach(dev);
15054
15055 tg3_full_lock(tp, 0);
15056
15057 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15058 err = tg3_restart_hw(tp, 1);
15059 if (err)
15060 goto out;
15061
15062 tp->timer.expires = jiffies + tp->timer_offset;
15063 add_timer(&tp->timer);
15064
15065 tg3_netif_start(tp);
15066
15067 out:
15068 tg3_full_unlock(tp);
15069
15070 if (!err)
15071 tg3_phy_start(tp);
15072
15073 return err;
15074 }
15075
15076 static struct pci_driver tg3_driver = {
15077 .name = DRV_MODULE_NAME,
15078 .id_table = tg3_pci_tbl,
15079 .probe = tg3_init_one,
15080 .remove = __devexit_p(tg3_remove_one),
15081 .suspend = tg3_suspend,
15082 .resume = tg3_resume
15083 };
15084
15085 static int __init tg3_init(void)
15086 {
15087 return pci_register_driver(&tg3_driver);
15088 }
15089
15090 static void __exit tg3_cleanup(void)
15091 {
15092 pci_unregister_driver(&tg3_driver);
15093 }
15094
15095 module_init(tg3_init);
15096 module_exit(tg3_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree