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ath9k_hw: Fix XPABIAS level configuration for AR9003
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob17f73e4d8f36e327d7f62e1751812663c9dae0e3
1 /*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "ar9003_phy.h"
19 #include "ar9003_eeprom.h"
20
21 #define COMP_HDR_LEN 4
22 #define COMP_CKSUM_LEN 2
23
24 #define AR_CH0_TOP (0x00016288)
25 #define AR_CH0_TOP_XPABIASLVL (0x300)
26 #define AR_CH0_TOP_XPABIASLVL_S (8)
27
28 #define AR_CH0_THERM (0x00016290)
29 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
30 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
31 #define AR_CH0_THERM_XPASHORT2GND 0x4
32 #define AR_CH0_THERM_XPASHORT2GND_S 2
33
34 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
35 #define AR_SWITCH_TABLE_COM_ALL_S (0)
36
37 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
38 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
39
40 #define AR_SWITCH_TABLE_ALL (0xfff)
41 #define AR_SWITCH_TABLE_ALL_S (0)
42
43 #define LE16(x) __constant_cpu_to_le16(x)
44 #define LE32(x) __constant_cpu_to_le32(x)
45
46 /* Local defines to distinguish between extension and control CTL's */
47 #define EXT_ADDITIVE (0x8000)
48 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
49 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
50 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
51 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
52 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
53 #define PWRINCR_3_TO_1_CHAIN 9 /* 10*log(3)*2 */
54 #define PWRINCR_3_TO_2_CHAIN 3 /* floor(10*log(3/2)*2) */
55 #define PWRINCR_2_TO_1_CHAIN 6 /* 10*log(2)*2 */
56
57 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
58 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
59
60 static const struct ar9300_eeprom ar9300_default = {
61 .eepromVersion = 2,
62 .templateVersion = 2,
63 .macAddr = {1, 2, 3, 4, 5, 6},
64 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
65 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
66 .baseEepHeader = {
67 .regDmn = { LE16(0), LE16(0x1f) },
68 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
69 .opCapFlags = {
70 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
71 .eepMisc = 0,
72 },
73 .rfSilent = 0,
74 .blueToothOptions = 0,
75 .deviceCap = 0,
76 .deviceType = 5, /* takes lower byte in eeprom location */
77 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
78 .params_for_tuning_caps = {0, 0},
79 .featureEnable = 0x0c,
80 /*
81 * bit0 - enable tx temp comp - disabled
82 * bit1 - enable tx volt comp - disabled
83 * bit2 - enable fastClock - enabled
84 * bit3 - enable doubling - enabled
85 * bit4 - enable internal regulator - disabled
86 * bit5 - enable pa predistortion - disabled
87 */
88 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
89 .eepromWriteEnableGpio = 3,
90 .wlanDisableGpio = 0,
91 .wlanLedGpio = 8,
92 .rxBandSelectGpio = 0xff,
93 .txrxgain = 0,
94 .swreg = 0,
95 },
96 .modalHeader2G = {
97 /* ar9300_modal_eep_header 2g */
98 /* 4 idle,t1,t2,b(4 bits per setting) */
99 .antCtrlCommon = LE32(0x110),
100 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
101 .antCtrlCommon2 = LE32(0x22222),
102
103 /*
104 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
105 * rx1, rx12, b (2 bits each)
106 */
107 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
108
109 /*
110 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
111 * for ar9280 (0xa20c/b20c 5:0)
112 */
113 .xatten1DB = {0, 0, 0},
114
115 /*
116 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
117 * for ar9280 (0xa20c/b20c 16:12
118 */
119 .xatten1Margin = {0, 0, 0},
120 .tempSlope = 36,
121 .voltSlope = 0,
122
123 /*
124 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
125 * channels in usual fbin coding format
126 */
127 .spurChans = {0, 0, 0, 0, 0},
128
129 /*
130 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
131 * if the register is per chain
132 */
133 .noiseFloorThreshCh = {-1, 0, 0},
134 .ob = {1, 1, 1},/* 3 chain */
135 .db_stage2 = {1, 1, 1}, /* 3 chain */
136 .db_stage3 = {0, 0, 0},
137 .db_stage4 = {0, 0, 0},
138 .xpaBiasLvl = 0,
139 .txFrameToDataStart = 0x0e,
140 .txFrameToPaOn = 0x0e,
141 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
142 .antennaGain = 0,
143 .switchSettling = 0x2c,
144 .adcDesiredSize = -30,
145 .txEndToXpaOff = 0,
146 .txEndToRxOn = 0x2,
147 .txFrameToXpaOn = 0xe,
148 .thresh62 = 28,
149 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
150 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
151 .futureModal = {
152 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
153 },
154 },
155 .base_ext1 = {
156 .ant_div_control = 0,
157 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
158 },
159 .calFreqPier2G = {
160 FREQ2FBIN(2412, 1),
161 FREQ2FBIN(2437, 1),
162 FREQ2FBIN(2472, 1),
163 },
164 /* ar9300_cal_data_per_freq_op_loop 2g */
165 .calPierData2G = {
166 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
167 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
168 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
169 },
170 .calTarget_freqbin_Cck = {
171 FREQ2FBIN(2412, 1),
172 FREQ2FBIN(2484, 1),
173 },
174 .calTarget_freqbin_2G = {
175 FREQ2FBIN(2412, 1),
176 FREQ2FBIN(2437, 1),
177 FREQ2FBIN(2472, 1)
178 },
179 .calTarget_freqbin_2GHT20 = {
180 FREQ2FBIN(2412, 1),
181 FREQ2FBIN(2437, 1),
182 FREQ2FBIN(2472, 1)
183 },
184 .calTarget_freqbin_2GHT40 = {
185 FREQ2FBIN(2412, 1),
186 FREQ2FBIN(2437, 1),
187 FREQ2FBIN(2472, 1)
188 },
189 .calTargetPowerCck = {
190 /* 1L-5L,5S,11L,11S */
191 { {36, 36, 36, 36} },
192 { {36, 36, 36, 36} },
193 },
194 .calTargetPower2G = {
195 /* 6-24,36,48,54 */
196 { {32, 32, 28, 24} },
197 { {32, 32, 28, 24} },
198 { {32, 32, 28, 24} },
199 },
200 .calTargetPower2GHT20 = {
201 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
202 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
203 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
204 },
205 .calTargetPower2GHT40 = {
206 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
207 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
208 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
209 },
210 .ctlIndex_2G = {
211 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
212 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
213 },
214 .ctl_freqbin_2G = {
215 {
216 FREQ2FBIN(2412, 1),
217 FREQ2FBIN(2417, 1),
218 FREQ2FBIN(2457, 1),
219 FREQ2FBIN(2462, 1)
220 },
221 {
222 FREQ2FBIN(2412, 1),
223 FREQ2FBIN(2417, 1),
224 FREQ2FBIN(2462, 1),
225 0xFF,
226 },
227
228 {
229 FREQ2FBIN(2412, 1),
230 FREQ2FBIN(2417, 1),
231 FREQ2FBIN(2462, 1),
232 0xFF,
233 },
234 {
235 FREQ2FBIN(2422, 1),
236 FREQ2FBIN(2427, 1),
237 FREQ2FBIN(2447, 1),
238 FREQ2FBIN(2452, 1)
239 },
240
241 {
242 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
243 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
244 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
245 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
246 },
247
248 {
249 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
250 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
251 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
252 0,
253 },
254
255 {
256 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
257 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
258 FREQ2FBIN(2472, 1),
259 0,
260 },
261
262 {
263 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
264 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
265 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
266 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
267 },
268
269 {
270 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
271 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
272 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
273 },
274
275 {
276 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
277 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
278 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
279 0
280 },
281
282 {
283 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
284 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
285 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
286 0
287 },
288
289 {
290 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
291 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
292 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
293 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
294 }
295 },
296 .ctlPowerData_2G = {
297 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
298 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
299 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
300
301 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
302 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
303 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
304
305 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
306 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
307 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
308
309 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
310 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
311 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
312 },
313 .modalHeader5G = {
314 /* 4 idle,t1,t2,b (4 bits per setting) */
315 .antCtrlCommon = LE32(0x110),
316 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
317 .antCtrlCommon2 = LE32(0x22222),
318 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
319 .antCtrlChain = {
320 LE16(0x000), LE16(0x000), LE16(0x000),
321 },
322 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
323 .xatten1DB = {0, 0, 0},
324
325 /*
326 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
327 * for merlin (0xa20c/b20c 16:12
328 */
329 .xatten1Margin = {0, 0, 0},
330 .tempSlope = 68,
331 .voltSlope = 0,
332 /* spurChans spur channels in usual fbin coding format */
333 .spurChans = {0, 0, 0, 0, 0},
334 /* noiseFloorThreshCh Check if the register is per chain */
335 .noiseFloorThreshCh = {-1, 0, 0},
336 .ob = {3, 3, 3}, /* 3 chain */
337 .db_stage2 = {3, 3, 3}, /* 3 chain */
338 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
339 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
340 .xpaBiasLvl = 0,
341 .txFrameToDataStart = 0x0e,
342 .txFrameToPaOn = 0x0e,
343 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
344 .antennaGain = 0,
345 .switchSettling = 0x2d,
346 .adcDesiredSize = -30,
347 .txEndToXpaOff = 0,
348 .txEndToRxOn = 0x2,
349 .txFrameToXpaOn = 0xe,
350 .thresh62 = 28,
351 .papdRateMaskHt20 = LE32(0x0c80c080),
352 .papdRateMaskHt40 = LE32(0x0080c080),
353 .futureModal = {
354 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
355 },
356 },
357 .base_ext2 = {
358 .tempSlopeLow = 0,
359 .tempSlopeHigh = 0,
360 .xatten1DBLow = {0, 0, 0},
361 .xatten1MarginLow = {0, 0, 0},
362 .xatten1DBHigh = {0, 0, 0},
363 .xatten1MarginHigh = {0, 0, 0}
364 },
365 .calFreqPier5G = {
366 FREQ2FBIN(5180, 0),
367 FREQ2FBIN(5220, 0),
368 FREQ2FBIN(5320, 0),
369 FREQ2FBIN(5400, 0),
370 FREQ2FBIN(5500, 0),
371 FREQ2FBIN(5600, 0),
372 FREQ2FBIN(5725, 0),
373 FREQ2FBIN(5825, 0)
374 },
375 .calPierData5G = {
376 {
377 {0, 0, 0, 0, 0},
378 {0, 0, 0, 0, 0},
379 {0, 0, 0, 0, 0},
380 {0, 0, 0, 0, 0},
381 {0, 0, 0, 0, 0},
382 {0, 0, 0, 0, 0},
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 },
386 {
387 {0, 0, 0, 0, 0},
388 {0, 0, 0, 0, 0},
389 {0, 0, 0, 0, 0},
390 {0, 0, 0, 0, 0},
391 {0, 0, 0, 0, 0},
392 {0, 0, 0, 0, 0},
393 {0, 0, 0, 0, 0},
394 {0, 0, 0, 0, 0},
395 },
396 {
397 {0, 0, 0, 0, 0},
398 {0, 0, 0, 0, 0},
399 {0, 0, 0, 0, 0},
400 {0, 0, 0, 0, 0},
401 {0, 0, 0, 0, 0},
402 {0, 0, 0, 0, 0},
403 {0, 0, 0, 0, 0},
404 {0, 0, 0, 0, 0},
405 },
406
407 },
408 .calTarget_freqbin_5G = {
409 FREQ2FBIN(5180, 0),
410 FREQ2FBIN(5220, 0),
411 FREQ2FBIN(5320, 0),
412 FREQ2FBIN(5400, 0),
413 FREQ2FBIN(5500, 0),
414 FREQ2FBIN(5600, 0),
415 FREQ2FBIN(5725, 0),
416 FREQ2FBIN(5825, 0)
417 },
418 .calTarget_freqbin_5GHT20 = {
419 FREQ2FBIN(5180, 0),
420 FREQ2FBIN(5240, 0),
421 FREQ2FBIN(5320, 0),
422 FREQ2FBIN(5500, 0),
423 FREQ2FBIN(5700, 0),
424 FREQ2FBIN(5745, 0),
425 FREQ2FBIN(5725, 0),
426 FREQ2FBIN(5825, 0)
427 },
428 .calTarget_freqbin_5GHT40 = {
429 FREQ2FBIN(5180, 0),
430 FREQ2FBIN(5240, 0),
431 FREQ2FBIN(5320, 0),
432 FREQ2FBIN(5500, 0),
433 FREQ2FBIN(5700, 0),
434 FREQ2FBIN(5745, 0),
435 FREQ2FBIN(5725, 0),
436 FREQ2FBIN(5825, 0)
437 },
438 .calTargetPower5G = {
439 /* 6-24,36,48,54 */
440 { {20, 20, 20, 10} },
441 { {20, 20, 20, 10} },
442 { {20, 20, 20, 10} },
443 { {20, 20, 20, 10} },
444 { {20, 20, 20, 10} },
445 { {20, 20, 20, 10} },
446 { {20, 20, 20, 10} },
447 { {20, 20, 20, 10} },
448 },
449 .calTargetPower5GHT20 = {
450 /*
451 * 0_8_16,1-3_9-11_17-19,
452 * 4,5,6,7,12,13,14,15,20,21,22,23
453 */
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
458 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
459 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
460 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
461 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
462 },
463 .calTargetPower5GHT40 = {
464 /*
465 * 0_8_16,1-3_9-11_17-19,
466 * 4,5,6,7,12,13,14,15,20,21,22,23
467 */
468 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
469 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
470 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
471 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
472 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
473 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
474 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
475 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
476 },
477 .ctlIndex_5G = {
478 0x10, 0x16, 0x18, 0x40, 0x46,
479 0x48, 0x30, 0x36, 0x38
480 },
481 .ctl_freqbin_5G = {
482 {
483 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
484 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
485 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
486 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
487 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
488 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
489 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
490 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
491 },
492 {
493 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
494 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
495 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
496 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
497 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
498 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
499 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
500 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
501 },
502
503 {
504 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
505 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
506 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
507 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
508 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
509 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
510 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
511 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
512 },
513
514 {
515 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
516 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
517 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
518 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
519 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
520 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
521 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
522 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
523 },
524
525 {
526 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
527 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
528 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
529 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
530 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
531 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
532 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
533 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
534 },
535
536 {
537 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
538 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
539 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
540 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
541 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
542 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
543 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
544 /* Data[5].ctlEdges[7].bChannel */ 0xFF
545 },
546
547 {
548 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
549 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
550 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
551 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
552 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
553 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
554 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
555 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
556 },
557
558 {
559 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
560 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
561 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
562 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
563 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
564 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
565 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
566 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
567 },
568
569 {
570 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
571 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
572 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
573 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
574 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
575 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
576 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
577 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
578 }
579 },
580 .ctlPowerData_5G = {
581 {
582 {
583 {60, 1}, {60, 1}, {60, 1}, {60, 1},
584 {60, 1}, {60, 1}, {60, 1}, {60, 0},
585 }
586 },
587 {
588 {
589 {60, 1}, {60, 1}, {60, 1}, {60, 1},
590 {60, 1}, {60, 1}, {60, 1}, {60, 0},
591 }
592 },
593 {
594 {
595 {60, 0}, {60, 1}, {60, 0}, {60, 1},
596 {60, 1}, {60, 1}, {60, 1}, {60, 1},
597 }
598 },
599 {
600 {
601 {60, 0}, {60, 1}, {60, 1}, {60, 0},
602 {60, 1}, {60, 0}, {60, 0}, {60, 0},
603 }
604 },
605 {
606 {
607 {60, 1}, {60, 1}, {60, 1}, {60, 0},
608 {60, 0}, {60, 0}, {60, 0}, {60, 0},
609 }
610 },
611 {
612 {
613 {60, 1}, {60, 1}, {60, 1}, {60, 1},
614 {60, 1}, {60, 0}, {60, 0}, {60, 0},
615 }
616 },
617 {
618 {
619 {60, 1}, {60, 1}, {60, 1}, {60, 1},
620 {60, 1}, {60, 1}, {60, 1}, {60, 1},
621 }
622 },
623 {
624 {
625 {60, 1}, {60, 1}, {60, 0}, {60, 1},
626 {60, 1}, {60, 1}, {60, 1}, {60, 0},
627 }
628 },
629 {
630 {
631 {60, 1}, {60, 0}, {60, 1}, {60, 1},
632 {60, 1}, {60, 1}, {60, 0}, {60, 1},
633 }
634 },
635 }
636 };
637
638 static const struct ar9300_eeprom ar9300_x113 = {
639 .eepromVersion = 2,
640 .templateVersion = 6,
641 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
642 .custData = {"x113-023-f0000"},
643 .baseEepHeader = {
644 .regDmn = { LE16(0), LE16(0x1f) },
645 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
646 .opCapFlags = {
647 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
648 .eepMisc = 0,
649 },
650 .rfSilent = 0,
651 .blueToothOptions = 0,
652 .deviceCap = 0,
653 .deviceType = 5, /* takes lower byte in eeprom location */
654 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
655 .params_for_tuning_caps = {0, 0},
656 .featureEnable = 0x0d,
657 /*
658 * bit0 - enable tx temp comp - disabled
659 * bit1 - enable tx volt comp - disabled
660 * bit2 - enable fastClock - enabled
661 * bit3 - enable doubling - enabled
662 * bit4 - enable internal regulator - disabled
663 * bit5 - enable pa predistortion - disabled
664 */
665 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
666 .eepromWriteEnableGpio = 6,
667 .wlanDisableGpio = 0,
668 .wlanLedGpio = 8,
669 .rxBandSelectGpio = 0xff,
670 .txrxgain = 0x21,
671 .swreg = 0,
672 },
673 .modalHeader2G = {
674 /* ar9300_modal_eep_header 2g */
675 /* 4 idle,t1,t2,b(4 bits per setting) */
676 .antCtrlCommon = LE32(0x110),
677 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
678 .antCtrlCommon2 = LE32(0x44444),
679
680 /*
681 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
682 * rx1, rx12, b (2 bits each)
683 */
684 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
685
686 /*
687 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
688 * for ar9280 (0xa20c/b20c 5:0)
689 */
690 .xatten1DB = {0, 0, 0},
691
692 /*
693 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
694 * for ar9280 (0xa20c/b20c 16:12
695 */
696 .xatten1Margin = {0, 0, 0},
697 .tempSlope = 25,
698 .voltSlope = 0,
699
700 /*
701 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
702 * channels in usual fbin coding format
703 */
704 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
705
706 /*
707 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
708 * if the register is per chain
709 */
710 .noiseFloorThreshCh = {-1, 0, 0},
711 .ob = {1, 1, 1},/* 3 chain */
712 .db_stage2 = {1, 1, 1}, /* 3 chain */
713 .db_stage3 = {0, 0, 0},
714 .db_stage4 = {0, 0, 0},
715 .xpaBiasLvl = 0,
716 .txFrameToDataStart = 0x0e,
717 .txFrameToPaOn = 0x0e,
718 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
719 .antennaGain = 0,
720 .switchSettling = 0x2c,
721 .adcDesiredSize = -30,
722 .txEndToXpaOff = 0,
723 .txEndToRxOn = 0x2,
724 .txFrameToXpaOn = 0xe,
725 .thresh62 = 28,
726 .papdRateMaskHt20 = LE32(0x0c80c080),
727 .papdRateMaskHt40 = LE32(0x0080c080),
728 .futureModal = {
729 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
730 },
731 },
732 .base_ext1 = {
733 .ant_div_control = 0,
734 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
735 },
736 .calFreqPier2G = {
737 FREQ2FBIN(2412, 1),
738 FREQ2FBIN(2437, 1),
739 FREQ2FBIN(2472, 1),
740 },
741 /* ar9300_cal_data_per_freq_op_loop 2g */
742 .calPierData2G = {
743 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
744 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
745 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
746 },
747 .calTarget_freqbin_Cck = {
748 FREQ2FBIN(2412, 1),
749 FREQ2FBIN(2472, 1),
750 },
751 .calTarget_freqbin_2G = {
752 FREQ2FBIN(2412, 1),
753 FREQ2FBIN(2437, 1),
754 FREQ2FBIN(2472, 1)
755 },
756 .calTarget_freqbin_2GHT20 = {
757 FREQ2FBIN(2412, 1),
758 FREQ2FBIN(2437, 1),
759 FREQ2FBIN(2472, 1)
760 },
761 .calTarget_freqbin_2GHT40 = {
762 FREQ2FBIN(2412, 1),
763 FREQ2FBIN(2437, 1),
764 FREQ2FBIN(2472, 1)
765 },
766 .calTargetPowerCck = {
767 /* 1L-5L,5S,11L,11S */
768 { {34, 34, 34, 34} },
769 { {34, 34, 34, 34} },
770 },
771 .calTargetPower2G = {
772 /* 6-24,36,48,54 */
773 { {34, 34, 32, 32} },
774 { {34, 34, 32, 32} },
775 { {34, 34, 32, 32} },
776 },
777 .calTargetPower2GHT20 = {
778 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
779 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
780 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
781 },
782 .calTargetPower2GHT40 = {
783 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
784 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
785 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
786 },
787 .ctlIndex_2G = {
788 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
789 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
790 },
791 .ctl_freqbin_2G = {
792 {
793 FREQ2FBIN(2412, 1),
794 FREQ2FBIN(2417, 1),
795 FREQ2FBIN(2457, 1),
796 FREQ2FBIN(2462, 1)
797 },
798 {
799 FREQ2FBIN(2412, 1),
800 FREQ2FBIN(2417, 1),
801 FREQ2FBIN(2462, 1),
802 0xFF,
803 },
804
805 {
806 FREQ2FBIN(2412, 1),
807 FREQ2FBIN(2417, 1),
808 FREQ2FBIN(2462, 1),
809 0xFF,
810 },
811 {
812 FREQ2FBIN(2422, 1),
813 FREQ2FBIN(2427, 1),
814 FREQ2FBIN(2447, 1),
815 FREQ2FBIN(2452, 1)
816 },
817
818 {
819 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
820 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
821 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
822 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
823 },
824
825 {
826 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
827 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
828 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
829 0,
830 },
831
832 {
833 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
834 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
835 FREQ2FBIN(2472, 1),
836 0,
837 },
838
839 {
840 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
841 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
842 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
843 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
844 },
845
846 {
847 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
848 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
849 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
850 },
851
852 {
853 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
854 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
855 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
856 0
857 },
858
859 {
860 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
861 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
862 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
863 0
864 },
865
866 {
867 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
868 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
869 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
870 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
871 }
872 },
873 .ctlPowerData_2G = {
874 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
875 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
876 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
877
878 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
879 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
880 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
881
882 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
883 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
884 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
885
886 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
887 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
888 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
889 },
890 .modalHeader5G = {
891 /* 4 idle,t1,t2,b (4 bits per setting) */
892 .antCtrlCommon = LE32(0x220),
893 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
894 .antCtrlCommon2 = LE32(0x11111),
895 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
896 .antCtrlChain = {
897 LE16(0x150), LE16(0x150), LE16(0x150),
898 },
899 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
900 .xatten1DB = {0, 0, 0},
901
902 /*
903 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
904 * for merlin (0xa20c/b20c 16:12
905 */
906 .xatten1Margin = {0, 0, 0},
907 .tempSlope = 68,
908 .voltSlope = 0,
909 /* spurChans spur channels in usual fbin coding format */
910 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
911 /* noiseFloorThreshCh Check if the register is per chain */
912 .noiseFloorThreshCh = {-1, 0, 0},
913 .ob = {3, 3, 3}, /* 3 chain */
914 .db_stage2 = {3, 3, 3}, /* 3 chain */
915 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
916 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
917 .xpaBiasLvl = 0,
918 .txFrameToDataStart = 0x0e,
919 .txFrameToPaOn = 0x0e,
920 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
921 .antennaGain = 0,
922 .switchSettling = 0x2d,
923 .adcDesiredSize = -30,
924 .txEndToXpaOff = 0,
925 .txEndToRxOn = 0x2,
926 .txFrameToXpaOn = 0xe,
927 .thresh62 = 28,
928 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
929 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
930 .futureModal = {
931 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
932 },
933 },
934 .base_ext2 = {
935 .tempSlopeLow = 72,
936 .tempSlopeHigh = 105,
937 .xatten1DBLow = {0, 0, 0},
938 .xatten1MarginLow = {0, 0, 0},
939 .xatten1DBHigh = {0, 0, 0},
940 .xatten1MarginHigh = {0, 0, 0}
941 },
942 .calFreqPier5G = {
943 FREQ2FBIN(5180, 0),
944 FREQ2FBIN(5240, 0),
945 FREQ2FBIN(5320, 0),
946 FREQ2FBIN(5400, 0),
947 FREQ2FBIN(5500, 0),
948 FREQ2FBIN(5600, 0),
949 FREQ2FBIN(5745, 0),
950 FREQ2FBIN(5785, 0)
951 },
952 .calPierData5G = {
953 {
954 {0, 0, 0, 0, 0},
955 {0, 0, 0, 0, 0},
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 {0, 0, 0, 0, 0},
960 {0, 0, 0, 0, 0},
961 {0, 0, 0, 0, 0},
962 },
963 {
964 {0, 0, 0, 0, 0},
965 {0, 0, 0, 0, 0},
966 {0, 0, 0, 0, 0},
967 {0, 0, 0, 0, 0},
968 {0, 0, 0, 0, 0},
969 {0, 0, 0, 0, 0},
970 {0, 0, 0, 0, 0},
971 {0, 0, 0, 0, 0},
972 },
973 {
974 {0, 0, 0, 0, 0},
975 {0, 0, 0, 0, 0},
976 {0, 0, 0, 0, 0},
977 {0, 0, 0, 0, 0},
978 {0, 0, 0, 0, 0},
979 {0, 0, 0, 0, 0},
980 {0, 0, 0, 0, 0},
981 {0, 0, 0, 0, 0},
982 },
983
984 },
985 .calTarget_freqbin_5G = {
986 FREQ2FBIN(5180, 0),
987 FREQ2FBIN(5220, 0),
988 FREQ2FBIN(5320, 0),
989 FREQ2FBIN(5400, 0),
990 FREQ2FBIN(5500, 0),
991 FREQ2FBIN(5600, 0),
992 FREQ2FBIN(5745, 0),
993 FREQ2FBIN(5785, 0)
994 },
995 .calTarget_freqbin_5GHT20 = {
996 FREQ2FBIN(5180, 0),
997 FREQ2FBIN(5240, 0),
998 FREQ2FBIN(5320, 0),
999 FREQ2FBIN(5400, 0),
1000 FREQ2FBIN(5500, 0),
1001 FREQ2FBIN(5700, 0),
1002 FREQ2FBIN(5745, 0),
1003 FREQ2FBIN(5825, 0)
1004 },
1005 .calTarget_freqbin_5GHT40 = {
1006 FREQ2FBIN(5190, 0),
1007 FREQ2FBIN(5230, 0),
1008 FREQ2FBIN(5320, 0),
1009 FREQ2FBIN(5410, 0),
1010 FREQ2FBIN(5510, 0),
1011 FREQ2FBIN(5670, 0),
1012 FREQ2FBIN(5755, 0),
1013 FREQ2FBIN(5825, 0)
1014 },
1015 .calTargetPower5G = {
1016 /* 6-24,36,48,54 */
1017 { {42, 40, 40, 34} },
1018 { {42, 40, 40, 34} },
1019 { {42, 40, 40, 34} },
1020 { {42, 40, 40, 34} },
1021 { {42, 40, 40, 34} },
1022 { {42, 40, 40, 34} },
1023 { {42, 40, 40, 34} },
1024 { {42, 40, 40, 34} },
1025 },
1026 .calTargetPower5GHT20 = {
1027 /*
1028 * 0_8_16,1-3_9-11_17-19,
1029 * 4,5,6,7,12,13,14,15,20,21,22,23
1030 */
1031 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1032 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1033 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1034 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1035 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1036 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1037 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1038 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1039 },
1040 .calTargetPower5GHT40 = {
1041 /*
1042 * 0_8_16,1-3_9-11_17-19,
1043 * 4,5,6,7,12,13,14,15,20,21,22,23
1044 */
1045 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1046 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1047 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1048 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1049 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1050 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1051 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1052 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1053 },
1054 .ctlIndex_5G = {
1055 0x10, 0x16, 0x18, 0x40, 0x46,
1056 0x48, 0x30, 0x36, 0x38
1057 },
1058 .ctl_freqbin_5G = {
1059 {
1060 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1061 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1062 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1063 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1064 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1065 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1066 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1067 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1068 },
1069 {
1070 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1071 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1072 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1073 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1074 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1075 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1076 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1077 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1078 },
1079
1080 {
1081 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1082 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1083 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1084 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1085 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1086 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1087 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1088 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1089 },
1090
1091 {
1092 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1093 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1094 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1095 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1096 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1097 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1098 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1099 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1100 },
1101
1102 {
1103 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1104 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1105 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1106 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1107 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1108 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1109 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1110 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1111 },
1112
1113 {
1114 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1115 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1116 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1117 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1118 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1119 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1120 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1121 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1122 },
1123
1124 {
1125 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1126 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1127 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1128 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1129 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1130 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1131 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1132 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1133 },
1134
1135 {
1136 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1137 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1138 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1139 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1140 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1141 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1142 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1143 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1144 },
1145
1146 {
1147 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1148 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1149 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1150 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1151 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1152 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1153 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1154 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1155 }
1156 },
1157 .ctlPowerData_5G = {
1158 {
1159 {
1160 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1161 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1162 }
1163 },
1164 {
1165 {
1166 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1167 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1168 }
1169 },
1170 {
1171 {
1172 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1173 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1174 }
1175 },
1176 {
1177 {
1178 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1179 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1180 }
1181 },
1182 {
1183 {
1184 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1185 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1186 }
1187 },
1188 {
1189 {
1190 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1191 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1192 }
1193 },
1194 {
1195 {
1196 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1197 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1198 }
1199 },
1200 {
1201 {
1202 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1203 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1204 }
1205 },
1206 {
1207 {
1208 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1209 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1210 }
1211 },
1212 }
1213 };
1214
1215
1216 static const struct ar9300_eeprom ar9300_h112 = {
1217 .eepromVersion = 2,
1218 .templateVersion = 3,
1219 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1220 .custData = {"h112-241-f0000"},
1221 .baseEepHeader = {
1222 .regDmn = { LE16(0), LE16(0x1f) },
1223 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1224 .opCapFlags = {
1225 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1226 .eepMisc = 0,
1227 },
1228 .rfSilent = 0,
1229 .blueToothOptions = 0,
1230 .deviceCap = 0,
1231 .deviceType = 5, /* takes lower byte in eeprom location */
1232 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1233 .params_for_tuning_caps = {0, 0},
1234 .featureEnable = 0x0d,
1235 /*
1236 * bit0 - enable tx temp comp - disabled
1237 * bit1 - enable tx volt comp - disabled
1238 * bit2 - enable fastClock - enabled
1239 * bit3 - enable doubling - enabled
1240 * bit4 - enable internal regulator - disabled
1241 * bit5 - enable pa predistortion - disabled
1242 */
1243 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1244 .eepromWriteEnableGpio = 6,
1245 .wlanDisableGpio = 0,
1246 .wlanLedGpio = 8,
1247 .rxBandSelectGpio = 0xff,
1248 .txrxgain = 0x10,
1249 .swreg = 0,
1250 },
1251 .modalHeader2G = {
1252 /* ar9300_modal_eep_header 2g */
1253 /* 4 idle,t1,t2,b(4 bits per setting) */
1254 .antCtrlCommon = LE32(0x110),
1255 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1256 .antCtrlCommon2 = LE32(0x44444),
1257
1258 /*
1259 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1260 * rx1, rx12, b (2 bits each)
1261 */
1262 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1263
1264 /*
1265 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1266 * for ar9280 (0xa20c/b20c 5:0)
1267 */
1268 .xatten1DB = {0, 0, 0},
1269
1270 /*
1271 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1272 * for ar9280 (0xa20c/b20c 16:12
1273 */
1274 .xatten1Margin = {0, 0, 0},
1275 .tempSlope = 25,
1276 .voltSlope = 0,
1277
1278 /*
1279 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1280 * channels in usual fbin coding format
1281 */
1282 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1283
1284 /*
1285 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1286 * if the register is per chain
1287 */
1288 .noiseFloorThreshCh = {-1, 0, 0},
1289 .ob = {1, 1, 1},/* 3 chain */
1290 .db_stage2 = {1, 1, 1}, /* 3 chain */
1291 .db_stage3 = {0, 0, 0},
1292 .db_stage4 = {0, 0, 0},
1293 .xpaBiasLvl = 0,
1294 .txFrameToDataStart = 0x0e,
1295 .txFrameToPaOn = 0x0e,
1296 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1297 .antennaGain = 0,
1298 .switchSettling = 0x2c,
1299 .adcDesiredSize = -30,
1300 .txEndToXpaOff = 0,
1301 .txEndToRxOn = 0x2,
1302 .txFrameToXpaOn = 0xe,
1303 .thresh62 = 28,
1304 .papdRateMaskHt20 = LE32(0x80c080),
1305 .papdRateMaskHt40 = LE32(0x80c080),
1306 .futureModal = {
1307 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1308 },
1309 },
1310 .base_ext1 = {
1311 .ant_div_control = 0,
1312 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1313 },
1314 .calFreqPier2G = {
1315 FREQ2FBIN(2412, 1),
1316 FREQ2FBIN(2437, 1),
1317 FREQ2FBIN(2472, 1),
1318 },
1319 /* ar9300_cal_data_per_freq_op_loop 2g */
1320 .calPierData2G = {
1321 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1322 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1323 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1324 },
1325 .calTarget_freqbin_Cck = {
1326 FREQ2FBIN(2412, 1),
1327 FREQ2FBIN(2484, 1),
1328 },
1329 .calTarget_freqbin_2G = {
1330 FREQ2FBIN(2412, 1),
1331 FREQ2FBIN(2437, 1),
1332 FREQ2FBIN(2472, 1)
1333 },
1334 .calTarget_freqbin_2GHT20 = {
1335 FREQ2FBIN(2412, 1),
1336 FREQ2FBIN(2437, 1),
1337 FREQ2FBIN(2472, 1)
1338 },
1339 .calTarget_freqbin_2GHT40 = {
1340 FREQ2FBIN(2412, 1),
1341 FREQ2FBIN(2437, 1),
1342 FREQ2FBIN(2472, 1)
1343 },
1344 .calTargetPowerCck = {
1345 /* 1L-5L,5S,11L,11S */
1346 { {34, 34, 34, 34} },
1347 { {34, 34, 34, 34} },
1348 },
1349 .calTargetPower2G = {
1350 /* 6-24,36,48,54 */
1351 { {34, 34, 32, 32} },
1352 { {34, 34, 32, 32} },
1353 { {34, 34, 32, 32} },
1354 },
1355 .calTargetPower2GHT20 = {
1356 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1357 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1358 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1359 },
1360 .calTargetPower2GHT40 = {
1361 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1362 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1363 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1364 },
1365 .ctlIndex_2G = {
1366 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1367 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1368 },
1369 .ctl_freqbin_2G = {
1370 {
1371 FREQ2FBIN(2412, 1),
1372 FREQ2FBIN(2417, 1),
1373 FREQ2FBIN(2457, 1),
1374 FREQ2FBIN(2462, 1)
1375 },
1376 {
1377 FREQ2FBIN(2412, 1),
1378 FREQ2FBIN(2417, 1),
1379 FREQ2FBIN(2462, 1),
1380 0xFF,
1381 },
1382
1383 {
1384 FREQ2FBIN(2412, 1),
1385 FREQ2FBIN(2417, 1),
1386 FREQ2FBIN(2462, 1),
1387 0xFF,
1388 },
1389 {
1390 FREQ2FBIN(2422, 1),
1391 FREQ2FBIN(2427, 1),
1392 FREQ2FBIN(2447, 1),
1393 FREQ2FBIN(2452, 1)
1394 },
1395
1396 {
1397 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1398 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1399 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1400 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1401 },
1402
1403 {
1404 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1405 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1406 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1407 0,
1408 },
1409
1410 {
1411 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1412 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1413 FREQ2FBIN(2472, 1),
1414 0,
1415 },
1416
1417 {
1418 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1419 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1420 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1421 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1422 },
1423
1424 {
1425 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1426 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1427 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1428 },
1429
1430 {
1431 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1432 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1433 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1434 0
1435 },
1436
1437 {
1438 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1439 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1440 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1441 0
1442 },
1443
1444 {
1445 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1446 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1447 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1448 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1449 }
1450 },
1451 .ctlPowerData_2G = {
1452 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1453 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1454 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1455
1456 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1457 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1458 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1459
1460 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1461 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1462 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1463
1464 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1465 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1466 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1467 },
1468 .modalHeader5G = {
1469 /* 4 idle,t1,t2,b (4 bits per setting) */
1470 .antCtrlCommon = LE32(0x220),
1471 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1472 .antCtrlCommon2 = LE32(0x44444),
1473 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1474 .antCtrlChain = {
1475 LE16(0x150), LE16(0x150), LE16(0x150),
1476 },
1477 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1478 .xatten1DB = {0, 0, 0},
1479
1480 /*
1481 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1482 * for merlin (0xa20c/b20c 16:12
1483 */
1484 .xatten1Margin = {0, 0, 0},
1485 .tempSlope = 45,
1486 .voltSlope = 0,
1487 /* spurChans spur channels in usual fbin coding format */
1488 .spurChans = {0, 0, 0, 0, 0},
1489 /* noiseFloorThreshCh Check if the register is per chain */
1490 .noiseFloorThreshCh = {-1, 0, 0},
1491 .ob = {3, 3, 3}, /* 3 chain */
1492 .db_stage2 = {3, 3, 3}, /* 3 chain */
1493 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1494 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
1495 .xpaBiasLvl = 0,
1496 .txFrameToDataStart = 0x0e,
1497 .txFrameToPaOn = 0x0e,
1498 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1499 .antennaGain = 0,
1500 .switchSettling = 0x2d,
1501 .adcDesiredSize = -30,
1502 .txEndToXpaOff = 0,
1503 .txEndToRxOn = 0x2,
1504 .txFrameToXpaOn = 0xe,
1505 .thresh62 = 28,
1506 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1507 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1508 .futureModal = {
1509 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1510 },
1511 },
1512 .base_ext2 = {
1513 .tempSlopeLow = 40,
1514 .tempSlopeHigh = 50,
1515 .xatten1DBLow = {0, 0, 0},
1516 .xatten1MarginLow = {0, 0, 0},
1517 .xatten1DBHigh = {0, 0, 0},
1518 .xatten1MarginHigh = {0, 0, 0}
1519 },
1520 .calFreqPier5G = {
1521 FREQ2FBIN(5180, 0),
1522 FREQ2FBIN(5220, 0),
1523 FREQ2FBIN(5320, 0),
1524 FREQ2FBIN(5400, 0),
1525 FREQ2FBIN(5500, 0),
1526 FREQ2FBIN(5600, 0),
1527 FREQ2FBIN(5700, 0),
1528 FREQ2FBIN(5825, 0)
1529 },
1530 .calPierData5G = {
1531 {
1532 {0, 0, 0, 0, 0},
1533 {0, 0, 0, 0, 0},
1534 {0, 0, 0, 0, 0},
1535 {0, 0, 0, 0, 0},
1536 {0, 0, 0, 0, 0},
1537 {0, 0, 0, 0, 0},
1538 {0, 0, 0, 0, 0},
1539 {0, 0, 0, 0, 0},
1540 },
1541 {
1542 {0, 0, 0, 0, 0},
1543 {0, 0, 0, 0, 0},
1544 {0, 0, 0, 0, 0},
1545 {0, 0, 0, 0, 0},
1546 {0, 0, 0, 0, 0},
1547 {0, 0, 0, 0, 0},
1548 {0, 0, 0, 0, 0},
1549 {0, 0, 0, 0, 0},
1550 },
1551 {
1552 {0, 0, 0, 0, 0},
1553 {0, 0, 0, 0, 0},
1554 {0, 0, 0, 0, 0},
1555 {0, 0, 0, 0, 0},
1556 {0, 0, 0, 0, 0},
1557 {0, 0, 0, 0, 0},
1558 {0, 0, 0, 0, 0},
1559 {0, 0, 0, 0, 0},
1560 },
1561
1562 },
1563 .calTarget_freqbin_5G = {
1564 FREQ2FBIN(5180, 0),
1565 FREQ2FBIN(5240, 0),
1566 FREQ2FBIN(5320, 0),
1567 FREQ2FBIN(5400, 0),
1568 FREQ2FBIN(5500, 0),
1569 FREQ2FBIN(5600, 0),
1570 FREQ2FBIN(5700, 0),
1571 FREQ2FBIN(5825, 0)
1572 },
1573 .calTarget_freqbin_5GHT20 = {
1574 FREQ2FBIN(5180, 0),
1575 FREQ2FBIN(5240, 0),
1576 FREQ2FBIN(5320, 0),
1577 FREQ2FBIN(5400, 0),
1578 FREQ2FBIN(5500, 0),
1579 FREQ2FBIN(5700, 0),
1580 FREQ2FBIN(5745, 0),
1581 FREQ2FBIN(5825, 0)
1582 },
1583 .calTarget_freqbin_5GHT40 = {
1584 FREQ2FBIN(5180, 0),
1585 FREQ2FBIN(5240, 0),
1586 FREQ2FBIN(5320, 0),
1587 FREQ2FBIN(5400, 0),
1588 FREQ2FBIN(5500, 0),
1589 FREQ2FBIN(5700, 0),
1590 FREQ2FBIN(5745, 0),
1591 FREQ2FBIN(5825, 0)
1592 },
1593 .calTargetPower5G = {
1594 /* 6-24,36,48,54 */
1595 { {30, 30, 28, 24} },
1596 { {30, 30, 28, 24} },
1597 { {30, 30, 28, 24} },
1598 { {30, 30, 28, 24} },
1599 { {30, 30, 28, 24} },
1600 { {30, 30, 28, 24} },
1601 { {30, 30, 28, 24} },
1602 { {30, 30, 28, 24} },
1603 },
1604 .calTargetPower5GHT20 = {
1605 /*
1606 * 0_8_16,1-3_9-11_17-19,
1607 * 4,5,6,7,12,13,14,15,20,21,22,23
1608 */
1609 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1610 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1611 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1612 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1613 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1614 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1615 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1616 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1617 },
1618 .calTargetPower5GHT40 = {
1619 /*
1620 * 0_8_16,1-3_9-11_17-19,
1621 * 4,5,6,7,12,13,14,15,20,21,22,23
1622 */
1623 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1624 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1625 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1626 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1627 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1628 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1629 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1630 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1631 },
1632 .ctlIndex_5G = {
1633 0x10, 0x16, 0x18, 0x40, 0x46,
1634 0x48, 0x30, 0x36, 0x38
1635 },
1636 .ctl_freqbin_5G = {
1637 {
1638 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1639 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1640 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1641 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1642 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1643 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1644 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1645 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1646 },
1647 {
1648 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1649 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1650 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1651 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1652 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1653 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1654 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1655 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1656 },
1657
1658 {
1659 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1660 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1661 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1662 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1663 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1664 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1665 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1666 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1667 },
1668
1669 {
1670 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1671 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1672 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1673 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1674 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1675 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1676 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1677 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1678 },
1679
1680 {
1681 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1682 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1683 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1684 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1685 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1686 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1687 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1688 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1689 },
1690
1691 {
1692 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1693 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1694 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1695 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1696 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1697 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1698 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1699 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1700 },
1701
1702 {
1703 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1704 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1705 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1706 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1707 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1708 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1709 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1710 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1711 },
1712
1713 {
1714 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1715 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1716 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1717 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1718 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1719 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1720 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1721 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1722 },
1723
1724 {
1725 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1726 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1727 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1728 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1729 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1730 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1731 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1732 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1733 }
1734 },
1735 .ctlPowerData_5G = {
1736 {
1737 {
1738 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1739 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1740 }
1741 },
1742 {
1743 {
1744 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1745 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1746 }
1747 },
1748 {
1749 {
1750 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1751 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1752 }
1753 },
1754 {
1755 {
1756 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1757 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1758 }
1759 },
1760 {
1761 {
1762 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1763 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1764 }
1765 },
1766 {
1767 {
1768 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1769 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1770 }
1771 },
1772 {
1773 {
1774 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1775 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1776 }
1777 },
1778 {
1779 {
1780 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1781 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1782 }
1783 },
1784 {
1785 {
1786 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1787 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1788 }
1789 },
1790 }
1791 };
1792
1793
1794 static const struct ar9300_eeprom ar9300_x112 = {
1795 .eepromVersion = 2,
1796 .templateVersion = 5,
1797 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1798 .custData = {"x112-041-f0000"},
1799 .baseEepHeader = {
1800 .regDmn = { LE16(0), LE16(0x1f) },
1801 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1802 .opCapFlags = {
1803 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1804 .eepMisc = 0,
1805 },
1806 .rfSilent = 0,
1807 .blueToothOptions = 0,
1808 .deviceCap = 0,
1809 .deviceType = 5, /* takes lower byte in eeprom location */
1810 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1811 .params_for_tuning_caps = {0, 0},
1812 .featureEnable = 0x0d,
1813 /*
1814 * bit0 - enable tx temp comp - disabled
1815 * bit1 - enable tx volt comp - disabled
1816 * bit2 - enable fastclock - enabled
1817 * bit3 - enable doubling - enabled
1818 * bit4 - enable internal regulator - disabled
1819 * bit5 - enable pa predistortion - disabled
1820 */
1821 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1822 .eepromWriteEnableGpio = 6,
1823 .wlanDisableGpio = 0,
1824 .wlanLedGpio = 8,
1825 .rxBandSelectGpio = 0xff,
1826 .txrxgain = 0x0,
1827 .swreg = 0,
1828 },
1829 .modalHeader2G = {
1830 /* ar9300_modal_eep_header 2g */
1831 /* 4 idle,t1,t2,b(4 bits per setting) */
1832 .antCtrlCommon = LE32(0x110),
1833 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1834 .antCtrlCommon2 = LE32(0x22222),
1835
1836 /*
1837 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1838 * rx1, rx12, b (2 bits each)
1839 */
1840 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1841
1842 /*
1843 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1844 * for ar9280 (0xa20c/b20c 5:0)
1845 */
1846 .xatten1DB = {0x1b, 0x1b, 0x1b},
1847
1848 /*
1849 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1850 * for ar9280 (0xa20c/b20c 16:12
1851 */
1852 .xatten1Margin = {0x15, 0x15, 0x15},
1853 .tempSlope = 50,
1854 .voltSlope = 0,
1855
1856 /*
1857 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1858 * channels in usual fbin coding format
1859 */
1860 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1861
1862 /*
1863 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1864 * if the register is per chain
1865 */
1866 .noiseFloorThreshCh = {-1, 0, 0},
1867 .ob = {1, 1, 1},/* 3 chain */
1868 .db_stage2 = {1, 1, 1}, /* 3 chain */
1869 .db_stage3 = {0, 0, 0},
1870 .db_stage4 = {0, 0, 0},
1871 .xpaBiasLvl = 0,
1872 .txFrameToDataStart = 0x0e,
1873 .txFrameToPaOn = 0x0e,
1874 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1875 .antennaGain = 0,
1876 .switchSettling = 0x2c,
1877 .adcDesiredSize = -30,
1878 .txEndToXpaOff = 0,
1879 .txEndToRxOn = 0x2,
1880 .txFrameToXpaOn = 0xe,
1881 .thresh62 = 28,
1882 .papdRateMaskHt20 = LE32(0x0c80c080),
1883 .papdRateMaskHt40 = LE32(0x0080c080),
1884 .futureModal = {
1885 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1886 },
1887 },
1888 .base_ext1 = {
1889 .ant_div_control = 0,
1890 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1891 },
1892 .calFreqPier2G = {
1893 FREQ2FBIN(2412, 1),
1894 FREQ2FBIN(2437, 1),
1895 FREQ2FBIN(2472, 1),
1896 },
1897 /* ar9300_cal_data_per_freq_op_loop 2g */
1898 .calPierData2G = {
1899 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1900 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1901 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1902 },
1903 .calTarget_freqbin_Cck = {
1904 FREQ2FBIN(2412, 1),
1905 FREQ2FBIN(2472, 1),
1906 },
1907 .calTarget_freqbin_2G = {
1908 FREQ2FBIN(2412, 1),
1909 FREQ2FBIN(2437, 1),
1910 FREQ2FBIN(2472, 1)
1911 },
1912 .calTarget_freqbin_2GHT20 = {
1913 FREQ2FBIN(2412, 1),
1914 FREQ2FBIN(2437, 1),
1915 FREQ2FBIN(2472, 1)
1916 },
1917 .calTarget_freqbin_2GHT40 = {
1918 FREQ2FBIN(2412, 1),
1919 FREQ2FBIN(2437, 1),
1920 FREQ2FBIN(2472, 1)
1921 },
1922 .calTargetPowerCck = {
1923 /* 1L-5L,5S,11L,11s */
1924 { {38, 38, 38, 38} },
1925 { {38, 38, 38, 38} },
1926 },
1927 .calTargetPower2G = {
1928 /* 6-24,36,48,54 */
1929 { {38, 38, 36, 34} },
1930 { {38, 38, 36, 34} },
1931 { {38, 38, 34, 32} },
1932 },
1933 .calTargetPower2GHT20 = {
1934 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1935 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1936 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1937 },
1938 .calTargetPower2GHT40 = {
1939 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1940 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1941 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1942 },
1943 .ctlIndex_2G = {
1944 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1945 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1946 },
1947 .ctl_freqbin_2G = {
1948 {
1949 FREQ2FBIN(2412, 1),
1950 FREQ2FBIN(2417, 1),
1951 FREQ2FBIN(2457, 1),
1952 FREQ2FBIN(2462, 1)
1953 },
1954 {
1955 FREQ2FBIN(2412, 1),
1956 FREQ2FBIN(2417, 1),
1957 FREQ2FBIN(2462, 1),
1958 0xFF,
1959 },
1960
1961 {
1962 FREQ2FBIN(2412, 1),
1963 FREQ2FBIN(2417, 1),
1964 FREQ2FBIN(2462, 1),
1965 0xFF,
1966 },
1967 {
1968 FREQ2FBIN(2422, 1),
1969 FREQ2FBIN(2427, 1),
1970 FREQ2FBIN(2447, 1),
1971 FREQ2FBIN(2452, 1)
1972 },
1973
1974 {
1975 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1976 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1977 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1978 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1979 },
1980
1981 {
1982 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1983 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1984 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1985 0,
1986 },
1987
1988 {
1989 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1990 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1991 FREQ2FBIN(2472, 1),
1992 0,
1993 },
1994
1995 {
1996 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1997 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1998 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1999 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2000 },
2001
2002 {
2003 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2004 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2005 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2006 },
2007
2008 {
2009 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2010 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2011 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2012 0
2013 },
2014
2015 {
2016 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2017 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2018 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2019 0
2020 },
2021
2022 {
2023 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2024 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2025 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2026 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2027 }
2028 },
2029 .ctlPowerData_2G = {
2030 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2031 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2032 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2033
2034 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2035 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2036 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2037
2038 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2039 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2040 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2041
2042 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2043 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2044 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2045 },
2046 .modalHeader5G = {
2047 /* 4 idle,t1,t2,b (4 bits per setting) */
2048 .antCtrlCommon = LE32(0x110),
2049 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2050 .antCtrlCommon2 = LE32(0x22222),
2051 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2052 .antCtrlChain = {
2053 LE16(0x0), LE16(0x0), LE16(0x0),
2054 },
2055 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2056 .xatten1DB = {0x13, 0x19, 0x17},
2057
2058 /*
2059 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2060 * for merlin (0xa20c/b20c 16:12
2061 */
2062 .xatten1Margin = {0x19, 0x19, 0x19},
2063 .tempSlope = 70,
2064 .voltSlope = 15,
2065 /* spurChans spur channels in usual fbin coding format */
2066 .spurChans = {0, 0, 0, 0, 0},
2067 /* noiseFloorThreshch check if the register is per chain */
2068 .noiseFloorThreshCh = {-1, 0, 0},
2069 .ob = {3, 3, 3}, /* 3 chain */
2070 .db_stage2 = {3, 3, 3}, /* 3 chain */
2071 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2072 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2073 .xpaBiasLvl = 0,
2074 .txFrameToDataStart = 0x0e,
2075 .txFrameToPaOn = 0x0e,
2076 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2077 .antennaGain = 0,
2078 .switchSettling = 0x2d,
2079 .adcDesiredSize = -30,
2080 .txEndToXpaOff = 0,
2081 .txEndToRxOn = 0x2,
2082 .txFrameToXpaOn = 0xe,
2083 .thresh62 = 28,
2084 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2085 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2086 .futureModal = {
2087 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2088 },
2089 },
2090 .base_ext2 = {
2091 .tempSlopeLow = 72,
2092 .tempSlopeHigh = 105,
2093 .xatten1DBLow = {0x10, 0x14, 0x10},
2094 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2095 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2096 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2097 },
2098 .calFreqPier5G = {
2099 FREQ2FBIN(5180, 0),
2100 FREQ2FBIN(5220, 0),
2101 FREQ2FBIN(5320, 0),
2102 FREQ2FBIN(5400, 0),
2103 FREQ2FBIN(5500, 0),
2104 FREQ2FBIN(5600, 0),
2105 FREQ2FBIN(5700, 0),
2106 FREQ2FBIN(5785, 0)
2107 },
2108 .calPierData5G = {
2109 {
2110 {0, 0, 0, 0, 0},
2111 {0, 0, 0, 0, 0},
2112 {0, 0, 0, 0, 0},
2113 {0, 0, 0, 0, 0},
2114 {0, 0, 0, 0, 0},
2115 {0, 0, 0, 0, 0},
2116 {0, 0, 0, 0, 0},
2117 {0, 0, 0, 0, 0},
2118 },
2119 {
2120 {0, 0, 0, 0, 0},
2121 {0, 0, 0, 0, 0},
2122 {0, 0, 0, 0, 0},
2123 {0, 0, 0, 0, 0},
2124 {0, 0, 0, 0, 0},
2125 {0, 0, 0, 0, 0},
2126 {0, 0, 0, 0, 0},
2127 {0, 0, 0, 0, 0},
2128 },
2129 {
2130 {0, 0, 0, 0, 0},
2131 {0, 0, 0, 0, 0},
2132 {0, 0, 0, 0, 0},
2133 {0, 0, 0, 0, 0},
2134 {0, 0, 0, 0, 0},
2135 {0, 0, 0, 0, 0},
2136 {0, 0, 0, 0, 0},
2137 {0, 0, 0, 0, 0},
2138 },
2139
2140 },
2141 .calTarget_freqbin_5G = {
2142 FREQ2FBIN(5180, 0),
2143 FREQ2FBIN(5220, 0),
2144 FREQ2FBIN(5320, 0),
2145 FREQ2FBIN(5400, 0),
2146 FREQ2FBIN(5500, 0),
2147 FREQ2FBIN(5600, 0),
2148 FREQ2FBIN(5725, 0),
2149 FREQ2FBIN(5825, 0)
2150 },
2151 .calTarget_freqbin_5GHT20 = {
2152 FREQ2FBIN(5180, 0),
2153 FREQ2FBIN(5220, 0),
2154 FREQ2FBIN(5320, 0),
2155 FREQ2FBIN(5400, 0),
2156 FREQ2FBIN(5500, 0),
2157 FREQ2FBIN(5600, 0),
2158 FREQ2FBIN(5725, 0),
2159 FREQ2FBIN(5825, 0)
2160 },
2161 .calTarget_freqbin_5GHT40 = {
2162 FREQ2FBIN(5180, 0),
2163 FREQ2FBIN(5220, 0),
2164 FREQ2FBIN(5320, 0),
2165 FREQ2FBIN(5400, 0),
2166 FREQ2FBIN(5500, 0),
2167 FREQ2FBIN(5600, 0),
2168 FREQ2FBIN(5725, 0),
2169 FREQ2FBIN(5825, 0)
2170 },
2171 .calTargetPower5G = {
2172 /* 6-24,36,48,54 */
2173 { {32, 32, 28, 26} },
2174 { {32, 32, 28, 26} },
2175 { {32, 32, 28, 26} },
2176 { {32, 32, 26, 24} },
2177 { {32, 32, 26, 24} },
2178 { {32, 32, 24, 22} },
2179 { {30, 30, 24, 22} },
2180 { {30, 30, 24, 22} },
2181 },
2182 .calTargetPower5GHT20 = {
2183 /*
2184 * 0_8_16,1-3_9-11_17-19,
2185 * 4,5,6,7,12,13,14,15,20,21,22,23
2186 */
2187 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2188 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2189 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2190 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2191 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2192 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2193 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2194 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2195 },
2196 .calTargetPower5GHT40 = {
2197 /*
2198 * 0_8_16,1-3_9-11_17-19,
2199 * 4,5,6,7,12,13,14,15,20,21,22,23
2200 */
2201 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2202 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2203 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2204 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2205 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2206 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2207 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2208 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2209 },
2210 .ctlIndex_5G = {
2211 0x10, 0x16, 0x18, 0x40, 0x46,
2212 0x48, 0x30, 0x36, 0x38
2213 },
2214 .ctl_freqbin_5G = {
2215 {
2216 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2217 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2218 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2219 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2220 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2221 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2222 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2223 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2224 },
2225 {
2226 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2227 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2228 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2229 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2230 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2231 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2232 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2233 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2234 },
2235
2236 {
2237 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2238 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2239 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2240 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2241 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2242 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2243 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2244 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2245 },
2246
2247 {
2248 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2249 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2250 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2251 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2252 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2253 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2254 /* Data[3].ctledges[6].bchannel */ 0xFF,
2255 /* Data[3].ctledges[7].bchannel */ 0xFF,
2256 },
2257
2258 {
2259 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2260 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2261 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2262 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2263 /* Data[4].ctledges[4].bchannel */ 0xFF,
2264 /* Data[4].ctledges[5].bchannel */ 0xFF,
2265 /* Data[4].ctledges[6].bchannel */ 0xFF,
2266 /* Data[4].ctledges[7].bchannel */ 0xFF,
2267 },
2268
2269 {
2270 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2271 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2272 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2273 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2274 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2275 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2276 /* Data[5].ctledges[6].bchannel */ 0xFF,
2277 /* Data[5].ctledges[7].bchannel */ 0xFF
2278 },
2279
2280 {
2281 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2282 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2283 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2284 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2285 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2286 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2287 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2288 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2289 },
2290
2291 {
2292 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2293 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2294 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2295 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2296 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2297 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2298 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2299 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2300 },
2301
2302 {
2303 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2304 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2305 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2306 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2307 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2308 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2309 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2310 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2311 }
2312 },
2313 .ctlPowerData_5G = {
2314 {
2315 {
2316 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2317 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2318 }
2319 },
2320 {
2321 {
2322 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2323 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2324 }
2325 },
2326 {
2327 {
2328 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2329 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2330 }
2331 },
2332 {
2333 {
2334 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2335 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2336 }
2337 },
2338 {
2339 {
2340 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2341 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2342 }
2343 },
2344 {
2345 {
2346 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2347 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2348 }
2349 },
2350 {
2351 {
2352 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2353 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2354 }
2355 },
2356 {
2357 {
2358 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2359 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2360 }
2361 },
2362 {
2363 {
2364 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2365 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2366 }
2367 },
2368 }
2369 };
2370
2371 static const struct ar9300_eeprom ar9300_h116 = {
2372 .eepromVersion = 2,
2373 .templateVersion = 4,
2374 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2375 .custData = {"h116-041-f0000"},
2376 .baseEepHeader = {
2377 .regDmn = { LE16(0), LE16(0x1f) },
2378 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2379 .opCapFlags = {
2380 .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2381 .eepMisc = 0,
2382 },
2383 .rfSilent = 0,
2384 .blueToothOptions = 0,
2385 .deviceCap = 0,
2386 .deviceType = 5, /* takes lower byte in eeprom location */
2387 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2388 .params_for_tuning_caps = {0, 0},
2389 .featureEnable = 0x0d,
2390 /*
2391 * bit0 - enable tx temp comp - disabled
2392 * bit1 - enable tx volt comp - disabled
2393 * bit2 - enable fastClock - enabled
2394 * bit3 - enable doubling - enabled
2395 * bit4 - enable internal regulator - disabled
2396 * bit5 - enable pa predistortion - disabled
2397 */
2398 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2399 .eepromWriteEnableGpio = 6,
2400 .wlanDisableGpio = 0,
2401 .wlanLedGpio = 8,
2402 .rxBandSelectGpio = 0xff,
2403 .txrxgain = 0x10,
2404 .swreg = 0,
2405 },
2406 .modalHeader2G = {
2407 /* ar9300_modal_eep_header 2g */
2408 /* 4 idle,t1,t2,b(4 bits per setting) */
2409 .antCtrlCommon = LE32(0x110),
2410 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2411 .antCtrlCommon2 = LE32(0x44444),
2412
2413 /*
2414 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2415 * rx1, rx12, b (2 bits each)
2416 */
2417 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2418
2419 /*
2420 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2421 * for ar9280 (0xa20c/b20c 5:0)
2422 */
2423 .xatten1DB = {0x1f, 0x1f, 0x1f},
2424
2425 /*
2426 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2427 * for ar9280 (0xa20c/b20c 16:12
2428 */
2429 .xatten1Margin = {0x12, 0x12, 0x12},
2430 .tempSlope = 25,
2431 .voltSlope = 0,
2432
2433 /*
2434 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2435 * channels in usual fbin coding format
2436 */
2437 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2438
2439 /*
2440 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2441 * if the register is per chain
2442 */
2443 .noiseFloorThreshCh = {-1, 0, 0},
2444 .ob = {1, 1, 1},/* 3 chain */
2445 .db_stage2 = {1, 1, 1}, /* 3 chain */
2446 .db_stage3 = {0, 0, 0},
2447 .db_stage4 = {0, 0, 0},
2448 .xpaBiasLvl = 0,
2449 .txFrameToDataStart = 0x0e,
2450 .txFrameToPaOn = 0x0e,
2451 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2452 .antennaGain = 0,
2453 .switchSettling = 0x2c,
2454 .adcDesiredSize = -30,
2455 .txEndToXpaOff = 0,
2456 .txEndToRxOn = 0x2,
2457 .txFrameToXpaOn = 0xe,
2458 .thresh62 = 28,
2459 .papdRateMaskHt20 = LE32(0x0c80C080),
2460 .papdRateMaskHt40 = LE32(0x0080C080),
2461 .futureModal = {
2462 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2463 },
2464 },
2465 .base_ext1 = {
2466 .ant_div_control = 0,
2467 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2468 },
2469 .calFreqPier2G = {
2470 FREQ2FBIN(2412, 1),
2471 FREQ2FBIN(2437, 1),
2472 FREQ2FBIN(2472, 1),
2473 },
2474 /* ar9300_cal_data_per_freq_op_loop 2g */
2475 .calPierData2G = {
2476 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2477 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2478 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2479 },
2480 .calTarget_freqbin_Cck = {
2481 FREQ2FBIN(2412, 1),
2482 FREQ2FBIN(2472, 1),
2483 },
2484 .calTarget_freqbin_2G = {
2485 FREQ2FBIN(2412, 1),
2486 FREQ2FBIN(2437, 1),
2487 FREQ2FBIN(2472, 1)
2488 },
2489 .calTarget_freqbin_2GHT20 = {
2490 FREQ2FBIN(2412, 1),
2491 FREQ2FBIN(2437, 1),
2492 FREQ2FBIN(2472, 1)
2493 },
2494 .calTarget_freqbin_2GHT40 = {
2495 FREQ2FBIN(2412, 1),
2496 FREQ2FBIN(2437, 1),
2497 FREQ2FBIN(2472, 1)
2498 },
2499 .calTargetPowerCck = {
2500 /* 1L-5L,5S,11L,11S */
2501 { {34, 34, 34, 34} },
2502 { {34, 34, 34, 34} },
2503 },
2504 .calTargetPower2G = {
2505 /* 6-24,36,48,54 */
2506 { {34, 34, 32, 32} },
2507 { {34, 34, 32, 32} },
2508 { {34, 34, 32, 32} },
2509 },
2510 .calTargetPower2GHT20 = {
2511 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2512 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2513 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2514 },
2515 .calTargetPower2GHT40 = {
2516 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2517 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2518 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2519 },
2520 .ctlIndex_2G = {
2521 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2522 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2523 },
2524 .ctl_freqbin_2G = {
2525 {
2526 FREQ2FBIN(2412, 1),
2527 FREQ2FBIN(2417, 1),
2528 FREQ2FBIN(2457, 1),
2529 FREQ2FBIN(2462, 1)
2530 },
2531 {
2532 FREQ2FBIN(2412, 1),
2533 FREQ2FBIN(2417, 1),
2534 FREQ2FBIN(2462, 1),
2535 0xFF,
2536 },
2537
2538 {
2539 FREQ2FBIN(2412, 1),
2540 FREQ2FBIN(2417, 1),
2541 FREQ2FBIN(2462, 1),
2542 0xFF,
2543 },
2544 {
2545 FREQ2FBIN(2422, 1),
2546 FREQ2FBIN(2427, 1),
2547 FREQ2FBIN(2447, 1),
2548 FREQ2FBIN(2452, 1)
2549 },
2550
2551 {
2552 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2553 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2554 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2555 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2556 },
2557
2558 {
2559 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2560 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2561 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2562 0,
2563 },
2564
2565 {
2566 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2567 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2568 FREQ2FBIN(2472, 1),
2569 0,
2570 },
2571
2572 {
2573 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2574 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2575 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2576 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2577 },
2578
2579 {
2580 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2581 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2582 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2583 },
2584
2585 {
2586 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2587 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2588 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2589 0
2590 },
2591
2592 {
2593 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2594 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2595 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2596 0
2597 },
2598
2599 {
2600 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2601 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2602 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2603 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2604 }
2605 },
2606 .ctlPowerData_2G = {
2607 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2608 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2609 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2610
2611 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2612 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2613 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2614
2615 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2616 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2617 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2618
2619 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2620 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2621 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2622 },
2623 .modalHeader5G = {
2624 /* 4 idle,t1,t2,b (4 bits per setting) */
2625 .antCtrlCommon = LE32(0x220),
2626 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2627 .antCtrlCommon2 = LE32(0x44444),
2628 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2629 .antCtrlChain = {
2630 LE16(0x150), LE16(0x150), LE16(0x150),
2631 },
2632 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2633 .xatten1DB = {0x19, 0x19, 0x19},
2634
2635 /*
2636 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2637 * for merlin (0xa20c/b20c 16:12
2638 */
2639 .xatten1Margin = {0x14, 0x14, 0x14},
2640 .tempSlope = 70,
2641 .voltSlope = 0,
2642 /* spurChans spur channels in usual fbin coding format */
2643 .spurChans = {0, 0, 0, 0, 0},
2644 /* noiseFloorThreshCh Check if the register is per chain */
2645 .noiseFloorThreshCh = {-1, 0, 0},
2646 .ob = {3, 3, 3}, /* 3 chain */
2647 .db_stage2 = {3, 3, 3}, /* 3 chain */
2648 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2649 .db_stage4 = {3, 3, 3}, /* don't exist for 2G */
2650 .xpaBiasLvl = 0,
2651 .txFrameToDataStart = 0x0e,
2652 .txFrameToPaOn = 0x0e,
2653 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2654 .antennaGain = 0,
2655 .switchSettling = 0x2d,
2656 .adcDesiredSize = -30,
2657 .txEndToXpaOff = 0,
2658 .txEndToRxOn = 0x2,
2659 .txFrameToXpaOn = 0xe,
2660 .thresh62 = 28,
2661 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2662 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2663 .futureModal = {
2664 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2665 },
2666 },
2667 .base_ext2 = {
2668 .tempSlopeLow = 35,
2669 .tempSlopeHigh = 50,
2670 .xatten1DBLow = {0, 0, 0},
2671 .xatten1MarginLow = {0, 0, 0},
2672 .xatten1DBHigh = {0, 0, 0},
2673 .xatten1MarginHigh = {0, 0, 0}
2674 },
2675 .calFreqPier5G = {
2676 FREQ2FBIN(5180, 0),
2677 FREQ2FBIN(5220, 0),
2678 FREQ2FBIN(5320, 0),
2679 FREQ2FBIN(5400, 0),
2680 FREQ2FBIN(5500, 0),
2681 FREQ2FBIN(5600, 0),
2682 FREQ2FBIN(5700, 0),
2683 FREQ2FBIN(5785, 0)
2684 },
2685 .calPierData5G = {
2686 {
2687 {0, 0, 0, 0, 0},
2688 {0, 0, 0, 0, 0},
2689 {0, 0, 0, 0, 0},
2690 {0, 0, 0, 0, 0},
2691 {0, 0, 0, 0, 0},
2692 {0, 0, 0, 0, 0},
2693 {0, 0, 0, 0, 0},
2694 {0, 0, 0, 0, 0},
2695 },
2696 {
2697 {0, 0, 0, 0, 0},
2698 {0, 0, 0, 0, 0},
2699 {0, 0, 0, 0, 0},
2700 {0, 0, 0, 0, 0},
2701 {0, 0, 0, 0, 0},
2702 {0, 0, 0, 0, 0},
2703 {0, 0, 0, 0, 0},
2704 {0, 0, 0, 0, 0},
2705 },
2706 {
2707 {0, 0, 0, 0, 0},
2708 {0, 0, 0, 0, 0},
2709 {0, 0, 0, 0, 0},
2710 {0, 0, 0, 0, 0},
2711 {0, 0, 0, 0, 0},
2712 {0, 0, 0, 0, 0},
2713 {0, 0, 0, 0, 0},
2714 {0, 0, 0, 0, 0},
2715 },
2716
2717 },
2718 .calTarget_freqbin_5G = {
2719 FREQ2FBIN(5180, 0),
2720 FREQ2FBIN(5240, 0),
2721 FREQ2FBIN(5320, 0),
2722 FREQ2FBIN(5400, 0),
2723 FREQ2FBIN(5500, 0),
2724 FREQ2FBIN(5600, 0),
2725 FREQ2FBIN(5700, 0),
2726 FREQ2FBIN(5825, 0)
2727 },
2728 .calTarget_freqbin_5GHT20 = {
2729 FREQ2FBIN(5180, 0),
2730 FREQ2FBIN(5240, 0),
2731 FREQ2FBIN(5320, 0),
2732 FREQ2FBIN(5400, 0),
2733 FREQ2FBIN(5500, 0),
2734 FREQ2FBIN(5700, 0),
2735 FREQ2FBIN(5745, 0),
2736 FREQ2FBIN(5825, 0)
2737 },
2738 .calTarget_freqbin_5GHT40 = {
2739 FREQ2FBIN(5180, 0),
2740 FREQ2FBIN(5240, 0),
2741 FREQ2FBIN(5320, 0),
2742 FREQ2FBIN(5400, 0),
2743 FREQ2FBIN(5500, 0),
2744 FREQ2FBIN(5700, 0),
2745 FREQ2FBIN(5745, 0),
2746 FREQ2FBIN(5825, 0)
2747 },
2748 .calTargetPower5G = {
2749 /* 6-24,36,48,54 */
2750 { {30, 30, 28, 24} },
2751 { {30, 30, 28, 24} },
2752 { {30, 30, 28, 24} },
2753 { {30, 30, 28, 24} },
2754 { {30, 30, 28, 24} },
2755 { {30, 30, 28, 24} },
2756 { {30, 30, 28, 24} },
2757 { {30, 30, 28, 24} },
2758 },
2759 .calTargetPower5GHT20 = {
2760 /*
2761 * 0_8_16,1-3_9-11_17-19,
2762 * 4,5,6,7,12,13,14,15,20,21,22,23
2763 */
2764 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2765 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2766 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2767 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2768 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2769 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2770 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2771 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2772 },
2773 .calTargetPower5GHT40 = {
2774 /*
2775 * 0_8_16,1-3_9-11_17-19,
2776 * 4,5,6,7,12,13,14,15,20,21,22,23
2777 */
2778 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2779 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2780 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2781 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2782 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2783 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2784 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2785 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2786 },
2787 .ctlIndex_5G = {
2788 0x10, 0x16, 0x18, 0x40, 0x46,
2789 0x48, 0x30, 0x36, 0x38
2790 },
2791 .ctl_freqbin_5G = {
2792 {
2793 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2794 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2795 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2796 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2797 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2798 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2799 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2800 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2801 },
2802 {
2803 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2804 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2805 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2806 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2807 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2808 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2809 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2810 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2811 },
2812
2813 {
2814 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2815 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2816 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2817 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2818 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2819 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2820 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2821 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2822 },
2823
2824 {
2825 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2826 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2827 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2828 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2829 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2830 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2831 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2832 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2833 },
2834
2835 {
2836 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2837 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2838 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2839 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2840 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2841 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2842 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2843 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2844 },
2845
2846 {
2847 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2848 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2849 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2850 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2851 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2852 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2853 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2854 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2855 },
2856
2857 {
2858 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2859 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2860 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2861 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2862 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2863 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2864 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2865 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2866 },
2867
2868 {
2869 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2870 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2871 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2872 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2873 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2874 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2875 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2876 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2877 },
2878
2879 {
2880 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2881 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2882 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2883 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2884 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2885 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2886 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2887 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2888 }
2889 },
2890 .ctlPowerData_5G = {
2891 {
2892 {
2893 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2894 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2895 }
2896 },
2897 {
2898 {
2899 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2900 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2901 }
2902 },
2903 {
2904 {
2905 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2906 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2907 }
2908 },
2909 {
2910 {
2911 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2912 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2913 }
2914 },
2915 {
2916 {
2917 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2918 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2919 }
2920 },
2921 {
2922 {
2923 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2924 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2925 }
2926 },
2927 {
2928 {
2929 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2930 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2931 }
2932 },
2933 {
2934 {
2935 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2936 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2937 }
2938 },
2939 {
2940 {
2941 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2942 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2943 }
2944 },
2945 }
2946 };
2947
2948
2949 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2950 &ar9300_default,
2951 &ar9300_x112,
2952 &ar9300_h116,
2953 &ar9300_h112,
2954 &ar9300_x113,
2955 };
2956
2957 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2958 {
2959 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2960 int it;
2961
2962 for (it = 0; it < N_LOOP; it++)
2963 if (ar9300_eep_templates[it]->templateVersion == id)
2964 return ar9300_eep_templates[it];
2965 return NULL;
2966 #undef N_LOOP
2967 }
2968
2969
2970 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2971 {
2972 if (fbin == AR9300_BCHAN_UNUSED)
2973 return fbin;
2974
2975 return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2976 }
2977
2978 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2979 {
2980 return 0;
2981 }
2982
2983 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2984 enum eeprom_param param)
2985 {
2986 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2987 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2988
2989 switch (param) {
2990 case EEP_MAC_LSW:
2991 return eep->macAddr[0] << 8 | eep->macAddr[1];
2992 case EEP_MAC_MID:
2993 return eep->macAddr[2] << 8 | eep->macAddr[3];
2994 case EEP_MAC_MSW:
2995 return eep->macAddr[4] << 8 | eep->macAddr[5];
2996 case EEP_REG_0:
2997 return le16_to_cpu(pBase->regDmn[0]);
2998 case EEP_REG_1:
2999 return le16_to_cpu(pBase->regDmn[1]);
3000 case EEP_OP_CAP:
3001 return pBase->deviceCap;
3002 case EEP_OP_MODE:
3003 return pBase->opCapFlags.opFlags;
3004 case EEP_RF_SILENT:
3005 return pBase->rfSilent;
3006 case EEP_TX_MASK:
3007 return (pBase->txrxMask >> 4) & 0xf;
3008 case EEP_RX_MASK:
3009 return pBase->txrxMask & 0xf;
3010 case EEP_DRIVE_STRENGTH:
3011 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
3012 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3013 case EEP_INTERNAL_REGULATOR:
3014 /* Bit 4 is internal regulator flag */
3015 return (pBase->featureEnable & 0x10) >> 4;
3016 case EEP_SWREG:
3017 return le32_to_cpu(pBase->swreg);
3018 case EEP_PAPRD:
3019 return !!(pBase->featureEnable & BIT(5));
3020 default:
3021 return 0;
3022 }
3023 }
3024
3025 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3026 u8 *buffer)
3027 {
3028 u16 val;
3029
3030 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3031 return false;
3032
3033 *buffer = (val >> (8 * (address % 2))) & 0xff;
3034 return true;
3035 }
3036
3037 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3038 u8 *buffer)
3039 {
3040 u16 val;
3041
3042 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3043 return false;
3044
3045 buffer[0] = val >> 8;
3046 buffer[1] = val & 0xff;
3047
3048 return true;
3049 }
3050
3051 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3052 int count)
3053 {
3054 struct ath_common *common = ath9k_hw_common(ah);
3055 int i;
3056
3057 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3058 ath_print(common, ATH_DBG_EEPROM,
3059 "eeprom address not in range\n");
3060 return false;
3061 }
3062
3063 /*
3064 * Since we're reading the bytes in reverse order from a little-endian
3065 * word stream, an even address means we only use the lower half of
3066 * the 16-bit word at that address
3067 */
3068 if (address % 2 == 0) {
3069 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3070 goto error;
3071
3072 count--;
3073 }
3074
3075 for (i = 0; i < count / 2; i++) {
3076 if (!ar9300_eeprom_read_word(common, address, buffer))
3077 goto error;
3078
3079 address -= 2;
3080 buffer += 2;
3081 }
3082
3083 if (count % 2)
3084 if (!ar9300_eeprom_read_byte(common, address, buffer))
3085 goto error;
3086
3087 return true;
3088
3089 error:
3090 ath_print(common, ATH_DBG_EEPROM,
3091 "unable to read eeprom region at offset %d\n", address);
3092 return false;
3093 }
3094
3095 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3096 int *length, int *major, int *minor)
3097 {
3098 unsigned long value[4];
3099
3100 value[0] = best[0];
3101 value[1] = best[1];
3102 value[2] = best[2];
3103 value[3] = best[3];
3104 *code = ((value[0] >> 5) & 0x0007);
3105 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3106 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3107 *major = (value[2] & 0x000f);
3108 *minor = (value[3] & 0x00ff);
3109 }
3110
3111 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3112 {
3113 int it, checksum = 0;
3114
3115 for (it = 0; it < dsize; it++) {
3116 checksum += data[it];
3117 checksum &= 0xffff;
3118 }
3119
3120 return checksum;
3121 }
3122
3123 static bool ar9300_uncompress_block(struct ath_hw *ah,
3124 u8 *mptr,
3125 int mdataSize,
3126 u8 *block,
3127 int size)
3128 {
3129 int it;
3130 int spot;
3131 int offset;
3132 int length;
3133 struct ath_common *common = ath9k_hw_common(ah);
3134
3135 spot = 0;
3136
3137 for (it = 0; it < size; it += (length+2)) {
3138 offset = block[it];
3139 offset &= 0xff;
3140 spot += offset;
3141 length = block[it+1];
3142 length &= 0xff;
3143
3144 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3145 ath_print(common, ATH_DBG_EEPROM,
3146 "Restore at %d: spot=%d "
3147 "offset=%d length=%d\n",
3148 it, spot, offset, length);
3149 memcpy(&mptr[spot], &block[it+2], length);
3150 spot += length;
3151 } else if (length > 0) {
3152 ath_print(common, ATH_DBG_EEPROM,
3153 "Bad restore at %d: spot=%d "
3154 "offset=%d length=%d\n",
3155 it, spot, offset, length);
3156 return false;
3157 }
3158 }
3159 return true;
3160 }
3161
3162 static int ar9300_compress_decision(struct ath_hw *ah,
3163 int it,
3164 int code,
3165 int reference,
3166 u8 *mptr,
3167 u8 *word, int length, int mdata_size)
3168 {
3169 struct ath_common *common = ath9k_hw_common(ah);
3170 u8 *dptr;
3171 const struct ar9300_eeprom *eep = NULL;
3172
3173 switch (code) {
3174 case _CompressNone:
3175 if (length != mdata_size) {
3176 ath_print(common, ATH_DBG_EEPROM,
3177 "EEPROM structure size mismatch"
3178 "memory=%d eeprom=%d\n", mdata_size, length);
3179 return -1;
3180 }
3181 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3182 ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
3183 " uncompressed, length %d\n", it, length);
3184 break;
3185 case _CompressBlock:
3186 if (reference == 0) {
3187 dptr = mptr;
3188 } else {
3189 eep = ar9003_eeprom_struct_find_by_id(reference);
3190 if (eep == NULL) {
3191 ath_print(common, ATH_DBG_EEPROM,
3192 "cant find reference eeprom"
3193 "struct %d\n", reference);
3194 return -1;
3195 }
3196 memcpy(mptr, eep, mdata_size);
3197 }
3198 ath_print(common, ATH_DBG_EEPROM,
3199 "restore eeprom %d: block, reference %d,"
3200 " length %d\n", it, reference, length);
3201 ar9300_uncompress_block(ah, mptr, mdata_size,
3202 (u8 *) (word + COMP_HDR_LEN), length);
3203 break;
3204 default:
3205 ath_print(common, ATH_DBG_EEPROM, "unknown compression"
3206 " code %d\n", code);
3207 return -1;
3208 }
3209 return 0;
3210 }
3211
3212 /*
3213 * Read the configuration data from the eeprom.
3214 * The data can be put in any specified memory buffer.
3215 *
3216 * Returns -1 on error.
3217 * Returns address of next memory location on success.
3218 */
3219 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3220 u8 *mptr, int mdata_size)
3221 {
3222 #define MDEFAULT 15
3223 #define MSTATE 100
3224 int cptr;
3225 u8 *word;
3226 int code;
3227 int reference, length, major, minor;
3228 int osize;
3229 int it;
3230 u16 checksum, mchecksum;
3231 struct ath_common *common = ath9k_hw_common(ah);
3232
3233 word = kzalloc(2048, GFP_KERNEL);
3234 if (!word)
3235 return -1;
3236
3237 memcpy(mptr, &ar9300_default, mdata_size);
3238
3239 cptr = AR9300_BASE_ADDR;
3240 for (it = 0; it < MSTATE; it++) {
3241 if (!ar9300_read_eeprom(ah, cptr, word, COMP_HDR_LEN))
3242 goto fail;
3243
3244 if ((word[0] == 0 && word[1] == 0 && word[2] == 0 &&
3245 word[3] == 0) || (word[0] == 0xff && word[1] == 0xff
3246 && word[2] == 0xff && word[3] == 0xff))
3247 break;
3248
3249 ar9300_comp_hdr_unpack(word, &code, &reference,
3250 &length, &major, &minor);
3251 ath_print(common, ATH_DBG_EEPROM,
3252 "Found block at %x: code=%d ref=%d"
3253 "length=%d major=%d minor=%d\n", cptr, code,
3254 reference, length, major, minor);
3255 if (length >= 1024) {
3256 ath_print(common, ATH_DBG_EEPROM,
3257 "Skipping bad header\n");
3258 cptr -= COMP_HDR_LEN;
3259 continue;
3260 }
3261
3262 osize = length;
3263 ar9300_read_eeprom(ah, cptr, word,
3264 COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3265 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3266 mchecksum = word[COMP_HDR_LEN + osize] |
3267 (word[COMP_HDR_LEN + osize + 1] << 8);
3268 ath_print(common, ATH_DBG_EEPROM,
3269 "checksum %x %x\n", checksum, mchecksum);
3270 if (checksum == mchecksum) {
3271 ar9300_compress_decision(ah, it, code, reference, mptr,
3272 word, length, mdata_size);
3273 } else {
3274 ath_print(common, ATH_DBG_EEPROM,
3275 "skipping block with bad checksum\n");
3276 }
3277 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3278 }
3279
3280 kfree(word);
3281 return cptr;
3282
3283 fail:
3284 kfree(word);
3285 return -1;
3286 }
3287
3288 /*
3289 * Restore the configuration structure by reading the eeprom.
3290 * This function destroys any existing in-memory structure
3291 * content.
3292 */
3293 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3294 {
3295 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3296
3297 if (ar9300_eeprom_restore_internal(ah, mptr,
3298 sizeof(struct ar9300_eeprom)) < 0)
3299 return false;
3300
3301 return true;
3302 }
3303
3304 /* XXX: review hardware docs */
3305 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3306 {
3307 return ah->eeprom.ar9300_eep.eepromVersion;
3308 }
3309
3310 /* XXX: could be read from the eepromVersion, not sure yet */
3311 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3312 {
3313 return 0;
3314 }
3315
3316 static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
3317 enum ath9k_hal_freq_band freq_band)
3318 {
3319 return 1;
3320 }
3321
3322 static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
3323 struct ath9k_channel *chan)
3324 {
3325 return -EINVAL;
3326 }
3327
3328 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3329 {
3330 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3331
3332 if (is2ghz)
3333 return eep->modalHeader2G.xpaBiasLvl;
3334 else
3335 return eep->modalHeader5G.xpaBiasLvl;
3336 }
3337
3338 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3339 {
3340 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3341 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3342 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
3343 REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
3344 }
3345
3346 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3347 {
3348 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3349 __le32 val;
3350
3351 if (is2ghz)
3352 val = eep->modalHeader2G.antCtrlCommon;
3353 else
3354 val = eep->modalHeader5G.antCtrlCommon;
3355 return le32_to_cpu(val);
3356 }
3357
3358 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3359 {
3360 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3361 __le32 val;
3362
3363 if (is2ghz)
3364 val = eep->modalHeader2G.antCtrlCommon2;
3365 else
3366 val = eep->modalHeader5G.antCtrlCommon2;
3367 return le32_to_cpu(val);
3368 }
3369
3370 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3371 int chain,
3372 bool is2ghz)
3373 {
3374 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3375 __le16 val = 0;
3376
3377 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3378 if (is2ghz)
3379 val = eep->modalHeader2G.antCtrlChain[chain];
3380 else
3381 val = eep->modalHeader5G.antCtrlChain[chain];
3382 }
3383
3384 return le16_to_cpu(val);
3385 }
3386
3387 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3388 {
3389 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3390 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3391
3392 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3393 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3394
3395 value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3396 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3397
3398 value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3399 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
3400
3401 value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3402 REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
3403 }
3404
3405 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3406 {
3407 int drive_strength;
3408 unsigned long reg;
3409
3410 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3411
3412 if (!drive_strength)
3413 return;
3414
3415 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3416 reg &= ~0x00ffffc0;
3417 reg |= 0x5 << 21;
3418 reg |= 0x5 << 18;
3419 reg |= 0x5 << 15;
3420 reg |= 0x5 << 12;
3421 reg |= 0x5 << 9;
3422 reg |= 0x5 << 6;
3423 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3424
3425 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3426 reg &= ~0xffffffe0;
3427 reg |= 0x5 << 29;
3428 reg |= 0x5 << 26;
3429 reg |= 0x5 << 23;
3430 reg |= 0x5 << 20;
3431 reg |= 0x5 << 17;
3432 reg |= 0x5 << 14;
3433 reg |= 0x5 << 11;
3434 reg |= 0x5 << 8;
3435 reg |= 0x5 << 5;
3436 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3437
3438 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3439 reg &= ~0xff800000;
3440 reg |= 0x5 << 29;
3441 reg |= 0x5 << 26;
3442 reg |= 0x5 << 23;
3443 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3444 }
3445
3446 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3447 {
3448 int internal_regulator =
3449 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3450
3451 if (internal_regulator) {
3452 /* Internal regulator is ON. Write swreg register. */
3453 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3454 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3455 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3456 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3457 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3458 /* Set REG_CONTROL1.SWREG_PROGRAM */
3459 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3460 REG_READ(ah,
3461 AR_RTC_REG_CONTROL1) |
3462 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3463 } else {
3464 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3465 (REG_READ(ah,
3466 AR_RTC_SLEEP_CLK) |
3467 AR_RTC_FORCE_SWREG_PRD));
3468 }
3469 }
3470
3471 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3472 struct ath9k_channel *chan)
3473 {
3474 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3475 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3476 ar9003_hw_drive_strength_apply(ah);
3477 ar9003_hw_internal_regulator_apply(ah);
3478 }
3479
3480 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3481 struct ath9k_channel *chan)
3482 {
3483 }
3484
3485 /*
3486 * Returns the interpolated y value corresponding to the specified x value
3487 * from the np ordered pairs of data (px,py).
3488 * The pairs do not have to be in any order.
3489 * If the specified x value is less than any of the px,
3490 * the returned y value is equal to the py for the lowest px.
3491 * If the specified x value is greater than any of the px,
3492 * the returned y value is equal to the py for the highest px.
3493 */
3494 static int ar9003_hw_power_interpolate(int32_t x,
3495 int32_t *px, int32_t *py, u_int16_t np)
3496 {
3497 int ip = 0;
3498 int lx = 0, ly = 0, lhave = 0;
3499 int hx = 0, hy = 0, hhave = 0;
3500 int dx = 0;
3501 int y = 0;
3502
3503 lhave = 0;
3504 hhave = 0;
3505
3506 /* identify best lower and higher x calibration measurement */
3507 for (ip = 0; ip < np; ip++) {
3508 dx = x - px[ip];
3509
3510 /* this measurement is higher than our desired x */
3511 if (dx <= 0) {
3512 if (!hhave || dx > (x - hx)) {
3513 /* new best higher x measurement */
3514 hx = px[ip];
3515 hy = py[ip];
3516 hhave = 1;
3517 }
3518 }
3519 /* this measurement is lower than our desired x */
3520 if (dx >= 0) {
3521 if (!lhave || dx < (x - lx)) {
3522 /* new best lower x measurement */
3523 lx = px[ip];
3524 ly = py[ip];
3525 lhave = 1;
3526 }
3527 }
3528 }
3529
3530 /* the low x is good */
3531 if (lhave) {
3532 /* so is the high x */
3533 if (hhave) {
3534 /* they're the same, so just pick one */
3535 if (hx == lx)
3536 y = ly;
3537 else /* interpolate */
3538 y = ly + (((x - lx) * (hy - ly)) / (hx - lx));
3539 } else /* only low is good, use it */
3540 y = ly;
3541 } else if (hhave) /* only high is good, use it */
3542 y = hy;
3543 else /* nothing is good,this should never happen unless np=0, ???? */
3544 y = -(1 << 30);
3545 return y;
3546 }
3547
3548 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3549 u16 rateIndex, u16 freq, bool is2GHz)
3550 {
3551 u16 numPiers, i;
3552 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3553 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3554 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3555 struct cal_tgt_pow_legacy *pEepromTargetPwr;
3556 u8 *pFreqBin;
3557
3558 if (is2GHz) {
3559 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3560 pEepromTargetPwr = eep->calTargetPower2G;
3561 pFreqBin = eep->calTarget_freqbin_2G;
3562 } else {
3563 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3564 pEepromTargetPwr = eep->calTargetPower5G;
3565 pFreqBin = eep->calTarget_freqbin_5G;
3566 }
3567
3568 /*
3569 * create array of channels and targetpower from
3570 * targetpower piers stored on eeprom
3571 */
3572 for (i = 0; i < numPiers; i++) {
3573 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3574 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3575 }
3576
3577 /* interpolate to get target power for given frequency */
3578 return (u8) ar9003_hw_power_interpolate((s32) freq,
3579 freqArray,
3580 targetPowerArray, numPiers);
3581 }
3582
3583 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3584 u16 rateIndex,
3585 u16 freq, bool is2GHz)
3586 {
3587 u16 numPiers, i;
3588 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3589 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3590 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3591 struct cal_tgt_pow_ht *pEepromTargetPwr;
3592 u8 *pFreqBin;
3593
3594 if (is2GHz) {
3595 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3596 pEepromTargetPwr = eep->calTargetPower2GHT20;
3597 pFreqBin = eep->calTarget_freqbin_2GHT20;
3598 } else {
3599 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3600 pEepromTargetPwr = eep->calTargetPower5GHT20;
3601 pFreqBin = eep->calTarget_freqbin_5GHT20;
3602 }
3603
3604 /*
3605 * create array of channels and targetpower
3606 * from targetpower piers stored on eeprom
3607 */
3608 for (i = 0; i < numPiers; i++) {
3609 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3610 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3611 }
3612
3613 /* interpolate to get target power for given frequency */
3614 return (u8) ar9003_hw_power_interpolate((s32) freq,
3615 freqArray,
3616 targetPowerArray, numPiers);
3617 }
3618
3619 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3620 u16 rateIndex,
3621 u16 freq, bool is2GHz)
3622 {
3623 u16 numPiers, i;
3624 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3625 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3626 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3627 struct cal_tgt_pow_ht *pEepromTargetPwr;
3628 u8 *pFreqBin;
3629
3630 if (is2GHz) {
3631 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3632 pEepromTargetPwr = eep->calTargetPower2GHT40;
3633 pFreqBin = eep->calTarget_freqbin_2GHT40;
3634 } else {
3635 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3636 pEepromTargetPwr = eep->calTargetPower5GHT40;
3637 pFreqBin = eep->calTarget_freqbin_5GHT40;
3638 }
3639
3640 /*
3641 * create array of channels and targetpower from
3642 * targetpower piers stored on eeprom
3643 */
3644 for (i = 0; i < numPiers; i++) {
3645 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3646 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3647 }
3648
3649 /* interpolate to get target power for given frequency */
3650 return (u8) ar9003_hw_power_interpolate((s32) freq,
3651 freqArray,
3652 targetPowerArray, numPiers);
3653 }
3654
3655 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3656 u16 rateIndex, u16 freq)
3657 {
3658 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3659 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3660 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3661 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3662 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3663 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3664
3665 /*
3666 * create array of channels and targetpower from
3667 * targetpower piers stored on eeprom
3668 */
3669 for (i = 0; i < numPiers; i++) {
3670 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3671 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3672 }
3673
3674 /* interpolate to get target power for given frequency */
3675 return (u8) ar9003_hw_power_interpolate((s32) freq,
3676 freqArray,
3677 targetPowerArray, numPiers);
3678 }
3679
3680 /* Set tx power registers to array of values passed in */
3681 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3682 {
3683 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
3684 /* make sure forced gain is not set */
3685 REG_WRITE(ah, 0xa458, 0);
3686
3687 /* Write the OFDM power per rate set */
3688
3689 /* 6 (LSB), 9, 12, 18 (MSB) */
3690 REG_WRITE(ah, 0xa3c0,
3691 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3692 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3693 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3694 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3695
3696 /* 24 (LSB), 36, 48, 54 (MSB) */
3697 REG_WRITE(ah, 0xa3c4,
3698 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3699 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3700 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3701 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3702
3703 /* Write the CCK power per rate set */
3704
3705 /* 1L (LSB), reserved, 2L, 2S (MSB) */
3706 REG_WRITE(ah, 0xa3c8,
3707 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3708 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3709 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
3710 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
3711
3712 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3713 REG_WRITE(ah, 0xa3cc,
3714 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
3715 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
3716 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
3717 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
3718 );
3719
3720 /* Write the HT20 power per rate set */
3721
3722 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3723 REG_WRITE(ah, 0xa3d0,
3724 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
3725 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
3726 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
3727 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
3728 );
3729
3730 /* 6 (LSB), 7, 12, 13 (MSB) */
3731 REG_WRITE(ah, 0xa3d4,
3732 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
3733 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
3734 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
3735 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
3736 );
3737
3738 /* 14 (LSB), 15, 20, 21 */
3739 REG_WRITE(ah, 0xa3e4,
3740 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
3741 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
3742 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
3743 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
3744 );
3745
3746 /* Mixed HT20 and HT40 rates */
3747
3748 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3749 REG_WRITE(ah, 0xa3e8,
3750 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
3751 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
3752 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
3753 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
3754 );
3755
3756 /*
3757 * Write the HT40 power per rate set
3758 * correct PAR difference between HT40 and HT20/LEGACY
3759 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
3760 */
3761 REG_WRITE(ah, 0xa3d8,
3762 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
3763 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
3764 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
3765 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
3766 );
3767
3768 /* 6 (LSB), 7, 12, 13 (MSB) */
3769 REG_WRITE(ah, 0xa3dc,
3770 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
3771 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
3772 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
3773 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
3774 );
3775
3776 /* 14 (LSB), 15, 20, 21 */
3777 REG_WRITE(ah, 0xa3ec,
3778 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
3779 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
3780 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
3781 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
3782 );
3783
3784 return 0;
3785 #undef POW_SM
3786 }
3787
3788 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
3789 u8 *targetPowerValT2)
3790 {
3791 /* XXX: hard code for now, need to get from eeprom struct */
3792 u8 ht40PowerIncForPdadc = 0;
3793 bool is2GHz = false;
3794 unsigned int i = 0;
3795 struct ath_common *common = ath9k_hw_common(ah);
3796
3797 if (freq < 4000)
3798 is2GHz = true;
3799
3800 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
3801 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
3802 is2GHz);
3803 targetPowerValT2[ALL_TARGET_LEGACY_36] =
3804 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
3805 is2GHz);
3806 targetPowerValT2[ALL_TARGET_LEGACY_48] =
3807 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
3808 is2GHz);
3809 targetPowerValT2[ALL_TARGET_LEGACY_54] =
3810 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
3811 is2GHz);
3812 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
3813 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
3814 freq);
3815 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
3816 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
3817 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
3818 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
3819 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
3820 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
3821 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
3822 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
3823 is2GHz);
3824 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
3825 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
3826 freq, is2GHz);
3827 targetPowerValT2[ALL_TARGET_HT20_4] =
3828 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
3829 is2GHz);
3830 targetPowerValT2[ALL_TARGET_HT20_5] =
3831 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
3832 is2GHz);
3833 targetPowerValT2[ALL_TARGET_HT20_6] =
3834 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
3835 is2GHz);
3836 targetPowerValT2[ALL_TARGET_HT20_7] =
3837 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
3838 is2GHz);
3839 targetPowerValT2[ALL_TARGET_HT20_12] =
3840 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
3841 is2GHz);
3842 targetPowerValT2[ALL_TARGET_HT20_13] =
3843 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
3844 is2GHz);
3845 targetPowerValT2[ALL_TARGET_HT20_14] =
3846 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
3847 is2GHz);
3848 targetPowerValT2[ALL_TARGET_HT20_15] =
3849 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
3850 is2GHz);
3851 targetPowerValT2[ALL_TARGET_HT20_20] =
3852 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
3853 is2GHz);
3854 targetPowerValT2[ALL_TARGET_HT20_21] =
3855 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
3856 is2GHz);
3857 targetPowerValT2[ALL_TARGET_HT20_22] =
3858 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
3859 is2GHz);
3860 targetPowerValT2[ALL_TARGET_HT20_23] =
3861 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
3862 is2GHz);
3863 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
3864 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
3865 is2GHz) + ht40PowerIncForPdadc;
3866 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
3867 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
3868 freq,
3869 is2GHz) + ht40PowerIncForPdadc;
3870 targetPowerValT2[ALL_TARGET_HT40_4] =
3871 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
3872 is2GHz) + ht40PowerIncForPdadc;
3873 targetPowerValT2[ALL_TARGET_HT40_5] =
3874 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
3875 is2GHz) + ht40PowerIncForPdadc;
3876 targetPowerValT2[ALL_TARGET_HT40_6] =
3877 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
3878 is2GHz) + ht40PowerIncForPdadc;
3879 targetPowerValT2[ALL_TARGET_HT40_7] =
3880 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
3881 is2GHz) + ht40PowerIncForPdadc;
3882 targetPowerValT2[ALL_TARGET_HT40_12] =
3883 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
3884 is2GHz) + ht40PowerIncForPdadc;
3885 targetPowerValT2[ALL_TARGET_HT40_13] =
3886 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
3887 is2GHz) + ht40PowerIncForPdadc;
3888 targetPowerValT2[ALL_TARGET_HT40_14] =
3889 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
3890 is2GHz) + ht40PowerIncForPdadc;
3891 targetPowerValT2[ALL_TARGET_HT40_15] =
3892 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
3893 is2GHz) + ht40PowerIncForPdadc;
3894 targetPowerValT2[ALL_TARGET_HT40_20] =
3895 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
3896 is2GHz) + ht40PowerIncForPdadc;
3897 targetPowerValT2[ALL_TARGET_HT40_21] =
3898 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
3899 is2GHz) + ht40PowerIncForPdadc;
3900 targetPowerValT2[ALL_TARGET_HT40_22] =
3901 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
3902 is2GHz) + ht40PowerIncForPdadc;
3903 targetPowerValT2[ALL_TARGET_HT40_23] =
3904 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
3905 is2GHz) + ht40PowerIncForPdadc;
3906
3907 while (i < ar9300RateSize) {
3908 ath_print(common, ATH_DBG_EEPROM,
3909 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3910 i++;
3911
3912 ath_print(common, ATH_DBG_EEPROM,
3913 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3914 i++;
3915
3916 ath_print(common, ATH_DBG_EEPROM,
3917 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
3918 i++;
3919
3920 ath_print(common, ATH_DBG_EEPROM,
3921 "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
3922 i++;
3923 }
3924 }
3925
3926 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
3927 int mode,
3928 int ipier,
3929 int ichain,
3930 int *pfrequency,
3931 int *pcorrection,
3932 int *ptemperature, int *pvoltage)
3933 {
3934 u8 *pCalPier;
3935 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
3936 int is2GHz;
3937 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3938 struct ath_common *common = ath9k_hw_common(ah);
3939
3940 if (ichain >= AR9300_MAX_CHAINS) {
3941 ath_print(common, ATH_DBG_EEPROM,
3942 "Invalid chain index, must be less than %d\n",
3943 AR9300_MAX_CHAINS);
3944 return -1;
3945 }
3946
3947 if (mode) { /* 5GHz */
3948 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
3949 ath_print(common, ATH_DBG_EEPROM,
3950 "Invalid 5GHz cal pier index, must "
3951 "be less than %d\n",
3952 AR9300_NUM_5G_CAL_PIERS);
3953 return -1;
3954 }
3955 pCalPier = &(eep->calFreqPier5G[ipier]);
3956 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
3957 is2GHz = 0;
3958 } else {
3959 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
3960 ath_print(common, ATH_DBG_EEPROM,
3961 "Invalid 2GHz cal pier index, must "
3962 "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
3963 return -1;
3964 }
3965
3966 pCalPier = &(eep->calFreqPier2G[ipier]);
3967 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
3968 is2GHz = 1;
3969 }
3970
3971 *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
3972 *pcorrection = pCalPierStruct->refPower;
3973 *ptemperature = pCalPierStruct->tempMeas;
3974 *pvoltage = pCalPierStruct->voltMeas;
3975
3976 return 0;
3977 }
3978
3979 static int ar9003_hw_power_control_override(struct ath_hw *ah,
3980 int frequency,
3981 int *correction,
3982 int *voltage, int *temperature)
3983 {
3984 int tempSlope = 0;
3985 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3986
3987 REG_RMW(ah, AR_PHY_TPC_11_B0,
3988 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3989 AR_PHY_TPC_OLPC_GAIN_DELTA);
3990 REG_RMW(ah, AR_PHY_TPC_11_B1,
3991 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3992 AR_PHY_TPC_OLPC_GAIN_DELTA);
3993 REG_RMW(ah, AR_PHY_TPC_11_B2,
3994 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
3995 AR_PHY_TPC_OLPC_GAIN_DELTA);
3996
3997 /* enable open loop power control on chip */
3998 REG_RMW(ah, AR_PHY_TPC_6_B0,
3999 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4000 AR_PHY_TPC_6_ERROR_EST_MODE);
4001 REG_RMW(ah, AR_PHY_TPC_6_B1,
4002 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4003 AR_PHY_TPC_6_ERROR_EST_MODE);
4004 REG_RMW(ah, AR_PHY_TPC_6_B2,
4005 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4006 AR_PHY_TPC_6_ERROR_EST_MODE);
4007
4008 /*
4009 * enable temperature compensation
4010 * Need to use register names
4011 */
4012 if (frequency < 4000)
4013 tempSlope = eep->modalHeader2G.tempSlope;
4014 else
4015 tempSlope = eep->modalHeader5G.tempSlope;
4016
4017 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4018 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4019 temperature[0]);
4020
4021 return 0;
4022 }
4023
4024 /* Apply the recorded correction values. */
4025 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4026 {
4027 int ichain, ipier, npier;
4028 int mode;
4029 int lfrequency[AR9300_MAX_CHAINS],
4030 lcorrection[AR9300_MAX_CHAINS],
4031 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4032 int hfrequency[AR9300_MAX_CHAINS],
4033 hcorrection[AR9300_MAX_CHAINS],
4034 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4035 int fdiff;
4036 int correction[AR9300_MAX_CHAINS],
4037 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4038 int pfrequency, pcorrection, ptemperature, pvoltage;
4039 struct ath_common *common = ath9k_hw_common(ah);
4040
4041 mode = (frequency >= 4000);
4042 if (mode)
4043 npier = AR9300_NUM_5G_CAL_PIERS;
4044 else
4045 npier = AR9300_NUM_2G_CAL_PIERS;
4046
4047 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4048 lfrequency[ichain] = 0;
4049 hfrequency[ichain] = 100000;
4050 }
4051 /* identify best lower and higher frequency calibration measurement */
4052 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4053 for (ipier = 0; ipier < npier; ipier++) {
4054 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4055 &pfrequency, &pcorrection,
4056 &ptemperature, &pvoltage)) {
4057 fdiff = frequency - pfrequency;
4058
4059 /*
4060 * this measurement is higher than
4061 * our desired frequency
4062 */
4063 if (fdiff <= 0) {
4064 if (hfrequency[ichain] <= 0 ||
4065 hfrequency[ichain] >= 100000 ||
4066 fdiff >
4067 (frequency - hfrequency[ichain])) {
4068 /*
4069 * new best higher
4070 * frequency measurement
4071 */
4072 hfrequency[ichain] = pfrequency;
4073 hcorrection[ichain] =
4074 pcorrection;
4075 htemperature[ichain] =
4076 ptemperature;
4077 hvoltage[ichain] = pvoltage;
4078 }
4079 }
4080 if (fdiff >= 0) {
4081 if (lfrequency[ichain] <= 0
4082 || fdiff <
4083 (frequency - lfrequency[ichain])) {
4084 /*
4085 * new best lower
4086 * frequency measurement
4087 */
4088 lfrequency[ichain] = pfrequency;
4089 lcorrection[ichain] =
4090 pcorrection;
4091 ltemperature[ichain] =
4092 ptemperature;
4093 lvoltage[ichain] = pvoltage;
4094 }
4095 }
4096 }
4097 }
4098 }
4099
4100 /* interpolate */
4101 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4102 ath_print(common, ATH_DBG_EEPROM,
4103 "ch=%d f=%d low=%d %d h=%d %d\n",
4104 ichain, frequency, lfrequency[ichain],
4105 lcorrection[ichain], hfrequency[ichain],
4106 hcorrection[ichain]);
4107 /* they're the same, so just pick one */
4108 if (hfrequency[ichain] == lfrequency[ichain]) {
4109 correction[ichain] = lcorrection[ichain];
4110 voltage[ichain] = lvoltage[ichain];
4111 temperature[ichain] = ltemperature[ichain];
4112 }
4113 /* the low frequency is good */
4114 else if (frequency - lfrequency[ichain] < 1000) {
4115 /* so is the high frequency, interpolate */
4116 if (hfrequency[ichain] - frequency < 1000) {
4117
4118 correction[ichain] = lcorrection[ichain] +
4119 (((frequency - lfrequency[ichain]) *
4120 (hcorrection[ichain] -
4121 lcorrection[ichain])) /
4122 (hfrequency[ichain] - lfrequency[ichain]));
4123
4124 temperature[ichain] = ltemperature[ichain] +
4125 (((frequency - lfrequency[ichain]) *
4126 (htemperature[ichain] -
4127 ltemperature[ichain])) /
4128 (hfrequency[ichain] - lfrequency[ichain]));
4129
4130 voltage[ichain] =
4131 lvoltage[ichain] +
4132 (((frequency -
4133 lfrequency[ichain]) * (hvoltage[ichain] -
4134 lvoltage[ichain]))
4135 / (hfrequency[ichain] -
4136 lfrequency[ichain]));
4137 }
4138 /* only low is good, use it */
4139 else {
4140 correction[ichain] = lcorrection[ichain];
4141 temperature[ichain] = ltemperature[ichain];
4142 voltage[ichain] = lvoltage[ichain];
4143 }
4144 }
4145 /* only high is good, use it */
4146 else if (hfrequency[ichain] - frequency < 1000) {
4147 correction[ichain] = hcorrection[ichain];
4148 temperature[ichain] = htemperature[ichain];
4149 voltage[ichain] = hvoltage[ichain];
4150 } else { /* nothing is good, presume 0???? */
4151 correction[ichain] = 0;
4152 temperature[ichain] = 0;
4153 voltage[ichain] = 0;
4154 }
4155 }
4156
4157 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4158 temperature);
4159
4160 ath_print(common, ATH_DBG_EEPROM,
4161 "for frequency=%d, calibration correction = %d %d %d\n",
4162 frequency, correction[0], correction[1], correction[2]);
4163
4164 return 0;
4165 }
4166
4167 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4168 int idx,
4169 int edge,
4170 bool is2GHz)
4171 {
4172 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4173 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4174
4175 if (is2GHz)
4176 return ctl_2g[idx].ctlEdges[edge].tPower;
4177 else
4178 return ctl_5g[idx].ctlEdges[edge].tPower;
4179 }
4180
4181 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4182 int idx,
4183 unsigned int edge,
4184 u16 freq,
4185 bool is2GHz)
4186 {
4187 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4188 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4189
4190 u8 *ctl_freqbin = is2GHz ?
4191 &eep->ctl_freqbin_2G[idx][0] :
4192 &eep->ctl_freqbin_5G[idx][0];
4193
4194 if (is2GHz) {
4195 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4196 ctl_2g[idx].ctlEdges[edge - 1].flag)
4197 return ctl_2g[idx].ctlEdges[edge - 1].tPower;
4198 } else {
4199 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4200 ctl_5g[idx].ctlEdges[edge - 1].flag)
4201 return ctl_5g[idx].ctlEdges[edge - 1].tPower;
4202 }
4203
4204 return AR9300_MAX_RATE_POWER;
4205 }
4206
4207 /*
4208 * Find the maximum conformance test limit for the given channel and CTL info
4209 */
4210 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4211 u16 freq, int idx, bool is2GHz)
4212 {
4213 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4214 u8 *ctl_freqbin = is2GHz ?
4215 &eep->ctl_freqbin_2G[idx][0] :
4216 &eep->ctl_freqbin_5G[idx][0];
4217 u16 num_edges = is2GHz ?
4218 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4219 unsigned int edge;
4220
4221 /* Get the edge power */
4222 for (edge = 0;
4223 (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
4224 edge++) {
4225 /*
4226 * If there's an exact channel match or an inband flag set
4227 * on the lower channel use the given rdEdgePower
4228 */
4229 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4230 twiceMaxEdgePower =
4231 ar9003_hw_get_direct_edge_power(eep, idx,
4232 edge, is2GHz);
4233 break;
4234 } else if ((edge > 0) &&
4235 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4236 is2GHz))) {
4237 twiceMaxEdgePower =
4238 ar9003_hw_get_indirect_edge_power(eep, idx,
4239 edge, freq,
4240 is2GHz);
4241 /*
4242 * Leave loop - no more affecting edges possible in
4243 * this monotonic increasing list
4244 */
4245 break;
4246 }
4247 }
4248 return twiceMaxEdgePower;
4249 }
4250
4251 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4252 struct ath9k_channel *chan,
4253 u8 *pPwrArray, u16 cfgCtl,
4254 u8 twiceAntennaReduction,
4255 u8 twiceMaxRegulatoryPower,
4256 u16 powerLimit)
4257 {
4258 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4259 struct ath_common *common = ath9k_hw_common(ah);
4260 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4261 u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4262 static const u16 tpScaleReductionTable[5] = {
4263 0, 3, 6, 9, AR9300_MAX_RATE_POWER
4264 };
4265 int i;
4266 int16_t twiceLargestAntenna;
4267 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4268 u16 ctlModesFor11a[] = {
4269 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4270 };
4271 u16 ctlModesFor11g[] = {
4272 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4273 CTL_11G_EXT, CTL_2GHT40
4274 };
4275 u16 numCtlModes, *pCtlMode, ctlMode, freq;
4276 struct chan_centers centers;
4277 u8 *ctlIndex;
4278 u8 ctlNum;
4279 u16 twiceMinEdgePower;
4280 bool is2ghz = IS_CHAN_2GHZ(chan);
4281
4282 ath9k_hw_get_channel_centers(ah, chan, &centers);
4283
4284 /* Compute TxPower reduction due to Antenna Gain */
4285 if (is2ghz)
4286 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4287 else
4288 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4289
4290 twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4291 twiceLargestAntenna, 0);
4292
4293 /*
4294 * scaledPower is the minimum of the user input power level
4295 * and the regulatory allowed power level
4296 */
4297 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4298
4299 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4300 maxRegAllowedPower -=
4301 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4302 }
4303
4304 scaledPower = min(powerLimit, maxRegAllowedPower);
4305
4306 /*
4307 * Reduce scaled Power by number of chains active to get
4308 * to per chain tx power level
4309 */
4310 switch (ar5416_get_ntxchains(ah->txchainmask)) {
4311 case 1:
4312 break;
4313 case 2:
4314 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4315 break;
4316 case 3:
4317 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4318 break;
4319 }
4320
4321 scaledPower = max((u16)0, scaledPower);
4322
4323 /*
4324 * Get target powers from EEPROM - our baseline for TX Power
4325 */
4326 if (is2ghz) {
4327 /* Setup for CTL modes */
4328 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4329 numCtlModes =
4330 ARRAY_SIZE(ctlModesFor11g) -
4331 SUB_NUM_CTL_MODES_AT_2G_40;
4332 pCtlMode = ctlModesFor11g;
4333 if (IS_CHAN_HT40(chan))
4334 /* All 2G CTL's */
4335 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4336 } else {
4337 /* Setup for CTL modes */
4338 /* CTL_11A, CTL_5GHT20 */
4339 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4340 SUB_NUM_CTL_MODES_AT_5G_40;
4341 pCtlMode = ctlModesFor11a;
4342 if (IS_CHAN_HT40(chan))
4343 /* All 5G CTL's */
4344 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4345 }
4346
4347 /*
4348 * For MIMO, need to apply regulatory caps individually across
4349 * dynamically running modes: CCK, OFDM, HT20, HT40
4350 *
4351 * The outer loop walks through each possible applicable runtime mode.
4352 * The inner loop walks through each ctlIndex entry in EEPROM.
4353 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4354 */
4355 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4356 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4357 (pCtlMode[ctlMode] == CTL_2GHT40);
4358 if (isHt40CtlMode)
4359 freq = centers.synth_center;
4360 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4361 freq = centers.ext_center;
4362 else
4363 freq = centers.ctl_center;
4364
4365 ath_print(common, ATH_DBG_REGULATORY,
4366 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4367 "EXT_ADDITIVE %d\n",
4368 ctlMode, numCtlModes, isHt40CtlMode,
4369 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4370
4371 /* walk through each CTL index stored in EEPROM */
4372 if (is2ghz) {
4373 ctlIndex = pEepData->ctlIndex_2G;
4374 ctlNum = AR9300_NUM_CTLS_2G;
4375 } else {
4376 ctlIndex = pEepData->ctlIndex_5G;
4377 ctlNum = AR9300_NUM_CTLS_5G;
4378 }
4379
4380 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4381 ath_print(common, ATH_DBG_REGULATORY,
4382 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4383 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4384 "chan %dn",
4385 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4386 chan->channel);
4387
4388 /*
4389 * compare test group from regulatory
4390 * channel list with test mode from pCtlMode
4391 * list
4392 */
4393 if ((((cfgCtl & ~CTL_MODE_M) |
4394 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4395 ctlIndex[i]) ||
4396 (((cfgCtl & ~CTL_MODE_M) |
4397 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4398 ((ctlIndex[i] & CTL_MODE_M) |
4399 SD_NO_CTL))) {
4400 twiceMinEdgePower =
4401 ar9003_hw_get_max_edge_power(pEepData,
4402 freq, i,
4403 is2ghz);
4404
4405 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4406 /*
4407 * Find the minimum of all CTL
4408 * edge powers that apply to
4409 * this channel
4410 */
4411 twiceMaxEdgePower =
4412 min(twiceMaxEdgePower,
4413 twiceMinEdgePower);
4414 else {
4415 /* specific */
4416 twiceMaxEdgePower =
4417 twiceMinEdgePower;
4418 break;
4419 }
4420 }
4421 }
4422
4423 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4424
4425 ath_print(common, ATH_DBG_REGULATORY,
4426 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
4427 "sP %d minCtlPwr %d\n",
4428 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4429 scaledPower, minCtlPower);
4430
4431 /* Apply ctl mode to correct target power set */
4432 switch (pCtlMode[ctlMode]) {
4433 case CTL_11B:
4434 for (i = ALL_TARGET_LEGACY_1L_5L;
4435 i <= ALL_TARGET_LEGACY_11S; i++)
4436 pPwrArray[i] =
4437 (u8)min((u16)pPwrArray[i],
4438 minCtlPower);
4439 break;
4440 case CTL_11A:
4441 case CTL_11G:
4442 for (i = ALL_TARGET_LEGACY_6_24;
4443 i <= ALL_TARGET_LEGACY_54; i++)
4444 pPwrArray[i] =
4445 (u8)min((u16)pPwrArray[i],
4446 minCtlPower);
4447 break;
4448 case CTL_5GHT20:
4449 case CTL_2GHT20:
4450 for (i = ALL_TARGET_HT20_0_8_16;
4451 i <= ALL_TARGET_HT20_21; i++)
4452 pPwrArray[i] =
4453 (u8)min((u16)pPwrArray[i],
4454 minCtlPower);
4455 pPwrArray[ALL_TARGET_HT20_22] =
4456 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4457 minCtlPower);
4458 pPwrArray[ALL_TARGET_HT20_23] =
4459 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4460 minCtlPower);
4461 break;
4462 case CTL_5GHT40:
4463 case CTL_2GHT40:
4464 for (i = ALL_TARGET_HT40_0_8_16;
4465 i <= ALL_TARGET_HT40_23; i++)
4466 pPwrArray[i] =
4467 (u8)min((u16)pPwrArray[i],
4468 minCtlPower);
4469 break;
4470 default:
4471 break;
4472 }
4473 } /* end ctl mode checking */
4474 }
4475
4476 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4477 struct ath9k_channel *chan, u16 cfgCtl,
4478 u8 twiceAntennaReduction,
4479 u8 twiceMaxRegulatoryPower,
4480 u8 powerLimit, bool test)
4481 {
4482 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4483 struct ath_common *common = ath9k_hw_common(ah);
4484 u8 targetPowerValT2[ar9300RateSize];
4485 unsigned int i = 0;
4486
4487 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4488 ar9003_hw_set_power_per_rate_table(ah, chan,
4489 targetPowerValT2, cfgCtl,
4490 twiceAntennaReduction,
4491 twiceMaxRegulatoryPower,
4492 powerLimit);
4493
4494 regulatory->max_power_level = 0;
4495 for (i = 0; i < ar9300RateSize; i++) {
4496 if (targetPowerValT2[i] > regulatory->max_power_level)
4497 regulatory->max_power_level = targetPowerValT2[i];
4498 }
4499
4500 if (test)
4501 return;
4502
4503 for (i = 0; i < ar9300RateSize; i++) {
4504 ath_print(common, ATH_DBG_EEPROM,
4505 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4506 i++;
4507 ath_print(common, ATH_DBG_EEPROM,
4508 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4509 i++;
4510 ath_print(common, ATH_DBG_EEPROM,
4511 "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4512 i++;
4513 ath_print(common, ATH_DBG_EEPROM,
4514 "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
4515 i++;
4516 }
4517
4518 /*
4519 * This is the TX power we send back to driver core,
4520 * and it can use to pass to userspace to display our
4521 * currently configured TX power setting.
4522 *
4523 * Since power is rate dependent, use one of the indices
4524 * from the AR9300_Rates enum to select an entry from
4525 * targetPowerValT2[] to report. Currently returns the
4526 * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4527 * as CCK power is less interesting (?).
4528 */
4529 i = ALL_TARGET_LEGACY_6_24; /* legacy */
4530 if (IS_CHAN_HT40(chan))
4531 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4532 else if (IS_CHAN_HT20(chan))
4533 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4534
4535 ah->txpower_limit = targetPowerValT2[i];
4536 regulatory->max_power_level = targetPowerValT2[i];
4537
4538 /* Write target power array to registers */
4539 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4540 ar9003_hw_calibration_apply(ah, chan->channel);
4541 }
4542
4543 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4544 u16 i, bool is2GHz)
4545 {
4546 return AR_NO_SPUR;
4547 }
4548
4549 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4550 {
4551 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4552
4553 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4554 }
4555
4556 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4557 {
4558 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4559
4560 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4561 }
4562
4563 const struct eeprom_ops eep_ar9300_ops = {
4564 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4565 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4566 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4567 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4568 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4569 .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
4570 .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
4571 .set_board_values = ath9k_hw_ar9300_set_board_values,
4572 .set_addac = ath9k_hw_ar9300_set_addac,
4573 .set_txpower = ath9k_hw_ar9300_set_txpower,
4574 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
4575 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree