2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses
);
20 EXPORT_SYMBOL(pci_root_buses
);
23 static int find_anything(struct device
*dev
, void *data
)
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
33 int no_pci_devices(void)
38 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
39 no_devices
= (dev
== NULL
);
43 EXPORT_SYMBOL(no_pci_devices
);
46 * PCI Bus Class Devices
48 static ssize_t
pci_bus_show_cpuaffinity(struct device
*dev
,
50 struct device_attribute
*attr
,
54 const struct cpumask
*cpumask
;
56 cpumask
= cpumask_of_pcibus(to_pci_bus(dev
));
58 cpulist_scnprintf(buf
, PAGE_SIZE
-2, cpumask
) :
59 cpumask_scnprintf(buf
, PAGE_SIZE
-2, cpumask
);
65 static ssize_t
inline pci_bus_show_cpumaskaffinity(struct device
*dev
,
66 struct device_attribute
*attr
,
69 return pci_bus_show_cpuaffinity(dev
, 0, attr
, buf
);
72 static ssize_t
inline pci_bus_show_cpulistaffinity(struct device
*dev
,
73 struct device_attribute
*attr
,
76 return pci_bus_show_cpuaffinity(dev
, 1, attr
, buf
);
79 DEVICE_ATTR(cpuaffinity
, S_IRUGO
, pci_bus_show_cpumaskaffinity
, NULL
);
80 DEVICE_ATTR(cpulistaffinity
, S_IRUGO
, pci_bus_show_cpulistaffinity
, NULL
);
85 static void release_pcibus_dev(struct device
*dev
)
87 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
90 put_device(pci_bus
->bridge
);
94 static struct class pcibus_class
= {
96 .dev_release
= &release_pcibus_dev
,
99 static int __init
pcibus_class_init(void)
101 return class_register(&pcibus_class
);
103 postcore_initcall(pcibus_class_init
);
106 * Translate the low bits of the PCI base
107 * to the resource type
109 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
111 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
112 return IORESOURCE_IO
;
114 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
115 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
117 return IORESOURCE_MEM
;
120 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
122 u64 size
= mask
& maxbase
; /* Find the significant bits */
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size
= (size
& ~(size
-1)) - 1;
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
138 static inline enum pci_bar_type
decode_bar(struct resource
*res
, u32 bar
)
140 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
141 res
->flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
145 res
->flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
147 if (res
->flags
& PCI_BASE_ADDRESS_MEM_TYPE_64
)
148 return pci_bar_mem64
;
149 return pci_bar_mem32
;
153 * pci_read_base - read a PCI BAR
154 * @dev: the PCI device
155 * @type: type of the BAR
156 * @res: resource buffer to be filled in
157 * @pos: BAR position in the config space
159 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
161 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
162 struct resource
*res
, unsigned int pos
)
166 mask
= type
? ~PCI_ROM_ADDRESS_ENABLE
: ~0;
168 res
->name
= pci_name(dev
);
170 pci_read_config_dword(dev
, pos
, &l
);
171 pci_write_config_dword(dev
, pos
, mask
);
172 pci_read_config_dword(dev
, pos
, &sz
);
173 pci_write_config_dword(dev
, pos
, l
);
176 * All bits set in sz means the device isn't working properly.
177 * If the BAR isn't implemented, all bits must be 0. If it's a
178 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
181 if (!sz
|| sz
== 0xffffffff)
185 * I don't know how l can have all bits set. Copied from old code.
186 * Maybe it fixes a bug on some ancient platform.
191 if (type
== pci_bar_unknown
) {
192 type
= decode_bar(res
, l
);
193 res
->flags
|= pci_calc_resource_flags(l
) | IORESOURCE_SIZEALIGN
;
194 if (type
== pci_bar_io
) {
195 l
&= PCI_BASE_ADDRESS_IO_MASK
;
196 mask
= PCI_BASE_ADDRESS_IO_MASK
& 0xffff;
198 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
199 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
202 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
203 l
&= PCI_ROM_ADDRESS_MASK
;
204 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
207 if (type
== pci_bar_mem64
) {
210 u64 mask64
= mask
| (u64
)~0 << 32;
212 pci_read_config_dword(dev
, pos
+ 4, &l
);
213 pci_write_config_dword(dev
, pos
+ 4, ~0);
214 pci_read_config_dword(dev
, pos
+ 4, &sz
);
215 pci_write_config_dword(dev
, pos
+ 4, l
);
217 l64
|= ((u64
)l
<< 32);
218 sz64
|= ((u64
)sz
<< 32);
220 sz64
= pci_size(l64
, sz64
, mask64
);
225 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
226 dev_err(&dev
->dev
, "can't handle 64-bit BAR\n");
228 } else if ((sizeof(resource_size_t
) < 8) && l
) {
229 /* Address above 32-bit boundary; disable the BAR */
230 pci_write_config_dword(dev
, pos
, 0);
231 pci_write_config_dword(dev
, pos
+ 4, 0);
236 res
->end
= l64
+ sz64
;
237 dev_printk(KERN_DEBUG
, &dev
->dev
,
238 "reg %x 64bit mmio: %pR\n", pos
, res
);
241 sz
= pci_size(l
, sz
, mask
);
249 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x %s: %pR\n", pos
,
250 (res
->flags
& IORESOURCE_IO
) ? "io port" : "32bit mmio",
255 return (type
== pci_bar_mem64
) ? 1 : 0;
261 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
263 unsigned int pos
, reg
;
265 for (pos
= 0; pos
< howmany
; pos
++) {
266 struct resource
*res
= &dev
->resource
[pos
];
267 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
268 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
272 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
273 dev
->rom_base_reg
= rom
;
274 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
275 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
276 IORESOURCE_SIZEALIGN
;
277 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
281 void __devinit
pci_read_bridge_bases(struct pci_bus
*child
)
283 struct pci_dev
*dev
= child
->self
;
284 u8 io_base_lo
, io_limit_lo
;
285 u16 mem_base_lo
, mem_limit_lo
;
286 unsigned long base
, limit
;
287 struct resource
*res
;
290 if (!dev
) /* It's a host bus, nothing to read */
293 if (dev
->transparent
) {
294 dev_info(&dev
->dev
, "transparent bridge\n");
295 for(i
= 3; i
< PCI_BUS_NUM_RESOURCES
; i
++)
296 child
->resource
[i
] = child
->parent
->resource
[i
- 3];
299 res
= child
->resource
[0];
300 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
301 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
302 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
303 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
305 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
306 u16 io_base_hi
, io_limit_hi
;
307 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
308 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
309 base
|= (io_base_hi
<< 16);
310 limit
|= (io_limit_hi
<< 16);
314 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
318 res
->end
= limit
+ 0xfff;
319 dev_printk(KERN_DEBUG
, &dev
->dev
, "bridge io port: %pR\n", res
);
322 res
= child
->resource
[1];
323 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
324 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
325 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
326 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
328 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
330 res
->end
= limit
+ 0xfffff;
331 dev_printk(KERN_DEBUG
, &dev
->dev
, "bridge 32bit mmio: %pR\n",
335 res
= child
->resource
[2];
336 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
337 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
338 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
339 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
341 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
342 u32 mem_base_hi
, mem_limit_hi
;
343 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
344 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
347 * Some bridges set the base > limit by default, and some
348 * (broken) BIOSes do not initialize them. If we find
349 * this, just assume they are not being used.
351 if (mem_base_hi
<= mem_limit_hi
) {
352 #if BITS_PER_LONG == 64
353 base
|= ((long) mem_base_hi
) << 32;
354 limit
|= ((long) mem_limit_hi
) << 32;
356 if (mem_base_hi
|| mem_limit_hi
) {
357 dev_err(&dev
->dev
, "can't handle 64-bit "
358 "address space for bridge\n");
365 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
367 res
->end
= limit
+ 0xfffff;
368 dev_printk(KERN_DEBUG
, &dev
->dev
, "bridge %sbit mmio pref: %pR\n",
369 (res
->flags
& PCI_PREF_RANGE_TYPE_64
) ? "64" : "32",
374 static struct pci_bus
* pci_alloc_bus(void)
378 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
380 INIT_LIST_HEAD(&b
->node
);
381 INIT_LIST_HEAD(&b
->children
);
382 INIT_LIST_HEAD(&b
->devices
);
383 INIT_LIST_HEAD(&b
->slots
);
388 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
389 struct pci_dev
*bridge
, int busnr
)
391 struct pci_bus
*child
;
395 * Allocate a new bus, and inherit stuff from the parent..
397 child
= pci_alloc_bus();
401 child
->parent
= parent
;
402 child
->ops
= parent
->ops
;
403 child
->sysdata
= parent
->sysdata
;
404 child
->bus_flags
= parent
->bus_flags
;
406 /* initialize some portions of the bus device, but don't register it
407 * now as the parent is not properly set up yet. This device will get
408 * registered later in pci_bus_add_devices()
410 child
->dev
.class = &pcibus_class
;
411 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
414 * Set up the primary, secondary and subordinate
417 child
->number
= child
->secondary
= busnr
;
418 child
->primary
= parent
->secondary
;
419 child
->subordinate
= 0xff;
424 child
->self
= bridge
;
425 child
->bridge
= get_device(&bridge
->dev
);
427 /* Set up default resource pointers and names.. */
428 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
429 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
430 child
->resource
[i
]->name
= child
->name
;
432 bridge
->subordinate
= child
;
437 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
439 struct pci_bus
*child
;
441 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
443 down_write(&pci_bus_sem
);
444 list_add_tail(&child
->node
, &parent
->children
);
445 up_write(&pci_bus_sem
);
450 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
452 struct pci_bus
*parent
= child
->parent
;
454 /* Attempts to fix that up are really dangerous unless
455 we're going to re-assign all bus numbers. */
456 if (!pcibios_assign_all_busses())
459 while (parent
->parent
&& parent
->subordinate
< max
) {
460 parent
->subordinate
= max
;
461 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
462 parent
= parent
->parent
;
467 * If it's a bridge, configure it and scan the bus behind it.
468 * For CardBus bridges, we don't scan behind as the devices will
469 * be handled by the bridge driver itself.
471 * We need to process bridges in two passes -- first we scan those
472 * already configured by the BIOS and after we are done with all of
473 * them, we proceed to assigning numbers to the remaining buses in
474 * order to avoid overlaps between old and new bus numbers.
476 int __devinit
pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
478 struct pci_bus
*child
;
479 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
484 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
486 dev_dbg(&dev
->dev
, "scanning behind bridge, config %06x, pass %d\n",
487 buses
& 0xffffff, pass
);
489 /* Check if setup is sensible at all */
491 ((buses
& 0xff) != bus
->number
|| ((buses
>> 8) & 0xff) <= bus
->number
)) {
492 dev_dbg(&dev
->dev
, "bus configuration invalid, reconfiguring\n");
496 /* Disable MasterAbortMode during probing to avoid reporting
497 of bus errors (in some architectures) */
498 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
499 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
500 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
502 if ((buses
& 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus
&& !broken
) {
503 unsigned int cmax
, busnr
;
505 * Bus already configured by firmware, process it in the first
506 * pass and just note the configuration.
510 busnr
= (buses
>> 8) & 0xFF;
513 * If we already got to this bus through a different bridge,
514 * ignore it. This can happen with the i450NX chipset.
516 if (pci_find_bus(pci_domain_nr(bus
), busnr
)) {
517 dev_info(&dev
->dev
, "bus %04x:%02x already known\n",
518 pci_domain_nr(bus
), busnr
);
522 child
= pci_add_new_bus(bus
, dev
, busnr
);
525 child
->primary
= buses
& 0xFF;
526 child
->subordinate
= (buses
>> 16) & 0xFF;
527 child
->bridge_ctl
= bctl
;
529 cmax
= pci_scan_child_bus(child
);
532 if (child
->subordinate
> max
)
533 max
= child
->subordinate
;
536 * We need to assign a number to this bus which we always
537 * do in the second pass.
540 if (pcibios_assign_all_busses() || broken
)
541 /* Temporarily disable forwarding of the
542 configuration cycles on all bridges in
543 this bus segment to avoid possible
544 conflicts in the second pass between two
545 bridges programmed with overlapping
547 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
553 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
555 /* Prevent assigning a bus number that already exists.
556 * This can happen when a bridge is hot-plugged */
557 if (pci_find_bus(pci_domain_nr(bus
), max
+1))
559 child
= pci_add_new_bus(bus
, dev
, ++max
);
560 buses
= (buses
& 0xff000000)
561 | ((unsigned int)(child
->primary
) << 0)
562 | ((unsigned int)(child
->secondary
) << 8)
563 | ((unsigned int)(child
->subordinate
) << 16);
566 * yenta.c forces a secondary latency timer of 176.
567 * Copy that behaviour here.
570 buses
&= ~0xff000000;
571 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
575 * We need to blast all three values with a single write.
577 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
580 child
->bridge_ctl
= bctl
;
582 * Adjust subordinate busnr in parent buses.
583 * We do this before scanning for children because
584 * some devices may not be detected if the bios
587 pci_fixup_parent_subordinate_busnr(child
, max
);
588 /* Now we can scan all subordinate buses... */
589 max
= pci_scan_child_bus(child
);
591 * now fix it up again since we have found
592 * the real value of max.
594 pci_fixup_parent_subordinate_busnr(child
, max
);
597 * For CardBus bridges, we leave 4 bus numbers
598 * as cards with a PCI-to-PCI bridge can be
601 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
602 struct pci_bus
*parent
= bus
;
603 if (pci_find_bus(pci_domain_nr(bus
),
606 while (parent
->parent
) {
607 if ((!pcibios_assign_all_busses()) &&
608 (parent
->subordinate
> max
) &&
609 (parent
->subordinate
<= max
+i
)) {
612 parent
= parent
->parent
;
616 * Often, there are two cardbus bridges
617 * -- try to leave one valid bus number
625 pci_fixup_parent_subordinate_busnr(child
, max
);
628 * Set the subordinate bus number to its real value.
630 child
->subordinate
= max
;
631 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
635 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
636 pci_domain_nr(bus
), child
->number
);
638 /* Has only triggered on CardBus, fixup is in yenta_socket */
639 while (bus
->parent
) {
640 if ((child
->subordinate
> bus
->subordinate
) ||
641 (child
->number
> bus
->subordinate
) ||
642 (child
->number
< bus
->number
) ||
643 (child
->subordinate
< bus
->number
)) {
644 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
645 "hidden behind%s bridge #%02x (-#%02x)\n",
646 child
->number
, child
->subordinate
,
647 (bus
->number
> child
->subordinate
&&
648 bus
->subordinate
< child
->number
) ?
649 "wholly" : "partially",
650 bus
->self
->transparent
? " transparent" : "",
651 bus
->number
, bus
->subordinate
);
657 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
663 * Read interrupt line and base address registers.
664 * The architecture-dependent code can tweak these, of course.
666 static void pci_read_irq(struct pci_dev
*dev
)
670 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
673 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
677 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
680 * pci_setup_device - fill in class and map information of a device
681 * @dev: the device structure to fill
683 * Initialize the device structure with information about the device's
684 * vendor,class,memory and IO-space addresses,IRQ lines etc.
685 * Called at initialisation of the PCI subsystem and by CardBus services.
686 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
689 static int pci_setup_device(struct pci_dev
* dev
)
693 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
694 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
695 PCI_FUNC(dev
->devfn
));
697 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
698 dev
->revision
= class & 0xff;
699 class >>= 8; /* upper 3 bytes */
703 dev_dbg(&dev
->dev
, "found [%04x:%04x] class %06x header type %02x\n",
704 dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
706 /* "Unknown power state" */
707 dev
->current_state
= PCI_UNKNOWN
;
709 /* Early fixups, before probing the BARs */
710 pci_fixup_device(pci_fixup_early
, dev
);
711 class = dev
->class >> 8;
713 switch (dev
->hdr_type
) { /* header type */
714 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
715 if (class == PCI_CLASS_BRIDGE_PCI
)
718 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
719 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
720 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
723 * Do the ugly legacy mode stuff here rather than broken chip
724 * quirk code. Legacy mode ATA controllers have fixed
725 * addresses. These are not always echoed in BAR0-3, and
726 * BAR0-3 in a few cases contain junk!
728 if (class == PCI_CLASS_STORAGE_IDE
) {
730 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
731 if ((progif
& 1) == 0) {
732 dev
->resource
[0].start
= 0x1F0;
733 dev
->resource
[0].end
= 0x1F7;
734 dev
->resource
[0].flags
= LEGACY_IO_RESOURCE
;
735 dev
->resource
[1].start
= 0x3F6;
736 dev
->resource
[1].end
= 0x3F6;
737 dev
->resource
[1].flags
= LEGACY_IO_RESOURCE
;
739 if ((progif
& 4) == 0) {
740 dev
->resource
[2].start
= 0x170;
741 dev
->resource
[2].end
= 0x177;
742 dev
->resource
[2].flags
= LEGACY_IO_RESOURCE
;
743 dev
->resource
[3].start
= 0x376;
744 dev
->resource
[3].end
= 0x376;
745 dev
->resource
[3].flags
= LEGACY_IO_RESOURCE
;
750 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
751 if (class != PCI_CLASS_BRIDGE_PCI
)
753 /* The PCI-to-PCI bridge spec requires that subtractive
754 decoding (i.e. transparent) bridge must have programming
755 interface code of 0x01. */
757 dev
->transparent
= ((dev
->class & 0xff) == 1);
758 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
761 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
762 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
765 pci_read_bases(dev
, 1, 0);
766 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
767 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
770 default: /* unknown header */
771 dev_err(&dev
->dev
, "unknown header type %02x, "
772 "ignoring device\n", dev
->hdr_type
);
776 dev_err(&dev
->dev
, "ignoring class %02x (doesn't match header "
777 "type %02x)\n", class, dev
->hdr_type
);
778 dev
->class = PCI_CLASS_NOT_DEFINED
;
781 /* We found a fine healthy device, go go go... */
785 static void pci_release_capabilities(struct pci_dev
*dev
)
787 pci_vpd_release(dev
);
791 * pci_release_dev - free a pci device structure when all users of it are finished.
792 * @dev: device that's been disconnected
794 * Will be called only by the device core when all users of this pci device are
797 static void pci_release_dev(struct device
*dev
)
799 struct pci_dev
*pci_dev
;
801 pci_dev
= to_pci_dev(dev
);
802 pci_release_capabilities(pci_dev
);
806 static void set_pcie_port_type(struct pci_dev
*pdev
)
811 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
815 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
816 pdev
->pcie_type
= (reg16
& PCI_EXP_FLAGS_TYPE
) >> 4;
820 * pci_cfg_space_size - get the configuration space size of the PCI device.
823 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
824 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
825 * access it. Maybe we don't have a way to generate extended config space
826 * accesses, or the device is behind a reverse Express bridge. So we try
827 * reading the dword at 0x100 which must either be 0 or a valid extended
830 int pci_cfg_space_size_ext(struct pci_dev
*dev
)
833 int pos
= PCI_CFG_SPACE_SIZE
;
835 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
837 if (status
== 0xffffffff)
840 return PCI_CFG_SPACE_EXP_SIZE
;
843 return PCI_CFG_SPACE_SIZE
;
846 int pci_cfg_space_size(struct pci_dev
*dev
)
852 class = dev
->class >> 8;
853 if (class == PCI_CLASS_BRIDGE_HOST
)
854 return pci_cfg_space_size_ext(dev
);
856 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
858 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
862 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
863 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
867 return pci_cfg_space_size_ext(dev
);
870 return PCI_CFG_SPACE_SIZE
;
873 static void pci_release_bus_bridge_dev(struct device
*dev
)
878 struct pci_dev
*alloc_pci_dev(void)
882 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
886 INIT_LIST_HEAD(&dev
->bus_list
);
890 EXPORT_SYMBOL(alloc_pci_dev
);
893 * Read the config data for a PCI device, sanity-check it
894 * and fill in the dev structure...
896 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
899 struct pci_slot
*slot
;
904 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
907 /* some broken boards return 0 or ~0 if a slot is empty: */
908 if (l
== 0xffffffff || l
== 0x00000000 ||
909 l
== 0x0000ffff || l
== 0xffff0000)
912 /* Configuration request Retry Status */
913 while (l
== 0xffff0001) {
916 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
918 /* Card hasn't responded in 60 seconds? Must be stuck. */
919 if (delay
> 60 * 1000) {
920 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
921 "responding\n", pci_domain_nr(bus
),
922 bus
->number
, PCI_SLOT(devfn
),
928 if (pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
))
931 dev
= alloc_pci_dev();
936 dev
->sysdata
= bus
->sysdata
;
937 dev
->dev
.parent
= bus
->bridge
;
938 dev
->dev
.bus
= &pci_bus_type
;
940 dev
->hdr_type
= hdr_type
& 0x7f;
941 dev
->multifunction
= !!(hdr_type
& 0x80);
942 dev
->vendor
= l
& 0xffff;
943 dev
->device
= (l
>> 16) & 0xffff;
944 dev
->error_state
= pci_channel_io_normal
;
945 set_pcie_port_type(dev
);
947 list_for_each_entry(slot
, &bus
->slots
, list
)
948 if (PCI_SLOT(devfn
) == slot
->number
)
951 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
952 set this higher, assuming the system even supports it. */
953 dev
->dma_mask
= 0xffffffff;
954 if (pci_setup_device(dev
) < 0) {
959 /* need to have dev->class ready */
960 dev
->cfg_size
= pci_cfg_space_size(dev
);
965 static void pci_init_capabilities(struct pci_dev
*dev
)
968 pci_msi_init_pci_dev(dev
);
970 /* Buffers for saving PCIe and PCI-X capabilities */
971 pci_allocate_cap_save_buffers(dev
);
973 /* Power Management */
975 platform_pci_wakeup_init(dev
);
977 /* Vital Product Data */
978 pci_vpd_pci22_init(dev
);
980 /* Alternative Routing-ID Forwarding */
984 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
986 device_initialize(&dev
->dev
);
987 dev
->dev
.release
= pci_release_dev
;
990 dev
->dev
.dma_mask
= &dev
->dma_mask
;
991 dev
->dev
.dma_parms
= &dev
->dma_parms
;
992 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
994 pci_set_dma_max_seg_size(dev
, 65536);
995 pci_set_dma_seg_boundary(dev
, 0xffffffff);
997 /* Fix up broken headers */
998 pci_fixup_device(pci_fixup_header
, dev
);
1000 /* Initialize various capabilities */
1001 pci_init_capabilities(dev
);
1004 * Add the device to our list of discovered devices
1005 * and the bus list for fixup functions, etc.
1007 down_write(&pci_bus_sem
);
1008 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1009 up_write(&pci_bus_sem
);
1012 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1014 struct pci_dev
*dev
;
1016 dev
= pci_scan_device(bus
, devfn
);
1020 pci_device_add(dev
, bus
);
1024 EXPORT_SYMBOL(pci_scan_single_device
);
1027 * pci_scan_slot - scan a PCI slot on a bus for devices.
1028 * @bus: PCI bus to scan
1029 * @devfn: slot number to scan (must have zero function.)
1031 * Scan a PCI slot on the specified PCI bus for devices, adding
1032 * discovered devices to the @bus->devices list. New devices
1033 * will not have is_added set.
1035 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1040 scan_all_fns
= pcibios_scan_all_fns(bus
, devfn
);
1042 for (func
= 0; func
< 8; func
++, devfn
++) {
1043 struct pci_dev
*dev
;
1045 dev
= pci_scan_single_device(bus
, devfn
);
1050 * If this is a single function device,
1051 * don't scan past the first function.
1053 if (!dev
->multifunction
) {
1055 dev
->multifunction
= 1;
1061 if (func
== 0 && !scan_all_fns
)
1066 /* only one slot has pcie device */
1067 if (bus
->self
&& nr
)
1068 pcie_aspm_init_link_state(bus
->self
);
1073 unsigned int __devinit
pci_scan_child_bus(struct pci_bus
*bus
)
1075 unsigned int devfn
, pass
, max
= bus
->secondary
;
1076 struct pci_dev
*dev
;
1078 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus
), bus
->number
);
1080 /* Go find them, Rover! */
1081 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1082 pci_scan_slot(bus
, devfn
);
1085 * After performing arch-dependent fixup of the bus, look behind
1086 * all PCI-to-PCI bridges on this bus.
1088 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus
), bus
->number
);
1089 pcibios_fixup_bus(bus
);
1090 for (pass
=0; pass
< 2; pass
++)
1091 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1092 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1093 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1094 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1098 * We've scanned the bus and so we know all about what's on
1099 * the other side of any bridges that may be on this bus plus
1102 * Return how far we've got finding sub-buses.
1104 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1105 pci_domain_nr(bus
), bus
->number
, max
);
1109 void __attribute__((weak
)) set_pci_bus_resources_arch_default(struct pci_bus
*b
)
1113 struct pci_bus
* pci_create_bus(struct device
*parent
,
1114 int bus
, struct pci_ops
*ops
, void *sysdata
)
1120 b
= pci_alloc_bus();
1124 dev
= kmalloc(sizeof(*dev
), GFP_KERNEL
);
1130 b
->sysdata
= sysdata
;
1133 if (pci_find_bus(pci_domain_nr(b
), bus
)) {
1134 /* If we already got to this bus through a different bridge, ignore it */
1135 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b
), bus
);
1139 down_write(&pci_bus_sem
);
1140 list_add_tail(&b
->node
, &pci_root_buses
);
1141 up_write(&pci_bus_sem
);
1143 memset(dev
, 0, sizeof(*dev
));
1144 dev
->parent
= parent
;
1145 dev
->release
= pci_release_bus_bridge_dev
;
1146 dev_set_name(dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1147 error
= device_register(dev
);
1150 b
->bridge
= get_device(dev
);
1153 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1155 b
->dev
.class = &pcibus_class
;
1156 b
->dev
.parent
= b
->bridge
;
1157 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1158 error
= device_register(&b
->dev
);
1160 goto class_dev_reg_err
;
1161 error
= device_create_file(&b
->dev
, &dev_attr_cpuaffinity
);
1163 goto dev_create_file_err
;
1165 /* Create legacy_io and legacy_mem files for this bus */
1166 pci_create_legacy_files(b
);
1168 b
->number
= b
->secondary
= bus
;
1169 b
->resource
[0] = &ioport_resource
;
1170 b
->resource
[1] = &iomem_resource
;
1172 set_pci_bus_resources_arch_default(b
);
1176 dev_create_file_err
:
1177 device_unregister(&b
->dev
);
1179 device_unregister(dev
);
1181 down_write(&pci_bus_sem
);
1183 up_write(&pci_bus_sem
);
1190 struct pci_bus
* __devinit
pci_scan_bus_parented(struct device
*parent
,
1191 int bus
, struct pci_ops
*ops
, void *sysdata
)
1195 b
= pci_create_bus(parent
, bus
, ops
, sysdata
);
1197 b
->subordinate
= pci_scan_child_bus(b
);
1200 EXPORT_SYMBOL(pci_scan_bus_parented
);
1202 #ifdef CONFIG_HOTPLUG
1203 EXPORT_SYMBOL(pci_add_new_bus
);
1204 EXPORT_SYMBOL(pci_scan_slot
);
1205 EXPORT_SYMBOL(pci_scan_bridge
);
1206 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1209 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
1211 const struct pci_dev
*a
= to_pci_dev(d_a
);
1212 const struct pci_dev
*b
= to_pci_dev(d_b
);
1214 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
1215 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
1217 if (a
->bus
->number
< b
->bus
->number
) return -1;
1218 else if (a
->bus
->number
> b
->bus
->number
) return 1;
1220 if (a
->devfn
< b
->devfn
) return -1;
1221 else if (a
->devfn
> b
->devfn
) return 1;
1226 void __init
pci_sort_breadthfirst(void)
1228 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);