| blob | caa6c396ec78433733da3db0c9e47bdc623959ae |
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
18 #include <asm/memory.h>
19 #include <asm/glue.h>
20 #include <asm/vfpmacros.h>
21 #include <mach/entry-macro.S>
22 #include <asm/thread_notify.h>
23 #include <asm/unwind.h>
24 #include <asm/unistd.h>
25 #include <asm/tls.h>
27 #include "entry-header.S"
29 /*
30 * Interrupt handling. Preserves r7, r8, r9
31 */
32 .macro irq_handler
33 #ifdef CONFIG_MULTI_IRQ_HANDLER
34 ldr r5, =handle_arch_irq
35 mov r0, sp
36 ldr r5, [r5]
37 adr lr, BSYM(9997f)
38 teq r5, #0
39 movne pc, r5
40 #endif
41 get_irqnr_preamble r5, lr
42 1: get_irqnr_and_base r0, r6, r5, lr
43 movne r1, sp
44 @
45 @ routine called with r0 = irq number, r1 = struct pt_regs *
46 @
47 adrne lr, BSYM(1b)
48 bne asm_do_IRQ
50 #ifdef CONFIG_SMP
51 /*
52 * XXX
53 *
54 * this macro assumes that irqstat (r6) and base (r5) are
55 * preserved from get_irqnr_and_base above
56 */
57 ALT_SMP(test_for_ipi r0, r6, r5, lr)
58 ALT_UP_B(9997f)
59 movne r0, sp
60 adrne lr, BSYM(1b)
61 bne do_IPI
63 #ifdef CONFIG_LOCAL_TIMERS
64 test_for_ltirq r0, r6, r5, lr
65 movne r0, sp
66 adrne lr, BSYM(1b)
67 bne do_local_timer
68 #endif
69 #endif
70 9997:
71 .endm
73 #ifdef CONFIG_KPROBES
74 .section .kprobes.text,"ax",%progbits
75 #else
76 .text
77 #endif
79 /*
80 * Invalid mode handlers
81 */
82 .macro inv_entry, reason
83 sub sp, sp, #S_FRAME_SIZE
84 ARM( stmib sp, {r1 - lr} )
85 THUMB( stmia sp, {r0 - r12} )
86 THUMB( str sp, [sp, #S_SP] )
87 THUMB( str lr, [sp, #S_LR] )
88 mov r1, #\reason
89 .endm
91 __pabt_invalid:
92 inv_entry BAD_PREFETCH
93 b common_invalid
94 ENDPROC(__pabt_invalid)
96 __dabt_invalid:
97 inv_entry BAD_DATA
98 b common_invalid
99 ENDPROC(__dabt_invalid)
101 __irq_invalid:
102 inv_entry BAD_IRQ
103 b common_invalid
104 ENDPROC(__irq_invalid)
106 __und_invalid:
107 inv_entry BAD_UNDEFINSTR
109 @
110 @ XXX fall through to common_invalid
111 @
113 @
114 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
115 @
116 common_invalid:
117 zero_fp
119 ldmia r0, {r4 - r6}
120 add r0, sp, #S_PC @ here for interlock avoidance
121 mov r7, #-1 @ "" "" "" ""
122 str r4, [sp] @ save preserved r0
123 stmia r0, {r5 - r7} @ lr_<exception>,
124 @ cpsr_<exception>, "old_r0"
126 mov r0, sp
127 b bad_mode
128 ENDPROC(__und_invalid)
130 /*
131 * SVC mode handlers
132 */
134 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
135 #define SPFIX(code...) code
136 #else
137 #define SPFIX(code...)
138 #endif
140 .macro svc_entry, stack_hole=0
141 UNWIND(.fnstart )
142 UNWIND(.save {r0 - pc} )
143 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
144 #ifdef CONFIG_THUMB2_KERNEL
145 SPFIX( str r0, [sp] ) @ temporarily saved
146 SPFIX( mov r0, sp )
147 SPFIX( tst r0, #4 ) @ test original stack alignment
148 SPFIX( ldr r0, [sp] ) @ restored
149 #else
150 SPFIX( tst sp, #4 )
151 #endif
152 SPFIX( subeq sp, sp, #4 )
153 stmia sp, {r1 - r12}
155 ldmia r0, {r1 - r3}
156 add r5, sp, #S_SP - 4 @ here for interlock avoidance
157 mov r4, #-1 @ "" "" "" ""
158 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
159 SPFIX( addeq r0, r0, #4 )
160 str r1, [sp, #-4]! @ save the "real" r0 copied
161 @ from the exception stack
163 mov r1, lr
165 @
166 @ We are now ready to fill in the remaining blanks on the stack:
167 @
168 @ r0 - sp_svc
169 @ r1 - lr_svc
170 @ r2 - lr_<exception>, already fixed up for correct return/restart
171 @ r3 - spsr_<exception>
172 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
173 @
174 stmia r5, {r0 - r4}
175 .endm
177 .align 5
178 __dabt_svc:
179 svc_entry
181 @
182 @ get ready to re-enable interrupts if appropriate
183 @
184 mrs r9, cpsr
185 tst r3, #PSR_I_BIT
186 biceq r9, r9, #PSR_I_BIT
188 @
189 @ Call the processor-specific abort handler:
190 @
191 @ r2 - aborted context pc
192 @ r3 - aborted context cpsr
193 @
194 @ The abort handler must return the aborted address in r0, and
195 @ the fault status register in r1. r9 must be preserved.
196 @
197 #ifdef MULTI_DABORT
198 ldr r4, .LCprocfns
199 mov lr, pc
200 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
201 #else
202 bl CPU_DABORT_HANDLER
203 #endif
205 @
206 @ set desired IRQ state, then call main handler
207 @
208 msr cpsr_c, r9
209 mov r2, sp
210 bl do_DataAbort
212 @
213 @ IRQs off again before pulling preserved data off the stack
214 @
215 disable_irq_notrace
217 @
218 @ restore SPSR and restart the instruction
219 @
220 ldr r2, [sp, #S_PSR]
221 svc_exit r2 @ return from exception
222 UNWIND(.fnend )
223 ENDPROC(__dabt_svc)
225 .align 5
226 __irq_svc:
227 svc_entry
229 #ifdef CONFIG_TRACE_IRQFLAGS
230 bl trace_hardirqs_off
231 #endif
232 #ifdef CONFIG_PREEMPT
233 get_thread_info tsk
234 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
235 add r7, r8, #1 @ increment it
236 str r7, [tsk, #TI_PREEMPT]
237 #endif
239 irq_handler
240 #ifdef CONFIG_PREEMPT
241 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
242 ldr r0, [tsk, #TI_FLAGS] @ get flags
243 teq r8, #0 @ if preempt count != 0
244 movne r0, #0 @ force flags to 0
245 tst r0, #_TIF_NEED_RESCHED
246 blne svc_preempt
247 #endif
248 ldr r4, [sp, #S_PSR] @ irqs are already disabled
249 #ifdef CONFIG_TRACE_IRQFLAGS
250 tst r4, #PSR_I_BIT
251 bleq trace_hardirqs_on
252 #endif
253 svc_exit r4 @ return from exception
254 UNWIND(.fnend )
255 ENDPROC(__irq_svc)
257 .ltorg
259 #ifdef CONFIG_PREEMPT
260 svc_preempt:
261 mov r8, lr
262 1: bl preempt_schedule_irq @ irq en/disable is done inside
263 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
264 tst r0, #_TIF_NEED_RESCHED
265 moveq pc, r8 @ go again
266 b 1b
267 #endif
269 .align 5
270 __und_svc:
271 #ifdef CONFIG_KPROBES
272 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
273 @ it obviously needs free stack space which then will belong to
274 @ the saved context.
275 svc_entry 64
276 #else
277 svc_entry
278 #endif
280 @
281 @ call emulation code, which returns using r9 if it has emulated
282 @ the instruction, or the more conventional lr if we are to treat
283 @ this as a real undefined instruction
284 @
285 @ r0 - instruction
286 @
287 #ifndef CONFIG_THUMB2_KERNEL
288 ldr r0, [r2, #-4]
289 #else
290 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
291 and r9, r0, #0xf800
292 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
293 ldrhhs r9, [r2] @ bottom 16 bits
294 orrhs r0, r9, r0, lsl #16
295 #endif
296 adr r9, BSYM(1f)
297 bl call_fpe
299 mov r0, sp @ struct pt_regs *regs
300 bl do_undefinstr
302 @
303 @ IRQs off again before pulling preserved data off the stack
304 @
305 1: disable_irq_notrace
307 @
308 @ restore SPSR and restart the instruction
309 @
310 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
311 svc_exit r2 @ return from exception
312 UNWIND(.fnend )
313 ENDPROC(__und_svc)
315 .align 5
316 __pabt_svc:
317 svc_entry
319 @
320 @ re-enable interrupts if appropriate
321 @
322 mrs r9, cpsr
323 tst r3, #PSR_I_BIT
324 biceq r9, r9, #PSR_I_BIT
326 mov r0, r2 @ pass address of aborted instruction.
327 #ifdef MULTI_PABORT
328 ldr r4, .LCprocfns
329 mov lr, pc
330 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
331 #else
332 bl CPU_PABORT_HANDLER
333 #endif
334 msr cpsr_c, r9 @ Maybe enable interrupts
335 mov r2, sp @ regs
336 bl do_PrefetchAbort @ call abort handler
338 @
339 @ IRQs off again before pulling preserved data off the stack
340 @
341 disable_irq_notrace
343 @
344 @ restore SPSR and restart the instruction
345 @
346 ldr r2, [sp, #S_PSR]
347 svc_exit r2 @ return from exception
348 UNWIND(.fnend )
349 ENDPROC(__pabt_svc)
351 .align 5
352 .LCcralign:
353 .word cr_alignment
354 #ifdef MULTI_DABORT
355 .LCprocfns:
356 .word processor
357 #endif
358 .LCfp:
359 .word fp_enter
361 /*
362 * User mode handlers
363 *
364 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
365 */
367 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
368 #error "sizeof(struct pt_regs) must be a multiple of 8"
369 #endif
371 .macro usr_entry
372 UNWIND(.fnstart )
373 UNWIND(.cantunwind ) @ don't unwind the user space
374 sub sp, sp, #S_FRAME_SIZE
375 ARM( stmib sp, {r1 - r12} )
376 THUMB( stmia sp, {r0 - r12} )
378 ldmia r0, {r1 - r3}
379 add r0, sp, #S_PC @ here for interlock avoidance
380 mov r4, #-1 @ "" "" "" ""
382 str r1, [sp] @ save the "real" r0 copied
383 @ from the exception stack
385 @
386 @ We are now ready to fill in the remaining blanks on the stack:
387 @
388 @ r2 - lr_<exception>, already fixed up for correct return/restart
389 @ r3 - spsr_<exception>
390 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
391 @
392 @ Also, separately save sp_usr and lr_usr
393 @
394 stmia r0, {r2 - r4}
395 ARM( stmdb r0, {sp, lr}^ )
396 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
398 @
399 @ Enable the alignment trap while in kernel mode
400 @
401 alignment_trap r0
403 @
404 @ Clear FP to mark the first stack frame
405 @
406 zero_fp
407 .endm
409 .macro kuser_cmpxchg_check
410 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
411 #ifndef CONFIG_MMU
412 #warning "NPTL on non MMU needs fixing"
413 #else
414 @ Make sure our user space atomic helper is restarted
415 @ if it was interrupted in a critical region. Here we
416 @ perform a quick test inline since it should be false
417 @ 99.9999% of the time. The rest is done out of line.
418 cmp r2, #TASK_SIZE
419 blhs kuser_cmpxchg_fixup
420 #endif
421 #endif
422 .endm
424 .align 5
425 __dabt_usr:
426 usr_entry
427 kuser_cmpxchg_check
429 @
430 @ Call the processor-specific abort handler:
431 @
432 @ r2 - aborted context pc
433 @ r3 - aborted context cpsr
434 @
435 @ The abort handler must return the aborted address in r0, and
436 @ the fault status register in r1.
437 @
438 #ifdef MULTI_DABORT
439 ldr r4, .LCprocfns
440 mov lr, pc
441 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
442 #else
443 bl CPU_DABORT_HANDLER
444 #endif
446 @
447 @ IRQs on, then call the main handler
448 @
449 enable_irq
450 mov r2, sp
451 adr lr, BSYM(ret_from_exception)
452 b do_DataAbort
453 UNWIND(.fnend )
454 ENDPROC(__dabt_usr)
456 .align 5
457 __irq_usr:
458 usr_entry
459 kuser_cmpxchg_check
461 get_thread_info tsk
462 #ifdef CONFIG_PREEMPT
463 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
464 add r7, r8, #1 @ increment it
465 str r7, [tsk, #TI_PREEMPT]
466 #endif
468 irq_handler
469 #ifdef CONFIG_PREEMPT
470 ldr r0, [tsk, #TI_PREEMPT]
471 str r8, [tsk, #TI_PREEMPT]
472 teq r0, r7
473 ARM( strne r0, [r0, -r0] )
474 THUMB( movne r0, #0 )
475 THUMB( strne r0, [r0] )
476 #endif
478 mov why, #0
479 b ret_to_user
480 UNWIND(.fnend )
481 ENDPROC(__irq_usr)
483 .ltorg
485 .align 5
486 __und_usr:
487 usr_entry
489 @
490 @ fall through to the emulation code, which returns using r9 if
491 @ it has emulated the instruction, or the more conventional lr
492 @ if we are to treat this as a real undefined instruction
493 @
494 @ r0 - instruction
495 @
496 adr r9, BSYM(ret_from_exception)
497 adr lr, BSYM(__und_usr_unknown)
498 tst r3, #PSR_T_BIT @ Thumb mode?
499 itet eq @ explicit IT needed for the 1f label
500 subeq r4, r2, #4 @ ARM instr at LR - 4
501 subne r4, r2, #2 @ Thumb instr at LR - 2
502 1: ldreqt r0, [r4]
503 #ifdef CONFIG_CPU_ENDIAN_BE8
504 reveq r0, r0 @ little endian instruction
505 #endif
506 beq call_fpe
507 @ Thumb instruction
508 #if __LINUX_ARM_ARCH__ >= 7
509 2:
510 ARM( ldrht r5, [r4], #2 )
511 THUMB( ldrht r5, [r4] )
512 THUMB( add r4, r4, #2 )
513 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
514 cmp r0, #0xe800 @ 32bit instruction if xx != 0
515 blo __und_usr_unknown
516 3: ldrht r0, [r4]
517 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
518 orr r0, r0, r5, lsl #16
519 #else
520 b __und_usr_unknown
521 #endif
522 UNWIND(.fnend )
523 ENDPROC(__und_usr)
525 @
526 @ fallthrough to call_fpe
527 @
529 /*
530 * The out of line fixup for the ldrt above.
531 */
532 .pushsection .fixup, "ax"
533 4: mov pc, r9
534 .popsection
535 .pushsection __ex_table,"a"
536 .long 1b, 4b
537 #if __LINUX_ARM_ARCH__ >= 7
538 .long 2b, 4b
539 .long 3b, 4b
540 #endif
541 .popsection
543 /*
544 * Check whether the instruction is a co-processor instruction.
545 * If yes, we need to call the relevant co-processor handler.
546 *
547 * Note that we don't do a full check here for the co-processor
548 * instructions; all instructions with bit 27 set are well
549 * defined. The only instructions that should fault are the
550 * co-processor instructions. However, we have to watch out
551 * for the ARM6/ARM7 SWI bug.
552 *
553 * NEON is a special case that has to be handled here. Not all
554 * NEON instructions are co-processor instructions, so we have
555 * to make a special case of checking for them. Plus, there's
556 * five groups of them, so we have a table of mask/opcode pairs
557 * to check against, and if any match then we branch off into the
558 * NEON handler code.
559 *
560 * Emulators may wish to make use of the following registers:
561 * r0 = instruction opcode.
562 * r2 = PC+4
563 * r9 = normal "successful" return address
564 * r10 = this threads thread_info structure.
565 * lr = unrecognised instruction return address
566 */
567 @
568 @ Fall-through from Thumb-2 __und_usr
569 @
570 #ifdef CONFIG_NEON
571 adr r6, .LCneon_thumb_opcodes
572 b 2f
573 #endif
574 call_fpe:
575 #ifdef CONFIG_NEON
576 adr r6, .LCneon_arm_opcodes
577 2:
578 ldr r7, [r6], #4 @ mask value
579 cmp r7, #0 @ end mask?
580 beq 1f
581 and r8, r0, r7
582 ldr r7, [r6], #4 @ opcode bits matching in mask
583 cmp r8, r7 @ NEON instruction?
584 bne 2b
585 get_thread_info r10
586 mov r7, #1
587 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
588 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
589 b do_vfp @ let VFP handler handle this
590 1:
591 #endif
592 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
593 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
594 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
595 and r8, r0, #0x0f000000 @ mask out op-code bits
596 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
597 #endif
598 moveq pc, lr
599 get_thread_info r10 @ get current thread
600 and r8, r0, #0x00000f00 @ mask out CP number
601 THUMB( lsr r8, r8, #8 )
602 mov r7, #1
603 add r6, r10, #TI_USED_CP
604 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
605 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
606 #ifdef CONFIG_IWMMXT
607 @ Test if we need to give access to iWMMXt coprocessors
608 ldr r5, [r10, #TI_FLAGS]
609 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
610 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
611 bcs iwmmxt_task_enable
612 #endif
613 ARM( add pc, pc, r8, lsr #6 )
614 THUMB( lsl r8, r8, #2 )
615 THUMB( add pc, r8 )
616 nop
618 movw_pc lr @ CP#0
619 W(b) do_fpe @ CP#1 (FPE)
620 W(b) do_fpe @ CP#2 (FPE)
621 movw_pc lr @ CP#3
622 #ifdef CONFIG_CRUNCH
623 b crunch_task_enable @ CP#4 (MaverickCrunch)
624 b crunch_task_enable @ CP#5 (MaverickCrunch)
625 b crunch_task_enable @ CP#6 (MaverickCrunch)
626 #else
627 movw_pc lr @ CP#4
628 movw_pc lr @ CP#5
629 movw_pc lr @ CP#6
630 #endif
631 movw_pc lr @ CP#7
632 movw_pc lr @ CP#8
633 movw_pc lr @ CP#9
634 #ifdef CONFIG_VFP
635 W(b) do_vfp @ CP#10 (VFP)
636 W(b) do_vfp @ CP#11 (VFP)
637 #else
638 movw_pc lr @ CP#10 (VFP)
639 movw_pc lr @ CP#11 (VFP)
640 #endif
641 movw_pc lr @ CP#12
642 movw_pc lr @ CP#13
643 movw_pc lr @ CP#14 (Debug)
644 movw_pc lr @ CP#15 (Control)
646 #ifdef CONFIG_NEON
647 .align 6
649 .LCneon_arm_opcodes:
650 .word 0xfe000000 @ mask
651 .word 0xf2000000 @ opcode
653 .word 0xff100000 @ mask
654 .word 0xf4000000 @ opcode
656 .word 0x00000000 @ mask
657 .word 0x00000000 @ opcode
659 .LCneon_thumb_opcodes:
660 .word 0xef000000 @ mask
661 .word 0xef000000 @ opcode
663 .word 0xff100000 @ mask
664 .word 0xf9000000 @ opcode
666 .word 0x00000000 @ mask
667 .word 0x00000000 @ opcode
668 #endif
670 do_fpe:
671 enable_irq
672 ldr r4, .LCfp
673 add r10, r10, #TI_FPSTATE @ r10 = workspace
674 ldr pc, [r4] @ Call FP module USR entry point
676 /*
677 * The FP module is called with these registers set:
678 * r0 = instruction
679 * r2 = PC+4
680 * r9 = normal "successful" return address
681 * r10 = FP workspace
682 * lr = unrecognised FP instruction return address
683 */
685 .pushsection .data
686 ENTRY(fp_enter)
687 .word no_fp
688 .popsection
690 ENTRY(no_fp)
691 mov pc, lr
692 ENDPROC(no_fp)
694 __und_usr_unknown:
695 enable_irq
696 mov r0, sp
697 adr lr, BSYM(ret_from_exception)
698 b do_undefinstr
699 ENDPROC(__und_usr_unknown)
701 .align 5
702 __pabt_usr:
703 usr_entry
705 mov r0, r2 @ pass address of aborted instruction.
706 #ifdef MULTI_PABORT
707 ldr r4, .LCprocfns
708 mov lr, pc
709 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
710 #else
711 bl CPU_PABORT_HANDLER
712 #endif
713 enable_irq @ Enable interrupts
714 mov r2, sp @ regs
715 bl do_PrefetchAbort @ call abort handler
716 UNWIND(.fnend )
717 /* fall through */
718 /*
719 * This is the return code to user mode for abort handlers
720 */
721 ENTRY(ret_from_exception)
722 UNWIND(.fnstart )
723 UNWIND(.cantunwind )
724 get_thread_info tsk
725 mov why, #0
726 b ret_to_user
727 UNWIND(.fnend )
728 ENDPROC(__pabt_usr)
729 ENDPROC(ret_from_exception)
731 /*
732 * Register switch for ARMv3 and ARMv4 processors
733 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
734 * previous and next are guaranteed not to be the same.
735 */
736 ENTRY(__switch_to)
737 UNWIND(.fnstart )
738 UNWIND(.cantunwind )
739 add ip, r1, #TI_CPU_SAVE
740 ldr r3, [r2, #TI_TP_VALUE]
741 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
742 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
743 THUMB( str sp, [ip], #4 )
744 THUMB( str lr, [ip], #4 )
745 #ifdef CONFIG_CPU_USE_DOMAINS
746 ldr r6, [r2, #TI_CPU_DOMAIN]
747 #endif
748 set_tls r3, r4, r5
749 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
750 ldr r7, [r2, #TI_TASK]
751 ldr r8, =__stack_chk_guard
752 ldr r7, [r7, #TSK_STACK_CANARY]
753 #endif
754 #ifdef CONFIG_CPU_USE_DOMAINS
755 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
756 #endif
757 mov r5, r0
758 add r4, r2, #TI_CPU_SAVE
759 ldr r0, =thread_notify_head
760 mov r1, #THREAD_NOTIFY_SWITCH
761 bl atomic_notifier_call_chain
762 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
763 str r7, [r8]
764 #endif
765 THUMB( mov ip, r4 )
766 mov r0, r5
767 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
768 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
769 THUMB( ldr sp, [ip], #4 )
770 THUMB( ldr pc, [ip] )
771 UNWIND(.fnend )
772 ENDPROC(__switch_to)
774 __INIT
776 /*
777 * User helpers.
778 *
779 * These are segment of kernel provided user code reachable from user space
780 * at a fixed address in kernel memory. This is used to provide user space
781 * with some operations which require kernel help because of unimplemented
782 * native feature and/or instructions in many ARM CPUs. The idea is for
783 * this code to be executed directly in user mode for best efficiency but
784 * which is too intimate with the kernel counter part to be left to user
785 * libraries. In fact this code might even differ from one CPU to another
786 * depending on the available instruction set and restrictions like on
787 * SMP systems. In other words, the kernel reserves the right to change
788 * this code as needed without warning. Only the entry points and their
789 * results are guaranteed to be stable.
790 *
791 * Each segment is 32-byte aligned and will be moved to the top of the high
792 * vector page. New segments (if ever needed) must be added in front of
793 * existing ones. This mechanism should be used only for things that are
794 * really small and justified, and not be abused freely.
795 *
796 * User space is expected to implement those things inline when optimizing
797 * for a processor that has the necessary native support, but only if such
798 * resulting binaries are already to be incompatible with earlier ARM
799 * processors due to the use of unsupported instructions other than what
800 * is provided here. In other words don't make binaries unable to run on
801 * earlier processors just for the sake of not using these kernel helpers
802 * if your compiled code is not going to use the new instructions for other
803 * purpose.
804 */
805 THUMB( .arm )
807 .macro usr_ret, reg
808 #ifdef CONFIG_ARM_THUMB
809 bx \reg
810 #else
811 mov pc, \reg
812 #endif
813 .endm
815 .align 5
816 .globl __kuser_helper_start
817 __kuser_helper_start:
819 /*
820 * Reference prototype:
821 *
822 * void __kernel_memory_barrier(void)
823 *
824 * Input:
825 *
826 * lr = return address
827 *
828 * Output:
829 *
830 * none
831 *
832 * Clobbered:
833 *
834 * none
835 *
836 * Definition and user space usage example:
837 *
838 * typedef void (__kernel_dmb_t)(void);
839 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
840 *
841 * Apply any needed memory barrier to preserve consistency with data modified
842 * manually and __kuser_cmpxchg usage.
843 *
844 * This could be used as follows:
845 *
846 * #define __kernel_dmb() \
847 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
848 * : : : "r0", "lr","cc" )
849 */
851 __kuser_memory_barrier: @ 0xffff0fa0
852 smp_dmb
853 usr_ret lr
855 .align 5
857 /*
858 * Reference prototype:
859 *
860 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
861 *
862 * Input:
863 *
864 * r0 = oldval
865 * r1 = newval
866 * r2 = ptr
867 * lr = return address
868 *
869 * Output:
870 *
871 * r0 = returned value (zero or non-zero)
872 * C flag = set if r0 == 0, clear if r0 != 0
873 *
874 * Clobbered:
875 *
876 * r3, ip, flags
877 *
878 * Definition and user space usage example:
879 *
880 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
881 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
882 *
883 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
884 * Return zero if *ptr was changed or non-zero if no exchange happened.
885 * The C flag is also set if *ptr was changed to allow for assembly
886 * optimization in the calling code.
887 *
888 * Notes:
889 *
890 * - This routine already includes memory barriers as needed.
891 *
892 * For example, a user space atomic_add implementation could look like this:
893 *
894 * #define atomic_add(ptr, val) \
895 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
896 * register unsigned int __result asm("r1"); \
897 * asm volatile ( \
898 * "1: @ atomic_add\n\t" \
899 * "ldr r0, [r2]\n\t" \
900 * "mov r3, #0xffff0fff\n\t" \
901 * "add lr, pc, #4\n\t" \
902 * "add r1, r0, %2\n\t" \
903 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
904 * "bcc 1b" \
905 * : "=&r" (__result) \
906 * : "r" (__ptr), "rIL" (val) \
907 * : "r0","r3","ip","lr","cc","memory" ); \
908 * __result; })
909 */
911 __kuser_cmpxchg: @ 0xffff0fc0
913 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
915 /*
916 * Poor you. No fast solution possible...
917 * The kernel itself must perform the operation.
918 * A special ghost syscall is used for that (see traps.c).
919 */
920 stmfd sp!, {r7, lr}
921 ldr r7, =1f @ it's 20 bits
922 swi __ARM_NR_cmpxchg
923 ldmfd sp!, {r7, pc}
924 1: .word __ARM_NR_cmpxchg
926 #elif __LINUX_ARM_ARCH__ < 6
928 #ifdef CONFIG_MMU
930 /*
931 * The only thing that can break atomicity in this cmpxchg
932 * implementation is either an IRQ or a data abort exception
933 * causing another process/thread to be scheduled in the middle
934 * of the critical sequence. To prevent this, code is added to
935 * the IRQ and data abort exception handlers to set the pc back
936 * to the beginning of the critical section if it is found to be
937 * within that critical section (see kuser_cmpxchg_fixup).
938 */
939 1: ldr r3, [r2] @ load current val
940 subs r3, r3, r0 @ compare with oldval
941 2: streq r1, [r2] @ store newval if eq
942 rsbs r0, r3, #0 @ set return val and C flag
943 usr_ret lr
945 .text
946 kuser_cmpxchg_fixup:
947 @ Called from kuser_cmpxchg_check macro.
948 @ r2 = address of interrupted insn (must be preserved).
949 @ sp = saved regs. r7 and r8 are clobbered.
950 @ 1b = first critical insn, 2b = last critical insn.
951 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
952 mov r7, #0xffff0fff
953 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
954 subs r8, r2, r7
955 rsbcss r8, r8, #(2b - 1b)
956 strcs r7, [sp, #S_PC]
957 mov pc, lr
958 .previous
960 #else
961 #warning "NPTL on non MMU needs fixing"
962 mov r0, #-1
963 adds r0, r0, #0
964 usr_ret lr
965 #endif
967 #else
969 smp_dmb
970 1: ldrex r3, [r2]
971 subs r3, r3, r0
972 strexeq r3, r1, [r2]
973 teqeq r3, #1
974 beq 1b
975 rsbs r0, r3, #0
976 /* beware -- each __kuser slot must be 8 instructions max */
977 ALT_SMP(b __kuser_memory_barrier)
978 ALT_UP(usr_ret lr)
980 #endif
982 .align 5
984 /*
985 * Reference prototype:
986 *
987 * int __kernel_get_tls(void)
988 *
989 * Input:
990 *
991 * lr = return address
992 *
993 * Output:
994 *
995 * r0 = TLS value
996 *
997 * Clobbered:
998 *
999 * none
1000 *
1001 * Definition and user space usage example:
1002 *
1003 * typedef int (__kernel_get_tls_t)(void);
1004 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
1005 *
1006 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
1007 *
1008 * This could be used as follows:
1009 *
1010 * #define __kernel_get_tls() \
1011 * ({ register unsigned int __val asm("r0"); \
1012 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1013 * : "=r" (__val) : : "lr","cc" ); \
1014 * __val; })
1015 */
1017 __kuser_get_tls: @ 0xffff0fe0
1018 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1019 usr_ret lr
1020 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1021 .rep 4
1022 .word 0 @ 0xffff0ff0 software TLS value, then
1023 .endr @ pad up to __kuser_helper_version
1025 /*
1026 * Reference declaration:
1027 *
1028 * extern unsigned int __kernel_helper_version;
1029 *
1030 * Definition and user space usage example:
1031 *
1032 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1033 *
1034 * User space may read this to determine the curent number of helpers
1035 * available.
1036 */
1038 __kuser_helper_version: @ 0xffff0ffc
1039 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1041 .globl __kuser_helper_end
1042 __kuser_helper_end:
1044 THUMB( .thumb )
1046 /*
1047 * Vector stubs.
1048 *
1049 * This code is copied to 0xffff0200 so we can use branches in the
1050 * vectors, rather than ldr's. Note that this code must not
1051 * exceed 0x300 bytes.
1052 *
1053 * Common stub entry macro:
1054 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1055 *
1056 * SP points to a minimal amount of processor-private memory, the address
1057 * of which is copied into r0 for the mode specific abort handler.
1058 */
1059 .macro vector_stub, name, mode, correction=0
1060 .align 5
1062 vector_\name:
1063 .if \correction
1064 sub lr, lr, #\correction
1065 .endif
1067 @
1068 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1069 @ (parent CPSR)
1070 @
1071 stmia sp, {r0, lr} @ save r0, lr
1072 mrs lr, spsr
1073 str lr, [sp, #8] @ save spsr
1075 @
1076 @ Prepare for SVC32 mode. IRQs remain disabled.
1077 @
1078 mrs r0, cpsr
1079 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1080 msr spsr_cxsf, r0
1082 @
1083 @ the branch table must immediately follow this code
1084 @
1085 and lr, lr, #0x0f
1086 THUMB( adr r0, 1f )
1087 THUMB( ldr lr, [r0, lr, lsl #2] )
1088 mov r0, sp
1089 ARM( ldr lr, [pc, lr, lsl #2] )
1090 movs pc, lr @ branch to handler in SVC mode
1091 ENDPROC(vector_\name)
1093 .align 2
1094 @ handler addresses follow this label
1095 1:
1096 .endm
1098 .globl __stubs_start
1099 __stubs_start:
1100 /*
1101 * Interrupt dispatcher
1102 */
1103 vector_stub irq, IRQ_MODE, 4
1105 .long __irq_usr @ 0 (USR_26 / USR_32)
1106 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1107 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1108 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1109 .long __irq_invalid @ 4
1110 .long __irq_invalid @ 5
1111 .long __irq_invalid @ 6
1112 .long __irq_invalid @ 7
1113 .long __irq_invalid @ 8
1114 .long __irq_invalid @ 9
1115 .long __irq_invalid @ a
1116 .long __irq_invalid @ b
1117 .long __irq_invalid @ c
1118 .long __irq_invalid @ d
1119 .long __irq_invalid @ e
1120 .long __irq_invalid @ f
1122 /*
1123 * Data abort dispatcher
1124 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1125 */
1126 vector_stub dabt, ABT_MODE, 8
1128 .long __dabt_usr @ 0 (USR_26 / USR_32)
1129 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1130 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1131 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1132 .long __dabt_invalid @ 4
1133 .long __dabt_invalid @ 5
1134 .long __dabt_invalid @ 6
1135 .long __dabt_invalid @ 7
1136 .long __dabt_invalid @ 8
1137 .long __dabt_invalid @ 9
1138 .long __dabt_invalid @ a
1139 .long __dabt_invalid @ b
1140 .long __dabt_invalid @ c
1141 .long __dabt_invalid @ d
1142 .long __dabt_invalid @ e
1143 .long __dabt_invalid @ f
1145 /*
1146 * Prefetch abort dispatcher
1147 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1148 */
1149 vector_stub pabt, ABT_MODE, 4
1151 .long __pabt_usr @ 0 (USR_26 / USR_32)
1152 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1153 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1154 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1155 .long __pabt_invalid @ 4
1156 .long __pabt_invalid @ 5
1157 .long __pabt_invalid @ 6
1158 .long __pabt_invalid @ 7
1159 .long __pabt_invalid @ 8
1160 .long __pabt_invalid @ 9
1161 .long __pabt_invalid @ a
1162 .long __pabt_invalid @ b
1163 .long __pabt_invalid @ c
1164 .long __pabt_invalid @ d
1165 .long __pabt_invalid @ e
1166 .long __pabt_invalid @ f
1168 /*
1169 * Undef instr entry dispatcher
1170 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1171 */
1172 vector_stub und, UND_MODE
1174 .long __und_usr @ 0 (USR_26 / USR_32)
1175 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1176 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1177 .long __und_svc @ 3 (SVC_26 / SVC_32)
1178 .long __und_invalid @ 4
1179 .long __und_invalid @ 5
1180 .long __und_invalid @ 6
1181 .long __und_invalid @ 7
1182 .long __und_invalid @ 8
1183 .long __und_invalid @ 9
1184 .long __und_invalid @ a
1185 .long __und_invalid @ b
1186 .long __und_invalid @ c
1187 .long __und_invalid @ d
1188 .long __und_invalid @ e
1189 .long __und_invalid @ f
1191 .align 5
1193 /*=============================================================================
1194 * Undefined FIQs
1195 *-----------------------------------------------------------------------------
1196 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1197 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1198 * Basically to switch modes, we *HAVE* to clobber one register... brain
1199 * damage alert! I don't think that we can execute any code in here in any
1200 * other mode than FIQ... Ok you can switch to another mode, but you can't
1201 * get out of that mode without clobbering one register.
1202 */
1203 vector_fiq:
1204 disable_fiq
1205 subs pc, lr, #4
1207 /*=============================================================================
1208 * Address exception handler
1209 *-----------------------------------------------------------------------------
1210 * These aren't too critical.
1211 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1212 */
1214 vector_addrexcptn:
1215 b vector_addrexcptn
1217 /*
1218 * We group all the following data together to optimise
1219 * for CPUs with separate I & D caches.
1220 */
1221 .align 5
1223 .LCvswi:
1224 .word vector_swi
1226 .globl __stubs_end
1227 __stubs_end:
1229 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1231 .globl __vectors_start
1232 __vectors_start:
1233 ARM( swi SYS_ERROR0 )
1234 THUMB( svc #0 )
1235 THUMB( nop )
1236 W(b) vector_und + stubs_offset
1237 W(ldr) pc, .LCvswi + stubs_offset
1238 W(b) vector_pabt + stubs_offset
1239 W(b) vector_dabt + stubs_offset
1240 W(b) vector_addrexcptn + stubs_offset
1241 W(b) vector_irq + stubs_offset
1242 W(b) vector_fiq + stubs_offset
1244 .globl __vectors_end
1245 __vectors_end:
1247 .data
1249 .globl cr_alignment
1250 .globl cr_no_alignment
1251 cr_alignment:
1252 .space 4
1253 cr_no_alignment:
1254 .space 4
1256 #ifdef CONFIG_MULTI_IRQ_HANDLER
1257 .globl handle_arch_irq
1258 handle_arch_irq:
1259 .space 4
1260 #endif