drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25
  26 #define RADEON_IDLE_LOOP_MS 100
  27 #define RADEON_RECLOCK_DELAY_MS 200
  28
  29 static void radeon_pm_check_limits(struct radeon_device *rdev);
  30 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev);
  31 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  32 static void radeon_pm_reclock_work_handler(struct work_struct *work);
  33 static void radeon_pm_idle_work_handler(struct work_struct *work);
  34 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  35
  36 static const char *pm_state_names[4] = {
  37         "PM_STATE_DISABLED",
  38         "PM_STATE_MINIMUM",
  39         "PM_STATE_PAUSED",
  40         "PM_STATE_ACTIVE"
  41 };
  42
  43 static const char *pm_state_types[5] = {
  44         "Default",
  45         "Powersave",
  46         "Battery",
  47         "Balanced",
  48         "Performance",
  49 };
  50
  51 static void radeon_print_power_mode_info(struct radeon_device *rdev)
  52 {
  53         int i, j;
  54         bool is_default;
  55
  56         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
  57         for (i = 0; i < rdev->pm.num_power_states; i++) {
  58                 if (rdev->pm.default_power_state == &rdev->pm.power_state[i])
  59                         is_default = true;
  60                 else
  61                         is_default = false;
  62                 DRM_INFO("State %d %s %s\n", i,
  63                          pm_state_types[rdev->pm.power_state[i].type],
  64                          is_default ? "(default)" : "");
  65                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
  66                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
  67                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
  68                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
  69                         if (rdev->flags & RADEON_IS_IGP)
  70                                 DRM_INFO("\t\t%d engine: %d\n",
  71                                          j,
  72                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
  73                         else
  74                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
  75                                          j,
  76                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
  77                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
  78                 }
  79         }
  80 }
  81
  82 static struct radeon_power_state * radeon_pick_power_state(struct radeon_device *rdev,
  83                                                            enum radeon_pm_state_type type)
  84 {
  85         int i;
  86         struct radeon_power_state *power_state = NULL;
  87
  88         switch (type) {
  89         case POWER_STATE_TYPE_DEFAULT:
  90         default:
  91                 return rdev->pm.default_power_state;
  92         case POWER_STATE_TYPE_POWERSAVE:
  93                 for (i = 0; i < rdev->pm.num_power_states; i++) {
  94                         if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) {
  95                                 power_state = &rdev->pm.power_state[i];
  96                                 break;
  97                         }
  98                 }
  99                 if (power_state == NULL) {
 100                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 101                                 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) {
 102                                         power_state = &rdev->pm.power_state[i];
 103                                         break;
 104                                 }
 105                         }
 106                 }
 107                 break;
 108         case POWER_STATE_TYPE_BATTERY:
 109                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 110                         if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY) {
 111                                 power_state = &rdev->pm.power_state[i];
 112                                 break;
 113                         }
 114                 }
 115                 if (power_state == NULL) {
 116                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 117                                 if (rdev->pm.power_state[i].type == POWER_STATE_TYPE_POWERSAVE) {
 118                                         power_state = &rdev->pm.power_state[i];
 119                                         break;
 120                                 }
 121                         }
 122                 }
 123                 break;
 124         case POWER_STATE_TYPE_BALANCED:
 125         case POWER_STATE_TYPE_PERFORMANCE:
 126                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 127                         if (rdev->pm.power_state[i].type == type) {
 128                                 power_state = &rdev->pm.power_state[i];
 129                                 break;
 130                         }
 131                 }
 132                 break;
 133         }
 134
 135         if (power_state == NULL)
 136                 return rdev->pm.default_power_state;
 137
 138         return power_state;
 139 }
 140
 141 static struct radeon_pm_clock_info * radeon_pick_clock_mode(struct radeon_device *rdev,
 142                                                             struct radeon_power_state *power_state,
 143                                                             enum radeon_pm_clock_mode_type type)
 144 {
 145         switch (type) {
 146         case POWER_MODE_TYPE_DEFAULT:
 147         default:
 148                 return power_state->default_clock_mode;
 149         case POWER_MODE_TYPE_LOW:
 150                 return &power_state->clock_info[0];
 151         case POWER_MODE_TYPE_MID:
 152                 if (power_state->num_clock_modes > 2)
 153                         return &power_state->clock_info[1];
 154                 else
 155                         return &power_state->clock_info[0];
 156                 break;
 157         case POWER_MODE_TYPE_HIGH:
 158                 return &power_state->clock_info[power_state->num_clock_modes - 1];
 159         }
 160
 161 }
 162
 163 static void radeon_get_power_state(struct radeon_device *rdev,
 164                                    enum radeon_pm_action action)
 165 {
 166         switch (action) {
 167         case PM_ACTION_NONE:
 168         default:
 169                 rdev->pm.requested_power_state = rdev->pm.current_power_state;
 170                 rdev->pm.requested_power_state->requested_clock_mode =
 171                         rdev->pm.requested_power_state->current_clock_mode;
 172                 break;
 173         case PM_ACTION_MINIMUM:
 174                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_BATTERY);
 175                 rdev->pm.requested_power_state->requested_clock_mode =
 176                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_LOW);
 177                 break;
 178         case PM_ACTION_DOWNCLOCK:
 179                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_POWERSAVE);
 180                 rdev->pm.requested_power_state->requested_clock_mode =
 181                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_MID);
 182                 break;
 183         case PM_ACTION_UPCLOCK:
 184                 rdev->pm.requested_power_state = radeon_pick_power_state(rdev, POWER_STATE_TYPE_DEFAULT);
 185                 rdev->pm.requested_power_state->requested_clock_mode =
 186                         radeon_pick_clock_mode(rdev, rdev->pm.requested_power_state, POWER_MODE_TYPE_HIGH);
 187                 break;
 188         }
 189 }
 190
 191 static void radeon_set_power_state(struct radeon_device *rdev)
 192 {
 193         if (rdev->pm.requested_power_state == rdev->pm.current_power_state)
 194                 return;
 195         /* set pcie lanes */
 196         /* set voltage */
 197         /* set engine clock */
 198         radeon_set_engine_clock(rdev, rdev->pm.requested_power_state->requested_clock_mode->sclk);
 199         /* set memory clock */
 200
 201         rdev->pm.current_power_state = rdev->pm.requested_power_state;
 202 }
 203
 204 int radeon_pm_init(struct radeon_device *rdev)
 205 {
 206         rdev->pm.state = PM_STATE_DISABLED;
 207         rdev->pm.planned_action = PM_ACTION_NONE;
 208         rdev->pm.downclocked = false;
 209         rdev->pm.vblank_callback = false;
 210
 211         if (rdev->bios) {
 212                 if (rdev->is_atom_bios)
 213                         radeon_atombios_get_power_modes(rdev);
 214                 else
 215                         radeon_combios_get_power_modes(rdev);
 216                 radeon_print_power_mode_info(rdev);
 217         }
 218
 219         radeon_pm_check_limits(rdev);
 220
 221         if (radeon_debugfs_pm_init(rdev)) {
 222                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 223         }
 224
 225         INIT_WORK(&rdev->pm.reclock_work, radeon_pm_reclock_work_handler);
 226         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 227
 228         if (radeon_dynpm != -1 && radeon_dynpm) {
 229                 rdev->pm.state = PM_STATE_PAUSED;
 230                 DRM_INFO("radeon: dynamic power management enabled\n");
 231         }
 232
 233         DRM_INFO("radeon: power management initialized\n");
 234
 235         return 0;
 236 }
 237
 238 static void radeon_pm_check_limits(struct radeon_device *rdev)
 239 {
 240         rdev->pm.min_gpu_engine_clock = rdev->clock.default_sclk - 5000;
 241         rdev->pm.min_gpu_memory_clock = rdev->clock.default_mclk - 5000;
 242 }
 243
 244 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 245 {
 246         struct drm_device *ddev = rdev->ddev;
 247         struct drm_connector *connector;
 248         struct radeon_crtc *radeon_crtc;
 249         int count = 0;
 250
 251         if (rdev->pm.state == PM_STATE_DISABLED)
 252                 return;
 253
 254         mutex_lock(&rdev->pm.mutex);
 255
 256         rdev->pm.active_crtcs = 0;
 257         list_for_each_entry(connector,
 258                 &ddev->mode_config.connector_list, head) {
 259                 if (connector->encoder &&
 260                         connector->dpms != DRM_MODE_DPMS_OFF) {
 261                         radeon_crtc = to_radeon_crtc(connector->encoder->crtc);
 262                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 263                         ++count;
 264                 }
 265         }
 266
 267         if (count > 1) {
 268                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 269                         wait_queue_head_t wait;
 270                         init_waitqueue_head(&wait);
 271
 272                         cancel_delayed_work(&rdev->pm.idle_work);
 273
 274                         rdev->pm.state = PM_STATE_PAUSED;
 275                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 276                         rdev->pm.vblank_callback = true;
 277
 278                         mutex_unlock(&rdev->pm.mutex);
 279
 280                         wait_event_timeout(wait, !rdev->pm.downclocked,
 281                                 msecs_to_jiffies(300));
 282                         if (!rdev->pm.downclocked)
 283                                 radeon_pm_set_clocks(rdev);
 284
 285                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 286                 } else {
 287                         mutex_unlock(&rdev->pm.mutex);
 288                 }
 289         } else if (count == 1) {
 290                 rdev->pm.min_mode_engine_clock = rdev->pm.min_gpu_engine_clock;
 291                 rdev->pm.min_mode_memory_clock = rdev->pm.min_gpu_memory_clock;
 292                 /* TODO: Increase clocks if needed for current mode */
 293
 294                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 295                         rdev->pm.state = PM_STATE_ACTIVE;
 296                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 297                         radeon_pm_set_clocks_locked(rdev);
 298
 299                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 300                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 301                 }
 302                 else if (rdev->pm.state == PM_STATE_PAUSED) {
 303                         rdev->pm.state = PM_STATE_ACTIVE;
 304                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 305                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 306                         DRM_DEBUG("radeon: dynamic power management activated\n");
 307                 }
 308
 309                 mutex_unlock(&rdev->pm.mutex);
 310         }
 311         else { /* count == 0 */
 312                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 313                         cancel_delayed_work(&rdev->pm.idle_work);
 314
 315                         rdev->pm.state = PM_STATE_MINIMUM;
 316                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 317                         radeon_pm_set_clocks_locked(rdev);
 318                 }
 319
 320                 mutex_unlock(&rdev->pm.mutex);
 321         }
 322 }
 323
 324 static void radeon_pm_set_clocks_locked(struct radeon_device *rdev)
 325 {
 326         /*radeon_fence_wait_last(rdev);*/
 327         switch (rdev->pm.planned_action) {
 328         case PM_ACTION_UPCLOCK:
 329                 radeon_set_engine_clock(rdev, rdev->clock.default_sclk);
 330                 rdev->pm.downclocked = false;
 331                 break;
 332         case PM_ACTION_DOWNCLOCK:
 333                 radeon_set_engine_clock(rdev,
 334                         rdev->pm.min_mode_engine_clock);
 335                 rdev->pm.downclocked = true;
 336                 break;
 337         case PM_ACTION_MINIMUM:
 338                 radeon_set_engine_clock(rdev,
 339                         rdev->pm.min_gpu_engine_clock);
 340                 break;
 341         case PM_ACTION_NONE:
 342                 DRM_ERROR("%s: PM_ACTION_NONE\n", __func__);
 343                 break;
 344         }
 345
 346         rdev->pm.planned_action = PM_ACTION_NONE;
 347 }
 348
 349 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 350 {
 351         mutex_lock(&rdev->pm.mutex);
 352         /* new VBLANK irq may come before handling previous one */
 353         if (rdev->pm.vblank_callback) {
 354                 mutex_lock(&rdev->cp.mutex);
 355                 if (rdev->pm.req_vblank & (1 << 0)) {
 356                         rdev->pm.req_vblank &= ~(1 << 0);
 357                         drm_vblank_put(rdev->ddev, 0);
 358                 }
 359                 if (rdev->pm.req_vblank & (1 << 1)) {
 360                         rdev->pm.req_vblank &= ~(1 << 1);
 361                         drm_vblank_put(rdev->ddev, 1);
 362                 }
 363                 rdev->pm.vblank_callback = false;
 364                 radeon_pm_set_clocks_locked(rdev);
 365                 mutex_unlock(&rdev->cp.mutex);
 366         }
 367         mutex_unlock(&rdev->pm.mutex);
 368 }
 369
 370 static void radeon_pm_reclock_work_handler(struct work_struct *work)
 371 {
 372         struct radeon_device *rdev;
 373         rdev = container_of(work, struct radeon_device,
 374                                 pm.reclock_work);
 375         radeon_pm_set_clocks(rdev);
 376 }
 377
 378 static void radeon_pm_idle_work_handler(struct work_struct *work)
 379 {
 380         struct radeon_device *rdev;
 381         rdev = container_of(work, struct radeon_device,
 382                                 pm.idle_work.work);
 383
 384         mutex_lock(&rdev->pm.mutex);
 385         if (rdev->pm.state == PM_STATE_ACTIVE &&
 386                 !rdev->pm.vblank_callback) {
 387                 unsigned long irq_flags;
 388                 int not_processed = 0;
 389
 390                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 391                 if (!list_empty(&rdev->fence_drv.emited)) {
 392                         struct list_head *ptr;
 393                         list_for_each(ptr, &rdev->fence_drv.emited) {
 394                                 /* count up to 3, that's enought info */
 395                                 if (++not_processed >= 3)
 396                                         break;
 397                         }
 398                 }
 399                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 400
 401                 if (not_processed >= 3) { /* should upclock */
 402                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 403                                 rdev->pm.planned_action = PM_ACTION_NONE;
 404                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 405                                 rdev->pm.downclocked) {
 406                                 rdev->pm.planned_action =
 407                                         PM_ACTION_UPCLOCK;
 408                                 rdev->pm.action_timeout = jiffies +
 409                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 410                         }
 411                 } else if (not_processed == 0) { /* should downclock */
 412                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 413                                 rdev->pm.planned_action = PM_ACTION_NONE;
 414                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 415                                 !rdev->pm.downclocked) {
 416                                 rdev->pm.planned_action =
 417                                         PM_ACTION_DOWNCLOCK;
 418                                 rdev->pm.action_timeout = jiffies +
 419                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 420                         }
 421                 }
 422
 423                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 424                         jiffies > rdev->pm.action_timeout) {
 425                         if (rdev->pm.active_crtcs & (1 << 0)) {
 426                                 rdev->pm.req_vblank |= (1 << 0);
 427                                 drm_vblank_get(rdev->ddev, 0);
 428                         }
 429                         if (rdev->pm.active_crtcs & (1 << 1)) {
 430                                 rdev->pm.req_vblank |= (1 << 1);
 431                                 drm_vblank_get(rdev->ddev, 1);
 432                         }
 433                         rdev->pm.vblank_callback = true;
 434                 }
 435         }
 436         mutex_unlock(&rdev->pm.mutex);
 437
 438         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 439                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 440 }
 441
 442 /*
 443  * Debugfs info
 444  */
 445 #if defined(CONFIG_DEBUG_FS)
 446
 447 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 448 {
 449         struct drm_info_node *node = (struct drm_info_node *) m->private;
 450         struct drm_device *dev = node->minor->dev;
 451         struct radeon_device *rdev = dev->dev_private;
 452
 453         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 454         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 455         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 456         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 457         if (rdev->asic->get_memory_clock)
 458                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 459
 460         return 0;
 461 }
 462
 463 static struct drm_info_list radeon_pm_info_list[] = {
 464         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 465 };
 466 #endif
 467
 468 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 469 {
 470 #if defined(CONFIG_DEBUG_FS)
 471         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 472 #else
 473         return 0;
 474 #endif
 475 }