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x86, AMD IOMMU: add map_page and unmap_page
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / amd_iommu.c
blob85704418644ae68fbc8a9fdb41afd3ed8c14df76
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #ifdef CONFIG_IOMMU_API
28 #include <linux/iommu.h>
29 #endif
30 #include <asm/proto.h>
31 #include <asm/iommu.h>
32 #include <asm/gart.h>
33 #include <asm/amd_iommu_types.h>
34 #include <asm/amd_iommu.h>
35
36 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37
38 #define EXIT_LOOP_COUNT 10000000
39
40 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41
42 /* A list of preallocated protection domains */
43 static LIST_HEAD(iommu_pd_list);
44 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45
46 #ifdef CONFIG_IOMMU_API
47 static struct iommu_ops amd_iommu_ops;
48 #endif
49
50 /*
51 * general struct to manage commands send to an IOMMU
52 */
53 struct iommu_cmd {
54 u32 data[4];
55 };
56
57 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
58 struct unity_map_entry *e);
59 static struct dma_ops_domain *find_protection_domain(u16 devid);
60
61
62 #ifdef CONFIG_AMD_IOMMU_STATS
63
64 /*
65 * Initialization code for statistics collection
66 */
67
68 DECLARE_STATS_COUNTER(compl_wait);
69 DECLARE_STATS_COUNTER(cnt_map_single);
70 DECLARE_STATS_COUNTER(cnt_unmap_single);
71 DECLARE_STATS_COUNTER(cnt_map_sg);
72 DECLARE_STATS_COUNTER(cnt_unmap_sg);
73 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
74 DECLARE_STATS_COUNTER(cnt_free_coherent);
75 DECLARE_STATS_COUNTER(cross_page);
76 DECLARE_STATS_COUNTER(domain_flush_single);
77 DECLARE_STATS_COUNTER(domain_flush_all);
78 DECLARE_STATS_COUNTER(alloced_io_mem);
79 DECLARE_STATS_COUNTER(total_map_requests);
80
81 static struct dentry *stats_dir;
82 static struct dentry *de_isolate;
83 static struct dentry *de_fflush;
84
85 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
86 {
87 if (stats_dir == NULL)
88 return;
89
90 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
91 &cnt->value);
92 }
93
94 static void amd_iommu_stats_init(void)
95 {
96 stats_dir = debugfs_create_dir("amd-iommu", NULL);
97 if (stats_dir == NULL)
98 return;
99
100 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
101 (u32 *)&amd_iommu_isolate);
102
103 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
104 (u32 *)&amd_iommu_unmap_flush);
105
106 amd_iommu_stats_add(&compl_wait);
107 amd_iommu_stats_add(&cnt_map_single);
108 amd_iommu_stats_add(&cnt_unmap_single);
109 amd_iommu_stats_add(&cnt_map_sg);
110 amd_iommu_stats_add(&cnt_unmap_sg);
111 amd_iommu_stats_add(&cnt_alloc_coherent);
112 amd_iommu_stats_add(&cnt_free_coherent);
113 amd_iommu_stats_add(&cross_page);
114 amd_iommu_stats_add(&domain_flush_single);
115 amd_iommu_stats_add(&domain_flush_all);
116 amd_iommu_stats_add(&alloced_io_mem);
117 amd_iommu_stats_add(&total_map_requests);
118 }
119
120 #endif
121
122 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
123 static int iommu_has_npcache(struct amd_iommu *iommu)
124 {
125 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
126 }
127
128 /****************************************************************************
129 *
130 * Interrupt handling functions
131 *
132 ****************************************************************************/
133
134 static void iommu_print_event(void *__evt)
135 {
136 u32 *event = __evt;
137 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
138 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
139 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
140 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
141 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
142
143 printk(KERN_ERR "AMD IOMMU: Event logged [");
144
145 switch (type) {
146 case EVENT_TYPE_ILL_DEV:
147 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
148 "address=0x%016llx flags=0x%04x]\n",
149 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
150 address, flags);
151 break;
152 case EVENT_TYPE_IO_FAULT:
153 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
154 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
155 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
156 domid, address, flags);
157 break;
158 case EVENT_TYPE_DEV_TAB_ERR:
159 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
160 "address=0x%016llx flags=0x%04x]\n",
161 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
162 address, flags);
163 break;
164 case EVENT_TYPE_PAGE_TAB_ERR:
165 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
166 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
167 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
168 domid, address, flags);
169 break;
170 case EVENT_TYPE_ILL_CMD:
171 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
172 break;
173 case EVENT_TYPE_CMD_HARD_ERR:
174 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
175 "flags=0x%04x]\n", address, flags);
176 break;
177 case EVENT_TYPE_IOTLB_INV_TO:
178 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
179 "address=0x%016llx]\n",
180 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 address);
182 break;
183 case EVENT_TYPE_INV_DEV_REQ:
184 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
185 "address=0x%016llx flags=0x%04x]\n",
186 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
187 address, flags);
188 break;
189 default:
190 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
191 }
192 }
193
194 static void iommu_poll_events(struct amd_iommu *iommu)
195 {
196 u32 head, tail;
197 unsigned long flags;
198
199 spin_lock_irqsave(&iommu->lock, flags);
200
201 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
202 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
203
204 while (head != tail) {
205 iommu_print_event(iommu->evt_buf + head);
206 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
207 }
208
209 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
210
211 spin_unlock_irqrestore(&iommu->lock, flags);
212 }
213
214 irqreturn_t amd_iommu_int_handler(int irq, void *data)
215 {
216 struct amd_iommu *iommu;
217
218 list_for_each_entry(iommu, &amd_iommu_list, list)
219 iommu_poll_events(iommu);
220
221 return IRQ_HANDLED;
222 }
223
224 /****************************************************************************
225 *
226 * IOMMU command queuing functions
227 *
228 ****************************************************************************/
229
230 /*
231 * Writes the command to the IOMMUs command buffer and informs the
232 * hardware about the new command. Must be called with iommu->lock held.
233 */
234 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
235 {
236 u32 tail, head;
237 u8 *target;
238
239 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
240 target = iommu->cmd_buf + tail;
241 memcpy_toio(target, cmd, sizeof(*cmd));
242 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
243 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
244 if (tail == head)
245 return -ENOMEM;
246 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
247
248 return 0;
249 }
250
251 /*
252 * General queuing function for commands. Takes iommu->lock and calls
253 * __iommu_queue_command().
254 */
255 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
256 {
257 unsigned long flags;
258 int ret;
259
260 spin_lock_irqsave(&iommu->lock, flags);
261 ret = __iommu_queue_command(iommu, cmd);
262 if (!ret)
263 iommu->need_sync = true;
264 spin_unlock_irqrestore(&iommu->lock, flags);
265
266 return ret;
267 }
268
269 /*
270 * This function waits until an IOMMU has completed a completion
271 * wait command
272 */
273 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
274 {
275 int ready = 0;
276 unsigned status = 0;
277 unsigned long i = 0;
278
279 INC_STATS_COUNTER(compl_wait);
280
281 while (!ready && (i < EXIT_LOOP_COUNT)) {
282 ++i;
283 /* wait for the bit to become one */
284 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
285 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
286 }
287
288 /* set bit back to zero */
289 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
290 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
291
292 if (unlikely(i == EXIT_LOOP_COUNT))
293 panic("AMD IOMMU: Completion wait loop failed\n");
294 }
295
296 /*
297 * This function queues a completion wait command into the command
298 * buffer of an IOMMU
299 */
300 static int __iommu_completion_wait(struct amd_iommu *iommu)
301 {
302 struct iommu_cmd cmd;
303
304 memset(&cmd, 0, sizeof(cmd));
305 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
306 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
307
308 return __iommu_queue_command(iommu, &cmd);
309 }
310
311 /*
312 * This function is called whenever we need to ensure that the IOMMU has
313 * completed execution of all commands we sent. It sends a
314 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
315 * us about that by writing a value to a physical address we pass with
316 * the command.
317 */
318 static int iommu_completion_wait(struct amd_iommu *iommu)
319 {
320 int ret = 0;
321 unsigned long flags;
322
323 spin_lock_irqsave(&iommu->lock, flags);
324
325 if (!iommu->need_sync)
326 goto out;
327
328 ret = __iommu_completion_wait(iommu);
329
330 iommu->need_sync = false;
331
332 if (ret)
333 goto out;
334
335 __iommu_wait_for_completion(iommu);
336
337 out:
338 spin_unlock_irqrestore(&iommu->lock, flags);
339
340 return 0;
341 }
342
343 /*
344 * Command send function for invalidating a device table entry
345 */
346 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
347 {
348 struct iommu_cmd cmd;
349 int ret;
350
351 BUG_ON(iommu == NULL);
352
353 memset(&cmd, 0, sizeof(cmd));
354 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
355 cmd.data[0] = devid;
356
357 ret = iommu_queue_command(iommu, &cmd);
358
359 return ret;
360 }
361
362 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
363 u16 domid, int pde, int s)
364 {
365 memset(cmd, 0, sizeof(*cmd));
366 address &= PAGE_MASK;
367 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
368 cmd->data[1] |= domid;
369 cmd->data[2] = lower_32_bits(address);
370 cmd->data[3] = upper_32_bits(address);
371 if (s) /* size bit - we flush more than one 4kb page */
372 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
373 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
374 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
375 }
376
377 /*
378 * Generic command send function for invalidaing TLB entries
379 */
380 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
381 u64 address, u16 domid, int pde, int s)
382 {
383 struct iommu_cmd cmd;
384 int ret;
385
386 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
387
388 ret = iommu_queue_command(iommu, &cmd);
389
390 return ret;
391 }
392
393 /*
394 * TLB invalidation function which is called from the mapping functions.
395 * It invalidates a single PTE if the range to flush is within a single
396 * page. Otherwise it flushes the whole TLB of the IOMMU.
397 */
398 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
399 u64 address, size_t size)
400 {
401 int s = 0;
402 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
403
404 address &= PAGE_MASK;
405
406 if (pages > 1) {
407 /*
408 * If we have to flush more than one page, flush all
409 * TLB entries for this domain
410 */
411 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
412 s = 1;
413 }
414
415 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
416
417 return 0;
418 }
419
420 /* Flush the whole IO/TLB for a given protection domain */
421 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
422 {
423 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
424
425 INC_STATS_COUNTER(domain_flush_single);
426
427 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
428 }
429
430 /*
431 * This function is used to flush the IO/TLB for a given protection domain
432 * on every IOMMU in the system
433 */
434 static void iommu_flush_domain(u16 domid)
435 {
436 unsigned long flags;
437 struct amd_iommu *iommu;
438 struct iommu_cmd cmd;
439
440 INC_STATS_COUNTER(domain_flush_all);
441
442 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
443 domid, 1, 1);
444
445 list_for_each_entry(iommu, &amd_iommu_list, list) {
446 spin_lock_irqsave(&iommu->lock, flags);
447 __iommu_queue_command(iommu, &cmd);
448 __iommu_completion_wait(iommu);
449 __iommu_wait_for_completion(iommu);
450 spin_unlock_irqrestore(&iommu->lock, flags);
451 }
452 }
453
454 /****************************************************************************
455 *
456 * The functions below are used the create the page table mappings for
457 * unity mapped regions.
458 *
459 ****************************************************************************/
460
461 /*
462 * Generic mapping functions. It maps a physical address into a DMA
463 * address space. It allocates the page table pages if necessary.
464 * In the future it can be extended to a generic mapping function
465 * supporting all features of AMD IOMMU page tables like level skipping
466 * and full 64 bit address spaces.
467 */
468 static int iommu_map_page(struct protection_domain *dom,
469 unsigned long bus_addr,
470 unsigned long phys_addr,
471 int prot)
472 {
473 u64 __pte, *pte, *page;
474
475 bus_addr = PAGE_ALIGN(bus_addr);
476 phys_addr = PAGE_ALIGN(phys_addr);
477
478 /* only support 512GB address spaces for now */
479 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
480 return -EINVAL;
481
482 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
483
484 if (!IOMMU_PTE_PRESENT(*pte)) {
485 page = (u64 *)get_zeroed_page(GFP_KERNEL);
486 if (!page)
487 return -ENOMEM;
488 *pte = IOMMU_L2_PDE(virt_to_phys(page));
489 }
490
491 pte = IOMMU_PTE_PAGE(*pte);
492 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
493
494 if (!IOMMU_PTE_PRESENT(*pte)) {
495 page = (u64 *)get_zeroed_page(GFP_KERNEL);
496 if (!page)
497 return -ENOMEM;
498 *pte = IOMMU_L1_PDE(virt_to_phys(page));
499 }
500
501 pte = IOMMU_PTE_PAGE(*pte);
502 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
503
504 if (IOMMU_PTE_PRESENT(*pte))
505 return -EBUSY;
506
507 __pte = phys_addr | IOMMU_PTE_P;
508 if (prot & IOMMU_PROT_IR)
509 __pte |= IOMMU_PTE_IR;
510 if (prot & IOMMU_PROT_IW)
511 __pte |= IOMMU_PTE_IW;
512
513 *pte = __pte;
514
515 return 0;
516 }
517
518 static void iommu_unmap_page(struct protection_domain *dom,
519 unsigned long bus_addr)
520 {
521 u64 *pte;
522
523 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
524
525 if (!IOMMU_PTE_PRESENT(*pte))
526 return;
527
528 pte = IOMMU_PTE_PAGE(*pte);
529 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
530
531 if (!IOMMU_PTE_PRESENT(*pte))
532 return;
533
534 pte = IOMMU_PTE_PAGE(*pte);
535 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
536
537 *pte = 0;
538 }
539
540 /*
541 * This function checks if a specific unity mapping entry is needed for
542 * this specific IOMMU.
543 */
544 static int iommu_for_unity_map(struct amd_iommu *iommu,
545 struct unity_map_entry *entry)
546 {
547 u16 bdf, i;
548
549 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
550 bdf = amd_iommu_alias_table[i];
551 if (amd_iommu_rlookup_table[bdf] == iommu)
552 return 1;
553 }
554
555 return 0;
556 }
557
558 /*
559 * Init the unity mappings for a specific IOMMU in the system
560 *
561 * Basically iterates over all unity mapping entries and applies them to
562 * the default domain DMA of that IOMMU if necessary.
563 */
564 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
565 {
566 struct unity_map_entry *entry;
567 int ret;
568
569 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
570 if (!iommu_for_unity_map(iommu, entry))
571 continue;
572 ret = dma_ops_unity_map(iommu->default_dom, entry);
573 if (ret)
574 return ret;
575 }
576
577 return 0;
578 }
579
580 /*
581 * This function actually applies the mapping to the page table of the
582 * dma_ops domain.
583 */
584 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
585 struct unity_map_entry *e)
586 {
587 u64 addr;
588 int ret;
589
590 for (addr = e->address_start; addr < e->address_end;
591 addr += PAGE_SIZE) {
592 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
593 if (ret)
594 return ret;
595 /*
596 * if unity mapping is in aperture range mark the page
597 * as allocated in the aperture
598 */
599 if (addr < dma_dom->aperture_size)
600 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
601 }
602
603 return 0;
604 }
605
606 /*
607 * Inits the unity mappings required for a specific device
608 */
609 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
610 u16 devid)
611 {
612 struct unity_map_entry *e;
613 int ret;
614
615 list_for_each_entry(e, &amd_iommu_unity_map, list) {
616 if (!(devid >= e->devid_start && devid <= e->devid_end))
617 continue;
618 ret = dma_ops_unity_map(dma_dom, e);
619 if (ret)
620 return ret;
621 }
622
623 return 0;
624 }
625
626 /****************************************************************************
627 *
628 * The next functions belong to the address allocator for the dma_ops
629 * interface functions. They work like the allocators in the other IOMMU
630 * drivers. Its basically a bitmap which marks the allocated pages in
631 * the aperture. Maybe it could be enhanced in the future to a more
632 * efficient allocator.
633 *
634 ****************************************************************************/
635
636 /*
637 * The address allocator core function.
638 *
639 * called with domain->lock held
640 */
641 static unsigned long dma_ops_alloc_addresses(struct device *dev,
642 struct dma_ops_domain *dom,
643 unsigned int pages,
644 unsigned long align_mask,
645 u64 dma_mask)
646 {
647 unsigned long limit;
648 unsigned long address;
649 unsigned long boundary_size;
650
651 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
652 PAGE_SIZE) >> PAGE_SHIFT;
653 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
654 dma_mask >> PAGE_SHIFT);
655
656 if (dom->next_bit >= limit) {
657 dom->next_bit = 0;
658 dom->need_flush = true;
659 }
660
661 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
662 0 , boundary_size, align_mask);
663 if (address == -1) {
664 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
665 0, boundary_size, align_mask);
666 dom->need_flush = true;
667 }
668
669 if (likely(address != -1)) {
670 dom->next_bit = address + pages;
671 address <<= PAGE_SHIFT;
672 } else
673 address = bad_dma_address;
674
675 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
676
677 return address;
678 }
679
680 /*
681 * The address free function.
682 *
683 * called with domain->lock held
684 */
685 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
686 unsigned long address,
687 unsigned int pages)
688 {
689 address >>= PAGE_SHIFT;
690 iommu_area_free(dom->bitmap, address, pages);
691
692 if (address >= dom->next_bit)
693 dom->need_flush = true;
694 }
695
696 /****************************************************************************
697 *
698 * The next functions belong to the domain allocation. A domain is
699 * allocated for every IOMMU as the default domain. If device isolation
700 * is enabled, every device get its own domain. The most important thing
701 * about domains is the page table mapping the DMA address space they
702 * contain.
703 *
704 ****************************************************************************/
705
706 static u16 domain_id_alloc(void)
707 {
708 unsigned long flags;
709 int id;
710
711 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
712 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
713 BUG_ON(id == 0);
714 if (id > 0 && id < MAX_DOMAIN_ID)
715 __set_bit(id, amd_iommu_pd_alloc_bitmap);
716 else
717 id = 0;
718 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
719
720 return id;
721 }
722
723 static void domain_id_free(int id)
724 {
725 unsigned long flags;
726
727 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
728 if (id > 0 && id < MAX_DOMAIN_ID)
729 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
730 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
731 }
732
733 /*
734 * Used to reserve address ranges in the aperture (e.g. for exclusion
735 * ranges.
736 */
737 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
738 unsigned long start_page,
739 unsigned int pages)
740 {
741 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
742
743 if (start_page + pages > last_page)
744 pages = last_page - start_page;
745
746 iommu_area_reserve(dom->bitmap, start_page, pages);
747 }
748
749 static void free_pagetable(struct protection_domain *domain)
750 {
751 int i, j;
752 u64 *p1, *p2, *p3;
753
754 p1 = domain->pt_root;
755
756 if (!p1)
757 return;
758
759 for (i = 0; i < 512; ++i) {
760 if (!IOMMU_PTE_PRESENT(p1[i]))
761 continue;
762
763 p2 = IOMMU_PTE_PAGE(p1[i]);
764 for (j = 0; j < 512; ++j) {
765 if (!IOMMU_PTE_PRESENT(p2[j]))
766 continue;
767 p3 = IOMMU_PTE_PAGE(p2[j]);
768 free_page((unsigned long)p3);
769 }
770
771 free_page((unsigned long)p2);
772 }
773
774 free_page((unsigned long)p1);
775
776 domain->pt_root = NULL;
777 }
778
779 /*
780 * Free a domain, only used if something went wrong in the
781 * allocation path and we need to free an already allocated page table
782 */
783 static void dma_ops_domain_free(struct dma_ops_domain *dom)
784 {
785 if (!dom)
786 return;
787
788 free_pagetable(&dom->domain);
789
790 kfree(dom->pte_pages);
791
792 kfree(dom->bitmap);
793
794 kfree(dom);
795 }
796
797 /*
798 * Allocates a new protection domain usable for the dma_ops functions.
799 * It also intializes the page table and the address allocator data
800 * structures required for the dma_ops interface
801 */
802 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
803 unsigned order)
804 {
805 struct dma_ops_domain *dma_dom;
806 unsigned i, num_pte_pages;
807 u64 *l2_pde;
808 u64 address;
809
810 /*
811 * Currently the DMA aperture must be between 32 MB and 1GB in size
812 */
813 if ((order < 25) || (order > 30))
814 return NULL;
815
816 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
817 if (!dma_dom)
818 return NULL;
819
820 spin_lock_init(&dma_dom->domain.lock);
821
822 dma_dom->domain.id = domain_id_alloc();
823 if (dma_dom->domain.id == 0)
824 goto free_dma_dom;
825 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
826 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
827 dma_dom->domain.flags = PD_DMA_OPS_MASK;
828 dma_dom->domain.priv = dma_dom;
829 if (!dma_dom->domain.pt_root)
830 goto free_dma_dom;
831 dma_dom->aperture_size = (1ULL << order);
832 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
833 GFP_KERNEL);
834 if (!dma_dom->bitmap)
835 goto free_dma_dom;
836 /*
837 * mark the first page as allocated so we never return 0 as
838 * a valid dma-address. So we can use 0 as error value
839 */
840 dma_dom->bitmap[0] = 1;
841 dma_dom->next_bit = 0;
842
843 dma_dom->need_flush = false;
844 dma_dom->target_dev = 0xffff;
845
846 /* Intialize the exclusion range if necessary */
847 if (iommu->exclusion_start &&
848 iommu->exclusion_start < dma_dom->aperture_size) {
849 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
850 int pages = iommu_num_pages(iommu->exclusion_start,
851 iommu->exclusion_length,
852 PAGE_SIZE);
853 dma_ops_reserve_addresses(dma_dom, startpage, pages);
854 }
855
856 /*
857 * At the last step, build the page tables so we don't need to
858 * allocate page table pages in the dma_ops mapping/unmapping
859 * path.
860 */
861 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
862 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
863 GFP_KERNEL);
864 if (!dma_dom->pte_pages)
865 goto free_dma_dom;
866
867 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
868 if (l2_pde == NULL)
869 goto free_dma_dom;
870
871 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
872
873 for (i = 0; i < num_pte_pages; ++i) {
874 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
875 if (!dma_dom->pte_pages[i])
876 goto free_dma_dom;
877 address = virt_to_phys(dma_dom->pte_pages[i]);
878 l2_pde[i] = IOMMU_L1_PDE(address);
879 }
880
881 return dma_dom;
882
883 free_dma_dom:
884 dma_ops_domain_free(dma_dom);
885
886 return NULL;
887 }
888
889 /*
890 * little helper function to check whether a given protection domain is a
891 * dma_ops domain
892 */
893 static bool dma_ops_domain(struct protection_domain *domain)
894 {
895 return domain->flags & PD_DMA_OPS_MASK;
896 }
897
898 /*
899 * Find out the protection domain structure for a given PCI device. This
900 * will give us the pointer to the page table root for example.
901 */
902 static struct protection_domain *domain_for_device(u16 devid)
903 {
904 struct protection_domain *dom;
905 unsigned long flags;
906
907 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
908 dom = amd_iommu_pd_table[devid];
909 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
910
911 return dom;
912 }
913
914 /*
915 * If a device is not yet associated with a domain, this function does
916 * assigns it visible for the hardware
917 */
918 static void attach_device(struct amd_iommu *iommu,
919 struct protection_domain *domain,
920 u16 devid)
921 {
922 unsigned long flags;
923 u64 pte_root = virt_to_phys(domain->pt_root);
924
925 domain->dev_cnt += 1;
926
927 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
928 << DEV_ENTRY_MODE_SHIFT;
929 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
930
931 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
932 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
933 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
934 amd_iommu_dev_table[devid].data[2] = domain->id;
935
936 amd_iommu_pd_table[devid] = domain;
937 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
938
939 iommu_queue_inv_dev_entry(iommu, devid);
940 }
941
942 /*
943 * Removes a device from a protection domain (unlocked)
944 */
945 static void __detach_device(struct protection_domain *domain, u16 devid)
946 {
947
948 /* lock domain */
949 spin_lock(&domain->lock);
950
951 /* remove domain from the lookup table */
952 amd_iommu_pd_table[devid] = NULL;
953
954 /* remove entry from the device table seen by the hardware */
955 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
956 amd_iommu_dev_table[devid].data[1] = 0;
957 amd_iommu_dev_table[devid].data[2] = 0;
958
959 /* decrease reference counter */
960 domain->dev_cnt -= 1;
961
962 /* ready */
963 spin_unlock(&domain->lock);
964 }
965
966 /*
967 * Removes a device from a protection domain (with devtable_lock held)
968 */
969 static void detach_device(struct protection_domain *domain, u16 devid)
970 {
971 unsigned long flags;
972
973 /* lock device table */
974 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
975 __detach_device(domain, devid);
976 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
977 }
978
979 static int device_change_notifier(struct notifier_block *nb,
980 unsigned long action, void *data)
981 {
982 struct device *dev = data;
983 struct pci_dev *pdev = to_pci_dev(dev);
984 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
985 struct protection_domain *domain;
986 struct dma_ops_domain *dma_domain;
987 struct amd_iommu *iommu;
988 int order = amd_iommu_aperture_order;
989 unsigned long flags;
990
991 if (devid > amd_iommu_last_bdf)
992 goto out;
993
994 devid = amd_iommu_alias_table[devid];
995
996 iommu = amd_iommu_rlookup_table[devid];
997 if (iommu == NULL)
998 goto out;
999
1000 domain = domain_for_device(devid);
1001
1002 if (domain && !dma_ops_domain(domain))
1003 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1004 "to a non-dma-ops domain\n", dev_name(dev));
1005
1006 switch (action) {
1007 case BUS_NOTIFY_BOUND_DRIVER:
1008 if (domain)
1009 goto out;
1010 dma_domain = find_protection_domain(devid);
1011 if (!dma_domain)
1012 dma_domain = iommu->default_dom;
1013 attach_device(iommu, &dma_domain->domain, devid);
1014 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1015 "device %s\n", dma_domain->domain.id, dev_name(dev));
1016 break;
1017 case BUS_NOTIFY_UNBIND_DRIVER:
1018 if (!domain)
1019 goto out;
1020 detach_device(domain, devid);
1021 break;
1022 case BUS_NOTIFY_ADD_DEVICE:
1023 /* allocate a protection domain if a device is added */
1024 dma_domain = find_protection_domain(devid);
1025 if (dma_domain)
1026 goto out;
1027 dma_domain = dma_ops_domain_alloc(iommu, order);
1028 if (!dma_domain)
1029 goto out;
1030 dma_domain->target_dev = devid;
1031
1032 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1033 list_add_tail(&dma_domain->list, &iommu_pd_list);
1034 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1035
1036 break;
1037 default:
1038 goto out;
1039 }
1040
1041 iommu_queue_inv_dev_entry(iommu, devid);
1042 iommu_completion_wait(iommu);
1043
1044 out:
1045 return 0;
1046 }
1047
1048 struct notifier_block device_nb = {
1049 .notifier_call = device_change_notifier,
1050 };
1051
1052 /*****************************************************************************
1053 *
1054 * The next functions belong to the dma_ops mapping/unmapping code.
1055 *
1056 *****************************************************************************/
1057
1058 /*
1059 * This function checks if the driver got a valid device from the caller to
1060 * avoid dereferencing invalid pointers.
1061 */
1062 static bool check_device(struct device *dev)
1063 {
1064 if (!dev || !dev->dma_mask)
1065 return false;
1066
1067 return true;
1068 }
1069
1070 /*
1071 * In this function the list of preallocated protection domains is traversed to
1072 * find the domain for a specific device
1073 */
1074 static struct dma_ops_domain *find_protection_domain(u16 devid)
1075 {
1076 struct dma_ops_domain *entry, *ret = NULL;
1077 unsigned long flags;
1078
1079 if (list_empty(&iommu_pd_list))
1080 return NULL;
1081
1082 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1083
1084 list_for_each_entry(entry, &iommu_pd_list, list) {
1085 if (entry->target_dev == devid) {
1086 ret = entry;
1087 break;
1088 }
1089 }
1090
1091 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1092
1093 return ret;
1094 }
1095
1096 /*
1097 * In the dma_ops path we only have the struct device. This function
1098 * finds the corresponding IOMMU, the protection domain and the
1099 * requestor id for a given device.
1100 * If the device is not yet associated with a domain this is also done
1101 * in this function.
1102 */
1103 static int get_device_resources(struct device *dev,
1104 struct amd_iommu **iommu,
1105 struct protection_domain **domain,
1106 u16 *bdf)
1107 {
1108 struct dma_ops_domain *dma_dom;
1109 struct pci_dev *pcidev;
1110 u16 _bdf;
1111
1112 *iommu = NULL;
1113 *domain = NULL;
1114 *bdf = 0xffff;
1115
1116 if (dev->bus != &pci_bus_type)
1117 return 0;
1118
1119 pcidev = to_pci_dev(dev);
1120 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1121
1122 /* device not translated by any IOMMU in the system? */
1123 if (_bdf > amd_iommu_last_bdf)
1124 return 0;
1125
1126 *bdf = amd_iommu_alias_table[_bdf];
1127
1128 *iommu = amd_iommu_rlookup_table[*bdf];
1129 if (*iommu == NULL)
1130 return 0;
1131 *domain = domain_for_device(*bdf);
1132 if (*domain == NULL) {
1133 dma_dom = find_protection_domain(*bdf);
1134 if (!dma_dom)
1135 dma_dom = (*iommu)->default_dom;
1136 *domain = &dma_dom->domain;
1137 attach_device(*iommu, *domain, *bdf);
1138 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1139 "device %s\n", (*domain)->id, dev_name(dev));
1140 }
1141
1142 if (domain_for_device(_bdf) == NULL)
1143 attach_device(*iommu, *domain, _bdf);
1144
1145 return 1;
1146 }
1147
1148 /*
1149 * This is the generic map function. It maps one 4kb page at paddr to
1150 * the given address in the DMA address space for the domain.
1151 */
1152 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1153 struct dma_ops_domain *dom,
1154 unsigned long address,
1155 phys_addr_t paddr,
1156 int direction)
1157 {
1158 u64 *pte, __pte;
1159
1160 WARN_ON(address > dom->aperture_size);
1161
1162 paddr &= PAGE_MASK;
1163
1164 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1165 pte += IOMMU_PTE_L0_INDEX(address);
1166
1167 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1168
1169 if (direction == DMA_TO_DEVICE)
1170 __pte |= IOMMU_PTE_IR;
1171 else if (direction == DMA_FROM_DEVICE)
1172 __pte |= IOMMU_PTE_IW;
1173 else if (direction == DMA_BIDIRECTIONAL)
1174 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1175
1176 WARN_ON(*pte);
1177
1178 *pte = __pte;
1179
1180 return (dma_addr_t)address;
1181 }
1182
1183 /*
1184 * The generic unmapping function for on page in the DMA address space.
1185 */
1186 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1187 struct dma_ops_domain *dom,
1188 unsigned long address)
1189 {
1190 u64 *pte;
1191
1192 if (address >= dom->aperture_size)
1193 return;
1194
1195 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1196
1197 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1198 pte += IOMMU_PTE_L0_INDEX(address);
1199
1200 WARN_ON(!*pte);
1201
1202 *pte = 0ULL;
1203 }
1204
1205 /*
1206 * This function contains common code for mapping of a physically
1207 * contiguous memory region into DMA address space. It is used by all
1208 * mapping functions provided with this IOMMU driver.
1209 * Must be called with the domain lock held.
1210 */
1211 static dma_addr_t __map_single(struct device *dev,
1212 struct amd_iommu *iommu,
1213 struct dma_ops_domain *dma_dom,
1214 phys_addr_t paddr,
1215 size_t size,
1216 int dir,
1217 bool align,
1218 u64 dma_mask)
1219 {
1220 dma_addr_t offset = paddr & ~PAGE_MASK;
1221 dma_addr_t address, start;
1222 unsigned int pages;
1223 unsigned long align_mask = 0;
1224 int i;
1225
1226 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1227 paddr &= PAGE_MASK;
1228
1229 INC_STATS_COUNTER(total_map_requests);
1230
1231 if (pages > 1)
1232 INC_STATS_COUNTER(cross_page);
1233
1234 if (align)
1235 align_mask = (1UL << get_order(size)) - 1;
1236
1237 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1238 dma_mask);
1239 if (unlikely(address == bad_dma_address))
1240 goto out;
1241
1242 start = address;
1243 for (i = 0; i < pages; ++i) {
1244 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1245 paddr += PAGE_SIZE;
1246 start += PAGE_SIZE;
1247 }
1248 address += offset;
1249
1250 ADD_STATS_COUNTER(alloced_io_mem, size);
1251
1252 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1253 iommu_flush_tlb(iommu, dma_dom->domain.id);
1254 dma_dom->need_flush = false;
1255 } else if (unlikely(iommu_has_npcache(iommu)))
1256 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1257
1258 out:
1259 return address;
1260 }
1261
1262 /*
1263 * Does the reverse of the __map_single function. Must be called with
1264 * the domain lock held too
1265 */
1266 static void __unmap_single(struct amd_iommu *iommu,
1267 struct dma_ops_domain *dma_dom,
1268 dma_addr_t dma_addr,
1269 size_t size,
1270 int dir)
1271 {
1272 dma_addr_t i, start;
1273 unsigned int pages;
1274
1275 if ((dma_addr == bad_dma_address) ||
1276 (dma_addr + size > dma_dom->aperture_size))
1277 return;
1278
1279 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1280 dma_addr &= PAGE_MASK;
1281 start = dma_addr;
1282
1283 for (i = 0; i < pages; ++i) {
1284 dma_ops_domain_unmap(iommu, dma_dom, start);
1285 start += PAGE_SIZE;
1286 }
1287
1288 SUB_STATS_COUNTER(alloced_io_mem, size);
1289
1290 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1291
1292 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1293 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1294 dma_dom->need_flush = false;
1295 }
1296 }
1297
1298 /*
1299 * The exported map_single function for dma_ops.
1300 */
1301 static dma_addr_t map_page(struct device *dev, struct page *page,
1302 unsigned long offset, size_t size,
1303 enum dma_data_direction dir,
1304 struct dma_attrs *attrs)
1305 {
1306 unsigned long flags;
1307 struct amd_iommu *iommu;
1308 struct protection_domain *domain;
1309 u16 devid;
1310 dma_addr_t addr;
1311 u64 dma_mask;
1312 phys_addr_t paddr = page_to_phys(page) + offset;
1313
1314 INC_STATS_COUNTER(cnt_map_single);
1315
1316 if (!check_device(dev))
1317 return bad_dma_address;
1318
1319 dma_mask = *dev->dma_mask;
1320
1321 get_device_resources(dev, &iommu, &domain, &devid);
1322
1323 if (iommu == NULL || domain == NULL)
1324 /* device not handled by any AMD IOMMU */
1325 return (dma_addr_t)paddr;
1326
1327 if (!dma_ops_domain(domain))
1328 return bad_dma_address;
1329
1330 spin_lock_irqsave(&domain->lock, flags);
1331 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1332 dma_mask);
1333 if (addr == bad_dma_address)
1334 goto out;
1335
1336 iommu_completion_wait(iommu);
1337
1338 out:
1339 spin_unlock_irqrestore(&domain->lock, flags);
1340
1341 return addr;
1342 }
1343
1344 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1345 size_t size, int dir)
1346 {
1347 return map_page(dev, pfn_to_page(paddr >> PAGE_SHIFT),
1348 paddr & ~PAGE_MASK, size, dir, NULL);
1349 }
1350
1351 /*
1352 * The exported unmap_single function for dma_ops.
1353 */
1354 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1355 enum dma_data_direction dir, struct dma_attrs *attrs)
1356 {
1357 unsigned long flags;
1358 struct amd_iommu *iommu;
1359 struct protection_domain *domain;
1360 u16 devid;
1361
1362 INC_STATS_COUNTER(cnt_unmap_single);
1363
1364 if (!check_device(dev) ||
1365 !get_device_resources(dev, &iommu, &domain, &devid))
1366 /* device not handled by any AMD IOMMU */
1367 return;
1368
1369 if (!dma_ops_domain(domain))
1370 return;
1371
1372 spin_lock_irqsave(&domain->lock, flags);
1373
1374 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1375
1376 iommu_completion_wait(iommu);
1377
1378 spin_unlock_irqrestore(&domain->lock, flags);
1379 }
1380
1381 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1382 size_t size, int dir)
1383 {
1384 return unmap_page(dev, dma_addr, size, dir, NULL);
1385 }
1386
1387 /*
1388 * This is a special map_sg function which is used if we should map a
1389 * device which is not handled by an AMD IOMMU in the system.
1390 */
1391 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1392 int nelems, int dir)
1393 {
1394 struct scatterlist *s;
1395 int i;
1396
1397 for_each_sg(sglist, s, nelems, i) {
1398 s->dma_address = (dma_addr_t)sg_phys(s);
1399 s->dma_length = s->length;
1400 }
1401
1402 return nelems;
1403 }
1404
1405 /*
1406 * The exported map_sg function for dma_ops (handles scatter-gather
1407 * lists).
1408 */
1409 static int map_sg(struct device *dev, struct scatterlist *sglist,
1410 int nelems, int dir)
1411 {
1412 unsigned long flags;
1413 struct amd_iommu *iommu;
1414 struct protection_domain *domain;
1415 u16 devid;
1416 int i;
1417 struct scatterlist *s;
1418 phys_addr_t paddr;
1419 int mapped_elems = 0;
1420 u64 dma_mask;
1421
1422 INC_STATS_COUNTER(cnt_map_sg);
1423
1424 if (!check_device(dev))
1425 return 0;
1426
1427 dma_mask = *dev->dma_mask;
1428
1429 get_device_resources(dev, &iommu, &domain, &devid);
1430
1431 if (!iommu || !domain)
1432 return map_sg_no_iommu(dev, sglist, nelems, dir);
1433
1434 if (!dma_ops_domain(domain))
1435 return 0;
1436
1437 spin_lock_irqsave(&domain->lock, flags);
1438
1439 for_each_sg(sglist, s, nelems, i) {
1440 paddr = sg_phys(s);
1441
1442 s->dma_address = __map_single(dev, iommu, domain->priv,
1443 paddr, s->length, dir, false,
1444 dma_mask);
1445
1446 if (s->dma_address) {
1447 s->dma_length = s->length;
1448 mapped_elems++;
1449 } else
1450 goto unmap;
1451 }
1452
1453 iommu_completion_wait(iommu);
1454
1455 out:
1456 spin_unlock_irqrestore(&domain->lock, flags);
1457
1458 return mapped_elems;
1459 unmap:
1460 for_each_sg(sglist, s, mapped_elems, i) {
1461 if (s->dma_address)
1462 __unmap_single(iommu, domain->priv, s->dma_address,
1463 s->dma_length, dir);
1464 s->dma_address = s->dma_length = 0;
1465 }
1466
1467 mapped_elems = 0;
1468
1469 goto out;
1470 }
1471
1472 /*
1473 * The exported map_sg function for dma_ops (handles scatter-gather
1474 * lists).
1475 */
1476 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1477 int nelems, int dir)
1478 {
1479 unsigned long flags;
1480 struct amd_iommu *iommu;
1481 struct protection_domain *domain;
1482 struct scatterlist *s;
1483 u16 devid;
1484 int i;
1485
1486 INC_STATS_COUNTER(cnt_unmap_sg);
1487
1488 if (!check_device(dev) ||
1489 !get_device_resources(dev, &iommu, &domain, &devid))
1490 return;
1491
1492 if (!dma_ops_domain(domain))
1493 return;
1494
1495 spin_lock_irqsave(&domain->lock, flags);
1496
1497 for_each_sg(sglist, s, nelems, i) {
1498 __unmap_single(iommu, domain->priv, s->dma_address,
1499 s->dma_length, dir);
1500 s->dma_address = s->dma_length = 0;
1501 }
1502
1503 iommu_completion_wait(iommu);
1504
1505 spin_unlock_irqrestore(&domain->lock, flags);
1506 }
1507
1508 /*
1509 * The exported alloc_coherent function for dma_ops.
1510 */
1511 static void *alloc_coherent(struct device *dev, size_t size,
1512 dma_addr_t *dma_addr, gfp_t flag)
1513 {
1514 unsigned long flags;
1515 void *virt_addr;
1516 struct amd_iommu *iommu;
1517 struct protection_domain *domain;
1518 u16 devid;
1519 phys_addr_t paddr;
1520 u64 dma_mask = dev->coherent_dma_mask;
1521
1522 INC_STATS_COUNTER(cnt_alloc_coherent);
1523
1524 if (!check_device(dev))
1525 return NULL;
1526
1527 if (!get_device_resources(dev, &iommu, &domain, &devid))
1528 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1529
1530 flag |= __GFP_ZERO;
1531 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1532 if (!virt_addr)
1533 return 0;
1534
1535 paddr = virt_to_phys(virt_addr);
1536
1537 if (!iommu || !domain) {
1538 *dma_addr = (dma_addr_t)paddr;
1539 return virt_addr;
1540 }
1541
1542 if (!dma_ops_domain(domain))
1543 goto out_free;
1544
1545 if (!dma_mask)
1546 dma_mask = *dev->dma_mask;
1547
1548 spin_lock_irqsave(&domain->lock, flags);
1549
1550 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1551 size, DMA_BIDIRECTIONAL, true, dma_mask);
1552
1553 if (*dma_addr == bad_dma_address)
1554 goto out_free;
1555
1556 iommu_completion_wait(iommu);
1557
1558 spin_unlock_irqrestore(&domain->lock, flags);
1559
1560 return virt_addr;
1561
1562 out_free:
1563
1564 free_pages((unsigned long)virt_addr, get_order(size));
1565
1566 return NULL;
1567 }
1568
1569 /*
1570 * The exported free_coherent function for dma_ops.
1571 */
1572 static void free_coherent(struct device *dev, size_t size,
1573 void *virt_addr, dma_addr_t dma_addr)
1574 {
1575 unsigned long flags;
1576 struct amd_iommu *iommu;
1577 struct protection_domain *domain;
1578 u16 devid;
1579
1580 INC_STATS_COUNTER(cnt_free_coherent);
1581
1582 if (!check_device(dev))
1583 return;
1584
1585 get_device_resources(dev, &iommu, &domain, &devid);
1586
1587 if (!iommu || !domain)
1588 goto free_mem;
1589
1590 if (!dma_ops_domain(domain))
1591 goto free_mem;
1592
1593 spin_lock_irqsave(&domain->lock, flags);
1594
1595 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1596
1597 iommu_completion_wait(iommu);
1598
1599 spin_unlock_irqrestore(&domain->lock, flags);
1600
1601 free_mem:
1602 free_pages((unsigned long)virt_addr, get_order(size));
1603 }
1604
1605 /*
1606 * This function is called by the DMA layer to find out if we can handle a
1607 * particular device. It is part of the dma_ops.
1608 */
1609 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1610 {
1611 u16 bdf;
1612 struct pci_dev *pcidev;
1613
1614 /* No device or no PCI device */
1615 if (!dev || dev->bus != &pci_bus_type)
1616 return 0;
1617
1618 pcidev = to_pci_dev(dev);
1619
1620 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1621
1622 /* Out of our scope? */
1623 if (bdf > amd_iommu_last_bdf)
1624 return 0;
1625
1626 return 1;
1627 }
1628
1629 /*
1630 * The function for pre-allocating protection domains.
1631 *
1632 * If the driver core informs the DMA layer if a driver grabs a device
1633 * we don't need to preallocate the protection domains anymore.
1634 * For now we have to.
1635 */
1636 static void prealloc_protection_domains(void)
1637 {
1638 struct pci_dev *dev = NULL;
1639 struct dma_ops_domain *dma_dom;
1640 struct amd_iommu *iommu;
1641 int order = amd_iommu_aperture_order;
1642 u16 devid;
1643
1644 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1645 devid = calc_devid(dev->bus->number, dev->devfn);
1646 if (devid > amd_iommu_last_bdf)
1647 continue;
1648 devid = amd_iommu_alias_table[devid];
1649 if (domain_for_device(devid))
1650 continue;
1651 iommu = amd_iommu_rlookup_table[devid];
1652 if (!iommu)
1653 continue;
1654 dma_dom = dma_ops_domain_alloc(iommu, order);
1655 if (!dma_dom)
1656 continue;
1657 init_unity_mappings_for_device(dma_dom, devid);
1658 dma_dom->target_dev = devid;
1659
1660 list_add_tail(&dma_dom->list, &iommu_pd_list);
1661 }
1662 }
1663
1664 static struct dma_mapping_ops amd_iommu_dma_ops = {
1665 .alloc_coherent = alloc_coherent,
1666 .free_coherent = free_coherent,
1667 .map_single = map_single,
1668 .unmap_single = unmap_single,
1669 .map_page = map_page,
1670 .unmap_page = unmap_page,
1671 .map_sg = map_sg,
1672 .unmap_sg = unmap_sg,
1673 .dma_supported = amd_iommu_dma_supported,
1674 };
1675
1676 /*
1677 * The function which clues the AMD IOMMU driver into dma_ops.
1678 */
1679 int __init amd_iommu_init_dma_ops(void)
1680 {
1681 struct amd_iommu *iommu;
1682 int order = amd_iommu_aperture_order;
1683 int ret;
1684
1685 /*
1686 * first allocate a default protection domain for every IOMMU we
1687 * found in the system. Devices not assigned to any other
1688 * protection domain will be assigned to the default one.
1689 */
1690 list_for_each_entry(iommu, &amd_iommu_list, list) {
1691 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1692 if (iommu->default_dom == NULL)
1693 return -ENOMEM;
1694 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1695 ret = iommu_init_unity_mappings(iommu);
1696 if (ret)
1697 goto free_domains;
1698 }
1699
1700 /*
1701 * If device isolation is enabled, pre-allocate the protection
1702 * domains for each device.
1703 */
1704 if (amd_iommu_isolate)
1705 prealloc_protection_domains();
1706
1707 iommu_detected = 1;
1708 force_iommu = 1;
1709 bad_dma_address = 0;
1710 #ifdef CONFIG_GART_IOMMU
1711 gart_iommu_aperture_disabled = 1;
1712 gart_iommu_aperture = 0;
1713 #endif
1714
1715 /* Make the driver finally visible to the drivers */
1716 dma_ops = &amd_iommu_dma_ops;
1717
1718 register_iommu(&amd_iommu_ops);
1719
1720 bus_register_notifier(&pci_bus_type, &device_nb);
1721
1722 amd_iommu_stats_init();
1723
1724 return 0;
1725
1726 free_domains:
1727
1728 list_for_each_entry(iommu, &amd_iommu_list, list) {
1729 if (iommu->default_dom)
1730 dma_ops_domain_free(iommu->default_dom);
1731 }
1732
1733 return ret;
1734 }
1735
1736 /*****************************************************************************
1737 *
1738 * The following functions belong to the exported interface of AMD IOMMU
1739 *
1740 * This interface allows access to lower level functions of the IOMMU
1741 * like protection domain handling and assignement of devices to domains
1742 * which is not possible with the dma_ops interface.
1743 *
1744 *****************************************************************************/
1745
1746 static void cleanup_domain(struct protection_domain *domain)
1747 {
1748 unsigned long flags;
1749 u16 devid;
1750
1751 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1752
1753 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1754 if (amd_iommu_pd_table[devid] == domain)
1755 __detach_device(domain, devid);
1756
1757 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1758 }
1759
1760 static int amd_iommu_domain_init(struct iommu_domain *dom)
1761 {
1762 struct protection_domain *domain;
1763
1764 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1765 if (!domain)
1766 return -ENOMEM;
1767
1768 spin_lock_init(&domain->lock);
1769 domain->mode = PAGE_MODE_3_LEVEL;
1770 domain->id = domain_id_alloc();
1771 if (!domain->id)
1772 goto out_free;
1773 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1774 if (!domain->pt_root)
1775 goto out_free;
1776
1777 dom->priv = domain;
1778
1779 return 0;
1780
1781 out_free:
1782 kfree(domain);
1783
1784 return -ENOMEM;
1785 }
1786
1787 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1788 {
1789 struct protection_domain *domain = dom->priv;
1790
1791 if (!domain)
1792 return;
1793
1794 if (domain->dev_cnt > 0)
1795 cleanup_domain(domain);
1796
1797 BUG_ON(domain->dev_cnt != 0);
1798
1799 free_pagetable(domain);
1800
1801 domain_id_free(domain->id);
1802
1803 kfree(domain);
1804
1805 dom->priv = NULL;
1806 }
1807
1808 static void amd_iommu_detach_device(struct iommu_domain *dom,
1809 struct device *dev)
1810 {
1811 struct protection_domain *domain = dom->priv;
1812 struct amd_iommu *iommu;
1813 struct pci_dev *pdev;
1814 u16 devid;
1815
1816 if (dev->bus != &pci_bus_type)
1817 return;
1818
1819 pdev = to_pci_dev(dev);
1820
1821 devid = calc_devid(pdev->bus->number, pdev->devfn);
1822
1823 if (devid > 0)
1824 detach_device(domain, devid);
1825
1826 iommu = amd_iommu_rlookup_table[devid];
1827 if (!iommu)
1828 return;
1829
1830 iommu_queue_inv_dev_entry(iommu, devid);
1831 iommu_completion_wait(iommu);
1832 }
1833
1834 static int amd_iommu_attach_device(struct iommu_domain *dom,
1835 struct device *dev)
1836 {
1837 struct protection_domain *domain = dom->priv;
1838 struct protection_domain *old_domain;
1839 struct amd_iommu *iommu;
1840 struct pci_dev *pdev;
1841 u16 devid;
1842
1843 if (dev->bus != &pci_bus_type)
1844 return -EINVAL;
1845
1846 pdev = to_pci_dev(dev);
1847
1848 devid = calc_devid(pdev->bus->number, pdev->devfn);
1849
1850 if (devid >= amd_iommu_last_bdf ||
1851 devid != amd_iommu_alias_table[devid])
1852 return -EINVAL;
1853
1854 iommu = amd_iommu_rlookup_table[devid];
1855 if (!iommu)
1856 return -EINVAL;
1857
1858 old_domain = domain_for_device(devid);
1859 if (old_domain)
1860 return -EBUSY;
1861
1862 attach_device(iommu, domain, devid);
1863
1864 iommu_completion_wait(iommu);
1865
1866 return 0;
1867 }
1868
1869 static int amd_iommu_map_range(struct iommu_domain *dom,
1870 unsigned long iova, phys_addr_t paddr,
1871 size_t size, int iommu_prot)
1872 {
1873 struct protection_domain *domain = dom->priv;
1874 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1875 int prot = 0;
1876 int ret;
1877
1878 if (iommu_prot & IOMMU_READ)
1879 prot |= IOMMU_PROT_IR;
1880 if (iommu_prot & IOMMU_WRITE)
1881 prot |= IOMMU_PROT_IW;
1882
1883 iova &= PAGE_MASK;
1884 paddr &= PAGE_MASK;
1885
1886 for (i = 0; i < npages; ++i) {
1887 ret = iommu_map_page(domain, iova, paddr, prot);
1888 if (ret)
1889 return ret;
1890
1891 iova += PAGE_SIZE;
1892 paddr += PAGE_SIZE;
1893 }
1894
1895 return 0;
1896 }
1897
1898 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1899 unsigned long iova, size_t size)
1900 {
1901
1902 struct protection_domain *domain = dom->priv;
1903 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1904
1905 iova &= PAGE_MASK;
1906
1907 for (i = 0; i < npages; ++i) {
1908 iommu_unmap_page(domain, iova);
1909 iova += PAGE_SIZE;
1910 }
1911
1912 iommu_flush_domain(domain->id);
1913 }
1914
1915 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1916 unsigned long iova)
1917 {
1918 struct protection_domain *domain = dom->priv;
1919 unsigned long offset = iova & ~PAGE_MASK;
1920 phys_addr_t paddr;
1921 u64 *pte;
1922
1923 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1924
1925 if (!IOMMU_PTE_PRESENT(*pte))
1926 return 0;
1927
1928 pte = IOMMU_PTE_PAGE(*pte);
1929 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1930
1931 if (!IOMMU_PTE_PRESENT(*pte))
1932 return 0;
1933
1934 pte = IOMMU_PTE_PAGE(*pte);
1935 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1936
1937 if (!IOMMU_PTE_PRESENT(*pte))
1938 return 0;
1939
1940 paddr = *pte & IOMMU_PAGE_MASK;
1941 paddr |= offset;
1942
1943 return paddr;
1944 }
1945
1946 static struct iommu_ops amd_iommu_ops = {
1947 .domain_init = amd_iommu_domain_init,
1948 .domain_destroy = amd_iommu_domain_destroy,
1949 .attach_dev = amd_iommu_attach_device,
1950 .detach_dev = amd_iommu_detach_device,
1951 .map = amd_iommu_map_range,
1952 .unmap = amd_iommu_unmap_range,
1953 .iova_to_phys = amd_iommu_iova_to_phys,
1954 };
1955
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree