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ASoC: Ensure we delay long enough for WM8994 FLL to lock
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / libahci.c
blobb5aecd0c724514cdb55591e19139494d2fbaa5d2
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include "ahci.h"
48
49 static int ahci_skip_host_reset;
50 int ahci_ignore_sss;
51 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
52
53 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
54 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
55
56 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
57 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
58
59 static int ahci_enable_alpm(struct ata_port *ap,
60 enum link_pm policy);
61 static void ahci_disable_alpm(struct ata_port *ap);
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_enable_fbs(struct ata_port *ap);
81 static void ahci_disable_fbs(struct ata_port *ap);
82 static void ahci_pmp_attach(struct ata_port *ap);
83 static void ahci_pmp_detach(struct ata_port *ap);
84 static int ahci_softreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static void ahci_postreset(struct ata_link *link, unsigned int *class);
89 static void ahci_error_handler(struct ata_port *ap);
90 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
91 static int ahci_port_resume(struct ata_port *ap);
92 static void ahci_dev_config(struct ata_device *dev);
93 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
94 u32 opts);
95 #ifdef CONFIG_PM
96 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97 #endif
98 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
99 static ssize_t ahci_activity_store(struct ata_device *dev,
100 enum sw_activity val);
101 static void ahci_init_sw_activity(struct ata_link *link);
102
103 static ssize_t ahci_show_host_caps(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_cap2(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_host_version(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_show_port_cmd(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_read_em_buffer(struct device *dev,
112 struct device_attribute *attr, char *buf);
113 static ssize_t ahci_store_em_buffer(struct device *dev,
114 struct device_attribute *attr,
115 const char *buf, size_t size);
116
117 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
118 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
119 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
120 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
121 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
122 ahci_read_em_buffer, ahci_store_em_buffer);
123
124 struct device_attribute *ahci_shost_attrs[] = {
125 &dev_attr_link_power_management_policy,
126 &dev_attr_em_message_type,
127 &dev_attr_em_message,
128 &dev_attr_ahci_host_caps,
129 &dev_attr_ahci_host_cap2,
130 &dev_attr_ahci_host_version,
131 &dev_attr_ahci_port_cmd,
132 &dev_attr_em_buffer,
133 NULL
134 };
135 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
136
137 struct device_attribute *ahci_sdev_attrs[] = {
138 &dev_attr_sw_activity,
139 &dev_attr_unload_heads,
140 NULL
141 };
142 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
143
144 struct ata_port_operations ahci_ops = {
145 .inherits = &sata_pmp_port_ops,
146
147 .qc_defer = ahci_pmp_qc_defer,
148 .qc_prep = ahci_qc_prep,
149 .qc_issue = ahci_qc_issue,
150 .qc_fill_rtf = ahci_qc_fill_rtf,
151
152 .freeze = ahci_freeze,
153 .thaw = ahci_thaw,
154 .softreset = ahci_softreset,
155 .hardreset = ahci_hardreset,
156 .postreset = ahci_postreset,
157 .pmp_softreset = ahci_softreset,
158 .error_handler = ahci_error_handler,
159 .post_internal_cmd = ahci_post_internal_cmd,
160 .dev_config = ahci_dev_config,
161
162 .scr_read = ahci_scr_read,
163 .scr_write = ahci_scr_write,
164 .pmp_attach = ahci_pmp_attach,
165 .pmp_detach = ahci_pmp_detach,
166
167 .enable_pm = ahci_enable_alpm,
168 .disable_pm = ahci_disable_alpm,
169 .em_show = ahci_led_show,
170 .em_store = ahci_led_store,
171 .sw_activity_show = ahci_activity_show,
172 .sw_activity_store = ahci_activity_store,
173 #ifdef CONFIG_PM
174 .port_suspend = ahci_port_suspend,
175 .port_resume = ahci_port_resume,
176 #endif
177 .port_start = ahci_port_start,
178 .port_stop = ahci_port_stop,
179 };
180 EXPORT_SYMBOL_GPL(ahci_ops);
181
182 int ahci_em_messages = 1;
183 EXPORT_SYMBOL_GPL(ahci_em_messages);
184 module_param(ahci_em_messages, int, 0444);
185 /* add other LED protocol types when they become supported */
186 MODULE_PARM_DESC(ahci_em_messages,
187 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
188
189 static void ahci_enable_ahci(void __iomem *mmio)
190 {
191 int i;
192 u32 tmp;
193
194 /* turn on AHCI_EN */
195 tmp = readl(mmio + HOST_CTL);
196 if (tmp & HOST_AHCI_EN)
197 return;
198
199 /* Some controllers need AHCI_EN to be written multiple times.
200 * Try a few times before giving up.
201 */
202 for (i = 0; i < 5; i++) {
203 tmp |= HOST_AHCI_EN;
204 writel(tmp, mmio + HOST_CTL);
205 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
206 if (tmp & HOST_AHCI_EN)
207 return;
208 msleep(10);
209 }
210
211 WARN_ON(1);
212 }
213
214 static ssize_t ahci_show_host_caps(struct device *dev,
215 struct device_attribute *attr, char *buf)
216 {
217 struct Scsi_Host *shost = class_to_shost(dev);
218 struct ata_port *ap = ata_shost_to_port(shost);
219 struct ahci_host_priv *hpriv = ap->host->private_data;
220
221 return sprintf(buf, "%x\n", hpriv->cap);
222 }
223
224 static ssize_t ahci_show_host_cap2(struct device *dev,
225 struct device_attribute *attr, char *buf)
226 {
227 struct Scsi_Host *shost = class_to_shost(dev);
228 struct ata_port *ap = ata_shost_to_port(shost);
229 struct ahci_host_priv *hpriv = ap->host->private_data;
230
231 return sprintf(buf, "%x\n", hpriv->cap2);
232 }
233
234 static ssize_t ahci_show_host_version(struct device *dev,
235 struct device_attribute *attr, char *buf)
236 {
237 struct Scsi_Host *shost = class_to_shost(dev);
238 struct ata_port *ap = ata_shost_to_port(shost);
239 struct ahci_host_priv *hpriv = ap->host->private_data;
240 void __iomem *mmio = hpriv->mmio;
241
242 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
243 }
244
245 static ssize_t ahci_show_port_cmd(struct device *dev,
246 struct device_attribute *attr, char *buf)
247 {
248 struct Scsi_Host *shost = class_to_shost(dev);
249 struct ata_port *ap = ata_shost_to_port(shost);
250 void __iomem *port_mmio = ahci_port_base(ap);
251
252 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
253 }
254
255 static ssize_t ahci_read_em_buffer(struct device *dev,
256 struct device_attribute *attr, char *buf)
257 {
258 struct Scsi_Host *shost = class_to_shost(dev);
259 struct ata_port *ap = ata_shost_to_port(shost);
260 struct ahci_host_priv *hpriv = ap->host->private_data;
261 void __iomem *mmio = hpriv->mmio;
262 void __iomem *em_mmio = mmio + hpriv->em_loc;
263 u32 em_ctl, msg;
264 unsigned long flags;
265 size_t count;
266 int i;
267
268 spin_lock_irqsave(ap->lock, flags);
269
270 em_ctl = readl(mmio + HOST_EM_CTL);
271 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
272 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
273 spin_unlock_irqrestore(ap->lock, flags);
274 return -EINVAL;
275 }
276
277 if (!(em_ctl & EM_CTL_MR)) {
278 spin_unlock_irqrestore(ap->lock, flags);
279 return -EAGAIN;
280 }
281
282 if (!(em_ctl & EM_CTL_SMB))
283 em_mmio += hpriv->em_buf_sz;
284
285 count = hpriv->em_buf_sz;
286
287 /* the count should not be larger than PAGE_SIZE */
288 if (count > PAGE_SIZE) {
289 if (printk_ratelimit())
290 ata_port_printk(ap, KERN_WARNING,
291 "EM read buffer size too large: "
292 "buffer size %u, page size %lu\n",
293 hpriv->em_buf_sz, PAGE_SIZE);
294 count = PAGE_SIZE;
295 }
296
297 for (i = 0; i < count; i += 4) {
298 msg = readl(em_mmio + i);
299 buf[i] = msg & 0xff;
300 buf[i + 1] = (msg >> 8) & 0xff;
301 buf[i + 2] = (msg >> 16) & 0xff;
302 buf[i + 3] = (msg >> 24) & 0xff;
303 }
304
305 spin_unlock_irqrestore(ap->lock, flags);
306
307 return i;
308 }
309
310 static ssize_t ahci_store_em_buffer(struct device *dev,
311 struct device_attribute *attr,
312 const char *buf, size_t size)
313 {
314 struct Scsi_Host *shost = class_to_shost(dev);
315 struct ata_port *ap = ata_shost_to_port(shost);
316 struct ahci_host_priv *hpriv = ap->host->private_data;
317 void __iomem *mmio = hpriv->mmio;
318 void __iomem *em_mmio = mmio + hpriv->em_loc;
319 const unsigned char *msg_buf = buf;
320 u32 em_ctl, msg;
321 unsigned long flags;
322 int i;
323
324 /* check size validity */
325 if (!(ap->flags & ATA_FLAG_EM) ||
326 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
327 size % 4 || size > hpriv->em_buf_sz)
328 return -EINVAL;
329
330 spin_lock_irqsave(ap->lock, flags);
331
332 em_ctl = readl(mmio + HOST_EM_CTL);
333 if (em_ctl & EM_CTL_TM) {
334 spin_unlock_irqrestore(ap->lock, flags);
335 return -EBUSY;
336 }
337
338 for (i = 0; i < size; i += 4) {
339 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
340 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
341 writel(msg, em_mmio + i);
342 }
343
344 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
345
346 spin_unlock_irqrestore(ap->lock, flags);
347
348 return size;
349 }
350
351 /**
352 * ahci_save_initial_config - Save and fixup initial config values
353 * @dev: target AHCI device
354 * @hpriv: host private area to store config values
355 * @force_port_map: force port map to a specified value
356 * @mask_port_map: mask out particular bits from port map
357 *
358 * Some registers containing configuration info might be setup by
359 * BIOS and might be cleared on reset. This function saves the
360 * initial values of those registers into @hpriv such that they
361 * can be restored after controller reset.
362 *
363 * If inconsistent, config values are fixed up by this function.
364 *
365 * LOCKING:
366 * None.
367 */
368 void ahci_save_initial_config(struct device *dev,
369 struct ahci_host_priv *hpriv,
370 unsigned int force_port_map,
371 unsigned int mask_port_map)
372 {
373 void __iomem *mmio = hpriv->mmio;
374 u32 cap, cap2, vers, port_map;
375 int i;
376
377 /* make sure AHCI mode is enabled before accessing CAP */
378 ahci_enable_ahci(mmio);
379
380 /* Values prefixed with saved_ are written back to host after
381 * reset. Values without are used for driver operation.
382 */
383 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
384 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
385
386 /* CAP2 register is only defined for AHCI 1.2 and later */
387 vers = readl(mmio + HOST_VERSION);
388 if ((vers >> 16) > 1 ||
389 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
390 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
391 else
392 hpriv->saved_cap2 = cap2 = 0;
393
394 /* some chips have errata preventing 64bit use */
395 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
396 dev_printk(KERN_INFO, dev,
397 "controller can't do 64bit DMA, forcing 32bit\n");
398 cap &= ~HOST_CAP_64;
399 }
400
401 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
402 dev_printk(KERN_INFO, dev,
403 "controller can't do NCQ, turning off CAP_NCQ\n");
404 cap &= ~HOST_CAP_NCQ;
405 }
406
407 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
408 dev_printk(KERN_INFO, dev,
409 "controller can do NCQ, turning on CAP_NCQ\n");
410 cap |= HOST_CAP_NCQ;
411 }
412
413 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
414 dev_printk(KERN_INFO, dev,
415 "controller can't do PMP, turning off CAP_PMP\n");
416 cap &= ~HOST_CAP_PMP;
417 }
418
419 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
420 dev_printk(KERN_INFO, dev,
421 "controller can't do SNTF, turning off CAP_SNTF\n");
422 cap &= ~HOST_CAP_SNTF;
423 }
424
425 if (force_port_map && port_map != force_port_map) {
426 dev_printk(KERN_INFO, dev, "forcing port_map 0x%x -> 0x%x\n",
427 port_map, force_port_map);
428 port_map = force_port_map;
429 }
430
431 if (mask_port_map) {
432 dev_printk(KERN_ERR, dev, "masking port_map 0x%x -> 0x%x\n",
433 port_map,
434 port_map & mask_port_map);
435 port_map &= mask_port_map;
436 }
437
438 /* cross check port_map and cap.n_ports */
439 if (port_map) {
440 int map_ports = 0;
441
442 for (i = 0; i < AHCI_MAX_PORTS; i++)
443 if (port_map & (1 << i))
444 map_ports++;
445
446 /* If PI has more ports than n_ports, whine, clear
447 * port_map and let it be generated from n_ports.
448 */
449 if (map_ports > ahci_nr_ports(cap)) {
450 dev_printk(KERN_WARNING, dev,
451 "implemented port map (0x%x) contains more "
452 "ports than nr_ports (%u), using nr_ports\n",
453 port_map, ahci_nr_ports(cap));
454 port_map = 0;
455 }
456 }
457
458 /* fabricate port_map from cap.nr_ports */
459 if (!port_map) {
460 port_map = (1 << ahci_nr_ports(cap)) - 1;
461 dev_printk(KERN_WARNING, dev,
462 "forcing PORTS_IMPL to 0x%x\n", port_map);
463
464 /* write the fixed up value to the PI register */
465 hpriv->saved_port_map = port_map;
466 }
467
468 /* record values to use during operation */
469 hpriv->cap = cap;
470 hpriv->cap2 = cap2;
471 hpriv->port_map = port_map;
472 }
473 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
474
475 /**
476 * ahci_restore_initial_config - Restore initial config
477 * @host: target ATA host
478 *
479 * Restore initial config stored by ahci_save_initial_config().
480 *
481 * LOCKING:
482 * None.
483 */
484 static void ahci_restore_initial_config(struct ata_host *host)
485 {
486 struct ahci_host_priv *hpriv = host->private_data;
487 void __iomem *mmio = hpriv->mmio;
488
489 writel(hpriv->saved_cap, mmio + HOST_CAP);
490 if (hpriv->saved_cap2)
491 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
492 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
493 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
494 }
495
496 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
497 {
498 static const int offset[] = {
499 [SCR_STATUS] = PORT_SCR_STAT,
500 [SCR_CONTROL] = PORT_SCR_CTL,
501 [SCR_ERROR] = PORT_SCR_ERR,
502 [SCR_ACTIVE] = PORT_SCR_ACT,
503 [SCR_NOTIFICATION] = PORT_SCR_NTF,
504 };
505 struct ahci_host_priv *hpriv = ap->host->private_data;
506
507 if (sc_reg < ARRAY_SIZE(offset) &&
508 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
509 return offset[sc_reg];
510 return 0;
511 }
512
513 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
514 {
515 void __iomem *port_mmio = ahci_port_base(link->ap);
516 int offset = ahci_scr_offset(link->ap, sc_reg);
517
518 if (offset) {
519 *val = readl(port_mmio + offset);
520 return 0;
521 }
522 return -EINVAL;
523 }
524
525 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
526 {
527 void __iomem *port_mmio = ahci_port_base(link->ap);
528 int offset = ahci_scr_offset(link->ap, sc_reg);
529
530 if (offset) {
531 writel(val, port_mmio + offset);
532 return 0;
533 }
534 return -EINVAL;
535 }
536
537 void ahci_start_engine(struct ata_port *ap)
538 {
539 void __iomem *port_mmio = ahci_port_base(ap);
540 u32 tmp;
541
542 /* start DMA */
543 tmp = readl(port_mmio + PORT_CMD);
544 tmp |= PORT_CMD_START;
545 writel(tmp, port_mmio + PORT_CMD);
546 readl(port_mmio + PORT_CMD); /* flush */
547 }
548 EXPORT_SYMBOL_GPL(ahci_start_engine);
549
550 int ahci_stop_engine(struct ata_port *ap)
551 {
552 void __iomem *port_mmio = ahci_port_base(ap);
553 u32 tmp;
554
555 tmp = readl(port_mmio + PORT_CMD);
556
557 /* check if the HBA is idle */
558 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
559 return 0;
560
561 /* setting HBA to idle */
562 tmp &= ~PORT_CMD_START;
563 writel(tmp, port_mmio + PORT_CMD);
564
565 /* wait for engine to stop. This could be as long as 500 msec */
566 tmp = ata_wait_register(port_mmio + PORT_CMD,
567 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
568 if (tmp & PORT_CMD_LIST_ON)
569 return -EIO;
570
571 return 0;
572 }
573 EXPORT_SYMBOL_GPL(ahci_stop_engine);
574
575 static void ahci_start_fis_rx(struct ata_port *ap)
576 {
577 void __iomem *port_mmio = ahci_port_base(ap);
578 struct ahci_host_priv *hpriv = ap->host->private_data;
579 struct ahci_port_priv *pp = ap->private_data;
580 u32 tmp;
581
582 /* set FIS registers */
583 if (hpriv->cap & HOST_CAP_64)
584 writel((pp->cmd_slot_dma >> 16) >> 16,
585 port_mmio + PORT_LST_ADDR_HI);
586 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
587
588 if (hpriv->cap & HOST_CAP_64)
589 writel((pp->rx_fis_dma >> 16) >> 16,
590 port_mmio + PORT_FIS_ADDR_HI);
591 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
592
593 /* enable FIS reception */
594 tmp = readl(port_mmio + PORT_CMD);
595 tmp |= PORT_CMD_FIS_RX;
596 writel(tmp, port_mmio + PORT_CMD);
597
598 /* flush */
599 readl(port_mmio + PORT_CMD);
600 }
601
602 static int ahci_stop_fis_rx(struct ata_port *ap)
603 {
604 void __iomem *port_mmio = ahci_port_base(ap);
605 u32 tmp;
606
607 /* disable FIS reception */
608 tmp = readl(port_mmio + PORT_CMD);
609 tmp &= ~PORT_CMD_FIS_RX;
610 writel(tmp, port_mmio + PORT_CMD);
611
612 /* wait for completion, spec says 500ms, give it 1000 */
613 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
614 PORT_CMD_FIS_ON, 10, 1000);
615 if (tmp & PORT_CMD_FIS_ON)
616 return -EBUSY;
617
618 return 0;
619 }
620
621 static void ahci_power_up(struct ata_port *ap)
622 {
623 struct ahci_host_priv *hpriv = ap->host->private_data;
624 void __iomem *port_mmio = ahci_port_base(ap);
625 u32 cmd;
626
627 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
628
629 /* spin up device */
630 if (hpriv->cap & HOST_CAP_SSS) {
631 cmd |= PORT_CMD_SPIN_UP;
632 writel(cmd, port_mmio + PORT_CMD);
633 }
634
635 /* wake up link */
636 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
637 }
638
639 static void ahci_disable_alpm(struct ata_port *ap)
640 {
641 struct ahci_host_priv *hpriv = ap->host->private_data;
642 void __iomem *port_mmio = ahci_port_base(ap);
643 u32 cmd;
644 struct ahci_port_priv *pp = ap->private_data;
645
646 /* IPM bits should be disabled by libata-core */
647 /* get the existing command bits */
648 cmd = readl(port_mmio + PORT_CMD);
649
650 /* disable ALPM and ASP */
651 cmd &= ~PORT_CMD_ASP;
652 cmd &= ~PORT_CMD_ALPE;
653
654 /* force the interface back to active */
655 cmd |= PORT_CMD_ICC_ACTIVE;
656
657 /* write out new cmd value */
658 writel(cmd, port_mmio + PORT_CMD);
659 cmd = readl(port_mmio + PORT_CMD);
660
661 /* wait 10ms to be sure we've come out of any low power state */
662 msleep(10);
663
664 /* clear out any PhyRdy stuff from interrupt status */
665 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
666
667 /* go ahead and clean out PhyRdy Change from Serror too */
668 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
669
670 /*
671 * Clear flag to indicate that we should ignore all PhyRdy
672 * state changes
673 */
674 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
675
676 /*
677 * Enable interrupts on Phy Ready.
678 */
679 pp->intr_mask |= PORT_IRQ_PHYRDY;
680 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
681
682 /*
683 * don't change the link pm policy - we can be called
684 * just to turn of link pm temporarily
685 */
686 }
687
688 static int ahci_enable_alpm(struct ata_port *ap,
689 enum link_pm policy)
690 {
691 struct ahci_host_priv *hpriv = ap->host->private_data;
692 void __iomem *port_mmio = ahci_port_base(ap);
693 u32 cmd;
694 struct ahci_port_priv *pp = ap->private_data;
695 u32 asp;
696
697 /* Make sure the host is capable of link power management */
698 if (!(hpriv->cap & HOST_CAP_ALPM))
699 return -EINVAL;
700
701 switch (policy) {
702 case MAX_PERFORMANCE:
703 case NOT_AVAILABLE:
704 /*
705 * if we came here with NOT_AVAILABLE,
706 * it just means this is the first time we
707 * have tried to enable - default to max performance,
708 * and let the user go to lower power modes on request.
709 */
710 ahci_disable_alpm(ap);
711 return 0;
712 case MIN_POWER:
713 /* configure HBA to enter SLUMBER */
714 asp = PORT_CMD_ASP;
715 break;
716 case MEDIUM_POWER:
717 /* configure HBA to enter PARTIAL */
718 asp = 0;
719 break;
720 default:
721 return -EINVAL;
722 }
723
724 /*
725 * Disable interrupts on Phy Ready. This keeps us from
726 * getting woken up due to spurious phy ready interrupts
727 * TBD - Hot plug should be done via polling now, is
728 * that even supported?
729 */
730 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
731 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
732
733 /*
734 * Set a flag to indicate that we should ignore all PhyRdy
735 * state changes since these can happen now whenever we
736 * change link state
737 */
738 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
739
740 /* get the existing command bits */
741 cmd = readl(port_mmio + PORT_CMD);
742
743 /*
744 * Set ASP based on Policy
745 */
746 cmd |= asp;
747
748 /*
749 * Setting this bit will instruct the HBA to aggressively
750 * enter a lower power link state when it's appropriate and
751 * based on the value set above for ASP
752 */
753 cmd |= PORT_CMD_ALPE;
754
755 /* write out new cmd value */
756 writel(cmd, port_mmio + PORT_CMD);
757 cmd = readl(port_mmio + PORT_CMD);
758
759 /* IPM bits should be set by libata-core */
760 return 0;
761 }
762
763 #ifdef CONFIG_PM
764 static void ahci_power_down(struct ata_port *ap)
765 {
766 struct ahci_host_priv *hpriv = ap->host->private_data;
767 void __iomem *port_mmio = ahci_port_base(ap);
768 u32 cmd, scontrol;
769
770 if (!(hpriv->cap & HOST_CAP_SSS))
771 return;
772
773 /* put device into listen mode, first set PxSCTL.DET to 0 */
774 scontrol = readl(port_mmio + PORT_SCR_CTL);
775 scontrol &= ~0xf;
776 writel(scontrol, port_mmio + PORT_SCR_CTL);
777
778 /* then set PxCMD.SUD to 0 */
779 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
780 cmd &= ~PORT_CMD_SPIN_UP;
781 writel(cmd, port_mmio + PORT_CMD);
782 }
783 #endif
784
785 static void ahci_start_port(struct ata_port *ap)
786 {
787 struct ahci_port_priv *pp = ap->private_data;
788 struct ata_link *link;
789 struct ahci_em_priv *emp;
790 ssize_t rc;
791 int i;
792
793 /* enable FIS reception */
794 ahci_start_fis_rx(ap);
795
796 /* enable DMA */
797 ahci_start_engine(ap);
798
799 /* turn on LEDs */
800 if (ap->flags & ATA_FLAG_EM) {
801 ata_for_each_link(link, ap, EDGE) {
802 emp = &pp->em_priv[link->pmp];
803
804 /* EM Transmit bit maybe busy during init */
805 for (i = 0; i < EM_MAX_RETRY; i++) {
806 rc = ahci_transmit_led_message(ap,
807 emp->led_state,
808 4);
809 if (rc == -EBUSY)
810 msleep(1);
811 else
812 break;
813 }
814 }
815 }
816
817 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
818 ata_for_each_link(link, ap, EDGE)
819 ahci_init_sw_activity(link);
820
821 }
822
823 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
824 {
825 int rc;
826
827 /* disable DMA */
828 rc = ahci_stop_engine(ap);
829 if (rc) {
830 *emsg = "failed to stop engine";
831 return rc;
832 }
833
834 /* disable FIS reception */
835 rc = ahci_stop_fis_rx(ap);
836 if (rc) {
837 *emsg = "failed stop FIS RX";
838 return rc;
839 }
840
841 return 0;
842 }
843
844 int ahci_reset_controller(struct ata_host *host)
845 {
846 struct ahci_host_priv *hpriv = host->private_data;
847 void __iomem *mmio = hpriv->mmio;
848 u32 tmp;
849
850 /* we must be in AHCI mode, before using anything
851 * AHCI-specific, such as HOST_RESET.
852 */
853 ahci_enable_ahci(mmio);
854
855 /* global controller reset */
856 if (!ahci_skip_host_reset) {
857 tmp = readl(mmio + HOST_CTL);
858 if ((tmp & HOST_RESET) == 0) {
859 writel(tmp | HOST_RESET, mmio + HOST_CTL);
860 readl(mmio + HOST_CTL); /* flush */
861 }
862
863 /*
864 * to perform host reset, OS should set HOST_RESET
865 * and poll until this bit is read to be "0".
866 * reset must complete within 1 second, or
867 * the hardware should be considered fried.
868 */
869 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
870 HOST_RESET, 10, 1000);
871
872 if (tmp & HOST_RESET) {
873 dev_printk(KERN_ERR, host->dev,
874 "controller reset failed (0x%x)\n", tmp);
875 return -EIO;
876 }
877
878 /* turn on AHCI mode */
879 ahci_enable_ahci(mmio);
880
881 /* Some registers might be cleared on reset. Restore
882 * initial values.
883 */
884 ahci_restore_initial_config(host);
885 } else
886 dev_printk(KERN_INFO, host->dev,
887 "skipping global host reset\n");
888
889 return 0;
890 }
891 EXPORT_SYMBOL_GPL(ahci_reset_controller);
892
893 static void ahci_sw_activity(struct ata_link *link)
894 {
895 struct ata_port *ap = link->ap;
896 struct ahci_port_priv *pp = ap->private_data;
897 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
898
899 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
900 return;
901
902 emp->activity++;
903 if (!timer_pending(&emp->timer))
904 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
905 }
906
907 static void ahci_sw_activity_blink(unsigned long arg)
908 {
909 struct ata_link *link = (struct ata_link *)arg;
910 struct ata_port *ap = link->ap;
911 struct ahci_port_priv *pp = ap->private_data;
912 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
913 unsigned long led_message = emp->led_state;
914 u32 activity_led_state;
915 unsigned long flags;
916
917 led_message &= EM_MSG_LED_VALUE;
918 led_message |= ap->port_no | (link->pmp << 8);
919
920 /* check to see if we've had activity. If so,
921 * toggle state of LED and reset timer. If not,
922 * turn LED to desired idle state.
923 */
924 spin_lock_irqsave(ap->lock, flags);
925 if (emp->saved_activity != emp->activity) {
926 emp->saved_activity = emp->activity;
927 /* get the current LED state */
928 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
929
930 if (activity_led_state)
931 activity_led_state = 0;
932 else
933 activity_led_state = 1;
934
935 /* clear old state */
936 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
937
938 /* toggle state */
939 led_message |= (activity_led_state << 16);
940 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
941 } else {
942 /* switch to idle */
943 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
944 if (emp->blink_policy == BLINK_OFF)
945 led_message |= (1 << 16);
946 }
947 spin_unlock_irqrestore(ap->lock, flags);
948 ahci_transmit_led_message(ap, led_message, 4);
949 }
950
951 static void ahci_init_sw_activity(struct ata_link *link)
952 {
953 struct ata_port *ap = link->ap;
954 struct ahci_port_priv *pp = ap->private_data;
955 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
956
957 /* init activity stats, setup timer */
958 emp->saved_activity = emp->activity = 0;
959 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
960
961 /* check our blink policy and set flag for link if it's enabled */
962 if (emp->blink_policy)
963 link->flags |= ATA_LFLAG_SW_ACTIVITY;
964 }
965
966 int ahci_reset_em(struct ata_host *host)
967 {
968 struct ahci_host_priv *hpriv = host->private_data;
969 void __iomem *mmio = hpriv->mmio;
970 u32 em_ctl;
971
972 em_ctl = readl(mmio + HOST_EM_CTL);
973 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
974 return -EINVAL;
975
976 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
977 return 0;
978 }
979 EXPORT_SYMBOL_GPL(ahci_reset_em);
980
981 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
982 ssize_t size)
983 {
984 struct ahci_host_priv *hpriv = ap->host->private_data;
985 struct ahci_port_priv *pp = ap->private_data;
986 void __iomem *mmio = hpriv->mmio;
987 u32 em_ctl;
988 u32 message[] = {0, 0};
989 unsigned long flags;
990 int pmp;
991 struct ahci_em_priv *emp;
992
993 /* get the slot number from the message */
994 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
995 if (pmp < EM_MAX_SLOTS)
996 emp = &pp->em_priv[pmp];
997 else
998 return -EINVAL;
999
1000 spin_lock_irqsave(ap->lock, flags);
1001
1002 /*
1003 * if we are still busy transmitting a previous message,
1004 * do not allow
1005 */
1006 em_ctl = readl(mmio + HOST_EM_CTL);
1007 if (em_ctl & EM_CTL_TM) {
1008 spin_unlock_irqrestore(ap->lock, flags);
1009 return -EBUSY;
1010 }
1011
1012 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
1013 /*
1014 * create message header - this is all zero except for
1015 * the message size, which is 4 bytes.
1016 */
1017 message[0] |= (4 << 8);
1018
1019 /* ignore 0:4 of byte zero, fill in port info yourself */
1020 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1021
1022 /* write message to EM_LOC */
1023 writel(message[0], mmio + hpriv->em_loc);
1024 writel(message[1], mmio + hpriv->em_loc+4);
1025
1026 /*
1027 * tell hardware to transmit the message
1028 */
1029 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1030 }
1031
1032 /* save off new led state for port/slot */
1033 emp->led_state = state;
1034
1035 spin_unlock_irqrestore(ap->lock, flags);
1036 return size;
1037 }
1038
1039 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1040 {
1041 struct ahci_port_priv *pp = ap->private_data;
1042 struct ata_link *link;
1043 struct ahci_em_priv *emp;
1044 int rc = 0;
1045
1046 ata_for_each_link(link, ap, EDGE) {
1047 emp = &pp->em_priv[link->pmp];
1048 rc += sprintf(buf, "%lx\n", emp->led_state);
1049 }
1050 return rc;
1051 }
1052
1053 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1054 size_t size)
1055 {
1056 int state;
1057 int pmp;
1058 struct ahci_port_priv *pp = ap->private_data;
1059 struct ahci_em_priv *emp;
1060
1061 state = simple_strtoul(buf, NULL, 0);
1062
1063 /* get the slot number from the message */
1064 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1065 if (pmp < EM_MAX_SLOTS)
1066 emp = &pp->em_priv[pmp];
1067 else
1068 return -EINVAL;
1069
1070 /* mask off the activity bits if we are in sw_activity
1071 * mode, user should turn off sw_activity before setting
1072 * activity led through em_message
1073 */
1074 if (emp->blink_policy)
1075 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1076
1077 return ahci_transmit_led_message(ap, state, size);
1078 }
1079
1080 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1081 {
1082 struct ata_link *link = dev->link;
1083 struct ata_port *ap = link->ap;
1084 struct ahci_port_priv *pp = ap->private_data;
1085 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1086 u32 port_led_state = emp->led_state;
1087
1088 /* save the desired Activity LED behavior */
1089 if (val == OFF) {
1090 /* clear LFLAG */
1091 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1092
1093 /* set the LED to OFF */
1094 port_led_state &= EM_MSG_LED_VALUE_OFF;
1095 port_led_state |= (ap->port_no | (link->pmp << 8));
1096 ahci_transmit_led_message(ap, port_led_state, 4);
1097 } else {
1098 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1099 if (val == BLINK_OFF) {
1100 /* set LED to ON for idle */
1101 port_led_state &= EM_MSG_LED_VALUE_OFF;
1102 port_led_state |= (ap->port_no | (link->pmp << 8));
1103 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1104 ahci_transmit_led_message(ap, port_led_state, 4);
1105 }
1106 }
1107 emp->blink_policy = val;
1108 return 0;
1109 }
1110
1111 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1112 {
1113 struct ata_link *link = dev->link;
1114 struct ata_port *ap = link->ap;
1115 struct ahci_port_priv *pp = ap->private_data;
1116 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1117
1118 /* display the saved value of activity behavior for this
1119 * disk.
1120 */
1121 return sprintf(buf, "%d\n", emp->blink_policy);
1122 }
1123
1124 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1125 int port_no, void __iomem *mmio,
1126 void __iomem *port_mmio)
1127 {
1128 const char *emsg = NULL;
1129 int rc;
1130 u32 tmp;
1131
1132 /* make sure port is not active */
1133 rc = ahci_deinit_port(ap, &emsg);
1134 if (rc)
1135 dev_warn(dev, "%s (%d)\n", emsg, rc);
1136
1137 /* clear SError */
1138 tmp = readl(port_mmio + PORT_SCR_ERR);
1139 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1140 writel(tmp, port_mmio + PORT_SCR_ERR);
1141
1142 /* clear port IRQ */
1143 tmp = readl(port_mmio + PORT_IRQ_STAT);
1144 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1145 if (tmp)
1146 writel(tmp, port_mmio + PORT_IRQ_STAT);
1147
1148 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1149 }
1150
1151 void ahci_init_controller(struct ata_host *host)
1152 {
1153 struct ahci_host_priv *hpriv = host->private_data;
1154 void __iomem *mmio = hpriv->mmio;
1155 int i;
1156 void __iomem *port_mmio;
1157 u32 tmp;
1158
1159 for (i = 0; i < host->n_ports; i++) {
1160 struct ata_port *ap = host->ports[i];
1161
1162 port_mmio = ahci_port_base(ap);
1163 if (ata_port_is_dummy(ap))
1164 continue;
1165
1166 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1167 }
1168
1169 tmp = readl(mmio + HOST_CTL);
1170 VPRINTK("HOST_CTL 0x%x\n", tmp);
1171 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1172 tmp = readl(mmio + HOST_CTL);
1173 VPRINTK("HOST_CTL 0x%x\n", tmp);
1174 }
1175 EXPORT_SYMBOL_GPL(ahci_init_controller);
1176
1177 static void ahci_dev_config(struct ata_device *dev)
1178 {
1179 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1180
1181 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1182 dev->max_sectors = 255;
1183 ata_dev_printk(dev, KERN_INFO,
1184 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1185 }
1186 }
1187
1188 static unsigned int ahci_dev_classify(struct ata_port *ap)
1189 {
1190 void __iomem *port_mmio = ahci_port_base(ap);
1191 struct ata_taskfile tf;
1192 u32 tmp;
1193
1194 tmp = readl(port_mmio + PORT_SIG);
1195 tf.lbah = (tmp >> 24) & 0xff;
1196 tf.lbam = (tmp >> 16) & 0xff;
1197 tf.lbal = (tmp >> 8) & 0xff;
1198 tf.nsect = (tmp) & 0xff;
1199
1200 return ata_dev_classify(&tf);
1201 }
1202
1203 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1204 u32 opts)
1205 {
1206 dma_addr_t cmd_tbl_dma;
1207
1208 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1209
1210 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1211 pp->cmd_slot[tag].status = 0;
1212 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1213 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1214 }
1215
1216 int ahci_kick_engine(struct ata_port *ap)
1217 {
1218 void __iomem *port_mmio = ahci_port_base(ap);
1219 struct ahci_host_priv *hpriv = ap->host->private_data;
1220 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1221 u32 tmp;
1222 int busy, rc;
1223
1224 /* stop engine */
1225 rc = ahci_stop_engine(ap);
1226 if (rc)
1227 goto out_restart;
1228
1229 /* need to do CLO?
1230 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1231 */
1232 busy = status & (ATA_BUSY | ATA_DRQ);
1233 if (!busy && !sata_pmp_attached(ap)) {
1234 rc = 0;
1235 goto out_restart;
1236 }
1237
1238 if (!(hpriv->cap & HOST_CAP_CLO)) {
1239 rc = -EOPNOTSUPP;
1240 goto out_restart;
1241 }
1242
1243 /* perform CLO */
1244 tmp = readl(port_mmio + PORT_CMD);
1245 tmp |= PORT_CMD_CLO;
1246 writel(tmp, port_mmio + PORT_CMD);
1247
1248 rc = 0;
1249 tmp = ata_wait_register(port_mmio + PORT_CMD,
1250 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1251 if (tmp & PORT_CMD_CLO)
1252 rc = -EIO;
1253
1254 /* restart engine */
1255 out_restart:
1256 ahci_start_engine(ap);
1257 return rc;
1258 }
1259 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1260
1261 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1262 struct ata_taskfile *tf, int is_cmd, u16 flags,
1263 unsigned long timeout_msec)
1264 {
1265 const u32 cmd_fis_len = 5; /* five dwords */
1266 struct ahci_port_priv *pp = ap->private_data;
1267 void __iomem *port_mmio = ahci_port_base(ap);
1268 u8 *fis = pp->cmd_tbl;
1269 u32 tmp;
1270
1271 /* prep the command */
1272 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1273 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1274
1275 /* issue & wait */
1276 writel(1, port_mmio + PORT_CMD_ISSUE);
1277
1278 if (timeout_msec) {
1279 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1280 1, timeout_msec);
1281 if (tmp & 0x1) {
1282 ahci_kick_engine(ap);
1283 return -EBUSY;
1284 }
1285 } else
1286 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1287
1288 return 0;
1289 }
1290
1291 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1292 int pmp, unsigned long deadline,
1293 int (*check_ready)(struct ata_link *link))
1294 {
1295 struct ata_port *ap = link->ap;
1296 struct ahci_host_priv *hpriv = ap->host->private_data;
1297 const char *reason = NULL;
1298 unsigned long now, msecs;
1299 struct ata_taskfile tf;
1300 int rc;
1301
1302 DPRINTK("ENTER\n");
1303
1304 /* prepare for SRST (AHCI-1.1 10.4.1) */
1305 rc = ahci_kick_engine(ap);
1306 if (rc && rc != -EOPNOTSUPP)
1307 ata_link_printk(link, KERN_WARNING,
1308 "failed to reset engine (errno=%d)\n", rc);
1309
1310 ata_tf_init(link->device, &tf);
1311
1312 /* issue the first D2H Register FIS */
1313 msecs = 0;
1314 now = jiffies;
1315 if (time_after(deadline, now))
1316 msecs = jiffies_to_msecs(deadline - now);
1317
1318 tf.ctl |= ATA_SRST;
1319 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1320 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1321 rc = -EIO;
1322 reason = "1st FIS failed";
1323 goto fail;
1324 }
1325
1326 /* spec says at least 5us, but be generous and sleep for 1ms */
1327 msleep(1);
1328
1329 /* issue the second D2H Register FIS */
1330 tf.ctl &= ~ATA_SRST;
1331 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1332
1333 /* wait for link to become ready */
1334 rc = ata_wait_after_reset(link, deadline, check_ready);
1335 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1336 /*
1337 * Workaround for cases where link online status can't
1338 * be trusted. Treat device readiness timeout as link
1339 * offline.
1340 */
1341 ata_link_printk(link, KERN_INFO,
1342 "device not ready, treating as offline\n");
1343 *class = ATA_DEV_NONE;
1344 } else if (rc) {
1345 /* link occupied, -ENODEV too is an error */
1346 reason = "device not ready";
1347 goto fail;
1348 } else
1349 *class = ahci_dev_classify(ap);
1350
1351 DPRINTK("EXIT, class=%u\n", *class);
1352 return 0;
1353
1354 fail:
1355 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1356 return rc;
1357 }
1358
1359 int ahci_check_ready(struct ata_link *link)
1360 {
1361 void __iomem *port_mmio = ahci_port_base(link->ap);
1362 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1363
1364 return ata_check_ready(status);
1365 }
1366 EXPORT_SYMBOL_GPL(ahci_check_ready);
1367
1368 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1369 unsigned long deadline)
1370 {
1371 int pmp = sata_srst_pmp(link);
1372
1373 DPRINTK("ENTER\n");
1374
1375 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1376 }
1377 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1378
1379 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1380 unsigned long deadline)
1381 {
1382 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1383 struct ata_port *ap = link->ap;
1384 struct ahci_port_priv *pp = ap->private_data;
1385 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1386 struct ata_taskfile tf;
1387 bool online;
1388 int rc;
1389
1390 DPRINTK("ENTER\n");
1391
1392 ahci_stop_engine(ap);
1393
1394 /* clear D2H reception area to properly wait for D2H FIS */
1395 ata_tf_init(link->device, &tf);
1396 tf.command = 0x80;
1397 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1398
1399 rc = sata_link_hardreset(link, timing, deadline, &online,
1400 ahci_check_ready);
1401
1402 ahci_start_engine(ap);
1403
1404 if (online)
1405 *class = ahci_dev_classify(ap);
1406
1407 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1408 return rc;
1409 }
1410
1411 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1412 {
1413 struct ata_port *ap = link->ap;
1414 void __iomem *port_mmio = ahci_port_base(ap);
1415 u32 new_tmp, tmp;
1416
1417 ata_std_postreset(link, class);
1418
1419 /* Make sure port's ATAPI bit is set appropriately */
1420 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1421 if (*class == ATA_DEV_ATAPI)
1422 new_tmp |= PORT_CMD_ATAPI;
1423 else
1424 new_tmp &= ~PORT_CMD_ATAPI;
1425 if (new_tmp != tmp) {
1426 writel(new_tmp, port_mmio + PORT_CMD);
1427 readl(port_mmio + PORT_CMD); /* flush */
1428 }
1429 }
1430
1431 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1432 {
1433 struct scatterlist *sg;
1434 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1435 unsigned int si;
1436
1437 VPRINTK("ENTER\n");
1438
1439 /*
1440 * Next, the S/G list.
1441 */
1442 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1443 dma_addr_t addr = sg_dma_address(sg);
1444 u32 sg_len = sg_dma_len(sg);
1445
1446 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1447 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1448 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1449 }
1450
1451 return si;
1452 }
1453
1454 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1455 {
1456 struct ata_port *ap = qc->ap;
1457 struct ahci_port_priv *pp = ap->private_data;
1458
1459 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1460 return ata_std_qc_defer(qc);
1461 else
1462 return sata_pmp_qc_defer_cmd_switch(qc);
1463 }
1464
1465 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1466 {
1467 struct ata_port *ap = qc->ap;
1468 struct ahci_port_priv *pp = ap->private_data;
1469 int is_atapi = ata_is_atapi(qc->tf.protocol);
1470 void *cmd_tbl;
1471 u32 opts;
1472 const u32 cmd_fis_len = 5; /* five dwords */
1473 unsigned int n_elem;
1474
1475 /*
1476 * Fill in command table information. First, the header,
1477 * a SATA Register - Host to Device command FIS.
1478 */
1479 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1480
1481 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1482 if (is_atapi) {
1483 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1484 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1485 }
1486
1487 n_elem = 0;
1488 if (qc->flags & ATA_QCFLAG_DMAMAP)
1489 n_elem = ahci_fill_sg(qc, cmd_tbl);
1490
1491 /*
1492 * Fill in command slot information.
1493 */
1494 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1495 if (qc->tf.flags & ATA_TFLAG_WRITE)
1496 opts |= AHCI_CMD_WRITE;
1497 if (is_atapi)
1498 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1499
1500 ahci_fill_cmd_slot(pp, qc->tag, opts);
1501 }
1502
1503 static void ahci_fbs_dec_intr(struct ata_port *ap)
1504 {
1505 struct ahci_port_priv *pp = ap->private_data;
1506 void __iomem *port_mmio = ahci_port_base(ap);
1507 u32 fbs = readl(port_mmio + PORT_FBS);
1508 int retries = 3;
1509
1510 DPRINTK("ENTER\n");
1511 BUG_ON(!pp->fbs_enabled);
1512
1513 /* time to wait for DEC is not specified by AHCI spec,
1514 * add a retry loop for safety.
1515 */
1516 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1517 fbs = readl(port_mmio + PORT_FBS);
1518 while ((fbs & PORT_FBS_DEC) && retries--) {
1519 udelay(1);
1520 fbs = readl(port_mmio + PORT_FBS);
1521 }
1522
1523 if (fbs & PORT_FBS_DEC)
1524 dev_printk(KERN_ERR, ap->host->dev,
1525 "failed to clear device error\n");
1526 }
1527
1528 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1529 {
1530 struct ahci_host_priv *hpriv = ap->host->private_data;
1531 struct ahci_port_priv *pp = ap->private_data;
1532 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1533 struct ata_link *link = NULL;
1534 struct ata_queued_cmd *active_qc;
1535 struct ata_eh_info *active_ehi;
1536 bool fbs_need_dec = false;
1537 u32 serror;
1538
1539 /* determine active link with error */
1540 if (pp->fbs_enabled) {
1541 void __iomem *port_mmio = ahci_port_base(ap);
1542 u32 fbs = readl(port_mmio + PORT_FBS);
1543 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1544
1545 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links) &&
1546 ata_link_online(&ap->pmp_link[pmp])) {
1547 link = &ap->pmp_link[pmp];
1548 fbs_need_dec = true;
1549 }
1550
1551 } else
1552 ata_for_each_link(link, ap, EDGE)
1553 if (ata_link_active(link))
1554 break;
1555
1556 if (!link)
1557 link = &ap->link;
1558
1559 active_qc = ata_qc_from_tag(ap, link->active_tag);
1560 active_ehi = &link->eh_info;
1561
1562 /* record irq stat */
1563 ata_ehi_clear_desc(host_ehi);
1564 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1565
1566 /* AHCI needs SError cleared; otherwise, it might lock up */
1567 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1568 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1569 host_ehi->serror |= serror;
1570
1571 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1572 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1573 irq_stat &= ~PORT_IRQ_IF_ERR;
1574
1575 if (irq_stat & PORT_IRQ_TF_ERR) {
1576 /* If qc is active, charge it; otherwise, the active
1577 * link. There's no active qc on NCQ errors. It will
1578 * be determined by EH by reading log page 10h.
1579 */
1580 if (active_qc)
1581 active_qc->err_mask |= AC_ERR_DEV;
1582 else
1583 active_ehi->err_mask |= AC_ERR_DEV;
1584
1585 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1586 host_ehi->serror &= ~SERR_INTERNAL;
1587 }
1588
1589 if (irq_stat & PORT_IRQ_UNK_FIS) {
1590 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1591
1592 active_ehi->err_mask |= AC_ERR_HSM;
1593 active_ehi->action |= ATA_EH_RESET;
1594 ata_ehi_push_desc(active_ehi,
1595 "unknown FIS %08x %08x %08x %08x" ,
1596 unk[0], unk[1], unk[2], unk[3]);
1597 }
1598
1599 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1600 active_ehi->err_mask |= AC_ERR_HSM;
1601 active_ehi->action |= ATA_EH_RESET;
1602 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1603 }
1604
1605 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1606 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1607 host_ehi->action |= ATA_EH_RESET;
1608 ata_ehi_push_desc(host_ehi, "host bus error");
1609 }
1610
1611 if (irq_stat & PORT_IRQ_IF_ERR) {
1612 if (fbs_need_dec)
1613 active_ehi->err_mask |= AC_ERR_DEV;
1614 else {
1615 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1616 host_ehi->action |= ATA_EH_RESET;
1617 }
1618
1619 ata_ehi_push_desc(host_ehi, "interface fatal error");
1620 }
1621
1622 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1623 ata_ehi_hotplugged(host_ehi);
1624 ata_ehi_push_desc(host_ehi, "%s",
1625 irq_stat & PORT_IRQ_CONNECT ?
1626 "connection status changed" : "PHY RDY changed");
1627 }
1628
1629 /* okay, let's hand over to EH */
1630
1631 if (irq_stat & PORT_IRQ_FREEZE)
1632 ata_port_freeze(ap);
1633 else if (fbs_need_dec) {
1634 ata_link_abort(link);
1635 ahci_fbs_dec_intr(ap);
1636 } else
1637 ata_port_abort(ap);
1638 }
1639
1640 static void ahci_port_intr(struct ata_port *ap)
1641 {
1642 void __iomem *port_mmio = ahci_port_base(ap);
1643 struct ata_eh_info *ehi = &ap->link.eh_info;
1644 struct ahci_port_priv *pp = ap->private_data;
1645 struct ahci_host_priv *hpriv = ap->host->private_data;
1646 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1647 u32 status, qc_active = 0;
1648 int rc;
1649
1650 status = readl(port_mmio + PORT_IRQ_STAT);
1651 writel(status, port_mmio + PORT_IRQ_STAT);
1652
1653 /* ignore BAD_PMP while resetting */
1654 if (unlikely(resetting))
1655 status &= ~PORT_IRQ_BAD_PMP;
1656
1657 /* If we are getting PhyRdy, this is
1658 * just a power state change, we should
1659 * clear out this, plus the PhyRdy/Comm
1660 * Wake bits from Serror
1661 */
1662 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1663 (status & PORT_IRQ_PHYRDY)) {
1664 status &= ~PORT_IRQ_PHYRDY;
1665 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1666 }
1667
1668 if (unlikely(status & PORT_IRQ_ERROR)) {
1669 ahci_error_intr(ap, status);
1670 return;
1671 }
1672
1673 if (status & PORT_IRQ_SDB_FIS) {
1674 /* If SNotification is available, leave notification
1675 * handling to sata_async_notification(). If not,
1676 * emulate it by snooping SDB FIS RX area.
1677 *
1678 * Snooping FIS RX area is probably cheaper than
1679 * poking SNotification but some constrollers which
1680 * implement SNotification, ICH9 for example, don't
1681 * store AN SDB FIS into receive area.
1682 */
1683 if (hpriv->cap & HOST_CAP_SNTF)
1684 sata_async_notification(ap);
1685 else {
1686 /* If the 'N' bit in word 0 of the FIS is set,
1687 * we just received asynchronous notification.
1688 * Tell libata about it.
1689 *
1690 * Lack of SNotification should not appear in
1691 * ahci 1.2, so the workaround is unnecessary
1692 * when FBS is enabled.
1693 */
1694 if (pp->fbs_enabled)
1695 WARN_ON_ONCE(1);
1696 else {
1697 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1698 u32 f0 = le32_to_cpu(f[0]);
1699 if (f0 & (1 << 15))
1700 sata_async_notification(ap);
1701 }
1702 }
1703 }
1704
1705 /* pp->active_link is not reliable once FBS is enabled, both
1706 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1707 * NCQ and non-NCQ commands may be in flight at the same time.
1708 */
1709 if (pp->fbs_enabled) {
1710 if (ap->qc_active) {
1711 qc_active = readl(port_mmio + PORT_SCR_ACT);
1712 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1713 }
1714 } else {
1715 /* pp->active_link is valid iff any command is in flight */
1716 if (ap->qc_active && pp->active_link->sactive)
1717 qc_active = readl(port_mmio + PORT_SCR_ACT);
1718 else
1719 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1720 }
1721
1722
1723 rc = ata_qc_complete_multiple(ap, qc_active);
1724
1725 /* while resetting, invalid completions are expected */
1726 if (unlikely(rc < 0 && !resetting)) {
1727 ehi->err_mask |= AC_ERR_HSM;
1728 ehi->action |= ATA_EH_RESET;
1729 ata_port_freeze(ap);
1730 }
1731 }
1732
1733 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1734 {
1735 struct ata_host *host = dev_instance;
1736 struct ahci_host_priv *hpriv;
1737 unsigned int i, handled = 0;
1738 void __iomem *mmio;
1739 u32 irq_stat, irq_masked;
1740
1741 VPRINTK("ENTER\n");
1742
1743 hpriv = host->private_data;
1744 mmio = hpriv->mmio;
1745
1746 /* sigh. 0xffffffff is a valid return from h/w */
1747 irq_stat = readl(mmio + HOST_IRQ_STAT);
1748 if (!irq_stat)
1749 return IRQ_NONE;
1750
1751 irq_masked = irq_stat & hpriv->port_map;
1752
1753 spin_lock(&host->lock);
1754
1755 for (i = 0; i < host->n_ports; i++) {
1756 struct ata_port *ap;
1757
1758 if (!(irq_masked & (1 << i)))
1759 continue;
1760
1761 ap = host->ports[i];
1762 if (ap) {
1763 ahci_port_intr(ap);
1764 VPRINTK("port %u\n", i);
1765 } else {
1766 VPRINTK("port %u (no irq)\n", i);
1767 if (ata_ratelimit())
1768 dev_printk(KERN_WARNING, host->dev,
1769 "interrupt on disabled port %u\n", i);
1770 }
1771
1772 handled = 1;
1773 }
1774
1775 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1776 * it should be cleared after all the port events are cleared;
1777 * otherwise, it will raise a spurious interrupt after each
1778 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1779 * information.
1780 *
1781 * Also, use the unmasked value to clear interrupt as spurious
1782 * pending event on a dummy port might cause screaming IRQ.
1783 */
1784 writel(irq_stat, mmio + HOST_IRQ_STAT);
1785
1786 spin_unlock(&host->lock);
1787
1788 VPRINTK("EXIT\n");
1789
1790 return IRQ_RETVAL(handled);
1791 }
1792 EXPORT_SYMBOL_GPL(ahci_interrupt);
1793
1794 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1795 {
1796 struct ata_port *ap = qc->ap;
1797 void __iomem *port_mmio = ahci_port_base(ap);
1798 struct ahci_port_priv *pp = ap->private_data;
1799
1800 /* Keep track of the currently active link. It will be used
1801 * in completion path to determine whether NCQ phase is in
1802 * progress.
1803 */
1804 pp->active_link = qc->dev->link;
1805
1806 if (qc->tf.protocol == ATA_PROT_NCQ)
1807 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1808
1809 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1810 u32 fbs = readl(port_mmio + PORT_FBS);
1811 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1812 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1813 writel(fbs, port_mmio + PORT_FBS);
1814 pp->fbs_last_dev = qc->dev->link->pmp;
1815 }
1816
1817 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1818
1819 ahci_sw_activity(qc->dev->link);
1820
1821 return 0;
1822 }
1823
1824 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1825 {
1826 struct ahci_port_priv *pp = qc->ap->private_data;
1827 u8 *rx_fis = pp->rx_fis;
1828
1829 if (pp->fbs_enabled)
1830 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1831
1832 /*
1833 * After a successful execution of an ATA PIO data-in command,
1834 * the device doesn't send D2H Reg FIS to update the TF and
1835 * the host should take TF and E_Status from the preceding PIO
1836 * Setup FIS.
1837 */
1838 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1839 !(qc->flags & ATA_QCFLAG_FAILED)) {
1840 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1841 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1842 } else
1843 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1844
1845 return true;
1846 }
1847
1848 static void ahci_freeze(struct ata_port *ap)
1849 {
1850 void __iomem *port_mmio = ahci_port_base(ap);
1851
1852 /* turn IRQ off */
1853 writel(0, port_mmio + PORT_IRQ_MASK);
1854 }
1855
1856 static void ahci_thaw(struct ata_port *ap)
1857 {
1858 struct ahci_host_priv *hpriv = ap->host->private_data;
1859 void __iomem *mmio = hpriv->mmio;
1860 void __iomem *port_mmio = ahci_port_base(ap);
1861 u32 tmp;
1862 struct ahci_port_priv *pp = ap->private_data;
1863
1864 /* clear IRQ */
1865 tmp = readl(port_mmio + PORT_IRQ_STAT);
1866 writel(tmp, port_mmio + PORT_IRQ_STAT);
1867 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1868
1869 /* turn IRQ back on */
1870 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1871 }
1872
1873 static void ahci_error_handler(struct ata_port *ap)
1874 {
1875 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1876 /* restart engine */
1877 ahci_stop_engine(ap);
1878 ahci_start_engine(ap);
1879 }
1880
1881 sata_pmp_error_handler(ap);
1882
1883 if (!ata_dev_enabled(ap->link.device))
1884 ahci_stop_engine(ap);
1885 }
1886
1887 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1888 {
1889 struct ata_port *ap = qc->ap;
1890
1891 /* make DMA engine forget about the failed command */
1892 if (qc->flags & ATA_QCFLAG_FAILED)
1893 ahci_kick_engine(ap);
1894 }
1895
1896 static void ahci_enable_fbs(struct ata_port *ap)
1897 {
1898 struct ahci_port_priv *pp = ap->private_data;
1899 void __iomem *port_mmio = ahci_port_base(ap);
1900 u32 fbs;
1901 int rc;
1902
1903 if (!pp->fbs_supported)
1904 return;
1905
1906 fbs = readl(port_mmio + PORT_FBS);
1907 if (fbs & PORT_FBS_EN) {
1908 pp->fbs_enabled = true;
1909 pp->fbs_last_dev = -1; /* initialization */
1910 return;
1911 }
1912
1913 rc = ahci_stop_engine(ap);
1914 if (rc)
1915 return;
1916
1917 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
1918 fbs = readl(port_mmio + PORT_FBS);
1919 if (fbs & PORT_FBS_EN) {
1920 dev_printk(KERN_INFO, ap->host->dev, "FBS is enabled.\n");
1921 pp->fbs_enabled = true;
1922 pp->fbs_last_dev = -1; /* initialization */
1923 } else
1924 dev_printk(KERN_ERR, ap->host->dev, "Failed to enable FBS\n");
1925
1926 ahci_start_engine(ap);
1927 }
1928
1929 static void ahci_disable_fbs(struct ata_port *ap)
1930 {
1931 struct ahci_port_priv *pp = ap->private_data;
1932 void __iomem *port_mmio = ahci_port_base(ap);
1933 u32 fbs;
1934 int rc;
1935
1936 if (!pp->fbs_supported)
1937 return;
1938
1939 fbs = readl(port_mmio + PORT_FBS);
1940 if ((fbs & PORT_FBS_EN) == 0) {
1941 pp->fbs_enabled = false;
1942 return;
1943 }
1944
1945 rc = ahci_stop_engine(ap);
1946 if (rc)
1947 return;
1948
1949 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
1950 fbs = readl(port_mmio + PORT_FBS);
1951 if (fbs & PORT_FBS_EN)
1952 dev_printk(KERN_ERR, ap->host->dev, "Failed to disable FBS\n");
1953 else {
1954 dev_printk(KERN_INFO, ap->host->dev, "FBS is disabled.\n");
1955 pp->fbs_enabled = false;
1956 }
1957
1958 ahci_start_engine(ap);
1959 }
1960
1961 static void ahci_pmp_attach(struct ata_port *ap)
1962 {
1963 void __iomem *port_mmio = ahci_port_base(ap);
1964 struct ahci_port_priv *pp = ap->private_data;
1965 u32 cmd;
1966
1967 cmd = readl(port_mmio + PORT_CMD);
1968 cmd |= PORT_CMD_PMP;
1969 writel(cmd, port_mmio + PORT_CMD);
1970
1971 ahci_enable_fbs(ap);
1972
1973 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1974 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1975 }
1976
1977 static void ahci_pmp_detach(struct ata_port *ap)
1978 {
1979 void __iomem *port_mmio = ahci_port_base(ap);
1980 struct ahci_port_priv *pp = ap->private_data;
1981 u32 cmd;
1982
1983 ahci_disable_fbs(ap);
1984
1985 cmd = readl(port_mmio + PORT_CMD);
1986 cmd &= ~PORT_CMD_PMP;
1987 writel(cmd, port_mmio + PORT_CMD);
1988
1989 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1990 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1991 }
1992
1993 static int ahci_port_resume(struct ata_port *ap)
1994 {
1995 ahci_power_up(ap);
1996 ahci_start_port(ap);
1997
1998 if (sata_pmp_attached(ap))
1999 ahci_pmp_attach(ap);
2000 else
2001 ahci_pmp_detach(ap);
2002
2003 return 0;
2004 }
2005
2006 #ifdef CONFIG_PM
2007 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2008 {
2009 const char *emsg = NULL;
2010 int rc;
2011
2012 rc = ahci_deinit_port(ap, &emsg);
2013 if (rc == 0)
2014 ahci_power_down(ap);
2015 else {
2016 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2017 ahci_start_port(ap);
2018 }
2019
2020 return rc;
2021 }
2022 #endif
2023
2024 static int ahci_port_start(struct ata_port *ap)
2025 {
2026 struct ahci_host_priv *hpriv = ap->host->private_data;
2027 struct device *dev = ap->host->dev;
2028 struct ahci_port_priv *pp;
2029 void *mem;
2030 dma_addr_t mem_dma;
2031 size_t dma_sz, rx_fis_sz;
2032
2033 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2034 if (!pp)
2035 return -ENOMEM;
2036
2037 /* check FBS capability */
2038 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2039 void __iomem *port_mmio = ahci_port_base(ap);
2040 u32 cmd = readl(port_mmio + PORT_CMD);
2041 if (cmd & PORT_CMD_FBSCP)
2042 pp->fbs_supported = true;
2043 else
2044 dev_printk(KERN_WARNING, dev,
2045 "The port is not capable of FBS\n");
2046 }
2047
2048 if (pp->fbs_supported) {
2049 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2050 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2051 } else {
2052 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2053 rx_fis_sz = AHCI_RX_FIS_SZ;
2054 }
2055
2056 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2057 if (!mem)
2058 return -ENOMEM;
2059 memset(mem, 0, dma_sz);
2060
2061 /*
2062 * First item in chunk of DMA memory: 32-slot command table,
2063 * 32 bytes each in size
2064 */
2065 pp->cmd_slot = mem;
2066 pp->cmd_slot_dma = mem_dma;
2067
2068 mem += AHCI_CMD_SLOT_SZ;
2069 mem_dma += AHCI_CMD_SLOT_SZ;
2070
2071 /*
2072 * Second item: Received-FIS area
2073 */
2074 pp->rx_fis = mem;
2075 pp->rx_fis_dma = mem_dma;
2076
2077 mem += rx_fis_sz;
2078 mem_dma += rx_fis_sz;
2079
2080 /*
2081 * Third item: data area for storing a single command
2082 * and its scatter-gather table
2083 */
2084 pp->cmd_tbl = mem;
2085 pp->cmd_tbl_dma = mem_dma;
2086
2087 /*
2088 * Save off initial list of interrupts to be enabled.
2089 * This could be changed later
2090 */
2091 pp->intr_mask = DEF_PORT_IRQ;
2092
2093 ap->private_data = pp;
2094
2095 /* engage engines, captain */
2096 return ahci_port_resume(ap);
2097 }
2098
2099 static void ahci_port_stop(struct ata_port *ap)
2100 {
2101 const char *emsg = NULL;
2102 int rc;
2103
2104 /* de-initialize port */
2105 rc = ahci_deinit_port(ap, &emsg);
2106 if (rc)
2107 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2108 }
2109
2110 void ahci_print_info(struct ata_host *host, const char *scc_s)
2111 {
2112 struct ahci_host_priv *hpriv = host->private_data;
2113 void __iomem *mmio = hpriv->mmio;
2114 u32 vers, cap, cap2, impl, speed;
2115 const char *speed_s;
2116
2117 vers = readl(mmio + HOST_VERSION);
2118 cap = hpriv->cap;
2119 cap2 = hpriv->cap2;
2120 impl = hpriv->port_map;
2121
2122 speed = (cap >> 20) & 0xf;
2123 if (speed == 1)
2124 speed_s = "1.5";
2125 else if (speed == 2)
2126 speed_s = "3";
2127 else if (speed == 3)
2128 speed_s = "6";
2129 else
2130 speed_s = "?";
2131
2132 dev_info(host->dev,
2133 "AHCI %02x%02x.%02x%02x "
2134 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2135 ,
2136
2137 (vers >> 24) & 0xff,
2138 (vers >> 16) & 0xff,
2139 (vers >> 8) & 0xff,
2140 vers & 0xff,
2141
2142 ((cap >> 8) & 0x1f) + 1,
2143 (cap & 0x1f) + 1,
2144 speed_s,
2145 impl,
2146 scc_s);
2147
2148 dev_info(host->dev,
2149 "flags: "
2150 "%s%s%s%s%s%s%s"
2151 "%s%s%s%s%s%s%s"
2152 "%s%s%s%s%s%s\n"
2153 ,
2154
2155 cap & HOST_CAP_64 ? "64bit " : "",
2156 cap & HOST_CAP_NCQ ? "ncq " : "",
2157 cap & HOST_CAP_SNTF ? "sntf " : "",
2158 cap & HOST_CAP_MPS ? "ilck " : "",
2159 cap & HOST_CAP_SSS ? "stag " : "",
2160 cap & HOST_CAP_ALPM ? "pm " : "",
2161 cap & HOST_CAP_LED ? "led " : "",
2162 cap & HOST_CAP_CLO ? "clo " : "",
2163 cap & HOST_CAP_ONLY ? "only " : "",
2164 cap & HOST_CAP_PMP ? "pmp " : "",
2165 cap & HOST_CAP_FBS ? "fbs " : "",
2166 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2167 cap & HOST_CAP_SSC ? "slum " : "",
2168 cap & HOST_CAP_PART ? "part " : "",
2169 cap & HOST_CAP_CCC ? "ccc " : "",
2170 cap & HOST_CAP_EMS ? "ems " : "",
2171 cap & HOST_CAP_SXS ? "sxs " : "",
2172 cap2 & HOST_CAP2_APST ? "apst " : "",
2173 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2174 cap2 & HOST_CAP2_BOH ? "boh " : ""
2175 );
2176 }
2177 EXPORT_SYMBOL_GPL(ahci_print_info);
2178
2179 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2180 struct ata_port_info *pi)
2181 {
2182 u8 messages;
2183 void __iomem *mmio = hpriv->mmio;
2184 u32 em_loc = readl(mmio + HOST_EM_LOC);
2185 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2186
2187 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2188 return;
2189
2190 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2191
2192 if (messages) {
2193 /* store em_loc */
2194 hpriv->em_loc = ((em_loc >> 16) * 4);
2195 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2196 hpriv->em_msg_type = messages;
2197 pi->flags |= ATA_FLAG_EM;
2198 if (!(em_ctl & EM_CTL_ALHD))
2199 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2200 }
2201 }
2202 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2203
2204 MODULE_AUTHOR("Jeff Garzik");
2205 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2206 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree