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ASoC: Ensure we delay long enough for WM8994 FLL to lock
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / ahci.c
blobdeb228c98fc90764750dad691107411f265f2c5e
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 };
57
58 enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63
64 /* board IDs for specific chipsets in alphabetical order */
65 board_ahci_mcp65,
66 board_ahci_mcp77,
67 board_ahci_mcp89,
68 board_ahci_mv,
69 board_ahci_sb600,
70 board_ahci_sb700, /* for SB700 and SB800 */
71 board_ahci_vt8251,
72
73 /* aliases */
74 board_ahci_mcp_linux = board_ahci_mcp65,
75 board_ahci_mcp67 = board_ahci_mcp65,
76 board_ahci_mcp73 = board_ahci_mcp65,
77 board_ahci_mcp79 = board_ahci_mcp77,
78 };
79
80 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
81 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
82 unsigned long deadline);
83 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
84 unsigned long deadline);
85 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 #ifdef CONFIG_PM
88 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
89 static int ahci_pci_device_resume(struct pci_dev *pdev);
90 #endif
91
92 static struct scsi_host_template ahci_sht = {
93 AHCI_SHT("ahci"),
94 };
95
96 static struct ata_port_operations ahci_vt8251_ops = {
97 .inherits = &ahci_ops,
98 .hardreset = ahci_vt8251_hardreset,
99 };
100
101 static struct ata_port_operations ahci_p5wdh_ops = {
102 .inherits = &ahci_ops,
103 .hardreset = ahci_p5wdh_hardreset,
104 };
105
106 static struct ata_port_operations ahci_sb600_ops = {
107 .inherits = &ahci_ops,
108 .softreset = ahci_sb600_softreset,
109 .pmp_softreset = ahci_sb600_softreset,
110 };
111
112 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
113
114 static const struct ata_port_info ahci_port_info[] = {
115 /* by features */
116 [board_ahci] =
117 {
118 .flags = AHCI_FLAG_COMMON,
119 .pio_mask = ATA_PIO4,
120 .udma_mask = ATA_UDMA6,
121 .port_ops = &ahci_ops,
122 },
123 [board_ahci_ign_iferr] =
124 {
125 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_nosntf] =
132 {
133 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
134 .flags = AHCI_FLAG_COMMON,
135 .pio_mask = ATA_PIO4,
136 .udma_mask = ATA_UDMA6,
137 .port_ops = &ahci_ops,
138 },
139 /* by chipsets */
140 [board_ahci_mcp65] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
143 AHCI_HFLAG_YES_NCQ),
144 .flags = AHCI_FLAG_COMMON,
145 .pio_mask = ATA_PIO4,
146 .udma_mask = ATA_UDMA6,
147 .port_ops = &ahci_ops,
148 },
149 [board_ahci_mcp77] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
152 .flags = AHCI_FLAG_COMMON,
153 .pio_mask = ATA_PIO4,
154 .udma_mask = ATA_UDMA6,
155 .port_ops = &ahci_ops,
156 },
157 [board_ahci_mcp89] =
158 {
159 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
160 .flags = AHCI_FLAG_COMMON,
161 .pio_mask = ATA_PIO4,
162 .udma_mask = ATA_UDMA6,
163 .port_ops = &ahci_ops,
164 },
165 [board_ahci_mv] =
166 {
167 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
168 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
169 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
170 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
175 [board_ahci_sb600] =
176 {
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_sb600_ops,
184 },
185 [board_ahci_sb700] = /* for SB700 and SB800 */
186 {
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_sb600_ops,
192 },
193 [board_ahci_vt8251] =
194 {
195 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_vt8251_ops,
200 },
201 };
202
203 static const struct pci_device_id ahci_pci_tbl[] = {
204 /* Intel */
205 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
206 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
207 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
208 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
209 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
210 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
211 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
215 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
234 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
244 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
252 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
256
257 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
258 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
259 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
260
261 /* ATI */
262 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
263 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
264 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
265 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
266 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
267 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
268 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
269
270 /* AMD */
271 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
272 /* AMD is using RAID class only for ahci controllers */
273 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
274 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
275
276 /* VIA */
277 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
278 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
279
280 /* NVIDIA */
281 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
282 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
283 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
284 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
285 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
286 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
287 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
290 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
291 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
292 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
293 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
294 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
295 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
302 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
303 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
304 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
305 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
306 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
307 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
318 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
319 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
320 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
321 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
322 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
323 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
330 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
331 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
332 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
333 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
334 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
342 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
343 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
344 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
345 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
346 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
347 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
354 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
355 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
356 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
357 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
358 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
359 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
365
366 /* SiS */
367 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
368 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
369 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
370
371 /* Marvell */
372 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
373 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
374
375 /* Promise */
376 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
377
378 /* Generic, PCI class code for AHCI */
379 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
380 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
381
382 { } /* terminate list */
383 };
384
385
386 static struct pci_driver ahci_pci_driver = {
387 .name = DRV_NAME,
388 .id_table = ahci_pci_tbl,
389 .probe = ahci_init_one,
390 .remove = ata_pci_remove_one,
391 #ifdef CONFIG_PM
392 .suspend = ahci_pci_device_suspend,
393 .resume = ahci_pci_device_resume,
394 #endif
395 };
396
397 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
398 static int marvell_enable;
399 #else
400 static int marvell_enable = 1;
401 #endif
402 module_param(marvell_enable, int, 0644);
403 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
404
405
406 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
407 struct ahci_host_priv *hpriv)
408 {
409 unsigned int force_port_map = 0;
410 unsigned int mask_port_map = 0;
411
412 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
413 dev_info(&pdev->dev, "JMB361 has only one port\n");
414 force_port_map = 1;
415 }
416
417 /*
418 * Temporary Marvell 6145 hack: PATA port presence
419 * is asserted through the standard AHCI port
420 * presence register, as bit 4 (counting from 0)
421 */
422 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
423 if (pdev->device == 0x6121)
424 mask_port_map = 0x3;
425 else
426 mask_port_map = 0xf;
427 dev_info(&pdev->dev,
428 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
429 }
430
431 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
432 mask_port_map);
433 }
434
435 static int ahci_pci_reset_controller(struct ata_host *host)
436 {
437 struct pci_dev *pdev = to_pci_dev(host->dev);
438
439 ahci_reset_controller(host);
440
441 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
442 struct ahci_host_priv *hpriv = host->private_data;
443 u16 tmp16;
444
445 /* configure PCS */
446 pci_read_config_word(pdev, 0x92, &tmp16);
447 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
448 tmp16 |= hpriv->port_map;
449 pci_write_config_word(pdev, 0x92, tmp16);
450 }
451 }
452
453 return 0;
454 }
455
456 static void ahci_pci_init_controller(struct ata_host *host)
457 {
458 struct ahci_host_priv *hpriv = host->private_data;
459 struct pci_dev *pdev = to_pci_dev(host->dev);
460 void __iomem *port_mmio;
461 u32 tmp;
462 int mv;
463
464 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
465 if (pdev->device == 0x6121)
466 mv = 2;
467 else
468 mv = 4;
469 port_mmio = __ahci_port_base(host, mv);
470
471 writel(0, port_mmio + PORT_IRQ_MASK);
472
473 /* clear port IRQ */
474 tmp = readl(port_mmio + PORT_IRQ_STAT);
475 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
476 if (tmp)
477 writel(tmp, port_mmio + PORT_IRQ_STAT);
478 }
479
480 ahci_init_controller(host);
481 }
482
483 static int ahci_sb600_check_ready(struct ata_link *link)
484 {
485 void __iomem *port_mmio = ahci_port_base(link->ap);
486 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
487 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
488
489 /*
490 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
491 * which can save timeout delay.
492 */
493 if (irq_status & PORT_IRQ_BAD_PMP)
494 return -EIO;
495
496 return ata_check_ready(status);
497 }
498
499 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
500 unsigned long deadline)
501 {
502 struct ata_port *ap = link->ap;
503 void __iomem *port_mmio = ahci_port_base(ap);
504 int pmp = sata_srst_pmp(link);
505 int rc;
506 u32 irq_sts;
507
508 DPRINTK("ENTER\n");
509
510 rc = ahci_do_softreset(link, class, pmp, deadline,
511 ahci_sb600_check_ready);
512
513 /*
514 * Soft reset fails on some ATI chips with IPMS set when PMP
515 * is enabled but SATA HDD/ODD is connected to SATA port,
516 * do soft reset again to port 0.
517 */
518 if (rc == -EIO) {
519 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
520 if (irq_sts & PORT_IRQ_BAD_PMP) {
521 ata_link_printk(link, KERN_WARNING,
522 "applying SB600 PMP SRST workaround "
523 "and retrying\n");
524 rc = ahci_do_softreset(link, class, 0, deadline,
525 ahci_check_ready);
526 }
527 }
528
529 return rc;
530 }
531
532 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
533 unsigned long deadline)
534 {
535 struct ata_port *ap = link->ap;
536 bool online;
537 int rc;
538
539 DPRINTK("ENTER\n");
540
541 ahci_stop_engine(ap);
542
543 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
544 deadline, &online, NULL);
545
546 ahci_start_engine(ap);
547
548 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
549
550 /* vt8251 doesn't clear BSY on signature FIS reception,
551 * request follow-up softreset.
552 */
553 return online ? -EAGAIN : rc;
554 }
555
556 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
557 unsigned long deadline)
558 {
559 struct ata_port *ap = link->ap;
560 struct ahci_port_priv *pp = ap->private_data;
561 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
562 struct ata_taskfile tf;
563 bool online;
564 int rc;
565
566 ahci_stop_engine(ap);
567
568 /* clear D2H reception area to properly wait for D2H FIS */
569 ata_tf_init(link->device, &tf);
570 tf.command = 0x80;
571 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
572
573 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
574 deadline, &online, NULL);
575
576 ahci_start_engine(ap);
577
578 /* The pseudo configuration device on SIMG4726 attached to
579 * ASUS P5W-DH Deluxe doesn't send signature FIS after
580 * hardreset if no device is attached to the first downstream
581 * port && the pseudo device locks up on SRST w/ PMP==0. To
582 * work around this, wait for !BSY only briefly. If BSY isn't
583 * cleared, perform CLO and proceed to IDENTIFY (achieved by
584 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
585 *
586 * Wait for two seconds. Devices attached to downstream port
587 * which can't process the following IDENTIFY after this will
588 * have to be reset again. For most cases, this should
589 * suffice while making probing snappish enough.
590 */
591 if (online) {
592 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
593 ahci_check_ready);
594 if (rc)
595 ahci_kick_engine(ap);
596 }
597 return rc;
598 }
599
600 #ifdef CONFIG_PM
601 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
602 {
603 struct ata_host *host = dev_get_drvdata(&pdev->dev);
604 struct ahci_host_priv *hpriv = host->private_data;
605 void __iomem *mmio = hpriv->mmio;
606 u32 ctl;
607
608 if (mesg.event & PM_EVENT_SUSPEND &&
609 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
610 dev_printk(KERN_ERR, &pdev->dev,
611 "BIOS update required for suspend/resume\n");
612 return -EIO;
613 }
614
615 if (mesg.event & PM_EVENT_SLEEP) {
616 /* AHCI spec rev1.1 section 8.3.3:
617 * Software must disable interrupts prior to requesting a
618 * transition of the HBA to D3 state.
619 */
620 ctl = readl(mmio + HOST_CTL);
621 ctl &= ~HOST_IRQ_EN;
622 writel(ctl, mmio + HOST_CTL);
623 readl(mmio + HOST_CTL); /* flush */
624 }
625
626 return ata_pci_device_suspend(pdev, mesg);
627 }
628
629 static int ahci_pci_device_resume(struct pci_dev *pdev)
630 {
631 struct ata_host *host = dev_get_drvdata(&pdev->dev);
632 int rc;
633
634 rc = ata_pci_device_do_resume(pdev);
635 if (rc)
636 return rc;
637
638 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
639 rc = ahci_pci_reset_controller(host);
640 if (rc)
641 return rc;
642
643 ahci_pci_init_controller(host);
644 }
645
646 ata_host_resume(host);
647
648 return 0;
649 }
650 #endif
651
652 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
653 {
654 int rc;
655
656 if (using_dac &&
657 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
658 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
659 if (rc) {
660 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
661 if (rc) {
662 dev_printk(KERN_ERR, &pdev->dev,
663 "64-bit DMA enable failed\n");
664 return rc;
665 }
666 }
667 } else {
668 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
669 if (rc) {
670 dev_printk(KERN_ERR, &pdev->dev,
671 "32-bit DMA enable failed\n");
672 return rc;
673 }
674 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
675 if (rc) {
676 dev_printk(KERN_ERR, &pdev->dev,
677 "32-bit consistent DMA enable failed\n");
678 return rc;
679 }
680 }
681 return 0;
682 }
683
684 static void ahci_pci_print_info(struct ata_host *host)
685 {
686 struct pci_dev *pdev = to_pci_dev(host->dev);
687 u16 cc;
688 const char *scc_s;
689
690 pci_read_config_word(pdev, 0x0a, &cc);
691 if (cc == PCI_CLASS_STORAGE_IDE)
692 scc_s = "IDE";
693 else if (cc == PCI_CLASS_STORAGE_SATA)
694 scc_s = "SATA";
695 else if (cc == PCI_CLASS_STORAGE_RAID)
696 scc_s = "RAID";
697 else
698 scc_s = "unknown";
699
700 ahci_print_info(host, scc_s);
701 }
702
703 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
704 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
705 * support PMP and the 4726 either directly exports the device
706 * attached to the first downstream port or acts as a hardware storage
707 * controller and emulate a single ATA device (can be RAID 0/1 or some
708 * other configuration).
709 *
710 * When there's no device attached to the first downstream port of the
711 * 4726, "Config Disk" appears, which is a pseudo ATA device to
712 * configure the 4726. However, ATA emulation of the device is very
713 * lame. It doesn't send signature D2H Reg FIS after the initial
714 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
715 *
716 * The following function works around the problem by always using
717 * hardreset on the port and not depending on receiving signature FIS
718 * afterward. If signature FIS isn't received soon, ATA class is
719 * assumed without follow-up softreset.
720 */
721 static void ahci_p5wdh_workaround(struct ata_host *host)
722 {
723 static struct dmi_system_id sysids[] = {
724 {
725 .ident = "P5W DH Deluxe",
726 .matches = {
727 DMI_MATCH(DMI_SYS_VENDOR,
728 "ASUSTEK COMPUTER INC"),
729 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
730 },
731 },
732 { }
733 };
734 struct pci_dev *pdev = to_pci_dev(host->dev);
735
736 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
737 dmi_check_system(sysids)) {
738 struct ata_port *ap = host->ports[1];
739
740 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
741 "Deluxe on-board SIMG4726 workaround\n");
742
743 ap->ops = &ahci_p5wdh_ops;
744 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
745 }
746 }
747
748 /* only some SB600 ahci controllers can do 64bit DMA */
749 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
750 {
751 static const struct dmi_system_id sysids[] = {
752 /*
753 * The oldest version known to be broken is 0901 and
754 * working is 1501 which was released on 2007-10-26.
755 * Enable 64bit DMA on 1501 and anything newer.
756 *
757 * Please read bko#9412 for more info.
758 */
759 {
760 .ident = "ASUS M2A-VM",
761 .matches = {
762 DMI_MATCH(DMI_BOARD_VENDOR,
763 "ASUSTeK Computer INC."),
764 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
765 },
766 .driver_data = "20071026", /* yyyymmdd */
767 },
768 /*
769 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
770 * support 64bit DMA.
771 *
772 * BIOS versions earlier than 1.5 had the Manufacturer DMI
773 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
774 * This spelling mistake was fixed in BIOS version 1.5, so
775 * 1.5 and later have the Manufacturer as
776 * "MICRO-STAR INTERNATIONAL CO.,LTD".
777 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
778 *
779 * BIOS versions earlier than 1.9 had a Board Product Name
780 * DMI field of "MS-7376". This was changed to be
781 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
782 * match on DMI_BOARD_NAME of "MS-7376".
783 */
784 {
785 .ident = "MSI K9A2 Platinum",
786 .matches = {
787 DMI_MATCH(DMI_BOARD_VENDOR,
788 "MICRO-STAR INTER"),
789 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
790 },
791 },
792 { }
793 };
794 const struct dmi_system_id *match;
795 int year, month, date;
796 char buf[9];
797
798 match = dmi_first_match(sysids);
799 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
800 !match)
801 return false;
802
803 if (!match->driver_data)
804 goto enable_64bit;
805
806 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
807 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
808
809 if (strcmp(buf, match->driver_data) >= 0)
810 goto enable_64bit;
811 else {
812 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
813 "forcing 32bit DMA, update BIOS\n", match->ident);
814 return false;
815 }
816
817 enable_64bit:
818 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
819 match->ident);
820 return true;
821 }
822
823 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
824 {
825 static const struct dmi_system_id broken_systems[] = {
826 {
827 .ident = "HP Compaq nx6310",
828 .matches = {
829 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
830 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
831 },
832 /* PCI slot number of the controller */
833 .driver_data = (void *)0x1FUL,
834 },
835 {
836 .ident = "HP Compaq 6720s",
837 .matches = {
838 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
839 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
840 },
841 /* PCI slot number of the controller */
842 .driver_data = (void *)0x1FUL,
843 },
844
845 { } /* terminate list */
846 };
847 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
848
849 if (dmi) {
850 unsigned long slot = (unsigned long)dmi->driver_data;
851 /* apply the quirk only to on-board controllers */
852 return slot == PCI_SLOT(pdev->devfn);
853 }
854
855 return false;
856 }
857
858 static bool ahci_broken_suspend(struct pci_dev *pdev)
859 {
860 static const struct dmi_system_id sysids[] = {
861 /*
862 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
863 * to the harddisk doesn't become online after
864 * resuming from STR. Warn and fail suspend.
865 *
866 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
867 *
868 * Use dates instead of versions to match as HP is
869 * apparently recycling both product and version
870 * strings.
871 *
872 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
873 */
874 {
875 .ident = "dv4",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
878 DMI_MATCH(DMI_PRODUCT_NAME,
879 "HP Pavilion dv4 Notebook PC"),
880 },
881 .driver_data = "20090105", /* F.30 */
882 },
883 {
884 .ident = "dv5",
885 .matches = {
886 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
887 DMI_MATCH(DMI_PRODUCT_NAME,
888 "HP Pavilion dv5 Notebook PC"),
889 },
890 .driver_data = "20090506", /* F.16 */
891 },
892 {
893 .ident = "dv6",
894 .matches = {
895 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
896 DMI_MATCH(DMI_PRODUCT_NAME,
897 "HP Pavilion dv6 Notebook PC"),
898 },
899 .driver_data = "20090423", /* F.21 */
900 },
901 {
902 .ident = "HDX18",
903 .matches = {
904 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
905 DMI_MATCH(DMI_PRODUCT_NAME,
906 "HP HDX18 Notebook PC"),
907 },
908 .driver_data = "20090430", /* F.23 */
909 },
910 /*
911 * Acer eMachines G725 has the same problem. BIOS
912 * V1.03 is known to be broken. V3.04 is known to
913 * work. Inbetween, there are V1.06, V2.06 and V3.03
914 * that we don't have much idea about. For now,
915 * blacklist anything older than V3.04.
916 *
917 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
918 */
919 {
920 .ident = "G725",
921 .matches = {
922 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
923 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
924 },
925 .driver_data = "20091216", /* V3.04 */
926 },
927 { } /* terminate list */
928 };
929 const struct dmi_system_id *dmi = dmi_first_match(sysids);
930 int year, month, date;
931 char buf[9];
932
933 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
934 return false;
935
936 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
937 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
938
939 return strcmp(buf, dmi->driver_data) < 0;
940 }
941
942 static bool ahci_broken_online(struct pci_dev *pdev)
943 {
944 #define ENCODE_BUSDEVFN(bus, slot, func) \
945 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
946 static const struct dmi_system_id sysids[] = {
947 /*
948 * There are several gigabyte boards which use
949 * SIMG5723s configured as hardware RAID. Certain
950 * 5723 firmware revisions shipped there keep the link
951 * online but fail to answer properly to SRST or
952 * IDENTIFY when no device is attached downstream
953 * causing libata to retry quite a few times leading
954 * to excessive detection delay.
955 *
956 * As these firmwares respond to the second reset try
957 * with invalid device signature, considering unknown
958 * sig as offline works around the problem acceptably.
959 */
960 {
961 .ident = "EP45-DQ6",
962 .matches = {
963 DMI_MATCH(DMI_BOARD_VENDOR,
964 "Gigabyte Technology Co., Ltd."),
965 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
966 },
967 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
968 },
969 {
970 .ident = "EP45-DS5",
971 .matches = {
972 DMI_MATCH(DMI_BOARD_VENDOR,
973 "Gigabyte Technology Co., Ltd."),
974 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
975 },
976 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
977 },
978 { } /* terminate list */
979 };
980 #undef ENCODE_BUSDEVFN
981 const struct dmi_system_id *dmi = dmi_first_match(sysids);
982 unsigned int val;
983
984 if (!dmi)
985 return false;
986
987 val = (unsigned long)dmi->driver_data;
988
989 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
990 }
991
992 #ifdef CONFIG_ATA_ACPI
993 static void ahci_gtf_filter_workaround(struct ata_host *host)
994 {
995 static const struct dmi_system_id sysids[] = {
996 /*
997 * Aspire 3810T issues a bunch of SATA enable commands
998 * via _GTF including an invalid one and one which is
999 * rejected by the device. Among the successful ones
1000 * is FPDMA non-zero offset enable which when enabled
1001 * only on the drive side leads to NCQ command
1002 * failures. Filter it out.
1003 */
1004 {
1005 .ident = "Aspire 3810T",
1006 .matches = {
1007 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1008 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1009 },
1010 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1011 },
1012 { }
1013 };
1014 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1015 unsigned int filter;
1016 int i;
1017
1018 if (!dmi)
1019 return;
1020
1021 filter = (unsigned long)dmi->driver_data;
1022 dev_printk(KERN_INFO, host->dev,
1023 "applying extra ACPI _GTF filter 0x%x for %s\n",
1024 filter, dmi->ident);
1025
1026 for (i = 0; i < host->n_ports; i++) {
1027 struct ata_port *ap = host->ports[i];
1028 struct ata_link *link;
1029 struct ata_device *dev;
1030
1031 ata_for_each_link(link, ap, EDGE)
1032 ata_for_each_dev(dev, link, ALL)
1033 dev->gtf_filter |= filter;
1034 }
1035 }
1036 #else
1037 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1038 {}
1039 #endif
1040
1041 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1042 {
1043 static int printed_version;
1044 unsigned int board_id = ent->driver_data;
1045 struct ata_port_info pi = ahci_port_info[board_id];
1046 const struct ata_port_info *ppi[] = { &pi, NULL };
1047 struct device *dev = &pdev->dev;
1048 struct ahci_host_priv *hpriv;
1049 struct ata_host *host;
1050 int n_ports, i, rc;
1051
1052 VPRINTK("ENTER\n");
1053
1054 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1055
1056 if (!printed_version++)
1057 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1058
1059 /* The AHCI driver can only drive the SATA ports, the PATA driver
1060 can drive them all so if both drivers are selected make sure
1061 AHCI stays out of the way */
1062 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1063 return -ENODEV;
1064
1065 /*
1066 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1067 * ahci, use ata_generic instead.
1068 */
1069 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1070 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1071 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1072 pdev->subsystem_device == 0xcb89)
1073 return -ENODEV;
1074
1075 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1076 * At the moment, we can only use the AHCI mode. Let the users know
1077 * that for SAS drives they're out of luck.
1078 */
1079 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1080 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1081 "can only drive SATA devices with this driver\n");
1082
1083 /* acquire resources */
1084 rc = pcim_enable_device(pdev);
1085 if (rc)
1086 return rc;
1087
1088 /* AHCI controllers often implement SFF compatible interface.
1089 * Grab all PCI BARs just in case.
1090 */
1091 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1092 if (rc == -EBUSY)
1093 pcim_pin_device(pdev);
1094 if (rc)
1095 return rc;
1096
1097 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1098 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1099 u8 map;
1100
1101 /* ICH6s share the same PCI ID for both piix and ahci
1102 * modes. Enabling ahci mode while MAP indicates
1103 * combined mode is a bad idea. Yield to ata_piix.
1104 */
1105 pci_read_config_byte(pdev, ICH_MAP, &map);
1106 if (map & 0x3) {
1107 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1108 "combined mode, can't enable AHCI mode\n");
1109 return -ENODEV;
1110 }
1111 }
1112
1113 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1114 if (!hpriv)
1115 return -ENOMEM;
1116 hpriv->flags |= (unsigned long)pi.private_data;
1117
1118 /* MCP65 revision A1 and A2 can't do MSI */
1119 if (board_id == board_ahci_mcp65 &&
1120 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1121 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1122
1123 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1124 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1125 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1126
1127 /* only some SB600s can do 64bit DMA */
1128 if (ahci_sb600_enable_64bit(pdev))
1129 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1130
1131 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1132 pci_intx(pdev, 1);
1133
1134 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1135
1136 /* save initial config */
1137 ahci_pci_save_initial_config(pdev, hpriv);
1138
1139 /* prepare host */
1140 if (hpriv->cap & HOST_CAP_NCQ) {
1141 pi.flags |= ATA_FLAG_NCQ;
1142 /*
1143 * Auto-activate optimization is supposed to be
1144 * supported on all AHCI controllers indicating NCQ
1145 * capability, but it seems to be broken on some
1146 * chipsets including NVIDIAs.
1147 */
1148 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1149 pi.flags |= ATA_FLAG_FPDMA_AA;
1150 }
1151
1152 if (hpriv->cap & HOST_CAP_PMP)
1153 pi.flags |= ATA_FLAG_PMP;
1154
1155 ahci_set_em_messages(hpriv, &pi);
1156
1157 if (ahci_broken_system_poweroff(pdev)) {
1158 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1159 dev_info(&pdev->dev,
1160 "quirky BIOS, skipping spindown on poweroff\n");
1161 }
1162
1163 if (ahci_broken_suspend(pdev)) {
1164 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1165 dev_printk(KERN_WARNING, &pdev->dev,
1166 "BIOS update required for suspend/resume\n");
1167 }
1168
1169 if (ahci_broken_online(pdev)) {
1170 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1171 dev_info(&pdev->dev,
1172 "online status unreliable, applying workaround\n");
1173 }
1174
1175 /* CAP.NP sometimes indicate the index of the last enabled
1176 * port, at other times, that of the last possible port, so
1177 * determining the maximum port number requires looking at
1178 * both CAP.NP and port_map.
1179 */
1180 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1181
1182 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1183 if (!host)
1184 return -ENOMEM;
1185 host->private_data = hpriv;
1186
1187 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1188 host->flags |= ATA_HOST_PARALLEL_SCAN;
1189 else
1190 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1191
1192 if (pi.flags & ATA_FLAG_EM)
1193 ahci_reset_em(host);
1194
1195 for (i = 0; i < host->n_ports; i++) {
1196 struct ata_port *ap = host->ports[i];
1197
1198 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1199 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1200 0x100 + ap->port_no * 0x80, "port");
1201
1202 /* set initial link pm policy */
1203 ap->pm_policy = NOT_AVAILABLE;
1204
1205 /* set enclosure management message type */
1206 if (ap->flags & ATA_FLAG_EM)
1207 ap->em_message_type = hpriv->em_msg_type;
1208
1209
1210 /* disabled/not-implemented port */
1211 if (!(hpriv->port_map & (1 << i)))
1212 ap->ops = &ata_dummy_port_ops;
1213 }
1214
1215 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1216 ahci_p5wdh_workaround(host);
1217
1218 /* apply gtf filter quirk */
1219 ahci_gtf_filter_workaround(host);
1220
1221 /* initialize adapter */
1222 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1223 if (rc)
1224 return rc;
1225
1226 rc = ahci_pci_reset_controller(host);
1227 if (rc)
1228 return rc;
1229
1230 ahci_pci_init_controller(host);
1231 ahci_pci_print_info(host);
1232
1233 pci_set_master(pdev);
1234 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1235 &ahci_sht);
1236 }
1237
1238 static int __init ahci_init(void)
1239 {
1240 return pci_register_driver(&ahci_pci_driver);
1241 }
1242
1243 static void __exit ahci_exit(void)
1244 {
1245 pci_unregister_driver(&ahci_pci_driver);
1246 }
1247
1248
1249 MODULE_AUTHOR("Jeff Garzik");
1250 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1251 MODULE_LICENSE("GPL");
1252 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1253 MODULE_VERSION(DRV_VERSION);
1254
1255 module_init(ahci_init);
1256 module_exit(ahci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree