arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/sched.h>
   8 #include <linux/thread_info.h>
   9 #include <linux/module.h>
  10 #include <linux/uaccess.h>
  11
  12 #include <asm/processor.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/msr.h>
  15 #include <asm/bugs.h>
  16 #include <asm/cpu.h>
  17
  18 #ifdef CONFIG_X86_64
  19 #include <linux/topology.h>
  20 #include <asm/numa_64.h>
  21 #endif
  22
  23 #include "cpu.h"
  24
  25 #ifdef CONFIG_X86_LOCAL_APIC
  26 #include <asm/mpspec.h>
  27 #include <asm/apic.h>
  28 #endif
  29
  30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  31 {
  32         u64 misc_enable;
  33
  34         /* Unmask CPUID levels if masked: */
  35         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
  36                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  37
  38                 if (misc_enable & MSR_IA32_MISC_ENABLE_LIMIT_CPUID) {
  39                         misc_enable &= ~MSR_IA32_MISC_ENABLE_LIMIT_CPUID;
  40                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
  41                         c->cpuid_level = cpuid_eax(0);
  42                         get_cpu_cap(c);
  43                 }
  44         }
  45
  46         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  47                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  48                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  49
  50         if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
  51                 unsigned lower_word;
  52
  53                 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
  54                 /* Required by the SDM */
  55                 sync_core();
  56                 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
  57         }
  58
  59         /*
  60          * Atom erratum AAE44/AAF40/AAG38/AAH41:
  61          *
  62          * A race condition between speculative fetches and invalidating
  63          * a large page.  This is worked around in microcode, but we
  64          * need the microcode to have already been loaded... so if it is
  65          * not, recommend a BIOS update and disable large pages.
  66          */
  67         if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2) {
  68                 u32 ucode, junk;
  69
  70                 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
  71                 sync_core();
  72                 rdmsr(MSR_IA32_UCODE_REV, junk, ucode);
  73
  74                 if (ucode < 0x20e) {
  75                         printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
  76                         clear_cpu_cap(c, X86_FEATURE_PSE);
  77                 }
  78         }
  79
  80 #ifdef CONFIG_X86_64
  81         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  82 #else
  83         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  84         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  85                 c->x86_cache_alignment = 128;
  86 #endif
  87
  88         /* CPUID workaround for 0F33/0F34 CPU */
  89         if (c->x86 == 0xF && c->x86_model == 0x3
  90             && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
  91                 c->x86_phys_bits = 36;
  92
  93         /*
  94          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  95          * with P/T states and does not stop in deep C-states.
  96          *
  97          * It is also reliable across cores and sockets. (but not across
  98          * cabinets - we turn it off in that case explicitly.)
  99          */
 100         if (c->x86_power & (1 << 8)) {
 101                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 102                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 103                 if (!check_tsc_unstable())
 104                         sched_clock_stable = 1;
 105         }
 106
 107         /*
 108          * There is a known erratum on Pentium III and Core Solo
 109          * and Core Duo CPUs.
 110          * " Page with PAT set to WC while associated MTRR is UC
 111          *   may consolidate to UC "
 112          * Because of this erratum, it is better to stick with
 113          * setting WC in MTRR rather than using PAT on these CPUs.
 114          *
 115          * Enable PAT WC only on P4, Core 2 or later CPUs.
 116          */
 117         if (c->x86 == 6 && c->x86_model < 15)
 118                 clear_cpu_cap(c, X86_FEATURE_PAT);
 119
 120 #ifdef CONFIG_KMEMCHECK
 121         /*
 122          * P4s have a "fast strings" feature which causes single-
 123          * stepping REP instructions to only generate a #DB on
 124          * cache-line boundaries.
 125          *
 126          * Ingo Molnar reported a Pentium D (model 6) and a Xeon
 127          * (model 2) with the same problem.
 128          */
 129         if (c->x86 == 15) {
 130                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 131
 132                 if (misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING) {
 133                         printk(KERN_INFO "kmemcheck: Disabling fast string operations\n");
 134
 135                         misc_enable &= ~MSR_IA32_MISC_ENABLE_FAST_STRING;
 136                         wrmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 137                 }
 138         }
 139 #endif
 140
 141         /*
 142          * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
 143          * clear the fast string and enhanced fast string CPU capabilities.
 144          */
 145         if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
 146                 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
 147                 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
 148                         printk(KERN_INFO "Disabled fast string operations\n");
 149                         setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
 150                         setup_clear_cpu_cap(X86_FEATURE_ERMS);
 151                 }
 152         }
 153 }
 154
 155 #ifdef CONFIG_X86_32
 156 /*
 157  *      Early probe support logic for ppro memory erratum #50
 158  *
 159  *      This is called before we do cpu ident work
 160  */
 161
 162 int __cpuinit ppro_with_ram_bug(void)
 163 {
 164         /* Uses data from early_cpu_detect now */
 165         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 166             boot_cpu_data.x86 == 6 &&
 167             boot_cpu_data.x86_model == 1 &&
 168             boot_cpu_data.x86_mask < 8) {
 169                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
 170                 return 1;
 171         }
 172         return 0;
 173 }
 174
 175 #ifdef CONFIG_X86_F00F_BUG
 176 static void __cpuinit trap_init_f00f_bug(void)
 177 {
 178         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 179
 180         /*
 181          * Update the IDT descriptor and reload the IDT so that
 182          * it uses the read-only mapped virtual address.
 183          */
 184         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
 185         load_idt(&idt_descr);
 186 }
 187 #endif
 188
 189 static void __cpuinit intel_smp_check(struct cpuinfo_x86 *c)
 190 {
 191 #ifdef CONFIG_SMP
 192         /* calling is from identify_secondary_cpu() ? */
 193         if (!c->cpu_index)
 194                 return;
 195
 196         /*
 197          * Mask B, Pentium, but not Pentium MMX
 198          */
 199         if (c->x86 == 5 &&
 200             c->x86_mask >= 1 && c->x86_mask <= 4 &&
 201             c->x86_model <= 3) {
 202                 /*
 203                  * Remember we have B step Pentia with bugs
 204                  */
 205                 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
 206                                     "with B stepping processors.\n");
 207         }
 208 #endif
 209 }
 210
 211 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 212 {
 213         unsigned long lo, hi;
 214
 215 #ifdef CONFIG_X86_F00F_BUG
 216         /*
 217          * All current models of Pentium and Pentium with MMX technology CPUs
 218          * have the F0 0F bug, which lets nonprivileged users lock up the
 219          * system.
 220          * Note that the workaround only should be initialized once...
 221          */
 222         c->f00f_bug = 0;
 223         if (!paravirt_enabled() && c->x86 == 5) {
 224                 static int f00f_workaround_enabled;
 225
 226                 c->f00f_bug = 1;
 227                 if (!f00f_workaround_enabled) {
 228                         trap_init_f00f_bug();
 229                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 230                         f00f_workaround_enabled = 1;
 231                 }
 232         }
 233 #endif
 234
 235         /*
 236          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 237          * model 3 mask 3
 238          */
 239         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 240                 clear_cpu_cap(c, X86_FEATURE_SEP);
 241
 242         /*
 243          * P4 Xeon errata 037 workaround.
 244          * Hardware prefetcher may cause stale data to be loaded into the cache.
 245          */
 246         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 247                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 248                 if ((lo & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE) == 0) {
 249                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 250                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 251                         lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
 252                         wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 253                 }
 254         }
 255
 256         /*
 257          * See if we have a good local APIC by checking for buggy Pentia,
 258          * i.e. all B steppings and the C2 stepping of P54C when using their
 259          * integrated APIC (see 11AP erratum in "Pentium Processor
 260          * Specification Update").
 261          */
 262         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 263             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 264                 set_cpu_cap(c, X86_FEATURE_11AP);
 265
 266
 267 #ifdef CONFIG_X86_INTEL_USERCOPY
 268         /*
 269          * Set up the preferred alignment for movsl bulk memory moves
 270          */
 271         switch (c->x86) {
 272         case 4:         /* 486: untested */
 273                 break;
 274         case 5:         /* Old Pentia: untested */
 275                 break;
 276         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 277                 movsl_mask.mask = 7;
 278                 break;
 279         case 15:        /* P4 is OK down to 8-byte alignment */
 280                 movsl_mask.mask = 7;
 281                 break;
 282         }
 283 #endif
 284
 285 #ifdef CONFIG_X86_NUMAQ
 286         numaq_tsc_disable();
 287 #endif
 288
 289         intel_smp_check(c);
 290 }
 291 #else
 292 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 293 {
 294 }
 295 #endif
 296
 297 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 298 {
 299 #ifdef CONFIG_NUMA
 300         unsigned node;
 301         int cpu = smp_processor_id();
 302
 303         /* Don't do the funky fallback heuristics the AMD version employs
 304            for now. */
 305         node = numa_cpu_node(cpu);
 306         if (node == NUMA_NO_NODE || !node_online(node)) {
 307                 /* reuse the value from init_cpu_to_node() */
 308                 node = cpu_to_node(cpu);
 309         }
 310         numa_set_node(cpu, node);
 311 #endif
 312 }
 313
 314 /*
 315  * find out the number of processor cores on the die
 316  */
 317 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 318 {
 319         unsigned int eax, ebx, ecx, edx;
 320
 321         if (c->cpuid_level < 4)
 322                 return 1;
 323
 324         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 325         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 326         if (eax & 0x1f)
 327                 return (eax >> 26) + 1;
 328         else
 329                 return 1;
 330 }
 331
 332 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 333 {
 334         /* Intel VMX MSR indicated features */
 335 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 336 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 337 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 338 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 339 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 340 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 341
 342         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 343
 344         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 345         clear_cpu_cap(c, X86_FEATURE_VNMI);
 346         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 347         clear_cpu_cap(c, X86_FEATURE_EPT);
 348         clear_cpu_cap(c, X86_FEATURE_VPID);
 349
 350         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 351         msr_ctl = vmx_msr_high | vmx_msr_low;
 352         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 353                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 354         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 355                 set_cpu_cap(c, X86_FEATURE_VNMI);
 356         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 357                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 358                       vmx_msr_low, vmx_msr_high);
 359                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 360                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 361                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 362                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 363                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 364                         set_cpu_cap(c, X86_FEATURE_EPT);
 365                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 366                         set_cpu_cap(c, X86_FEATURE_VPID);
 367         }
 368 }
 369
 370 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 371 {
 372         unsigned int l2 = 0;
 373
 374         early_init_intel(c);
 375
 376         intel_workarounds(c);
 377
 378         /*
 379          * Detect the extended topology information if available. This
 380          * will reinitialise the initial_apicid which will be used
 381          * in init_intel_cacheinfo()
 382          */
 383         detect_extended_topology(c);
 384
 385         l2 = init_intel_cacheinfo(c);
 386         if (c->cpuid_level > 9) {
 387                 unsigned eax = cpuid_eax(10);
 388                 /* Check for version and the number of counters */
 389                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 390                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 391         }
 392
 393         if (cpu_has_xmm2)
 394                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 395         if (cpu_has_ds) {
 396                 unsigned int l1;
 397                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 398                 if (!(l1 & (1<<11)))
 399                         set_cpu_cap(c, X86_FEATURE_BTS);
 400                 if (!(l1 & (1<<12)))
 401                         set_cpu_cap(c, X86_FEATURE_PEBS);
 402         }
 403
 404         if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
 405                 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
 406
 407 #ifdef CONFIG_X86_64
 408         if (c->x86 == 15)
 409                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 410         if (c->x86 == 6)
 411                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 412 #else
 413         /*
 414          * Names for the Pentium II/Celeron processors
 415          * detectable only by also checking the cache size.
 416          * Dixon is NOT a Celeron.
 417          */
 418         if (c->x86 == 6) {
 419                 char *p = NULL;
 420
 421                 switch (c->x86_model) {
 422                 case 5:
 423                         if (l2 == 0)
 424                                 p = "Celeron (Covington)";
 425                         else if (l2 == 256)
 426                                 p = "Mobile Pentium II (Dixon)";
 427                         break;
 428
 429                 case 6:
 430                         if (l2 == 128)
 431                                 p = "Celeron (Mendocino)";
 432                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 433                                 p = "Celeron-A";
 434                         break;
 435
 436                 case 8:
 437                         if (l2 == 128)
 438                                 p = "Celeron (Coppermine)";
 439                         break;
 440                 }
 441
 442                 if (p)
 443                         strcpy(c->x86_model_id, p);
 444         }
 445
 446         if (c->x86 == 15)
 447                 set_cpu_cap(c, X86_FEATURE_P4);
 448         if (c->x86 == 6)
 449                 set_cpu_cap(c, X86_FEATURE_P3);
 450 #endif
 451
 452         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 453                 /*
 454                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 455                  * detection.
 456                  */
 457                 c->x86_max_cores = intel_num_cpu_cores(c);
 458 #ifdef CONFIG_X86_32
 459                 detect_ht(c);
 460 #endif
 461         }
 462
 463         /* Work around errata */
 464         srat_detect_node(c);
 465
 466         if (cpu_has(c, X86_FEATURE_VMX))
 467                 detect_vmx_virtcap(c);
 468
 469         /*
 470          * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
 471          * x86_energy_perf_policy(8) is available to change it at run-time
 472          */
 473         if (cpu_has(c, X86_FEATURE_EPB)) {
 474                 u64 epb;
 475
 476                 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
 477                 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
 478                         printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
 479                                 " Set to 'normal', was 'performance'\n"
 480                                 "ENERGY_PERF_BIAS: View and update with"
 481                                 " x86_energy_perf_policy(8)\n");
 482                         epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
 483                         wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
 484                 }
 485         }
 486 }
 487
 488 #ifdef CONFIG_X86_32
 489 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 490 {
 491         /*
 492          * Intel PIII Tualatin. This comes in two flavours.
 493          * One has 256kb of cache, the other 512. We have no way
 494          * to determine which, so we use a boottime override
 495          * for the 512kb model, and assume 256 otherwise.
 496          */
 497         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 498                 size = 256;
 499         return size;
 500 }
 501 #endif
 502
 503 static const struct cpu_dev __cpuinitconst intel_cpu_dev = {
 504         .c_vendor       = "Intel",
 505         .c_ident        = { "GenuineIntel" },
 506 #ifdef CONFIG_X86_32
 507         .c_models = {
 508                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 509                   {
 510                           [0] = "486 DX-25/33",
 511                           [1] = "486 DX-50",
 512                           [2] = "486 SX",
 513                           [3] = "486 DX/2",
 514                           [4] = "486 SL",
 515                           [5] = "486 SX/2",
 516                           [7] = "486 DX/2-WB",
 517                           [8] = "486 DX/4",
 518                           [9] = "486 DX/4-WB"
 519                   }
 520                 },
 521                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 522                   {
 523                           [0] = "Pentium 60/66 A-step",
 524                           [1] = "Pentium 60/66",
 525                           [2] = "Pentium 75 - 200",
 526                           [3] = "OverDrive PODP5V83",
 527                           [4] = "Pentium MMX",
 528                           [7] = "Mobile Pentium 75 - 200",
 529                           [8] = "Mobile Pentium MMX"
 530                   }
 531                 },
 532                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 533                   {
 534                           [0] = "Pentium Pro A-step",
 535                           [1] = "Pentium Pro",
 536                           [3] = "Pentium II (Klamath)",
 537                           [4] = "Pentium II (Deschutes)",
 538                           [5] = "Pentium II (Deschutes)",
 539                           [6] = "Mobile Pentium II",
 540                           [7] = "Pentium III (Katmai)",
 541                           [8] = "Pentium III (Coppermine)",
 542                           [10] = "Pentium III (Cascades)",
 543                           [11] = "Pentium III (Tualatin)",
 544                   }
 545                 },
 546                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 547                   {
 548                           [0] = "Pentium 4 (Unknown)",
 549                           [1] = "Pentium 4 (Willamette)",
 550                           [2] = "Pentium 4 (Northwood)",
 551                           [4] = "Pentium 4 (Foster)",
 552                           [5] = "Pentium 4 (Foster)",
 553                   }
 554                 },
 555         },
 556         .c_size_cache   = intel_size_cache,
 557 #endif
 558         .c_early_init   = early_init_intel,
 559         .c_init         = init_intel,
 560         .c_x86_vendor   = X86_VENDOR_INTEL,
 561 };
 562
 563 cpu_dev_register(intel_cpu_dev);
 564