?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
stmmac: mask mmc interrupts
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_main.c
blob72cd190b9c1a0734d401b193e1bd7b12cb49b3af
1 /*******************************************************************************
2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
3 ST Ethernet IPs are built around a Synopsys IP Core.
4
5 Copyright(C) 2007-2011 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24
25 Documentation available at:
26 http://www.stlinux.com
27 Support available at:
28 https://bugzilla.stlinux.com/
29 *******************************************************************************/
30
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/kernel.h>
34 #include <linux/interrupt.h>
35 #include <linux/etherdevice.h>
36 #include <linux/platform_device.h>
37 #include <linux/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/skbuff.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_ether.h>
42 #include <linux/crc32.h>
43 #include <linux/mii.h>
44 #include <linux/if.h>
45 #include <linux/if_vlan.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/slab.h>
48 #include <linux/prefetch.h>
49 #ifdef CONFIG_STMMAC_DEBUG_FS
50 #include <linux/debugfs.h>
51 #include <linux/seq_file.h>
52 #endif
53 #include "stmmac.h"
54
55 #define STMMAC_RESOURCE_NAME "stmmaceth"
56
57 #undef STMMAC_DEBUG
58 /*#define STMMAC_DEBUG*/
59 #ifdef STMMAC_DEBUG
60 #define DBG(nlevel, klevel, fmt, args...) \
61 ((void)(netif_msg_##nlevel(priv) && \
62 printk(KERN_##klevel fmt, ## args)))
63 #else
64 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
65 #endif
66
67 #undef STMMAC_RX_DEBUG
68 /*#define STMMAC_RX_DEBUG*/
69 #ifdef STMMAC_RX_DEBUG
70 #define RX_DBG(fmt, args...) printk(fmt, ## args)
71 #else
72 #define RX_DBG(fmt, args...) do { } while (0)
73 #endif
74
75 #undef STMMAC_XMIT_DEBUG
76 /*#define STMMAC_XMIT_DEBUG*/
77 #ifdef STMMAC_TX_DEBUG
78 #define TX_DBG(fmt, args...) printk(fmt, ## args)
79 #else
80 #define TX_DBG(fmt, args...) do { } while (0)
81 #endif
82
83 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
84 #define JUMBO_LEN 9000
85
86 /* Module parameters */
87 #define TX_TIMEO 5000 /* default 5 seconds */
88 static int watchdog = TX_TIMEO;
89 module_param(watchdog, int, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
91
92 static int debug = -1; /* -1: default, 0: no output, 16: all */
93 module_param(debug, int, S_IRUGO | S_IWUSR);
94 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
95
96 static int phyaddr = -1;
97 module_param(phyaddr, int, S_IRUGO);
98 MODULE_PARM_DESC(phyaddr, "Physical device address");
99
100 #define DMA_TX_SIZE 256
101 static int dma_txsize = DMA_TX_SIZE;
102 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
103 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
104
105 #define DMA_RX_SIZE 256
106 static int dma_rxsize = DMA_RX_SIZE;
107 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
108 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
109
110 static int flow_ctrl = FLOW_OFF;
111 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
112 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
113
114 static int pause = PAUSE_TIME;
115 module_param(pause, int, S_IRUGO | S_IWUSR);
116 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
117
118 #define TC_DEFAULT 64
119 static int tc = TC_DEFAULT;
120 module_param(tc, int, S_IRUGO | S_IWUSR);
121 MODULE_PARM_DESC(tc, "DMA threshold control value");
122
123 /* Pay attention to tune this parameter; take care of both
124 * hardware capability and network stabitily/performance impact.
125 * Many tests showed that ~4ms latency seems to be good enough. */
126 #ifdef CONFIG_STMMAC_TIMER
127 #define DEFAULT_PERIODIC_RATE 256
128 static int tmrate = DEFAULT_PERIODIC_RATE;
129 module_param(tmrate, int, S_IRUGO | S_IWUSR);
130 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
131 #endif
132
133 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
134 static int buf_sz = DMA_BUFFER_SIZE;
135 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
136 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
137
138 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
139 NETIF_MSG_LINK | NETIF_MSG_IFUP |
140 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
141
142 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
143
144 /**
145 * stmmac_verify_args - verify the driver parameters.
146 * Description: it verifies if some wrong parameter is passed to the driver.
147 * Note that wrong parameters are replaced with the default values.
148 */
149 static void stmmac_verify_args(void)
150 {
151 if (unlikely(watchdog < 0))
152 watchdog = TX_TIMEO;
153 if (unlikely(dma_rxsize < 0))
154 dma_rxsize = DMA_RX_SIZE;
155 if (unlikely(dma_txsize < 0))
156 dma_txsize = DMA_TX_SIZE;
157 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
158 buf_sz = DMA_BUFFER_SIZE;
159 if (unlikely(flow_ctrl > 1))
160 flow_ctrl = FLOW_AUTO;
161 else if (likely(flow_ctrl < 0))
162 flow_ctrl = FLOW_OFF;
163 if (unlikely((pause < 0) || (pause > 0xffff)))
164 pause = PAUSE_TIME;
165 }
166
167 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
168 static void print_pkt(unsigned char *buf, int len)
169 {
170 int j;
171 pr_info("len = %d byte, buf addr: 0x%p", len, buf);
172 for (j = 0; j < len; j++) {
173 if ((j % 16) == 0)
174 pr_info("\n %03x:", j);
175 pr_info(" %02x", buf[j]);
176 }
177 pr_info("\n");
178 }
179 #endif
180
181 /* minimum number of free TX descriptors required to wake up TX process */
182 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4)
183
184 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
185 {
186 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
187 }
188
189 /* On some ST platforms, some HW system configuraton registers have to be
190 * set according to the link speed negotiated.
191 */
192 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
193 {
194 struct phy_device *phydev = priv->phydev;
195
196 if (likely(priv->plat->fix_mac_speed))
197 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
198 phydev->speed);
199 }
200
201 /**
202 * stmmac_adjust_link
203 * @dev: net device structure
204 * Description: it adjusts the link parameters.
205 */
206 static void stmmac_adjust_link(struct net_device *dev)
207 {
208 struct stmmac_priv *priv = netdev_priv(dev);
209 struct phy_device *phydev = priv->phydev;
210 unsigned long flags;
211 int new_state = 0;
212 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
213
214 if (phydev == NULL)
215 return;
216
217 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n",
218 phydev->addr, phydev->link);
219
220 spin_lock_irqsave(&priv->lock, flags);
221 if (phydev->link) {
222 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
223
224 /* Now we make sure that we can be in full duplex mode.
225 * If not, we operate in half-duplex mode. */
226 if (phydev->duplex != priv->oldduplex) {
227 new_state = 1;
228 if (!(phydev->duplex))
229 ctrl &= ~priv->hw->link.duplex;
230 else
231 ctrl |= priv->hw->link.duplex;
232 priv->oldduplex = phydev->duplex;
233 }
234 /* Flow Control operation */
235 if (phydev->pause)
236 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
237 fc, pause_time);
238
239 if (phydev->speed != priv->speed) {
240 new_state = 1;
241 switch (phydev->speed) {
242 case 1000:
243 if (likely(priv->plat->has_gmac))
244 ctrl &= ~priv->hw->link.port;
245 stmmac_hw_fix_mac_speed(priv);
246 break;
247 case 100:
248 case 10:
249 if (priv->plat->has_gmac) {
250 ctrl |= priv->hw->link.port;
251 if (phydev->speed == SPEED_100) {
252 ctrl |= priv->hw->link.speed;
253 } else {
254 ctrl &= ~(priv->hw->link.speed);
255 }
256 } else {
257 ctrl &= ~priv->hw->link.port;
258 }
259 stmmac_hw_fix_mac_speed(priv);
260 break;
261 default:
262 if (netif_msg_link(priv))
263 pr_warning("%s: Speed (%d) is not 10"
264 " or 100!\n", dev->name, phydev->speed);
265 break;
266 }
267
268 priv->speed = phydev->speed;
269 }
270
271 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
272
273 if (!priv->oldlink) {
274 new_state = 1;
275 priv->oldlink = 1;
276 }
277 } else if (priv->oldlink) {
278 new_state = 1;
279 priv->oldlink = 0;
280 priv->speed = 0;
281 priv->oldduplex = -1;
282 }
283
284 if (new_state && netif_msg_link(priv))
285 phy_print_status(phydev);
286
287 spin_unlock_irqrestore(&priv->lock, flags);
288
289 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
290 }
291
292 /**
293 * stmmac_init_phy - PHY initialization
294 * @dev: net device structure
295 * Description: it initializes the driver's PHY state, and attaches the PHY
296 * to the mac driver.
297 * Return value:
298 * 0 on success
299 */
300 static int stmmac_init_phy(struct net_device *dev)
301 {
302 struct stmmac_priv *priv = netdev_priv(dev);
303 struct phy_device *phydev;
304 char phy_id[MII_BUS_ID_SIZE + 3];
305 char bus_id[MII_BUS_ID_SIZE];
306 int interface = priv->plat->interface;
307 priv->oldlink = 0;
308 priv->speed = 0;
309 priv->oldduplex = -1;
310
311 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->plat->bus_id);
312 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
313 priv->plat->phy_addr);
314 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
315
316 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface);
317
318 if (IS_ERR(phydev)) {
319 pr_err("%s: Could not attach to PHY\n", dev->name);
320 return PTR_ERR(phydev);
321 }
322
323 /* Stop Advertising 1000BASE Capability if interface is not GMII */
324 if ((interface == PHY_INTERFACE_MODE_MII) ||
325 (interface == PHY_INTERFACE_MODE_RMII))
326 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
327 SUPPORTED_1000baseT_Full);
328
329 /*
330 * Broken HW is sometimes missing the pull-up resistor on the
331 * MDIO line, which results in reads to non-existent devices returning
332 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
333 * device as well.
334 * Note: phydev->phy_id is the result of reading the UID PHY registers.
335 */
336 if (phydev->phy_id == 0) {
337 phy_disconnect(phydev);
338 return -ENODEV;
339 }
340 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)"
341 " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
342
343 priv->phydev = phydev;
344
345 return 0;
346 }
347
348 static inline void stmmac_enable_mac(void __iomem *ioaddr)
349 {
350 u32 value = readl(ioaddr + MAC_CTRL_REG);
351
352 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
353 writel(value, ioaddr + MAC_CTRL_REG);
354 }
355
356 static inline void stmmac_disable_mac(void __iomem *ioaddr)
357 {
358 u32 value = readl(ioaddr + MAC_CTRL_REG);
359
360 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
361 writel(value, ioaddr + MAC_CTRL_REG);
362 }
363
364 /**
365 * display_ring
366 * @p: pointer to the ring.
367 * @size: size of the ring.
368 * Description: display all the descriptors within the ring.
369 */
370 static void display_ring(struct dma_desc *p, int size)
371 {
372 struct tmp_s {
373 u64 a;
374 unsigned int b;
375 unsigned int c;
376 };
377 int i;
378 for (i = 0; i < size; i++) {
379 struct tmp_s *x = (struct tmp_s *)(p + i);
380 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
381 i, (unsigned int)virt_to_phys(&p[i]),
382 (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
383 x->b, x->c);
384 pr_info("\n");
385 }
386 }
387
388 static int stmmac_set_bfsize(int mtu, int bufsize)
389 {
390 int ret = bufsize;
391
392 if (mtu >= BUF_SIZE_4KiB)
393 ret = BUF_SIZE_8KiB;
394 else if (mtu >= BUF_SIZE_2KiB)
395 ret = BUF_SIZE_4KiB;
396 else if (mtu >= DMA_BUFFER_SIZE)
397 ret = BUF_SIZE_2KiB;
398 else
399 ret = DMA_BUFFER_SIZE;
400
401 return ret;
402 }
403
404 /**
405 * init_dma_desc_rings - init the RX/TX descriptor rings
406 * @dev: net device structure
407 * Description: this function initializes the DMA RX/TX descriptors
408 * and allocates the socket buffers. It suppors the chained and ring
409 * modes.
410 */
411 static void init_dma_desc_rings(struct net_device *dev)
412 {
413 int i;
414 struct stmmac_priv *priv = netdev_priv(dev);
415 struct sk_buff *skb;
416 unsigned int txsize = priv->dma_tx_size;
417 unsigned int rxsize = priv->dma_rx_size;
418 unsigned int bfsize;
419 int dis_ic = 0;
420 int des3_as_data_buf = 0;
421
422 /* Set the max buffer size according to the DESC mode
423 * and the MTU. Note that RING mode allows 16KiB bsize. */
424 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
425
426 if (bfsize == BUF_SIZE_16KiB)
427 des3_as_data_buf = 1;
428 else
429 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
430
431 #ifdef CONFIG_STMMAC_TIMER
432 /* Disable interrupts on completion for the reception if timer is on */
433 if (likely(priv->tm->enable))
434 dis_ic = 1;
435 #endif
436
437 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
438 txsize, rxsize, bfsize);
439
440 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
441 priv->rx_skbuff =
442 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
443 priv->dma_rx =
444 (struct dma_desc *)dma_alloc_coherent(priv->device,
445 rxsize *
446 sizeof(struct dma_desc),
447 &priv->dma_rx_phy,
448 GFP_KERNEL);
449 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
450 GFP_KERNEL);
451 priv->dma_tx =
452 (struct dma_desc *)dma_alloc_coherent(priv->device,
453 txsize *
454 sizeof(struct dma_desc),
455 &priv->dma_tx_phy,
456 GFP_KERNEL);
457
458 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
459 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
460 return;
461 }
462
463 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
464 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
465 dev->name, priv->dma_rx, priv->dma_tx,
466 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
467
468 /* RX INITIALIZATION */
469 DBG(probe, INFO, "stmmac: SKB addresses:\n"
470 "skb\t\tskb data\tdma data\n");
471
472 for (i = 0; i < rxsize; i++) {
473 struct dma_desc *p = priv->dma_rx + i;
474
475 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
476 GFP_KERNEL);
477 if (unlikely(skb == NULL)) {
478 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
479 break;
480 }
481 skb_reserve(skb, NET_IP_ALIGN);
482 priv->rx_skbuff[i] = skb;
483 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
484 bfsize, DMA_FROM_DEVICE);
485
486 p->des2 = priv->rx_skbuff_dma[i];
487
488 priv->hw->ring->init_desc3(des3_as_data_buf, p);
489
490 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
491 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
492 }
493 priv->cur_rx = 0;
494 priv->dirty_rx = (unsigned int)(i - rxsize);
495 priv->dma_buf_sz = bfsize;
496 buf_sz = bfsize;
497
498 /* TX INITIALIZATION */
499 for (i = 0; i < txsize; i++) {
500 priv->tx_skbuff[i] = NULL;
501 priv->dma_tx[i].des2 = 0;
502 }
503
504 /* In case of Chained mode this sets the des3 to the next
505 * element in the chain */
506 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
507 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
508
509 priv->dirty_tx = 0;
510 priv->cur_tx = 0;
511
512 /* Clear the Rx/Tx descriptors */
513 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
514 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
515
516 if (netif_msg_hw(priv)) {
517 pr_info("RX descriptor ring:\n");
518 display_ring(priv->dma_rx, rxsize);
519 pr_info("TX descriptor ring:\n");
520 display_ring(priv->dma_tx, txsize);
521 }
522 }
523
524 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
525 {
526 int i;
527
528 for (i = 0; i < priv->dma_rx_size; i++) {
529 if (priv->rx_skbuff[i]) {
530 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
531 priv->dma_buf_sz, DMA_FROM_DEVICE);
532 dev_kfree_skb_any(priv->rx_skbuff[i]);
533 }
534 priv->rx_skbuff[i] = NULL;
535 }
536 }
537
538 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
539 {
540 int i;
541
542 for (i = 0; i < priv->dma_tx_size; i++) {
543 if (priv->tx_skbuff[i] != NULL) {
544 struct dma_desc *p = priv->dma_tx + i;
545 if (p->des2)
546 dma_unmap_single(priv->device, p->des2,
547 priv->hw->desc->get_tx_len(p),
548 DMA_TO_DEVICE);
549 dev_kfree_skb_any(priv->tx_skbuff[i]);
550 priv->tx_skbuff[i] = NULL;
551 }
552 }
553 }
554
555 static void free_dma_desc_resources(struct stmmac_priv *priv)
556 {
557 /* Release the DMA TX/RX socket buffers */
558 dma_free_rx_skbufs(priv);
559 dma_free_tx_skbufs(priv);
560
561 /* Free the region of consistent memory previously allocated for
562 * the DMA */
563 dma_free_coherent(priv->device,
564 priv->dma_tx_size * sizeof(struct dma_desc),
565 priv->dma_tx, priv->dma_tx_phy);
566 dma_free_coherent(priv->device,
567 priv->dma_rx_size * sizeof(struct dma_desc),
568 priv->dma_rx, priv->dma_rx_phy);
569 kfree(priv->rx_skbuff_dma);
570 kfree(priv->rx_skbuff);
571 kfree(priv->tx_skbuff);
572 }
573
574 /**
575 * stmmac_dma_operation_mode - HW DMA operation mode
576 * @priv : pointer to the private device structure.
577 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
578 * or Store-And-Forward capability.
579 */
580 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
581 {
582 if (likely(priv->plat->force_sf_dma_mode ||
583 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
584 /*
585 * In case of GMAC, SF mode can be enabled
586 * to perform the TX COE in HW. This depends on:
587 * 1) TX COE if actually supported
588 * 2) There is no bugged Jumbo frame support
589 * that needs to not insert csum in the TDES.
590 */
591 priv->hw->dma->dma_mode(priv->ioaddr,
592 SF_DMA_MODE, SF_DMA_MODE);
593 tc = SF_DMA_MODE;
594 } else
595 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
596 }
597
598 /**
599 * stmmac_tx:
600 * @priv: private driver structure
601 * Description: it reclaims resources after transmission completes.
602 */
603 static void stmmac_tx(struct stmmac_priv *priv)
604 {
605 unsigned int txsize = priv->dma_tx_size;
606
607 spin_lock(&priv->tx_lock);
608
609 while (priv->dirty_tx != priv->cur_tx) {
610 int last;
611 unsigned int entry = priv->dirty_tx % txsize;
612 struct sk_buff *skb = priv->tx_skbuff[entry];
613 struct dma_desc *p = priv->dma_tx + entry;
614
615 /* Check if the descriptor is owned by the DMA. */
616 if (priv->hw->desc->get_tx_owner(p))
617 break;
618
619 /* Verify tx error by looking at the last segment */
620 last = priv->hw->desc->get_tx_ls(p);
621 if (likely(last)) {
622 int tx_error =
623 priv->hw->desc->tx_status(&priv->dev->stats,
624 &priv->xstats, p,
625 priv->ioaddr);
626 if (likely(tx_error == 0)) {
627 priv->dev->stats.tx_packets++;
628 priv->xstats.tx_pkt_n++;
629 } else
630 priv->dev->stats.tx_errors++;
631 }
632 TX_DBG("%s: curr %d, dirty %d\n", __func__,
633 priv->cur_tx, priv->dirty_tx);
634
635 if (likely(p->des2))
636 dma_unmap_single(priv->device, p->des2,
637 priv->hw->desc->get_tx_len(p),
638 DMA_TO_DEVICE);
639 priv->hw->ring->clean_desc3(p);
640
641 if (likely(skb != NULL)) {
642 /*
643 * If there's room in the queue (limit it to size)
644 * we add this skb back into the pool,
645 * if it's the right size.
646 */
647 if ((skb_queue_len(&priv->rx_recycle) <
648 priv->dma_rx_size) &&
649 skb_recycle_check(skb, priv->dma_buf_sz))
650 __skb_queue_head(&priv->rx_recycle, skb);
651 else
652 dev_kfree_skb(skb);
653
654 priv->tx_skbuff[entry] = NULL;
655 }
656
657 priv->hw->desc->release_tx_desc(p);
658
659 entry = (++priv->dirty_tx) % txsize;
660 }
661 if (unlikely(netif_queue_stopped(priv->dev) &&
662 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
663 netif_tx_lock(priv->dev);
664 if (netif_queue_stopped(priv->dev) &&
665 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
666 TX_DBG("%s: restart transmit\n", __func__);
667 netif_wake_queue(priv->dev);
668 }
669 netif_tx_unlock(priv->dev);
670 }
671 spin_unlock(&priv->tx_lock);
672 }
673
674 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
675 {
676 #ifdef CONFIG_STMMAC_TIMER
677 if (likely(priv->tm->enable))
678 priv->tm->timer_start(tmrate);
679 else
680 #endif
681 priv->hw->dma->enable_dma_irq(priv->ioaddr);
682 }
683
684 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
685 {
686 #ifdef CONFIG_STMMAC_TIMER
687 if (likely(priv->tm->enable))
688 priv->tm->timer_stop();
689 else
690 #endif
691 priv->hw->dma->disable_dma_irq(priv->ioaddr);
692 }
693
694 static int stmmac_has_work(struct stmmac_priv *priv)
695 {
696 unsigned int has_work = 0;
697 int rxret, tx_work = 0;
698
699 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
700 (priv->cur_rx % priv->dma_rx_size));
701
702 if (priv->dirty_tx != priv->cur_tx)
703 tx_work = 1;
704
705 if (likely(!rxret || tx_work))
706 has_work = 1;
707
708 return has_work;
709 }
710
711 static inline void _stmmac_schedule(struct stmmac_priv *priv)
712 {
713 if (likely(stmmac_has_work(priv))) {
714 stmmac_disable_irq(priv);
715 napi_schedule(&priv->napi);
716 }
717 }
718
719 #ifdef CONFIG_STMMAC_TIMER
720 void stmmac_schedule(struct net_device *dev)
721 {
722 struct stmmac_priv *priv = netdev_priv(dev);
723
724 priv->xstats.sched_timer_n++;
725
726 _stmmac_schedule(priv);
727 }
728
729 static void stmmac_no_timer_started(unsigned int x)
730 {;
731 };
732
733 static void stmmac_no_timer_stopped(void)
734 {;
735 };
736 #endif
737
738 /**
739 * stmmac_tx_err:
740 * @priv: pointer to the private device structure
741 * Description: it cleans the descriptors and restarts the transmission
742 * in case of errors.
743 */
744 static void stmmac_tx_err(struct stmmac_priv *priv)
745 {
746 netif_stop_queue(priv->dev);
747
748 priv->hw->dma->stop_tx(priv->ioaddr);
749 dma_free_tx_skbufs(priv);
750 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
751 priv->dirty_tx = 0;
752 priv->cur_tx = 0;
753 priv->hw->dma->start_tx(priv->ioaddr);
754
755 priv->dev->stats.tx_errors++;
756 netif_wake_queue(priv->dev);
757 }
758
759
760 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
761 {
762 int status;
763
764 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
765 if (likely(status == handle_tx_rx))
766 _stmmac_schedule(priv);
767
768 else if (unlikely(status == tx_hard_error_bump_tc)) {
769 /* Try to bump up the dma threshold on this failure */
770 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
771 tc += 64;
772 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
773 priv->xstats.threshold = tc;
774 }
775 } else if (unlikely(status == tx_hard_error))
776 stmmac_tx_err(priv);
777 }
778
779 static void stmmac_mmc_setup(struct stmmac_priv *priv)
780 {
781 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
782 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
783
784 /* Mask MMC irq, counters are managed in SW and registers
785 * are cleared on each READ eventually. */
786 dwmac_mmc_intr_all_mask(priv->ioaddr);
787
788 if (priv->dma_cap.rmon) {
789 dwmac_mmc_ctrl(priv->ioaddr, mode);
790 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
791 } else
792 pr_info(" No MAC Management Counters available");
793 }
794
795 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
796 {
797 u32 hwid = priv->hw->synopsys_uid;
798
799 /* Only check valid Synopsys Id because old MAC chips
800 * have no HW registers where get the ID */
801 if (likely(hwid)) {
802 u32 uid = ((hwid & 0x0000ff00) >> 8);
803 u32 synid = (hwid & 0x000000ff);
804
805 pr_info("STMMAC - user ID: 0x%x, Synopsys ID: 0x%x\n",
806 uid, synid);
807
808 return synid;
809 }
810 return 0;
811 }
812
813 /**
814 * stmmac_selec_desc_mode
815 * @dev : device pointer
816 * Description: select the Enhanced/Alternate or Normal descriptors */
817 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
818 {
819 if (priv->plat->enh_desc) {
820 pr_info(" Enhanced/Alternate descriptors\n");
821 priv->hw->desc = &enh_desc_ops;
822 } else {
823 pr_info(" Normal descriptors\n");
824 priv->hw->desc = &ndesc_ops;
825 }
826 }
827
828 /**
829 * stmmac_get_hw_features
830 * @priv : private device pointer
831 * Description:
832 * new GMAC chip generations have a new register to indicate the
833 * presence of the optional feature/functions.
834 * This can be also used to override the value passed through the
835 * platform and necessary for old MAC10/100 and GMAC chips.
836 */
837 static int stmmac_get_hw_features(struct stmmac_priv *priv)
838 {
839 u32 hw_cap = 0;
840
841 if (priv->hw->dma->get_hw_feature) {
842 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
843
844 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
845 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
846 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
847 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
848 priv->dma_cap.multi_addr =
849 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
850 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
851 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
852 priv->dma_cap.pmt_remote_wake_up =
853 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
854 priv->dma_cap.pmt_magic_frame =
855 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
856 /* MMC */
857 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
858 /* IEEE 1588-2002*/
859 priv->dma_cap.time_stamp =
860 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
861 /* IEEE 1588-2008*/
862 priv->dma_cap.atime_stamp =
863 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
864 /* 802.3az - Energy-Efficient Ethernet (EEE) */
865 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
866 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
867 /* TX and RX csum */
868 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
869 priv->dma_cap.rx_coe_type1 =
870 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
871 priv->dma_cap.rx_coe_type2 =
872 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
873 priv->dma_cap.rxfifo_over_2048 =
874 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
875 /* TX and RX number of channels */
876 priv->dma_cap.number_rx_channel =
877 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
878 priv->dma_cap.number_tx_channel =
879 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
880 /* Alternate (enhanced) DESC mode*/
881 priv->dma_cap.enh_desc =
882 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
883
884 }
885
886 return hw_cap;
887 }
888
889 /**
890 * stmmac_open - open entry point of the driver
891 * @dev : pointer to the device structure.
892 * Description:
893 * This function is the open entry point of the driver.
894 * Return value:
895 * 0 on success and an appropriate (-)ve integer as defined in errno.h
896 * file on failure.
897 */
898 static int stmmac_open(struct net_device *dev)
899 {
900 struct stmmac_priv *priv = netdev_priv(dev);
901 int ret;
902
903 /* Check that the MAC address is valid. If its not, refuse
904 * to bring the device up. The user must specify an
905 * address using the following linux command:
906 * ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx */
907 if (!is_valid_ether_addr(dev->dev_addr)) {
908 random_ether_addr(dev->dev_addr);
909 pr_warning("%s: generated random MAC address %pM\n", dev->name,
910 dev->dev_addr);
911 }
912
913 stmmac_verify_args();
914
915 #ifdef CONFIG_STMMAC_TIMER
916 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
917 if (unlikely(priv->tm == NULL)) {
918 pr_err("%s: ERROR: timer memory alloc failed\n", __func__);
919 return -ENOMEM;
920 }
921 priv->tm->freq = tmrate;
922
923 /* Test if the external timer can be actually used.
924 * In case of failure continue without timer. */
925 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
926 pr_warning("stmmaceth: cannot attach the external timer.\n");
927 priv->tm->freq = 0;
928 priv->tm->timer_start = stmmac_no_timer_started;
929 priv->tm->timer_stop = stmmac_no_timer_stopped;
930 } else
931 priv->tm->enable = 1;
932 #endif
933 ret = stmmac_init_phy(dev);
934 if (unlikely(ret)) {
935 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
936 goto open_error;
937 }
938
939 stmmac_get_synopsys_id(priv);
940
941 priv->hw_cap_support = stmmac_get_hw_features(priv);
942
943 if (priv->hw_cap_support) {
944 pr_info(" Support DMA HW capability register");
945
946 /* We can override some gmac/dma configuration fields: e.g.
947 * enh_desc, tx_coe (e.g. that are passed through the
948 * platform) with the values from the HW capability
949 * register (if supported).
950 */
951 priv->plat->enh_desc = priv->dma_cap.enh_desc;
952 priv->plat->tx_coe = priv->dma_cap.tx_coe;
953 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
954
955 /* By default disable wol on magic frame if not supported */
956 if (!priv->dma_cap.pmt_magic_frame)
957 priv->wolopts &= ~WAKE_MAGIC;
958
959 } else
960 pr_info(" No HW DMA feature register supported");
961
962 /* Select the enhnaced/normal descriptor structures */
963 stmmac_selec_desc_mode(priv);
964
965 /* PMT module is not integrated in all the MAC devices. */
966 if (priv->plat->pmt) {
967 pr_info(" Remote wake-up capable\n");
968 device_set_wakeup_capable(priv->device, 1);
969 }
970
971 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
972 if (priv->rx_coe)
973 pr_info(" Checksum Offload Engine supported\n");
974 if (priv->plat->tx_coe)
975 pr_info(" Checksum insertion supported\n");
976
977 /* Create and initialize the TX/RX descriptors chains. */
978 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
979 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
980 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
981 init_dma_desc_rings(dev);
982
983 /* DMA initialization and SW reset */
984 ret = priv->hw->dma->init(priv->ioaddr, priv->plat->pbl,
985 priv->dma_tx_phy, priv->dma_rx_phy);
986 if (ret < 0) {
987 pr_err("%s: DMA initialization failed\n", __func__);
988 goto open_error;
989 }
990
991 /* Copy the MAC addr into the HW */
992 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
993 /* If required, perform hw setup of the bus. */
994 if (priv->plat->bus_setup)
995 priv->plat->bus_setup(priv->ioaddr);
996 /* Initialize the MAC Core */
997 priv->hw->mac->core_init(priv->ioaddr);
998
999 netdev_update_features(dev);
1000
1001 /* Request the IRQ lines */
1002 ret = request_irq(dev->irq, stmmac_interrupt,
1003 IRQF_SHARED, dev->name, dev);
1004 if (unlikely(ret < 0)) {
1005 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1006 __func__, dev->irq, ret);
1007 goto open_error;
1008 }
1009
1010 /* Enable the MAC Rx/Tx */
1011 stmmac_enable_mac(priv->ioaddr);
1012
1013 /* Set the HW DMA mode and the COE */
1014 stmmac_dma_operation_mode(priv);
1015
1016 /* Extra statistics */
1017 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1018 priv->xstats.threshold = tc;
1019
1020 stmmac_mmc_setup(priv);
1021
1022 /* Start the ball rolling... */
1023 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1024 priv->hw->dma->start_tx(priv->ioaddr);
1025 priv->hw->dma->start_rx(priv->ioaddr);
1026
1027 #ifdef CONFIG_STMMAC_TIMER
1028 priv->tm->timer_start(tmrate);
1029 #endif
1030 /* Dump DMA/MAC registers */
1031 if (netif_msg_hw(priv)) {
1032 priv->hw->mac->dump_regs(priv->ioaddr);
1033 priv->hw->dma->dump_regs(priv->ioaddr);
1034 }
1035
1036 if (priv->phydev)
1037 phy_start(priv->phydev);
1038
1039 napi_enable(&priv->napi);
1040 skb_queue_head_init(&priv->rx_recycle);
1041 netif_start_queue(dev);
1042
1043 return 0;
1044
1045 open_error:
1046 #ifdef CONFIG_STMMAC_TIMER
1047 kfree(priv->tm);
1048 #endif
1049 if (priv->phydev)
1050 phy_disconnect(priv->phydev);
1051
1052 return ret;
1053 }
1054
1055 /**
1056 * stmmac_release - close entry point of the driver
1057 * @dev : device pointer.
1058 * Description:
1059 * This is the stop entry point of the driver.
1060 */
1061 static int stmmac_release(struct net_device *dev)
1062 {
1063 struct stmmac_priv *priv = netdev_priv(dev);
1064
1065 /* Stop and disconnect the PHY */
1066 if (priv->phydev) {
1067 phy_stop(priv->phydev);
1068 phy_disconnect(priv->phydev);
1069 priv->phydev = NULL;
1070 }
1071
1072 netif_stop_queue(dev);
1073
1074 #ifdef CONFIG_STMMAC_TIMER
1075 /* Stop and release the timer */
1076 stmmac_close_ext_timer();
1077 if (priv->tm != NULL)
1078 kfree(priv->tm);
1079 #endif
1080 napi_disable(&priv->napi);
1081 skb_queue_purge(&priv->rx_recycle);
1082
1083 /* Free the IRQ lines */
1084 free_irq(dev->irq, dev);
1085
1086 /* Stop TX/RX DMA and clear the descriptors */
1087 priv->hw->dma->stop_tx(priv->ioaddr);
1088 priv->hw->dma->stop_rx(priv->ioaddr);
1089
1090 /* Release and free the Rx/Tx resources */
1091 free_dma_desc_resources(priv);
1092
1093 /* Disable the MAC Rx/Tx */
1094 stmmac_disable_mac(priv->ioaddr);
1095
1096 netif_carrier_off(dev);
1097
1098 return 0;
1099 }
1100
1101 /**
1102 * stmmac_xmit:
1103 * @skb : the socket buffer
1104 * @dev : device pointer
1105 * Description : Tx entry point of the driver.
1106 */
1107 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1108 {
1109 struct stmmac_priv *priv = netdev_priv(dev);
1110 unsigned int txsize = priv->dma_tx_size;
1111 unsigned int entry;
1112 int i, csum_insertion = 0;
1113 int nfrags = skb_shinfo(skb)->nr_frags;
1114 struct dma_desc *desc, *first;
1115 unsigned int nopaged_len = skb_headlen(skb);
1116
1117 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1118 if (!netif_queue_stopped(dev)) {
1119 netif_stop_queue(dev);
1120 /* This is a hard error, log it. */
1121 pr_err("%s: BUG! Tx Ring full when queue awake\n",
1122 __func__);
1123 }
1124 return NETDEV_TX_BUSY;
1125 }
1126
1127 spin_lock(&priv->tx_lock);
1128
1129 entry = priv->cur_tx % txsize;
1130
1131 #ifdef STMMAC_XMIT_DEBUG
1132 if ((skb->len > ETH_FRAME_LEN) || nfrags)
1133 pr_info("stmmac xmit:\n"
1134 "\tskb addr %p - len: %d - nopaged_len: %d\n"
1135 "\tn_frags: %d - ip_summed: %d - %s gso\n",
1136 skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1137 !skb_is_gso(skb) ? "isn't" : "is");
1138 #endif
1139
1140 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1141
1142 desc = priv->dma_tx + entry;
1143 first = desc;
1144
1145 #ifdef STMMAC_XMIT_DEBUG
1146 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1147 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1148 "\t\tn_frags: %d, ip_summed: %d\n",
1149 skb->len, nopaged_len, nfrags, skb->ip_summed);
1150 #endif
1151 priv->tx_skbuff[entry] = skb;
1152
1153 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1154 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1155 desc = priv->dma_tx + entry;
1156 } else {
1157 desc->des2 = dma_map_single(priv->device, skb->data,
1158 nopaged_len, DMA_TO_DEVICE);
1159 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1160 csum_insertion);
1161 }
1162
1163 for (i = 0; i < nfrags; i++) {
1164 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1165 int len = skb_frag_size(frag);
1166
1167 entry = (++priv->cur_tx) % txsize;
1168 desc = priv->dma_tx + entry;
1169
1170 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1171 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1172 DMA_TO_DEVICE);
1173 priv->tx_skbuff[entry] = NULL;
1174 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1175 wmb();
1176 priv->hw->desc->set_tx_owner(desc);
1177 }
1178
1179 /* Interrupt on completition only for the latest segment */
1180 priv->hw->desc->close_tx_desc(desc);
1181
1182 #ifdef CONFIG_STMMAC_TIMER
1183 /* Clean IC while using timer */
1184 if (likely(priv->tm->enable))
1185 priv->hw->desc->clear_tx_ic(desc);
1186 #endif
1187
1188 wmb();
1189
1190 /* To avoid raise condition */
1191 priv->hw->desc->set_tx_owner(first);
1192
1193 priv->cur_tx++;
1194
1195 #ifdef STMMAC_XMIT_DEBUG
1196 if (netif_msg_pktdata(priv)) {
1197 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1198 "first=%p, nfrags=%d\n",
1199 (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1200 entry, first, nfrags);
1201 display_ring(priv->dma_tx, txsize);
1202 pr_info(">>> frame to be transmitted: ");
1203 print_pkt(skb->data, skb->len);
1204 }
1205 #endif
1206 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1207 TX_DBG("%s: stop transmitted packets\n", __func__);
1208 netif_stop_queue(dev);
1209 }
1210
1211 dev->stats.tx_bytes += skb->len;
1212
1213 skb_tx_timestamp(skb);
1214
1215 priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1216
1217 spin_unlock(&priv->tx_lock);
1218
1219 return NETDEV_TX_OK;
1220 }
1221
1222 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1223 {
1224 unsigned int rxsize = priv->dma_rx_size;
1225 int bfsize = priv->dma_buf_sz;
1226 struct dma_desc *p = priv->dma_rx;
1227
1228 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1229 unsigned int entry = priv->dirty_rx % rxsize;
1230 if (likely(priv->rx_skbuff[entry] == NULL)) {
1231 struct sk_buff *skb;
1232
1233 skb = __skb_dequeue(&priv->rx_recycle);
1234 if (skb == NULL)
1235 skb = netdev_alloc_skb_ip_align(priv->dev,
1236 bfsize);
1237
1238 if (unlikely(skb == NULL))
1239 break;
1240
1241 priv->rx_skbuff[entry] = skb;
1242 priv->rx_skbuff_dma[entry] =
1243 dma_map_single(priv->device, skb->data, bfsize,
1244 DMA_FROM_DEVICE);
1245
1246 (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1247
1248 if (unlikely(priv->plat->has_gmac))
1249 priv->hw->ring->refill_desc3(bfsize, p + entry);
1250
1251 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1252 }
1253 wmb();
1254 priv->hw->desc->set_rx_owner(p + entry);
1255 }
1256 }
1257
1258 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1259 {
1260 unsigned int rxsize = priv->dma_rx_size;
1261 unsigned int entry = priv->cur_rx % rxsize;
1262 unsigned int next_entry;
1263 unsigned int count = 0;
1264 struct dma_desc *p = priv->dma_rx + entry;
1265 struct dma_desc *p_next;
1266
1267 #ifdef STMMAC_RX_DEBUG
1268 if (netif_msg_hw(priv)) {
1269 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1270 display_ring(priv->dma_rx, rxsize);
1271 }
1272 #endif
1273 count = 0;
1274 while (!priv->hw->desc->get_rx_owner(p)) {
1275 int status;
1276
1277 if (count >= limit)
1278 break;
1279
1280 count++;
1281
1282 next_entry = (++priv->cur_rx) % rxsize;
1283 p_next = priv->dma_rx + next_entry;
1284 prefetch(p_next);
1285
1286 /* read the status of the incoming frame */
1287 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1288 &priv->xstats, p));
1289 if (unlikely(status == discard_frame))
1290 priv->dev->stats.rx_errors++;
1291 else {
1292 struct sk_buff *skb;
1293 int frame_len;
1294
1295 frame_len = priv->hw->desc->get_rx_frame_len(p);
1296 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1297 * Type frames (LLC/LLC-SNAP) */
1298 if (unlikely(status != llc_snap))
1299 frame_len -= ETH_FCS_LEN;
1300 #ifdef STMMAC_RX_DEBUG
1301 if (frame_len > ETH_FRAME_LEN)
1302 pr_debug("\tRX frame size %d, COE status: %d\n",
1303 frame_len, status);
1304
1305 if (netif_msg_hw(priv))
1306 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1307 p, entry, p->des2);
1308 #endif
1309 skb = priv->rx_skbuff[entry];
1310 if (unlikely(!skb)) {
1311 pr_err("%s: Inconsistent Rx descriptor chain\n",
1312 priv->dev->name);
1313 priv->dev->stats.rx_dropped++;
1314 break;
1315 }
1316 prefetch(skb->data - NET_IP_ALIGN);
1317 priv->rx_skbuff[entry] = NULL;
1318
1319 skb_put(skb, frame_len);
1320 dma_unmap_single(priv->device,
1321 priv->rx_skbuff_dma[entry],
1322 priv->dma_buf_sz, DMA_FROM_DEVICE);
1323 #ifdef STMMAC_RX_DEBUG
1324 if (netif_msg_pktdata(priv)) {
1325 pr_info(" frame received (%dbytes)", frame_len);
1326 print_pkt(skb->data, frame_len);
1327 }
1328 #endif
1329 skb->protocol = eth_type_trans(skb, priv->dev);
1330
1331 if (unlikely(!priv->rx_coe)) {
1332 /* No RX COE for old mac10/100 devices */
1333 skb_checksum_none_assert(skb);
1334 netif_receive_skb(skb);
1335 } else {
1336 skb->ip_summed = CHECKSUM_UNNECESSARY;
1337 napi_gro_receive(&priv->napi, skb);
1338 }
1339
1340 priv->dev->stats.rx_packets++;
1341 priv->dev->stats.rx_bytes += frame_len;
1342 }
1343 entry = next_entry;
1344 p = p_next; /* use prefetched values */
1345 }
1346
1347 stmmac_rx_refill(priv);
1348
1349 priv->xstats.rx_pkt_n += count;
1350
1351 return count;
1352 }
1353
1354 /**
1355 * stmmac_poll - stmmac poll method (NAPI)
1356 * @napi : pointer to the napi structure.
1357 * @budget : maximum number of packets that the current CPU can receive from
1358 * all interfaces.
1359 * Description :
1360 * This function implements the the reception process.
1361 * Also it runs the TX completion thread
1362 */
1363 static int stmmac_poll(struct napi_struct *napi, int budget)
1364 {
1365 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1366 int work_done = 0;
1367
1368 priv->xstats.poll_n++;
1369 stmmac_tx(priv);
1370 work_done = stmmac_rx(priv, budget);
1371
1372 if (work_done < budget) {
1373 napi_complete(napi);
1374 stmmac_enable_irq(priv);
1375 }
1376 return work_done;
1377 }
1378
1379 /**
1380 * stmmac_tx_timeout
1381 * @dev : Pointer to net device structure
1382 * Description: this function is called when a packet transmission fails to
1383 * complete within a reasonable tmrate. The driver will mark the error in the
1384 * netdev structure and arrange for the device to be reset to a sane state
1385 * in order to transmit a new packet.
1386 */
1387 static void stmmac_tx_timeout(struct net_device *dev)
1388 {
1389 struct stmmac_priv *priv = netdev_priv(dev);
1390
1391 /* Clear Tx resources and restart transmitting again */
1392 stmmac_tx_err(priv);
1393 }
1394
1395 /* Configuration changes (passed on by ifconfig) */
1396 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1397 {
1398 if (dev->flags & IFF_UP) /* can't act on a running interface */
1399 return -EBUSY;
1400
1401 /* Don't allow changing the I/O address */
1402 if (map->base_addr != dev->base_addr) {
1403 pr_warning("%s: can't change I/O address\n", dev->name);
1404 return -EOPNOTSUPP;
1405 }
1406
1407 /* Don't allow changing the IRQ */
1408 if (map->irq != dev->irq) {
1409 pr_warning("%s: can't change IRQ number %d\n",
1410 dev->name, dev->irq);
1411 return -EOPNOTSUPP;
1412 }
1413
1414 /* ignore other fields */
1415 return 0;
1416 }
1417
1418 /**
1419 * stmmac_set_rx_mode - entry point for multicast addressing
1420 * @dev : pointer to the device structure
1421 * Description:
1422 * This function is a driver entry point which gets called by the kernel
1423 * whenever multicast addresses must be enabled/disabled.
1424 * Return value:
1425 * void.
1426 */
1427 static void stmmac_set_rx_mode(struct net_device *dev)
1428 {
1429 struct stmmac_priv *priv = netdev_priv(dev);
1430
1431 spin_lock(&priv->lock);
1432 priv->hw->mac->set_filter(dev);
1433 spin_unlock(&priv->lock);
1434 }
1435
1436 /**
1437 * stmmac_change_mtu - entry point to change MTU size for the device.
1438 * @dev : device pointer.
1439 * @new_mtu : the new MTU size for the device.
1440 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
1441 * to drive packet transmission. Ethernet has an MTU of 1500 octets
1442 * (ETH_DATA_LEN). This value can be changed with ifconfig.
1443 * Return value:
1444 * 0 on success and an appropriate (-)ve integer as defined in errno.h
1445 * file on failure.
1446 */
1447 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1448 {
1449 struct stmmac_priv *priv = netdev_priv(dev);
1450 int max_mtu;
1451
1452 if (netif_running(dev)) {
1453 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1454 return -EBUSY;
1455 }
1456
1457 if (priv->plat->enh_desc)
1458 max_mtu = JUMBO_LEN;
1459 else
1460 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1461
1462 if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1463 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1464 return -EINVAL;
1465 }
1466
1467 dev->mtu = new_mtu;
1468 netdev_update_features(dev);
1469
1470 return 0;
1471 }
1472
1473 static u32 stmmac_fix_features(struct net_device *dev, u32 features)
1474 {
1475 struct stmmac_priv *priv = netdev_priv(dev);
1476
1477 if (!priv->rx_coe)
1478 features &= ~NETIF_F_RXCSUM;
1479 if (!priv->plat->tx_coe)
1480 features &= ~NETIF_F_ALL_CSUM;
1481
1482 /* Some GMAC devices have a bugged Jumbo frame support that
1483 * needs to have the Tx COE disabled for oversized frames
1484 * (due to limited buffer sizes). In this case we disable
1485 * the TX csum insertionin the TDES and not use SF. */
1486 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1487 features &= ~NETIF_F_ALL_CSUM;
1488
1489 return features;
1490 }
1491
1492 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1493 {
1494 struct net_device *dev = (struct net_device *)dev_id;
1495 struct stmmac_priv *priv = netdev_priv(dev);
1496
1497 if (unlikely(!dev)) {
1498 pr_err("%s: invalid dev pointer\n", __func__);
1499 return IRQ_NONE;
1500 }
1501
1502 if (priv->plat->has_gmac)
1503 /* To handle GMAC own interrupts */
1504 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr);
1505
1506 stmmac_dma_interrupt(priv);
1507
1508 return IRQ_HANDLED;
1509 }
1510
1511 #ifdef CONFIG_NET_POLL_CONTROLLER
1512 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1513 * to allow network I/O with interrupts disabled. */
1514 static void stmmac_poll_controller(struct net_device *dev)
1515 {
1516 disable_irq(dev->irq);
1517 stmmac_interrupt(dev->irq, dev);
1518 enable_irq(dev->irq);
1519 }
1520 #endif
1521
1522 /**
1523 * stmmac_ioctl - Entry point for the Ioctl
1524 * @dev: Device pointer.
1525 * @rq: An IOCTL specefic structure, that can contain a pointer to
1526 * a proprietary structure used to pass information to the driver.
1527 * @cmd: IOCTL command
1528 * Description:
1529 * Currently there are no special functionality supported in IOCTL, just the
1530 * phy_mii_ioctl(...) can be invoked.
1531 */
1532 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1533 {
1534 struct stmmac_priv *priv = netdev_priv(dev);
1535 int ret;
1536
1537 if (!netif_running(dev))
1538 return -EINVAL;
1539
1540 if (!priv->phydev)
1541 return -EINVAL;
1542
1543 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1544
1545 return ret;
1546 }
1547
1548 #ifdef CONFIG_STMMAC_DEBUG_FS
1549 static struct dentry *stmmac_fs_dir;
1550 static struct dentry *stmmac_rings_status;
1551 static struct dentry *stmmac_dma_cap;
1552
1553 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1554 {
1555 struct tmp_s {
1556 u64 a;
1557 unsigned int b;
1558 unsigned int c;
1559 };
1560 int i;
1561 struct net_device *dev = seq->private;
1562 struct stmmac_priv *priv = netdev_priv(dev);
1563
1564 seq_printf(seq, "=======================\n");
1565 seq_printf(seq, " RX descriptor ring\n");
1566 seq_printf(seq, "=======================\n");
1567
1568 for (i = 0; i < priv->dma_rx_size; i++) {
1569 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1570 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1571 i, (unsigned int)(x->a),
1572 (unsigned int)((x->a) >> 32), x->b, x->c);
1573 seq_printf(seq, "\n");
1574 }
1575
1576 seq_printf(seq, "\n");
1577 seq_printf(seq, "=======================\n");
1578 seq_printf(seq, " TX descriptor ring\n");
1579 seq_printf(seq, "=======================\n");
1580
1581 for (i = 0; i < priv->dma_tx_size; i++) {
1582 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1583 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1584 i, (unsigned int)(x->a),
1585 (unsigned int)((x->a) >> 32), x->b, x->c);
1586 seq_printf(seq, "\n");
1587 }
1588
1589 return 0;
1590 }
1591
1592 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1593 {
1594 return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1595 }
1596
1597 static const struct file_operations stmmac_rings_status_fops = {
1598 .owner = THIS_MODULE,
1599 .open = stmmac_sysfs_ring_open,
1600 .read = seq_read,
1601 .llseek = seq_lseek,
1602 .release = seq_release,
1603 };
1604
1605 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1606 {
1607 struct net_device *dev = seq->private;
1608 struct stmmac_priv *priv = netdev_priv(dev);
1609
1610 if (!priv->hw_cap_support) {
1611 seq_printf(seq, "DMA HW features not supported\n");
1612 return 0;
1613 }
1614
1615 seq_printf(seq, "==============================\n");
1616 seq_printf(seq, "\tDMA HW features\n");
1617 seq_printf(seq, "==============================\n");
1618
1619 seq_printf(seq, "\t10/100 Mbps %s\n",
1620 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1621 seq_printf(seq, "\t1000 Mbps %s\n",
1622 (priv->dma_cap.mbps_1000) ? "Y" : "N");
1623 seq_printf(seq, "\tHalf duple %s\n",
1624 (priv->dma_cap.half_duplex) ? "Y" : "N");
1625 seq_printf(seq, "\tHash Filter: %s\n",
1626 (priv->dma_cap.hash_filter) ? "Y" : "N");
1627 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1628 (priv->dma_cap.multi_addr) ? "Y" : "N");
1629 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1630 (priv->dma_cap.pcs) ? "Y" : "N");
1631 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1632 (priv->dma_cap.sma_mdio) ? "Y" : "N");
1633 seq_printf(seq, "\tPMT Remote wake up: %s\n",
1634 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1635 seq_printf(seq, "\tPMT Magic Frame: %s\n",
1636 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1637 seq_printf(seq, "\tRMON module: %s\n",
1638 (priv->dma_cap.rmon) ? "Y" : "N");
1639 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1640 (priv->dma_cap.time_stamp) ? "Y" : "N");
1641 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1642 (priv->dma_cap.atime_stamp) ? "Y" : "N");
1643 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1644 (priv->dma_cap.eee) ? "Y" : "N");
1645 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1646 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1647 (priv->dma_cap.tx_coe) ? "Y" : "N");
1648 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1649 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1650 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1651 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1652 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1653 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1654 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1655 priv->dma_cap.number_rx_channel);
1656 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1657 priv->dma_cap.number_tx_channel);
1658 seq_printf(seq, "\tEnhanced descriptors: %s\n",
1659 (priv->dma_cap.enh_desc) ? "Y" : "N");
1660
1661 return 0;
1662 }
1663
1664 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1665 {
1666 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1667 }
1668
1669 static const struct file_operations stmmac_dma_cap_fops = {
1670 .owner = THIS_MODULE,
1671 .open = stmmac_sysfs_dma_cap_open,
1672 .read = seq_read,
1673 .llseek = seq_lseek,
1674 .release = seq_release,
1675 };
1676
1677 static int stmmac_init_fs(struct net_device *dev)
1678 {
1679 /* Create debugfs entries */
1680 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1681
1682 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1683 pr_err("ERROR %s, debugfs create directory failed\n",
1684 STMMAC_RESOURCE_NAME);
1685
1686 return -ENOMEM;
1687 }
1688
1689 /* Entry to report DMA RX/TX rings */
1690 stmmac_rings_status = debugfs_create_file("descriptors_status",
1691 S_IRUGO, stmmac_fs_dir, dev,
1692 &stmmac_rings_status_fops);
1693
1694 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1695 pr_info("ERROR creating stmmac ring debugfs file\n");
1696 debugfs_remove(stmmac_fs_dir);
1697
1698 return -ENOMEM;
1699 }
1700
1701 /* Entry to report the DMA HW features */
1702 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1703 dev, &stmmac_dma_cap_fops);
1704
1705 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1706 pr_info("ERROR creating stmmac MMC debugfs file\n");
1707 debugfs_remove(stmmac_rings_status);
1708 debugfs_remove(stmmac_fs_dir);
1709
1710 return -ENOMEM;
1711 }
1712
1713 return 0;
1714 }
1715
1716 static void stmmac_exit_fs(void)
1717 {
1718 debugfs_remove(stmmac_rings_status);
1719 debugfs_remove(stmmac_dma_cap);
1720 debugfs_remove(stmmac_fs_dir);
1721 }
1722 #endif /* CONFIG_STMMAC_DEBUG_FS */
1723
1724 static const struct net_device_ops stmmac_netdev_ops = {
1725 .ndo_open = stmmac_open,
1726 .ndo_start_xmit = stmmac_xmit,
1727 .ndo_stop = stmmac_release,
1728 .ndo_change_mtu = stmmac_change_mtu,
1729 .ndo_fix_features = stmmac_fix_features,
1730 .ndo_set_rx_mode = stmmac_set_rx_mode,
1731 .ndo_tx_timeout = stmmac_tx_timeout,
1732 .ndo_do_ioctl = stmmac_ioctl,
1733 .ndo_set_config = stmmac_config,
1734 #ifdef CONFIG_NET_POLL_CONTROLLER
1735 .ndo_poll_controller = stmmac_poll_controller,
1736 #endif
1737 .ndo_set_mac_address = eth_mac_addr,
1738 };
1739
1740 /**
1741 * stmmac_probe - Initialization of the adapter .
1742 * @dev : device pointer
1743 * Description: The function initializes the network device structure for
1744 * the STMMAC driver. It also calls the low level routines
1745 * in order to init the HW (i.e. the DMA engine)
1746 */
1747 static int stmmac_probe(struct net_device *dev)
1748 {
1749 int ret = 0;
1750 struct stmmac_priv *priv = netdev_priv(dev);
1751
1752 ether_setup(dev);
1753
1754 dev->netdev_ops = &stmmac_netdev_ops;
1755 stmmac_set_ethtool_ops(dev);
1756
1757 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1758 dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
1759 dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1760 #ifdef STMMAC_VLAN_TAG_USED
1761 /* Both mac100 and gmac support receive VLAN tag detection */
1762 dev->features |= NETIF_F_HW_VLAN_RX;
1763 #endif
1764 priv->msg_enable = netif_msg_init(debug, default_msg_level);
1765
1766 if (flow_ctrl)
1767 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
1768
1769 priv->pause = pause;
1770 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1771
1772 /* Get the MAC address */
1773 priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr,
1774 dev->dev_addr, 0);
1775
1776 if (!is_valid_ether_addr(dev->dev_addr))
1777 pr_warning("\tno valid MAC address;"
1778 "please, use ifconfig or nwhwconfig!\n");
1779
1780 spin_lock_init(&priv->lock);
1781 spin_lock_init(&priv->tx_lock);
1782
1783 ret = register_netdev(dev);
1784 if (ret) {
1785 pr_err("%s: ERROR %i registering the device\n",
1786 __func__, ret);
1787 return -ENODEV;
1788 }
1789
1790 DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1791 dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1792 (dev->features & NETIF_F_IP_CSUM) ? "on" : "off");
1793
1794 return ret;
1795 }
1796
1797 /**
1798 * stmmac_mac_device_setup
1799 * @dev : device pointer
1800 * Description: select and initialise the mac device (mac100 or Gmac).
1801 */
1802 static int stmmac_mac_device_setup(struct net_device *dev)
1803 {
1804 struct stmmac_priv *priv = netdev_priv(dev);
1805
1806 struct mac_device_info *device;
1807
1808 if (priv->plat->has_gmac) {
1809 dev->priv_flags |= IFF_UNICAST_FLT;
1810 device = dwmac1000_setup(priv->ioaddr);
1811 } else {
1812 device = dwmac100_setup(priv->ioaddr);
1813 }
1814
1815 if (!device)
1816 return -ENOMEM;
1817
1818 priv->hw = device;
1819 priv->hw->ring = &ring_mode_ops;
1820
1821 if (device_can_wakeup(priv->device)) {
1822 priv->wolopts = WAKE_MAGIC; /* Magic Frame as default */
1823 enable_irq_wake(priv->wol_irq);
1824 }
1825
1826 return 0;
1827 }
1828
1829 /**
1830 * stmmac_dvr_probe
1831 * @pdev: platform device pointer
1832 * Description: the driver is initialized through platform_device.
1833 */
1834 static int stmmac_dvr_probe(struct platform_device *pdev)
1835 {
1836 int ret = 0;
1837 struct resource *res;
1838 void __iomem *addr = NULL;
1839 struct net_device *ndev = NULL;
1840 struct stmmac_priv *priv = NULL;
1841 struct plat_stmmacenet_data *plat_dat;
1842
1843 pr_info("STMMAC driver:\n\tplatform registration... ");
1844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1845 if (!res)
1846 return -ENODEV;
1847 pr_info("\tdone!\n");
1848
1849 if (!request_mem_region(res->start, resource_size(res),
1850 pdev->name)) {
1851 pr_err("%s: ERROR: memory allocation failed"
1852 "cannot get the I/O addr 0x%x\n",
1853 __func__, (unsigned int)res->start);
1854 return -EBUSY;
1855 }
1856
1857 addr = ioremap(res->start, resource_size(res));
1858 if (!addr) {
1859 pr_err("%s: ERROR: memory mapping failed\n", __func__);
1860 ret = -ENOMEM;
1861 goto out_release_region;
1862 }
1863
1864 ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1865 if (!ndev) {
1866 pr_err("%s: ERROR: allocating the device\n", __func__);
1867 ret = -ENOMEM;
1868 goto out_unmap;
1869 }
1870
1871 SET_NETDEV_DEV(ndev, &pdev->dev);
1872
1873 /* Get the MAC information */
1874 ndev->irq = platform_get_irq_byname(pdev, "macirq");
1875 if (ndev->irq == -ENXIO) {
1876 pr_err("%s: ERROR: MAC IRQ configuration "
1877 "information not found\n", __func__);
1878 ret = -ENXIO;
1879 goto out_free_ndev;
1880 }
1881
1882 priv = netdev_priv(ndev);
1883 priv->device = &(pdev->dev);
1884 priv->dev = ndev;
1885 plat_dat = pdev->dev.platform_data;
1886
1887 priv->plat = plat_dat;
1888
1889 priv->ioaddr = addr;
1890
1891 /*
1892 * On some platforms e.g. SPEAr the wake up irq differs from the mac irq
1893 * The external wake up irq can be passed through the platform code
1894 * named as "eth_wake_irq"
1895 *
1896 * In case the wake up interrupt is not passed from the platform
1897 * so the driver will continue to use the mac irq (ndev->irq)
1898 */
1899 priv->wol_irq = platform_get_irq_byname(pdev, "eth_wake_irq");
1900 if (priv->wol_irq == -ENXIO)
1901 priv->wol_irq = ndev->irq;
1902
1903 platform_set_drvdata(pdev, ndev);
1904
1905 /* Set the I/O base addr */
1906 ndev->base_addr = (unsigned long)addr;
1907
1908 /* Custom initialisation */
1909 if (priv->plat->init) {
1910 ret = priv->plat->init(pdev);
1911 if (unlikely(ret))
1912 goto out_free_ndev;
1913 }
1914
1915 /* MAC HW device detection */
1916 ret = stmmac_mac_device_setup(ndev);
1917 if (ret < 0)
1918 goto out_plat_exit;
1919
1920 /* Network Device Registration */
1921 ret = stmmac_probe(ndev);
1922 if (ret < 0)
1923 goto out_plat_exit;
1924
1925 /* Override with kernel parameters if supplied XXX CRS XXX
1926 * this needs to have multiple instances */
1927 if ((phyaddr >= 0) && (phyaddr <= 31))
1928 priv->plat->phy_addr = phyaddr;
1929
1930 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1931 "\tIO base addr: 0x%p)\n", ndev->name, pdev->name,
1932 pdev->id, ndev->irq, addr);
1933
1934 /* MDIO bus Registration */
1935 pr_debug("\tMDIO bus (id: %d)...", priv->plat->bus_id);
1936 ret = stmmac_mdio_register(ndev);
1937 if (ret < 0)
1938 goto out_unregister;
1939 pr_debug("registered!\n");
1940
1941 #ifdef CONFIG_STMMAC_DEBUG_FS
1942 ret = stmmac_init_fs(ndev);
1943 if (ret < 0)
1944 pr_warning("\tFailed debugFS registration");
1945 #endif
1946
1947 return 0;
1948
1949 out_unregister:
1950 unregister_netdev(ndev);
1951 out_plat_exit:
1952 if (priv->plat->exit)
1953 priv->plat->exit(pdev);
1954 out_free_ndev:
1955 free_netdev(ndev);
1956 platform_set_drvdata(pdev, NULL);
1957 out_unmap:
1958 iounmap(addr);
1959 out_release_region:
1960 release_mem_region(res->start, resource_size(res));
1961
1962 return ret;
1963 }
1964
1965 /**
1966 * stmmac_dvr_remove
1967 * @pdev: platform device pointer
1968 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1969 * changes the link status, releases the DMA descriptor rings,
1970 * unregisters the MDIO bus and unmaps the allocated memory.
1971 */
1972 static int stmmac_dvr_remove(struct platform_device *pdev)
1973 {
1974 struct net_device *ndev = platform_get_drvdata(pdev);
1975 struct stmmac_priv *priv = netdev_priv(ndev);
1976 struct resource *res;
1977
1978 pr_info("%s:\n\tremoving driver", __func__);
1979
1980 priv->hw->dma->stop_rx(priv->ioaddr);
1981 priv->hw->dma->stop_tx(priv->ioaddr);
1982
1983 stmmac_disable_mac(priv->ioaddr);
1984
1985 netif_carrier_off(ndev);
1986
1987 stmmac_mdio_unregister(ndev);
1988
1989 if (priv->plat->exit)
1990 priv->plat->exit(pdev);
1991
1992 platform_set_drvdata(pdev, NULL);
1993 unregister_netdev(ndev);
1994
1995 iounmap((void *)priv->ioaddr);
1996 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1997 release_mem_region(res->start, resource_size(res));
1998
1999 #ifdef CONFIG_STMMAC_DEBUG_FS
2000 stmmac_exit_fs();
2001 #endif
2002
2003 free_netdev(ndev);
2004
2005 return 0;
2006 }
2007
2008 #ifdef CONFIG_PM
2009 static int stmmac_suspend(struct device *dev)
2010 {
2011 struct net_device *ndev = dev_get_drvdata(dev);
2012 struct stmmac_priv *priv = netdev_priv(ndev);
2013 int dis_ic = 0;
2014
2015 if (!ndev || !netif_running(ndev))
2016 return 0;
2017
2018 if (priv->phydev)
2019 phy_stop(priv->phydev);
2020
2021 spin_lock(&priv->lock);
2022
2023 netif_device_detach(ndev);
2024 netif_stop_queue(ndev);
2025
2026 #ifdef CONFIG_STMMAC_TIMER
2027 priv->tm->timer_stop();
2028 if (likely(priv->tm->enable))
2029 dis_ic = 1;
2030 #endif
2031 napi_disable(&priv->napi);
2032
2033 /* Stop TX/RX DMA */
2034 priv->hw->dma->stop_tx(priv->ioaddr);
2035 priv->hw->dma->stop_rx(priv->ioaddr);
2036 /* Clear the Rx/Tx descriptors */
2037 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2038 dis_ic);
2039 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2040
2041 /* Enable Power down mode by programming the PMT regs */
2042 if (device_may_wakeup(priv->device))
2043 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2044 else
2045 stmmac_disable_mac(priv->ioaddr);
2046
2047 spin_unlock(&priv->lock);
2048 return 0;
2049 }
2050
2051 static int stmmac_resume(struct device *dev)
2052 {
2053 struct net_device *ndev = dev_get_drvdata(dev);
2054 struct stmmac_priv *priv = netdev_priv(ndev);
2055
2056 if (!netif_running(ndev))
2057 return 0;
2058
2059 spin_lock(&priv->lock);
2060
2061 /* Power Down bit, into the PM register, is cleared
2062 * automatically as soon as a magic packet or a Wake-up frame
2063 * is received. Anyway, it's better to manually clear
2064 * this bit because it can generate problems while resuming
2065 * from another devices (e.g. serial console). */
2066 if (device_may_wakeup(priv->device))
2067 priv->hw->mac->pmt(priv->ioaddr, 0);
2068
2069 netif_device_attach(ndev);
2070
2071 /* Enable the MAC and DMA */
2072 stmmac_enable_mac(priv->ioaddr);
2073 priv->hw->dma->start_tx(priv->ioaddr);
2074 priv->hw->dma->start_rx(priv->ioaddr);
2075
2076 #ifdef CONFIG_STMMAC_TIMER
2077 if (likely(priv->tm->enable))
2078 priv->tm->timer_start(tmrate);
2079 #endif
2080 napi_enable(&priv->napi);
2081
2082 netif_start_queue(ndev);
2083
2084 spin_unlock(&priv->lock);
2085
2086 if (priv->phydev)
2087 phy_start(priv->phydev);
2088
2089 return 0;
2090 }
2091
2092 static int stmmac_freeze(struct device *dev)
2093 {
2094 struct net_device *ndev = dev_get_drvdata(dev);
2095
2096 if (!ndev || !netif_running(ndev))
2097 return 0;
2098
2099 return stmmac_release(ndev);
2100 }
2101
2102 static int stmmac_restore(struct device *dev)
2103 {
2104 struct net_device *ndev = dev_get_drvdata(dev);
2105
2106 if (!ndev || !netif_running(ndev))
2107 return 0;
2108
2109 return stmmac_open(ndev);
2110 }
2111
2112 static const struct dev_pm_ops stmmac_pm_ops = {
2113 .suspend = stmmac_suspend,
2114 .resume = stmmac_resume,
2115 .freeze = stmmac_freeze,
2116 .thaw = stmmac_restore,
2117 .restore = stmmac_restore,
2118 };
2119 #else
2120 static const struct dev_pm_ops stmmac_pm_ops;
2121 #endif /* CONFIG_PM */
2122
2123 static struct platform_driver stmmac_driver = {
2124 .probe = stmmac_dvr_probe,
2125 .remove = stmmac_dvr_remove,
2126 .driver = {
2127 .name = STMMAC_RESOURCE_NAME,
2128 .owner = THIS_MODULE,
2129 .pm = &stmmac_pm_ops,
2130 },
2131 };
2132
2133 /**
2134 * stmmac_init_module - Entry point for the driver
2135 * Description: This function is the entry point for the driver.
2136 */
2137 static int __init stmmac_init_module(void)
2138 {
2139 int ret;
2140
2141 ret = platform_driver_register(&stmmac_driver);
2142 return ret;
2143 }
2144
2145 /**
2146 * stmmac_cleanup_module - Cleanup routine for the driver
2147 * Description: This function is the cleanup routine for the driver.
2148 */
2149 static void __exit stmmac_cleanup_module(void)
2150 {
2151 platform_driver_unregister(&stmmac_driver);
2152 }
2153
2154 #ifndef MODULE
2155 static int __init stmmac_cmdline_opt(char *str)
2156 {
2157 char *opt;
2158
2159 if (!str || !*str)
2160 return -EINVAL;
2161 while ((opt = strsep(&str, ",")) != NULL) {
2162 if (!strncmp(opt, "debug:", 6)) {
2163 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug))
2164 goto err;
2165 } else if (!strncmp(opt, "phyaddr:", 8)) {
2166 if (strict_strtoul(opt + 8, 0,
2167 (unsigned long *)&phyaddr))
2168 goto err;
2169 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2170 if (strict_strtoul(opt + 11, 0,
2171 (unsigned long *)&dma_txsize))
2172 goto err;
2173 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2174 if (strict_strtoul(opt + 11, 0,
2175 (unsigned long *)&dma_rxsize))
2176 goto err;
2177 } else if (!strncmp(opt, "buf_sz:", 7)) {
2178 if (strict_strtoul(opt + 7, 0,
2179 (unsigned long *)&buf_sz))
2180 goto err;
2181 } else if (!strncmp(opt, "tc:", 3)) {
2182 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc))
2183 goto err;
2184 } else if (!strncmp(opt, "watchdog:", 9)) {
2185 if (strict_strtoul(opt + 9, 0,
2186 (unsigned long *)&watchdog))
2187 goto err;
2188 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2189 if (strict_strtoul(opt + 10, 0,
2190 (unsigned long *)&flow_ctrl))
2191 goto err;
2192 } else if (!strncmp(opt, "pause:", 6)) {
2193 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause))
2194 goto err;
2195 #ifdef CONFIG_STMMAC_TIMER
2196 } else if (!strncmp(opt, "tmrate:", 7)) {
2197 if (strict_strtoul(opt + 7, 0,
2198 (unsigned long *)&tmrate))
2199 goto err;
2200 #endif
2201 }
2202 }
2203 return 0;
2204
2205 err:
2206 pr_err("%s: ERROR broken module parameter conversion", __func__);
2207 return -EINVAL;
2208 }
2209
2210 __setup("stmmaceth=", stmmac_cmdline_opt);
2211 #endif
2212
2213 module_init(stmmac_init_module);
2214 module_exit(stmmac_cleanup_module);
2215
2216 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2217 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2218 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree