arch/arm/mach-pxa/zeus.c

   1 /*
   2  *  Support for the Arcom ZEUS.
   3  *
   4  *  Copyright (C) 2006 Arcom Control Systems Ltd.
   5  *
   6  *  Loosely based on Arcom's 2.6.16.28.
   7  *  Maintained by Marc Zyngier <maz@misterjones.org>
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/cpufreq.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/pm.h>
  18 #include <linux/gpio.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/dm9000.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/spi/spi.h>
  23 #include <linux/spi/pxa2xx_spi.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26 #include <linux/mtd/physmap.h>
  27 #include <linux/i2c.h>
  28 #include <linux/i2c/pca953x.h>
  29 #include <linux/apm-emulation.h>
  30 #include <linux/can/platform/mcp251x.h>
  31
  32 #include <asm/mach-types.h>
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/map.h>
  35
  36 #include <plat/i2c.h>
  37
  38 #include <mach/pxa2xx-regs.h>
  39 #include <mach/regs-uart.h>
  40 #include <mach/ohci.h>
  41 #include <mach/mmc.h>
  42 #include <mach/pxa27x-udc.h>
  43 #include <mach/udc.h>
  44 #include <mach/pxafb.h>
  45 #include <mach/mfp-pxa27x.h>
  46 #include <mach/pm.h>
  47 #include <mach/audio.h>
  48 #include <mach/arcom-pcmcia.h>
  49 #include <mach/zeus.h>
  50 #include <mach/smemc.h>
  51
  52 #include "generic.h"
  53
  54 /*
  55  * Interrupt handling
  56  */
  57
  58 static unsigned long zeus_irq_enabled_mask;
  59 static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
  60 static const int zeus_isa_irq_map[] = {
  61         0,              /* ISA irq #0, invalid */
  62         0,              /* ISA irq #1, invalid */
  63         0,              /* ISA irq #2, invalid */
  64         1 << 0,         /* ISA irq #3 */
  65         1 << 1,         /* ISA irq #4 */
  66         1 << 2,         /* ISA irq #5 */
  67         1 << 3,         /* ISA irq #6 */
  68         1 << 4,         /* ISA irq #7 */
  69         0,              /* ISA irq #8, invalid */
  70         0,              /* ISA irq #9, invalid */
  71         1 << 5,         /* ISA irq #10 */
  72         1 << 6,         /* ISA irq #11 */
  73         1 << 7,         /* ISA irq #12 */
  74 };
  75
  76 static inline int zeus_irq_to_bitmask(unsigned int irq)
  77 {
  78         return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
  79 }
  80
  81 static inline int zeus_bit_to_irq(int bit)
  82 {
  83         return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
  84 }
  85
  86 static void zeus_ack_irq(struct irq_data *d)
  87 {
  88         __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
  89 }
  90
  91 static void zeus_mask_irq(struct irq_data *d)
  92 {
  93         zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
  94 }
  95
  96 static void zeus_unmask_irq(struct irq_data *d)
  97 {
  98         zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
  99 }
 100
 101 static inline unsigned long zeus_irq_pending(void)
 102 {
 103         return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
 104 }
 105
 106 static void zeus_irq_handler(unsigned int irq, struct irq_desc *desc)
 107 {
 108         unsigned long pending;
 109
 110         pending = zeus_irq_pending();
 111         do {
 112                 /* we're in a chained irq handler,
 113                  * so ack the interrupt by hand */
 114                 desc->irq_data.chip->irq_ack(&desc->irq_data);
 115
 116                 if (likely(pending)) {
 117                         irq = zeus_bit_to_irq(__ffs(pending));
 118                         generic_handle_irq(irq);
 119                 }
 120                 pending = zeus_irq_pending();
 121         } while (pending);
 122 }
 123
 124 static struct irq_chip zeus_irq_chip = {
 125         .name           = "ISA",
 126         .irq_ack        = zeus_ack_irq,
 127         .irq_mask       = zeus_mask_irq,
 128         .irq_unmask     = zeus_unmask_irq,
 129 };
 130
 131 static void __init zeus_init_irq(void)
 132 {
 133         int level;
 134         int isa_irq;
 135
 136         pxa27x_init_irq();
 137
 138         /* Peripheral IRQs. It would be nice to move those inside driver
 139            configuration, but it is not supported at the moment. */
 140         set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO),       IRQ_TYPE_EDGE_RISING);
 141         set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO),     IRQ_TYPE_EDGE_RISING);
 142         set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO),        IRQ_TYPE_EDGE_RISING);
 143         set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),    IRQ_TYPE_EDGE_FALLING);
 144         set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO),        IRQ_TYPE_EDGE_FALLING);
 145
 146         /* Setup ISA IRQs */
 147         for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
 148                 isa_irq = zeus_bit_to_irq(level);
 149                 set_irq_chip(isa_irq, &zeus_irq_chip);
 150                 set_irq_handler(isa_irq, handle_edge_irq);
 151                 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
 152         }
 153
 154         set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
 155         set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
 156 }
 157
 158
 159 /*
 160  * Platform devices
 161  */
 162
 163 /* Flash */
 164 static struct resource zeus_mtd_resources[] = {
 165         [0] = { /* NOR Flash (up to 64MB) */
 166                 .start  = ZEUS_FLASH_PHYS,
 167                 .end    = ZEUS_FLASH_PHYS + SZ_64M - 1,
 168                 .flags  = IORESOURCE_MEM,
 169         },
 170         [1] = { /* SRAM */
 171                 .start  = ZEUS_SRAM_PHYS,
 172                 .end    = ZEUS_SRAM_PHYS + SZ_512K - 1,
 173                 .flags  = IORESOURCE_MEM,
 174         },
 175 };
 176
 177 static struct physmap_flash_data zeus_flash_data[] = {
 178         [0] = {
 179                 .width          = 2,
 180                 .parts          = NULL,
 181                 .nr_parts       = 0,
 182         },
 183 };
 184
 185 static struct platform_device zeus_mtd_devices[] = {
 186         [0] = {
 187                 .name           = "physmap-flash",
 188                 .id             = 0,
 189                 .dev            = {
 190                         .platform_data = &zeus_flash_data[0],
 191                 },
 192                 .resource       = &zeus_mtd_resources[0],
 193                 .num_resources  = 1,
 194         },
 195 };
 196
 197 /* Serial */
 198 static struct resource zeus_serial_resources[] = {
 199         {
 200                 .start  = 0x10000000,
 201                 .end    = 0x1000000f,
 202                 .flags  = IORESOURCE_MEM,
 203         },
 204         {
 205                 .start  = 0x10800000,
 206                 .end    = 0x1080000f,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209         {
 210                 .start  = 0x11000000,
 211                 .end    = 0x1100000f,
 212                 .flags  = IORESOURCE_MEM,
 213         },
 214         {
 215                 .start  = 0x40100000,
 216                 .end    = 0x4010001f,
 217                 .flags  = IORESOURCE_MEM,
 218         },
 219         {
 220                 .start  = 0x40200000,
 221                 .end    = 0x4020001f,
 222                 .flags  = IORESOURCE_MEM,
 223         },
 224         {
 225                 .start  = 0x40700000,
 226                 .end    = 0x4070001f,
 227                 .flags  = IORESOURCE_MEM,
 228         },
 229 };
 230
 231 static struct plat_serial8250_port serial_platform_data[] = {
 232         /* External UARTs */
 233         /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
 234         { /* COM1 */
 235                 .mapbase        = 0x10000000,
 236                 .irq            = gpio_to_irq(ZEUS_UARTA_GPIO),
 237                 .irqflags       = IRQF_TRIGGER_RISING,
 238                 .uartclk        = 14745600,
 239                 .regshift       = 1,
 240                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 241                 .iotype         = UPIO_MEM,
 242         },
 243         { /* COM2 */
 244                 .mapbase        = 0x10800000,
 245                 .irq            = gpio_to_irq(ZEUS_UARTB_GPIO),
 246                 .irqflags       = IRQF_TRIGGER_RISING,
 247                 .uartclk        = 14745600,
 248                 .regshift       = 1,
 249                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 250                 .iotype         = UPIO_MEM,
 251         },
 252         { /* COM3 */
 253                 .mapbase        = 0x11000000,
 254                 .irq            = gpio_to_irq(ZEUS_UARTC_GPIO),
 255                 .irqflags       = IRQF_TRIGGER_RISING,
 256                 .uartclk        = 14745600,
 257                 .regshift       = 1,
 258                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 259                 .iotype         = UPIO_MEM,
 260         },
 261         { /* COM4 */
 262                 .mapbase        = 0x11800000,
 263                 .irq            = gpio_to_irq(ZEUS_UARTD_GPIO),
 264                 .irqflags       = IRQF_TRIGGER_RISING,
 265                 .uartclk        = 14745600,
 266                 .regshift       = 1,
 267                 .flags          = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 268                 .iotype         = UPIO_MEM,
 269         },
 270         /* Internal UARTs */
 271         { /* FFUART */
 272                 .membase        = (void *)&FFUART,
 273                 .mapbase        = __PREG(FFUART),
 274                 .irq            = IRQ_FFUART,
 275                 .uartclk        = 921600 * 16,
 276                 .regshift       = 2,
 277                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 278                 .iotype         = UPIO_MEM,
 279         },
 280         { /* BTUART */
 281                 .membase        = (void *)&BTUART,
 282                 .mapbase        = __PREG(BTUART),
 283                 .irq            = IRQ_BTUART,
 284                 .uartclk        = 921600 * 16,
 285                 .regshift       = 2,
 286                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 287                 .iotype         = UPIO_MEM,
 288         },
 289         { /* STUART */
 290                 .membase        = (void *)&STUART,
 291                 .mapbase        = __PREG(STUART),
 292                 .irq            = IRQ_STUART,
 293                 .uartclk        = 921600 * 16,
 294                 .regshift       = 2,
 295                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 296                 .iotype         = UPIO_MEM,
 297         },
 298         { },
 299 };
 300
 301 static struct platform_device zeus_serial_device = {
 302         .name = "serial8250",
 303         .id   = PLAT8250_DEV_PLATFORM,
 304         .dev  = {
 305                 .platform_data = serial_platform_data,
 306         },
 307         .num_resources  = ARRAY_SIZE(zeus_serial_resources),
 308         .resource       = zeus_serial_resources,
 309 };
 310
 311 /* Ethernet */
 312 static struct resource zeus_dm9k0_resource[] = {
 313         [0] = {
 314                 .start = ZEUS_ETH0_PHYS,
 315                 .end   = ZEUS_ETH0_PHYS + 1,
 316                 .flags = IORESOURCE_MEM
 317         },
 318         [1] = {
 319                 .start = ZEUS_ETH0_PHYS + 2,
 320                 .end   = ZEUS_ETH0_PHYS + 3,
 321                 .flags = IORESOURCE_MEM
 322         },
 323         [2] = {
 324                 .start = gpio_to_irq(ZEUS_ETH0_GPIO),
 325                 .end   = gpio_to_irq(ZEUS_ETH0_GPIO),
 326                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 327         },
 328 };
 329
 330 static struct resource zeus_dm9k1_resource[] = {
 331         [0] = {
 332                 .start = ZEUS_ETH1_PHYS,
 333                 .end   = ZEUS_ETH1_PHYS + 1,
 334                 .flags = IORESOURCE_MEM
 335         },
 336         [1] = {
 337                 .start = ZEUS_ETH1_PHYS + 2,
 338                 .end   = ZEUS_ETH1_PHYS + 3,
 339                 .flags = IORESOURCE_MEM,
 340         },
 341         [2] = {
 342                 .start = gpio_to_irq(ZEUS_ETH1_GPIO),
 343                 .end   = gpio_to_irq(ZEUS_ETH1_GPIO),
 344                 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
 345         },
 346 };
 347
 348 static struct dm9000_plat_data zeus_dm9k_platdata = {
 349         .flags          = DM9000_PLATF_16BITONLY,
 350 };
 351
 352 static struct platform_device zeus_dm9k0_device = {
 353         .name           = "dm9000",
 354         .id             = 0,
 355         .num_resources  = ARRAY_SIZE(zeus_dm9k0_resource),
 356         .resource       = zeus_dm9k0_resource,
 357         .dev            = {
 358                 .platform_data = &zeus_dm9k_platdata,
 359         }
 360 };
 361
 362 static struct platform_device zeus_dm9k1_device = {
 363         .name           = "dm9000",
 364         .id             = 1,
 365         .num_resources  = ARRAY_SIZE(zeus_dm9k1_resource),
 366         .resource       = zeus_dm9k1_resource,
 367         .dev            = {
 368                 .platform_data = &zeus_dm9k_platdata,
 369         }
 370 };
 371
 372 /* External SRAM */
 373 static struct resource zeus_sram_resource = {
 374         .start          = ZEUS_SRAM_PHYS,
 375         .end            = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
 376         .flags          = IORESOURCE_MEM,
 377 };
 378
 379 static struct platform_device zeus_sram_device = {
 380         .name           = "pxa2xx-8bit-sram",
 381         .id             = 0,
 382         .num_resources  = 1,
 383         .resource       = &zeus_sram_resource,
 384 };
 385
 386 /* SPI interface on SSP3 */
 387 static struct pxa2xx_spi_master pxa2xx_spi_ssp3_master_info = {
 388         .num_chipselect = 1,
 389         .enable_dma     = 1,
 390 };
 391
 392 /* CAN bus on SPI */
 393 static int zeus_mcp2515_setup(struct spi_device *sdev)
 394 {
 395         int err;
 396
 397         err = gpio_request(ZEUS_CAN_SHDN_GPIO, "CAN shutdown");
 398         if (err)
 399                 return err;
 400
 401         err = gpio_direction_output(ZEUS_CAN_SHDN_GPIO, 1);
 402         if (err) {
 403                 gpio_free(ZEUS_CAN_SHDN_GPIO);
 404                 return err;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int zeus_mcp2515_transceiver_enable(int enable)
 411 {
 412         gpio_set_value(ZEUS_CAN_SHDN_GPIO, !enable);
 413         return 0;
 414 }
 415
 416 static struct mcp251x_platform_data zeus_mcp2515_pdata = {
 417         .oscillator_frequency   = 16*1000*1000,
 418         .board_specific_setup   = zeus_mcp2515_setup,
 419         .power_enable           = zeus_mcp2515_transceiver_enable,
 420 };
 421
 422 static struct spi_board_info zeus_spi_board_info[] = {
 423         [0] = {
 424                 .modalias       = "mcp2515",
 425                 .platform_data  = &zeus_mcp2515_pdata,
 426                 .irq            = gpio_to_irq(ZEUS_CAN_GPIO),
 427                 .max_speed_hz   = 1*1000*1000,
 428                 .bus_num        = 3,
 429                 .mode           = SPI_MODE_0,
 430                 .chip_select    = 0,
 431         },
 432 };
 433
 434 /* Leds */
 435 static struct gpio_led zeus_leds[] = {
 436         [0] = {
 437                 .name            = "zeus:yellow:1",
 438                 .default_trigger = "heartbeat",
 439                 .gpio            = ZEUS_EXT0_GPIO(3),
 440                 .active_low      = 1,
 441         },
 442         [1] = {
 443                 .name            = "zeus:yellow:2",
 444                 .default_trigger = "default-on",
 445                 .gpio            = ZEUS_EXT0_GPIO(4),
 446                 .active_low      = 1,
 447         },
 448         [2] = {
 449                 .name            = "zeus:yellow:3",
 450                 .default_trigger = "default-on",
 451                 .gpio            = ZEUS_EXT0_GPIO(5),
 452                 .active_low      = 1,
 453         },
 454 };
 455
 456 static struct gpio_led_platform_data zeus_leds_info = {
 457         .leds           = zeus_leds,
 458         .num_leds       = ARRAY_SIZE(zeus_leds),
 459 };
 460
 461 static struct platform_device zeus_leds_device = {
 462         .name           = "leds-gpio",
 463         .id             = -1,
 464         .dev            = {
 465                 .platform_data  = &zeus_leds_info,
 466         },
 467 };
 468
 469 static void zeus_cf_reset(int state)
 470 {
 471         u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
 472
 473         if (state)
 474                 cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
 475         else
 476                 cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
 477
 478         __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
 479 }
 480
 481 static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
 482         .cd_gpio        = ZEUS_CF_CD_GPIO,
 483         .rdy_gpio       = ZEUS_CF_RDY_GPIO,
 484         .pwr_gpio       = ZEUS_CF_PWEN_GPIO,
 485         .reset          = zeus_cf_reset,
 486 };
 487
 488 static struct platform_device zeus_pcmcia_device = {
 489         .name           = "zeus-pcmcia",
 490         .id             = -1,
 491         .dev            = {
 492                 .platform_data  = &zeus_pcmcia_info,
 493         },
 494 };
 495
 496 static struct resource zeus_max6369_resource = {
 497         .start          = ZEUS_CPLD_EXTWDOG_PHYS,
 498         .end            = ZEUS_CPLD_EXTWDOG_PHYS,
 499         .flags          = IORESOURCE_MEM,
 500 };
 501
 502 struct platform_device zeus_max6369_device = {
 503         .name           = "max6369_wdt",
 504         .id             = -1,
 505         .resource       = &zeus_max6369_resource,
 506         .num_resources  = 1,
 507 };
 508
 509 static struct platform_device *zeus_devices[] __initdata = {
 510         &zeus_serial_device,
 511         &zeus_mtd_devices[0],
 512         &zeus_dm9k0_device,
 513         &zeus_dm9k1_device,
 514         &zeus_sram_device,
 515         &zeus_leds_device,
 516         &zeus_pcmcia_device,
 517         &zeus_max6369_device,
 518 };
 519
 520 /* AC'97 */
 521 static pxa2xx_audio_ops_t zeus_ac97_info = {
 522         .reset_gpio = 95,
 523 };
 524
 525
 526 /*
 527  * USB host
 528  */
 529
 530 static int zeus_ohci_init(struct device *dev)
 531 {
 532         int err;
 533
 534         /* Switch on port 2. */
 535         if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
 536                 dev_err(dev, "Can't request USB2_PWREN\n");
 537                 return err;
 538         }
 539
 540         if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
 541                 gpio_free(ZEUS_USB2_PWREN_GPIO);
 542                 dev_err(dev, "Can't enable USB2_PWREN\n");
 543                 return err;
 544         }
 545
 546         /* Port 2 is shared between host and client interface. */
 547         UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 548
 549         return 0;
 550 }
 551
 552 static void zeus_ohci_exit(struct device *dev)
 553 {
 554         /* Power-off port 2 */
 555         gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
 556         gpio_free(ZEUS_USB2_PWREN_GPIO);
 557 }
 558
 559 static struct pxaohci_platform_data zeus_ohci_platform_data = {
 560         .port_mode      = PMM_NPS_MODE,
 561         /* Clear Power Control Polarity Low and set Power Sense
 562          * Polarity Low. Supply power to USB ports. */
 563         .flags          = ENABLE_PORT_ALL | POWER_SENSE_LOW,
 564         .init           = zeus_ohci_init,
 565         .exit           = zeus_ohci_exit,
 566 };
 567
 568 /*
 569  * Flat Panel
 570  */
 571
 572 static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
 573 {
 574         gpio_set_value(ZEUS_LCD_EN_GPIO, on);
 575 }
 576
 577 static void zeus_backlight_power(int on)
 578 {
 579         gpio_set_value(ZEUS_BKLEN_GPIO, on);
 580 }
 581
 582 static int zeus_setup_fb_gpios(void)
 583 {
 584         int err;
 585
 586         if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
 587                 goto out_err;
 588
 589         if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
 590                 goto out_err_lcd;
 591
 592         if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
 593                 goto out_err_lcd;
 594
 595         if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
 596                 goto out_err_bkl;
 597
 598         return 0;
 599
 600 out_err_bkl:
 601         gpio_free(ZEUS_BKLEN_GPIO);
 602 out_err_lcd:
 603         gpio_free(ZEUS_LCD_EN_GPIO);
 604 out_err:
 605         return err;
 606 }
 607
 608 static struct pxafb_mode_info zeus_fb_mode_info[] = {
 609         {
 610                 .pixclock       = 39722,
 611
 612                 .xres           = 640,
 613                 .yres           = 480,
 614
 615                 .bpp            = 16,
 616
 617                 .hsync_len      = 63,
 618                 .left_margin    = 16,
 619                 .right_margin   = 81,
 620
 621                 .vsync_len      = 2,
 622                 .upper_margin   = 12,
 623                 .lower_margin   = 31,
 624
 625                 .sync           = 0,
 626         },
 627 };
 628
 629 static struct pxafb_mach_info zeus_fb_info = {
 630         .modes                  = zeus_fb_mode_info,
 631         .num_modes              = 1,
 632         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 633         .pxafb_lcd_power        = zeus_lcd_power,
 634         .pxafb_backlight_power  = zeus_backlight_power,
 635 };
 636
 637 /*
 638  * MMC/SD Device
 639  *
 640  * The card detect interrupt isn't debounced so we delay it by 250ms
 641  * to give the card a chance to fully insert/eject.
 642  */
 643
 644 static struct pxamci_platform_data zeus_mci_platform_data = {
 645         .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
 646         .detect_delay_ms        = 250,
 647         .gpio_card_detect       = ZEUS_MMC_CD_GPIO,
 648         .gpio_card_ro           = ZEUS_MMC_WP_GPIO,
 649         .gpio_card_ro_invert    = 1,
 650         .gpio_power             = -1
 651 };
 652
 653 /*
 654  * USB Device Controller
 655  */
 656 static void zeus_udc_command(int cmd)
 657 {
 658         switch (cmd) {
 659         case PXA2XX_UDC_CMD_DISCONNECT:
 660                 pr_info("zeus: disconnecting USB client\n");
 661                 UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
 662                 break;
 663
 664         case PXA2XX_UDC_CMD_CONNECT:
 665                 pr_info("zeus: connecting USB client\n");
 666                 UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
 667                 break;
 668         }
 669 }
 670
 671 static struct pxa2xx_udc_mach_info zeus_udc_info = {
 672         .udc_command = zeus_udc_command,
 673 };
 674
 675 #ifdef CONFIG_PM
 676 static void zeus_power_off(void)
 677 {
 678         local_irq_disable();
 679         pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
 680 }
 681 #else
 682 #define zeus_power_off   NULL
 683 #endif
 684
 685 #ifdef CONFIG_APM_EMULATION
 686 static void zeus_get_power_status(struct apm_power_info *info)
 687 {
 688         /* Power supply is always present */
 689         info->ac_line_status    = APM_AC_ONLINE;
 690         info->battery_status    = APM_BATTERY_STATUS_NOT_PRESENT;
 691         info->battery_flag      = APM_BATTERY_FLAG_NOT_PRESENT;
 692 }
 693
 694 static inline void zeus_setup_apm(void)
 695 {
 696         apm_get_power_status = zeus_get_power_status;
 697 }
 698 #else
 699 static inline void zeus_setup_apm(void)
 700 {
 701 }
 702 #endif
 703
 704 static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
 705                              unsigned ngpio, void *context)
 706 {
 707         int i;
 708         u8 pcb_info = 0;
 709
 710         for (i = 0; i < 8; i++) {
 711                 int pcb_bit = gpio + i + 8;
 712
 713                 if (gpio_request(pcb_bit, "pcb info")) {
 714                         dev_err(&client->dev, "Can't request pcb info %d\n", i);
 715                         continue;
 716                 }
 717
 718                 if (gpio_direction_input(pcb_bit)) {
 719                         dev_err(&client->dev, "Can't read pcb info %d\n", i);
 720                         gpio_free(pcb_bit);
 721                         continue;
 722                 }
 723
 724                 pcb_info |= !!gpio_get_value(pcb_bit) << i;
 725
 726                 gpio_free(pcb_bit);
 727         }
 728
 729         dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
 730                  pcb_info >> 4, pcb_info & 0xf);
 731
 732         return 0;
 733 }
 734
 735 static struct pca953x_platform_data zeus_pca953x_pdata[] = {
 736         [0] = { .gpio_base      = ZEUS_EXT0_GPIO_BASE, },
 737         [1] = {
 738                 .gpio_base      = ZEUS_EXT1_GPIO_BASE,
 739                 .setup          = zeus_get_pcb_info,
 740         },
 741         [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
 742 };
 743
 744 static struct i2c_board_info __initdata zeus_i2c_devices[] = {
 745         {
 746                 I2C_BOARD_INFO("pca9535",       0x21),
 747                 .platform_data  = &zeus_pca953x_pdata[0],
 748         },
 749         {
 750                 I2C_BOARD_INFO("pca9535",       0x22),
 751                 .platform_data  = &zeus_pca953x_pdata[1],
 752         },
 753         {
 754                 I2C_BOARD_INFO("pca9535",       0x20),
 755                 .platform_data  = &zeus_pca953x_pdata[2],
 756                 .irq            = gpio_to_irq(ZEUS_EXTGPIO_GPIO),
 757         },
 758         { I2C_BOARD_INFO("lm75a",       0x48) },
 759         { I2C_BOARD_INFO("24c01",       0x50) },
 760         { I2C_BOARD_INFO("isl1208",     0x6f) },
 761 };
 762
 763 static mfp_cfg_t zeus_pin_config[] __initdata = {
 764         /* AC97 */
 765         GPIO28_AC97_BITCLK,
 766         GPIO29_AC97_SDATA_IN_0,
 767         GPIO30_AC97_SDATA_OUT,
 768         GPIO31_AC97_SYNC,
 769
 770         GPIO15_nCS_1,
 771         GPIO78_nCS_2,
 772         GPIO80_nCS_4,
 773         GPIO33_nCS_5,
 774
 775         GPIO22_GPIO,
 776         GPIO32_MMC_CLK,
 777         GPIO92_MMC_DAT_0,
 778         GPIO109_MMC_DAT_1,
 779         GPIO110_MMC_DAT_2,
 780         GPIO111_MMC_DAT_3,
 781         GPIO112_MMC_CMD,
 782
 783         GPIO88_USBH1_PWR,
 784         GPIO89_USBH1_PEN,
 785         GPIO119_USBH2_PWR,
 786         GPIO120_USBH2_PEN,
 787
 788         GPIO86_LCD_LDD_16,
 789         GPIO87_LCD_LDD_17,
 790
 791         GPIO102_GPIO,
 792         GPIO104_CIF_DD_2,
 793         GPIO105_CIF_DD_1,
 794
 795         GPIO81_SSP3_TXD,
 796         GPIO82_SSP3_RXD,
 797         GPIO83_SSP3_SFRM,
 798         GPIO84_SSP3_SCLK,
 799
 800         GPIO48_nPOE,
 801         GPIO49_nPWE,
 802         GPIO50_nPIOR,
 803         GPIO51_nPIOW,
 804         GPIO85_nPCE_1,
 805         GPIO54_nPCE_2,
 806         GPIO79_PSKTSEL,
 807         GPIO55_nPREG,
 808         GPIO56_nPWAIT,
 809         GPIO57_nIOIS16,
 810         GPIO36_GPIO,            /* CF CD */
 811         GPIO97_GPIO,            /* CF PWREN */
 812         GPIO99_GPIO,            /* CF RDY */
 813 };
 814
 815 /*
 816  * DM9k MSCx settings:  SRAM, 16 bits
 817  *                      17 cycles delay first access
 818  *                       5 cycles delay next access
 819  *                      13 cycles recovery time
 820  *                      faster device
 821  */
 822 #define DM9K_MSC_VALUE          0xe4c9
 823
 824 static void __init zeus_init(void)
 825 {
 826         u16 dm9000_msc = DM9K_MSC_VALUE;
 827         u32 msc0, msc1;
 828
 829         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
 830         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
 831
 832         /* Fix timings for dm9000s (CS1/CS2)*/
 833         msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
 834         msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
 835         __raw_writel(msc0, MSC0);
 836         __raw_writel(msc1, MSC1);
 837
 838         pm_power_off = zeus_power_off;
 839         zeus_setup_apm();
 840
 841         pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
 842
 843         platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
 844
 845         pxa_set_ohci_info(&zeus_ohci_platform_data);
 846
 847         if (zeus_setup_fb_gpios())
 848                 pr_err("Failed to setup fb gpios\n");
 849         else
 850                 set_pxa_fb_info(&zeus_fb_info);
 851
 852         pxa_set_mci_info(&zeus_mci_platform_data);
 853         pxa_set_udc_info(&zeus_udc_info);
 854         pxa_set_ac97_info(&zeus_ac97_info);
 855         pxa_set_i2c_info(NULL);
 856         i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
 857         pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
 858         spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
 859 }
 860
 861 static struct map_desc zeus_io_desc[] __initdata = {
 862         {
 863                 .virtual = ZEUS_CPLD_VERSION,
 864                 .pfn     = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
 865                 .length  = 0x1000,
 866                 .type    = MT_DEVICE,
 867         },
 868         {
 869                 .virtual = ZEUS_CPLD_ISA_IRQ,
 870                 .pfn     = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
 871                 .length  = 0x1000,
 872                 .type    = MT_DEVICE,
 873         },
 874         {
 875                 .virtual = ZEUS_CPLD_CONTROL,
 876                 .pfn     = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
 877                 .length  = 0x1000,
 878                 .type    = MT_DEVICE,
 879         },
 880         {
 881                 .virtual = ZEUS_PC104IO,
 882                 .pfn     = __phys_to_pfn(ZEUS_PC104IO_PHYS),
 883                 .length  = 0x00800000,
 884                 .type    = MT_DEVICE,
 885         },
 886 };
 887
 888 static void __init zeus_map_io(void)
 889 {
 890         pxa27x_map_io();
 891
 892         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
 893
 894         /* Clear PSPR to ensure a full restart on wake-up. */
 895         PMCR = PSPR = 0;
 896
 897         /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
 898         OSCC |= OSCC_OON;
 899
 900         /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
 901          * float chip selects and PCMCIA */
 902         PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
 903 }
 904
 905 MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
 906         /* Maintainer: Marc Zyngier <maz@misterjones.org> */
 907         .boot_params    = 0xa0000100,
 908         .map_io         = zeus_map_io,
 909         .nr_irqs        = ZEUS_NR_IRQS,
 910         .init_irq       = zeus_init_irq,
 911         .timer          = &pxa_timer,
 912         .init_machine   = zeus_init,
 913 MACHINE_END
 914