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KVM: Handle virtualization instruction #UD faults during reboot
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / svm.c
blob9390a31c06f4c68e9f2689f16661df2d29c71830
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "kvm_svm.h"
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/vmalloc.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27
28 #include <asm/desc.h>
29
30 #define __ex(x) __kvm_handle_fault_on_reboot(x)
31
32 MODULE_AUTHOR("Qumranet");
33 MODULE_LICENSE("GPL");
34
35 #define IOPM_ALLOC_ORDER 2
36 #define MSRPM_ALLOC_ORDER 1
37
38 #define DB_VECTOR 1
39 #define UD_VECTOR 6
40 #define GP_VECTOR 13
41
42 #define DR7_GD_MASK (1 << 13)
43 #define DR6_BD_MASK (1 << 13)
44
45 #define SEG_TYPE_LDT 2
46 #define SEG_TYPE_BUSY_TSS16 3
47
48 #define SVM_FEATURE_NPT (1 << 0)
49 #define SVM_FEATURE_LBRV (1 << 1)
50 #define SVM_DEATURE_SVML (1 << 2)
51
52 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
53
54 /* enable NPT for AMD64 and X86 with PAE */
55 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
56 static bool npt_enabled = true;
57 #else
58 static bool npt_enabled = false;
59 #endif
60 static int npt = 1;
61
62 module_param(npt, int, S_IRUGO);
63
64 static void kvm_reput_irq(struct vcpu_svm *svm);
65
66 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
67 {
68 return container_of(vcpu, struct vcpu_svm, vcpu);
69 }
70
71 static unsigned long iopm_base;
72
73 struct kvm_ldttss_desc {
74 u16 limit0;
75 u16 base0;
76 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
77 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
78 u32 base3;
79 u32 zero1;
80 } __attribute__((packed));
81
82 struct svm_cpu_data {
83 int cpu;
84
85 u64 asid_generation;
86 u32 max_asid;
87 u32 next_asid;
88 struct kvm_ldttss_desc *tss_desc;
89
90 struct page *save_area;
91 };
92
93 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
94 static uint32_t svm_features;
95
96 struct svm_init_data {
97 int cpu;
98 int r;
99 };
100
101 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
102
103 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
104 #define MSRS_RANGE_SIZE 2048
105 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
106
107 #define MAX_INST_SIZE 15
108
109 static inline u32 svm_has(u32 feat)
110 {
111 return svm_features & feat;
112 }
113
114 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
115 {
116 int word_index = __ffs(vcpu->arch.irq_summary);
117 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
118 int irq = word_index * BITS_PER_LONG + bit_index;
119
120 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
121 if (!vcpu->arch.irq_pending[word_index])
122 clear_bit(word_index, &vcpu->arch.irq_summary);
123 return irq;
124 }
125
126 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
127 {
128 set_bit(irq, vcpu->arch.irq_pending);
129 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
130 }
131
132 static inline void clgi(void)
133 {
134 asm volatile (__ex(SVM_CLGI));
135 }
136
137 static inline void stgi(void)
138 {
139 asm volatile (__ex(SVM_STGI));
140 }
141
142 static inline void invlpga(unsigned long addr, u32 asid)
143 {
144 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
145 }
146
147 static inline unsigned long kvm_read_cr2(void)
148 {
149 unsigned long cr2;
150
151 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
152 return cr2;
153 }
154
155 static inline void kvm_write_cr2(unsigned long val)
156 {
157 asm volatile ("mov %0, %%cr2" :: "r" (val));
158 }
159
160 static inline unsigned long read_dr6(void)
161 {
162 unsigned long dr6;
163
164 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
165 return dr6;
166 }
167
168 static inline void write_dr6(unsigned long val)
169 {
170 asm volatile ("mov %0, %%dr6" :: "r" (val));
171 }
172
173 static inline unsigned long read_dr7(void)
174 {
175 unsigned long dr7;
176
177 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
178 return dr7;
179 }
180
181 static inline void write_dr7(unsigned long val)
182 {
183 asm volatile ("mov %0, %%dr7" :: "r" (val));
184 }
185
186 static inline void force_new_asid(struct kvm_vcpu *vcpu)
187 {
188 to_svm(vcpu)->asid_generation--;
189 }
190
191 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
192 {
193 force_new_asid(vcpu);
194 }
195
196 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
197 {
198 if (!npt_enabled && !(efer & EFER_LMA))
199 efer &= ~EFER_LME;
200
201 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
202 vcpu->arch.shadow_efer = efer;
203 }
204
205 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
206 bool has_error_code, u32 error_code)
207 {
208 struct vcpu_svm *svm = to_svm(vcpu);
209
210 svm->vmcb->control.event_inj = nr
211 | SVM_EVTINJ_VALID
212 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
213 | SVM_EVTINJ_TYPE_EXEPT;
214 svm->vmcb->control.event_inj_err = error_code;
215 }
216
217 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
218 {
219 struct vcpu_svm *svm = to_svm(vcpu);
220
221 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
222 }
223
224 static int is_external_interrupt(u32 info)
225 {
226 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
227 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
228 }
229
230 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
231 {
232 struct vcpu_svm *svm = to_svm(vcpu);
233
234 if (!svm->next_rip) {
235 printk(KERN_DEBUG "%s: NOP\n", __func__);
236 return;
237 }
238 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
239 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
240 __func__,
241 svm->vmcb->save.rip,
242 svm->next_rip);
243
244 vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
245 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
246
247 vcpu->arch.interrupt_window_open = 1;
248 }
249
250 static int has_svm(void)
251 {
252 uint32_t eax, ebx, ecx, edx;
253
254 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
255 printk(KERN_INFO "has_svm: not amd\n");
256 return 0;
257 }
258
259 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
260 if (eax < SVM_CPUID_FUNC) {
261 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
262 return 0;
263 }
264
265 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
266 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
267 printk(KERN_DEBUG "has_svm: svm not available\n");
268 return 0;
269 }
270 return 1;
271 }
272
273 static void svm_hardware_disable(void *garbage)
274 {
275 struct svm_cpu_data *svm_data
276 = per_cpu(svm_data, raw_smp_processor_id());
277
278 if (svm_data) {
279 uint64_t efer;
280
281 wrmsrl(MSR_VM_HSAVE_PA, 0);
282 rdmsrl(MSR_EFER, efer);
283 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
284 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
285 __free_page(svm_data->save_area);
286 kfree(svm_data);
287 }
288 }
289
290 static void svm_hardware_enable(void *garbage)
291 {
292
293 struct svm_cpu_data *svm_data;
294 uint64_t efer;
295 struct desc_ptr gdt_descr;
296 struct desc_struct *gdt;
297 int me = raw_smp_processor_id();
298
299 if (!has_svm()) {
300 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
301 return;
302 }
303 svm_data = per_cpu(svm_data, me);
304
305 if (!svm_data) {
306 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
307 me);
308 return;
309 }
310
311 svm_data->asid_generation = 1;
312 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
313 svm_data->next_asid = svm_data->max_asid + 1;
314
315 asm volatile ("sgdt %0" : "=m"(gdt_descr));
316 gdt = (struct desc_struct *)gdt_descr.address;
317 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
318
319 rdmsrl(MSR_EFER, efer);
320 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
321
322 wrmsrl(MSR_VM_HSAVE_PA,
323 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
324 }
325
326 static int svm_cpu_init(int cpu)
327 {
328 struct svm_cpu_data *svm_data;
329 int r;
330
331 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
332 if (!svm_data)
333 return -ENOMEM;
334 svm_data->cpu = cpu;
335 svm_data->save_area = alloc_page(GFP_KERNEL);
336 r = -ENOMEM;
337 if (!svm_data->save_area)
338 goto err_1;
339
340 per_cpu(svm_data, cpu) = svm_data;
341
342 return 0;
343
344 err_1:
345 kfree(svm_data);
346 return r;
347
348 }
349
350 static void set_msr_interception(u32 *msrpm, unsigned msr,
351 int read, int write)
352 {
353 int i;
354
355 for (i = 0; i < NUM_MSR_MAPS; i++) {
356 if (msr >= msrpm_ranges[i] &&
357 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
358 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
359 msrpm_ranges[i]) * 2;
360
361 u32 *base = msrpm + (msr_offset / 32);
362 u32 msr_shift = msr_offset % 32;
363 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
364 *base = (*base & ~(0x3 << msr_shift)) |
365 (mask << msr_shift);
366 return;
367 }
368 }
369 BUG();
370 }
371
372 static void svm_vcpu_init_msrpm(u32 *msrpm)
373 {
374 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
375
376 #ifdef CONFIG_X86_64
377 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
378 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
379 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
380 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
381 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
382 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
383 #endif
384 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
385 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
386 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
387 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
388 }
389
390 static void svm_enable_lbrv(struct vcpu_svm *svm)
391 {
392 u32 *msrpm = svm->msrpm;
393
394 svm->vmcb->control.lbr_ctl = 1;
395 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
396 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
397 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
398 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
399 }
400
401 static void svm_disable_lbrv(struct vcpu_svm *svm)
402 {
403 u32 *msrpm = svm->msrpm;
404
405 svm->vmcb->control.lbr_ctl = 0;
406 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
407 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
408 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
409 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
410 }
411
412 static __init int svm_hardware_setup(void)
413 {
414 int cpu;
415 struct page *iopm_pages;
416 void *iopm_va;
417 int r;
418
419 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
420
421 if (!iopm_pages)
422 return -ENOMEM;
423
424 iopm_va = page_address(iopm_pages);
425 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
426 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
427 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
428
429 if (boot_cpu_has(X86_FEATURE_NX))
430 kvm_enable_efer_bits(EFER_NX);
431
432 for_each_online_cpu(cpu) {
433 r = svm_cpu_init(cpu);
434 if (r)
435 goto err;
436 }
437
438 svm_features = cpuid_edx(SVM_CPUID_FUNC);
439
440 if (!svm_has(SVM_FEATURE_NPT))
441 npt_enabled = false;
442
443 if (npt_enabled && !npt) {
444 printk(KERN_INFO "kvm: Nested Paging disabled\n");
445 npt_enabled = false;
446 }
447
448 if (npt_enabled) {
449 printk(KERN_INFO "kvm: Nested Paging enabled\n");
450 kvm_enable_tdp();
451 }
452
453 return 0;
454
455 err:
456 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
457 iopm_base = 0;
458 return r;
459 }
460
461 static __exit void svm_hardware_unsetup(void)
462 {
463 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
464 iopm_base = 0;
465 }
466
467 static void init_seg(struct vmcb_seg *seg)
468 {
469 seg->selector = 0;
470 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
471 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
472 seg->limit = 0xffff;
473 seg->base = 0;
474 }
475
476 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
477 {
478 seg->selector = 0;
479 seg->attrib = SVM_SELECTOR_P_MASK | type;
480 seg->limit = 0xffff;
481 seg->base = 0;
482 }
483
484 static void init_vmcb(struct vcpu_svm *svm)
485 {
486 struct vmcb_control_area *control = &svm->vmcb->control;
487 struct vmcb_save_area *save = &svm->vmcb->save;
488
489 control->intercept_cr_read = INTERCEPT_CR0_MASK |
490 INTERCEPT_CR3_MASK |
491 INTERCEPT_CR4_MASK;
492
493 control->intercept_cr_write = INTERCEPT_CR0_MASK |
494 INTERCEPT_CR3_MASK |
495 INTERCEPT_CR4_MASK |
496 INTERCEPT_CR8_MASK;
497
498 control->intercept_dr_read = INTERCEPT_DR0_MASK |
499 INTERCEPT_DR1_MASK |
500 INTERCEPT_DR2_MASK |
501 INTERCEPT_DR3_MASK;
502
503 control->intercept_dr_write = INTERCEPT_DR0_MASK |
504 INTERCEPT_DR1_MASK |
505 INTERCEPT_DR2_MASK |
506 INTERCEPT_DR3_MASK |
507 INTERCEPT_DR5_MASK |
508 INTERCEPT_DR7_MASK;
509
510 control->intercept_exceptions = (1 << PF_VECTOR) |
511 (1 << UD_VECTOR) |
512 (1 << MC_VECTOR);
513
514
515 control->intercept = (1ULL << INTERCEPT_INTR) |
516 (1ULL << INTERCEPT_NMI) |
517 (1ULL << INTERCEPT_SMI) |
518 (1ULL << INTERCEPT_CPUID) |
519 (1ULL << INTERCEPT_INVD) |
520 (1ULL << INTERCEPT_HLT) |
521 (1ULL << INTERCEPT_INVLPGA) |
522 (1ULL << INTERCEPT_IOIO_PROT) |
523 (1ULL << INTERCEPT_MSR_PROT) |
524 (1ULL << INTERCEPT_TASK_SWITCH) |
525 (1ULL << INTERCEPT_SHUTDOWN) |
526 (1ULL << INTERCEPT_VMRUN) |
527 (1ULL << INTERCEPT_VMMCALL) |
528 (1ULL << INTERCEPT_VMLOAD) |
529 (1ULL << INTERCEPT_VMSAVE) |
530 (1ULL << INTERCEPT_STGI) |
531 (1ULL << INTERCEPT_CLGI) |
532 (1ULL << INTERCEPT_SKINIT) |
533 (1ULL << INTERCEPT_WBINVD) |
534 (1ULL << INTERCEPT_MONITOR) |
535 (1ULL << INTERCEPT_MWAIT);
536
537 control->iopm_base_pa = iopm_base;
538 control->msrpm_base_pa = __pa(svm->msrpm);
539 control->tsc_offset = 0;
540 control->int_ctl = V_INTR_MASKING_MASK;
541
542 init_seg(&save->es);
543 init_seg(&save->ss);
544 init_seg(&save->ds);
545 init_seg(&save->fs);
546 init_seg(&save->gs);
547
548 save->cs.selector = 0xf000;
549 /* Executable/Readable Code Segment */
550 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
551 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
552 save->cs.limit = 0xffff;
553 /*
554 * cs.base should really be 0xffff0000, but vmx can't handle that, so
555 * be consistent with it.
556 *
557 * Replace when we have real mode working for vmx.
558 */
559 save->cs.base = 0xf0000;
560
561 save->gdtr.limit = 0xffff;
562 save->idtr.limit = 0xffff;
563
564 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
565 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
566
567 save->efer = MSR_EFER_SVME_MASK;
568 save->dr6 = 0xffff0ff0;
569 save->dr7 = 0x400;
570 save->rflags = 2;
571 save->rip = 0x0000fff0;
572
573 /*
574 * cr0 val on cpu init should be 0x60000010, we enable cpu
575 * cache by default. the orderly way is to enable cache in bios.
576 */
577 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
578 save->cr4 = X86_CR4_PAE;
579 /* rdx = ?? */
580
581 if (npt_enabled) {
582 /* Setup VMCB for Nested Paging */
583 control->nested_ctl = 1;
584 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
585 control->intercept_exceptions &= ~(1 << PF_VECTOR);
586 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
587 INTERCEPT_CR3_MASK);
588 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
589 INTERCEPT_CR3_MASK);
590 save->g_pat = 0x0007040600070406ULL;
591 /* enable caching because the QEMU Bios doesn't enable it */
592 save->cr0 = X86_CR0_ET;
593 save->cr3 = 0;
594 save->cr4 = 0;
595 }
596 force_new_asid(&svm->vcpu);
597 }
598
599 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
600 {
601 struct vcpu_svm *svm = to_svm(vcpu);
602
603 init_vmcb(svm);
604
605 if (vcpu->vcpu_id != 0) {
606 svm->vmcb->save.rip = 0;
607 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
608 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
609 }
610
611 return 0;
612 }
613
614 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
615 {
616 struct vcpu_svm *svm;
617 struct page *page;
618 struct page *msrpm_pages;
619 int err;
620
621 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
622 if (!svm) {
623 err = -ENOMEM;
624 goto out;
625 }
626
627 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
628 if (err)
629 goto free_svm;
630
631 page = alloc_page(GFP_KERNEL);
632 if (!page) {
633 err = -ENOMEM;
634 goto uninit;
635 }
636
637 err = -ENOMEM;
638 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
639 if (!msrpm_pages)
640 goto uninit;
641 svm->msrpm = page_address(msrpm_pages);
642 svm_vcpu_init_msrpm(svm->msrpm);
643
644 svm->vmcb = page_address(page);
645 clear_page(svm->vmcb);
646 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
647 svm->asid_generation = 0;
648 memset(svm->db_regs, 0, sizeof(svm->db_regs));
649 init_vmcb(svm);
650
651 fx_init(&svm->vcpu);
652 svm->vcpu.fpu_active = 1;
653 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
654 if (svm->vcpu.vcpu_id == 0)
655 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
656
657 return &svm->vcpu;
658
659 uninit:
660 kvm_vcpu_uninit(&svm->vcpu);
661 free_svm:
662 kmem_cache_free(kvm_vcpu_cache, svm);
663 out:
664 return ERR_PTR(err);
665 }
666
667 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
668 {
669 struct vcpu_svm *svm = to_svm(vcpu);
670
671 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
672 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
673 kvm_vcpu_uninit(vcpu);
674 kmem_cache_free(kvm_vcpu_cache, svm);
675 }
676
677 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
678 {
679 struct vcpu_svm *svm = to_svm(vcpu);
680 int i;
681
682 if (unlikely(cpu != vcpu->cpu)) {
683 u64 tsc_this, delta;
684
685 /*
686 * Make sure that the guest sees a monotonically
687 * increasing TSC.
688 */
689 rdtscll(tsc_this);
690 delta = vcpu->arch.host_tsc - tsc_this;
691 svm->vmcb->control.tsc_offset += delta;
692 vcpu->cpu = cpu;
693 kvm_migrate_timers(vcpu);
694 }
695
696 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
697 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
698 }
699
700 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
701 {
702 struct vcpu_svm *svm = to_svm(vcpu);
703 int i;
704
705 ++vcpu->stat.host_state_reload;
706 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
707 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
708
709 rdtscll(vcpu->arch.host_tsc);
710 }
711
712 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
713 {
714 }
715
716 static void svm_cache_regs(struct kvm_vcpu *vcpu)
717 {
718 struct vcpu_svm *svm = to_svm(vcpu);
719
720 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
721 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
722 vcpu->arch.rip = svm->vmcb->save.rip;
723 }
724
725 static void svm_decache_regs(struct kvm_vcpu *vcpu)
726 {
727 struct vcpu_svm *svm = to_svm(vcpu);
728 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
729 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
730 svm->vmcb->save.rip = vcpu->arch.rip;
731 }
732
733 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
734 {
735 return to_svm(vcpu)->vmcb->save.rflags;
736 }
737
738 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
739 {
740 to_svm(vcpu)->vmcb->save.rflags = rflags;
741 }
742
743 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
744 {
745 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
746
747 switch (seg) {
748 case VCPU_SREG_CS: return &save->cs;
749 case VCPU_SREG_DS: return &save->ds;
750 case VCPU_SREG_ES: return &save->es;
751 case VCPU_SREG_FS: return &save->fs;
752 case VCPU_SREG_GS: return &save->gs;
753 case VCPU_SREG_SS: return &save->ss;
754 case VCPU_SREG_TR: return &save->tr;
755 case VCPU_SREG_LDTR: return &save->ldtr;
756 }
757 BUG();
758 return NULL;
759 }
760
761 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
762 {
763 struct vmcb_seg *s = svm_seg(vcpu, seg);
764
765 return s->base;
766 }
767
768 static void svm_get_segment(struct kvm_vcpu *vcpu,
769 struct kvm_segment *var, int seg)
770 {
771 struct vmcb_seg *s = svm_seg(vcpu, seg);
772
773 var->base = s->base;
774 var->limit = s->limit;
775 var->selector = s->selector;
776 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
777 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
778 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
779 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
780 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
781 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
782 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
783 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
784 var->unusable = !var->present;
785 }
786
787 static int svm_get_cpl(struct kvm_vcpu *vcpu)
788 {
789 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
790
791 return save->cpl;
792 }
793
794 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
795 {
796 struct vcpu_svm *svm = to_svm(vcpu);
797
798 dt->limit = svm->vmcb->save.idtr.limit;
799 dt->base = svm->vmcb->save.idtr.base;
800 }
801
802 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
803 {
804 struct vcpu_svm *svm = to_svm(vcpu);
805
806 svm->vmcb->save.idtr.limit = dt->limit;
807 svm->vmcb->save.idtr.base = dt->base ;
808 }
809
810 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
811 {
812 struct vcpu_svm *svm = to_svm(vcpu);
813
814 dt->limit = svm->vmcb->save.gdtr.limit;
815 dt->base = svm->vmcb->save.gdtr.base;
816 }
817
818 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
819 {
820 struct vcpu_svm *svm = to_svm(vcpu);
821
822 svm->vmcb->save.gdtr.limit = dt->limit;
823 svm->vmcb->save.gdtr.base = dt->base ;
824 }
825
826 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
827 {
828 }
829
830 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
831 {
832 struct vcpu_svm *svm = to_svm(vcpu);
833
834 #ifdef CONFIG_X86_64
835 if (vcpu->arch.shadow_efer & EFER_LME) {
836 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
837 vcpu->arch.shadow_efer |= EFER_LMA;
838 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
839 }
840
841 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
842 vcpu->arch.shadow_efer &= ~EFER_LMA;
843 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
844 }
845 }
846 #endif
847 if (npt_enabled)
848 goto set;
849
850 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
851 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
852 vcpu->fpu_active = 1;
853 }
854
855 vcpu->arch.cr0 = cr0;
856 cr0 |= X86_CR0_PG | X86_CR0_WP;
857 if (!vcpu->fpu_active) {
858 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
859 cr0 |= X86_CR0_TS;
860 }
861 set:
862 /*
863 * re-enable caching here because the QEMU bios
864 * does not do it - this results in some delay at
865 * reboot
866 */
867 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
868 svm->vmcb->save.cr0 = cr0;
869 }
870
871 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
872 {
873 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
874
875 vcpu->arch.cr4 = cr4;
876 if (!npt_enabled)
877 cr4 |= X86_CR4_PAE;
878 cr4 |= host_cr4_mce;
879 to_svm(vcpu)->vmcb->save.cr4 = cr4;
880 }
881
882 static void svm_set_segment(struct kvm_vcpu *vcpu,
883 struct kvm_segment *var, int seg)
884 {
885 struct vcpu_svm *svm = to_svm(vcpu);
886 struct vmcb_seg *s = svm_seg(vcpu, seg);
887
888 s->base = var->base;
889 s->limit = var->limit;
890 s->selector = var->selector;
891 if (var->unusable)
892 s->attrib = 0;
893 else {
894 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
895 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
896 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
897 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
898 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
899 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
900 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
901 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
902 }
903 if (seg == VCPU_SREG_CS)
904 svm->vmcb->save.cpl
905 = (svm->vmcb->save.cs.attrib
906 >> SVM_SELECTOR_DPL_SHIFT) & 3;
907
908 }
909
910 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
911 {
912 return -EOPNOTSUPP;
913 }
914
915 static int svm_get_irq(struct kvm_vcpu *vcpu)
916 {
917 struct vcpu_svm *svm = to_svm(vcpu);
918 u32 exit_int_info = svm->vmcb->control.exit_int_info;
919
920 if (is_external_interrupt(exit_int_info))
921 return exit_int_info & SVM_EVTINJ_VEC_MASK;
922 return -1;
923 }
924
925 static void load_host_msrs(struct kvm_vcpu *vcpu)
926 {
927 #ifdef CONFIG_X86_64
928 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
929 #endif
930 }
931
932 static void save_host_msrs(struct kvm_vcpu *vcpu)
933 {
934 #ifdef CONFIG_X86_64
935 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
936 #endif
937 }
938
939 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
940 {
941 if (svm_data->next_asid > svm_data->max_asid) {
942 ++svm_data->asid_generation;
943 svm_data->next_asid = 1;
944 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
945 }
946
947 svm->vcpu.cpu = svm_data->cpu;
948 svm->asid_generation = svm_data->asid_generation;
949 svm->vmcb->control.asid = svm_data->next_asid++;
950 }
951
952 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
953 {
954 unsigned long val = to_svm(vcpu)->db_regs[dr];
955 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
956 return val;
957 }
958
959 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
960 int *exception)
961 {
962 struct vcpu_svm *svm = to_svm(vcpu);
963
964 *exception = 0;
965
966 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
967 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
968 svm->vmcb->save.dr6 |= DR6_BD_MASK;
969 *exception = DB_VECTOR;
970 return;
971 }
972
973 switch (dr) {
974 case 0 ... 3:
975 svm->db_regs[dr] = value;
976 return;
977 case 4 ... 5:
978 if (vcpu->arch.cr4 & X86_CR4_DE) {
979 *exception = UD_VECTOR;
980 return;
981 }
982 case 7: {
983 if (value & ~((1ULL << 32) - 1)) {
984 *exception = GP_VECTOR;
985 return;
986 }
987 svm->vmcb->save.dr7 = value;
988 return;
989 }
990 default:
991 printk(KERN_DEBUG "%s: unexpected dr %u\n",
992 __func__, dr);
993 *exception = UD_VECTOR;
994 return;
995 }
996 }
997
998 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
999 {
1000 u32 exit_int_info = svm->vmcb->control.exit_int_info;
1001 struct kvm *kvm = svm->vcpu.kvm;
1002 u64 fault_address;
1003 u32 error_code;
1004
1005 if (!irqchip_in_kernel(kvm) &&
1006 is_external_interrupt(exit_int_info))
1007 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1008
1009 fault_address = svm->vmcb->control.exit_info_2;
1010 error_code = svm->vmcb->control.exit_info_1;
1011
1012 if (!npt_enabled)
1013 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1014 (u32)fault_address, (u32)(fault_address >> 32),
1015 handler);
1016 else
1017 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1018 (u32)fault_address, (u32)(fault_address >> 32),
1019 handler);
1020
1021 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1022 }
1023
1024 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1025 {
1026 int er;
1027
1028 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1029 if (er != EMULATE_DONE)
1030 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1031 return 1;
1032 }
1033
1034 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1035 {
1036 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1037 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1038 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1039 svm->vcpu.fpu_active = 1;
1040
1041 return 1;
1042 }
1043
1044 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1045 {
1046 /*
1047 * On an #MC intercept the MCE handler is not called automatically in
1048 * the host. So do it by hand here.
1049 */
1050 asm volatile (
1051 "int $0x12\n");
1052 /* not sure if we ever come back to this point */
1053
1054 return 1;
1055 }
1056
1057 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058 {
1059 /*
1060 * VMCB is undefined after a SHUTDOWN intercept
1061 * so reinitialize it.
1062 */
1063 clear_page(svm->vmcb);
1064 init_vmcb(svm);
1065
1066 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1067 return 0;
1068 }
1069
1070 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1071 {
1072 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1073 int size, down, in, string, rep;
1074 unsigned port;
1075
1076 ++svm->vcpu.stat.io_exits;
1077
1078 svm->next_rip = svm->vmcb->control.exit_info_2;
1079
1080 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1081
1082 if (string) {
1083 if (emulate_instruction(&svm->vcpu,
1084 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1085 return 0;
1086 return 1;
1087 }
1088
1089 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1090 port = io_info >> 16;
1091 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1092 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1093 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1094
1095 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1096 }
1097
1098 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1099 {
1100 KVMTRACE_0D(NMI, &svm->vcpu, handler);
1101 return 1;
1102 }
1103
1104 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1105 {
1106 ++svm->vcpu.stat.irq_exits;
1107 KVMTRACE_0D(INTR, &svm->vcpu, handler);
1108 return 1;
1109 }
1110
1111 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1112 {
1113 return 1;
1114 }
1115
1116 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1117 {
1118 svm->next_rip = svm->vmcb->save.rip + 1;
1119 skip_emulated_instruction(&svm->vcpu);
1120 return kvm_emulate_halt(&svm->vcpu);
1121 }
1122
1123 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1124 {
1125 svm->next_rip = svm->vmcb->save.rip + 3;
1126 skip_emulated_instruction(&svm->vcpu);
1127 kvm_emulate_hypercall(&svm->vcpu);
1128 return 1;
1129 }
1130
1131 static int invalid_op_interception(struct vcpu_svm *svm,
1132 struct kvm_run *kvm_run)
1133 {
1134 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1135 return 1;
1136 }
1137
1138 static int task_switch_interception(struct vcpu_svm *svm,
1139 struct kvm_run *kvm_run)
1140 {
1141 u16 tss_selector;
1142
1143 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1144 if (svm->vmcb->control.exit_info_2 &
1145 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1146 return kvm_task_switch(&svm->vcpu, tss_selector,
1147 TASK_SWITCH_IRET);
1148 if (svm->vmcb->control.exit_info_2 &
1149 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1150 return kvm_task_switch(&svm->vcpu, tss_selector,
1151 TASK_SWITCH_JMP);
1152 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1153 }
1154
1155 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1156 {
1157 svm->next_rip = svm->vmcb->save.rip + 2;
1158 kvm_emulate_cpuid(&svm->vcpu);
1159 return 1;
1160 }
1161
1162 static int emulate_on_interception(struct vcpu_svm *svm,
1163 struct kvm_run *kvm_run)
1164 {
1165 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1166 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1167 return 1;
1168 }
1169
1170 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1171 {
1172 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1173 if (irqchip_in_kernel(svm->vcpu.kvm))
1174 return 1;
1175 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1176 return 0;
1177 }
1178
1179 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1180 {
1181 struct vcpu_svm *svm = to_svm(vcpu);
1182
1183 switch (ecx) {
1184 case MSR_IA32_TIME_STAMP_COUNTER: {
1185 u64 tsc;
1186
1187 rdtscll(tsc);
1188 *data = svm->vmcb->control.tsc_offset + tsc;
1189 break;
1190 }
1191 case MSR_K6_STAR:
1192 *data = svm->vmcb->save.star;
1193 break;
1194 #ifdef CONFIG_X86_64
1195 case MSR_LSTAR:
1196 *data = svm->vmcb->save.lstar;
1197 break;
1198 case MSR_CSTAR:
1199 *data = svm->vmcb->save.cstar;
1200 break;
1201 case MSR_KERNEL_GS_BASE:
1202 *data = svm->vmcb->save.kernel_gs_base;
1203 break;
1204 case MSR_SYSCALL_MASK:
1205 *data = svm->vmcb->save.sfmask;
1206 break;
1207 #endif
1208 case MSR_IA32_SYSENTER_CS:
1209 *data = svm->vmcb->save.sysenter_cs;
1210 break;
1211 case MSR_IA32_SYSENTER_EIP:
1212 *data = svm->vmcb->save.sysenter_eip;
1213 break;
1214 case MSR_IA32_SYSENTER_ESP:
1215 *data = svm->vmcb->save.sysenter_esp;
1216 break;
1217 /* Nobody will change the following 5 values in the VMCB so
1218 we can safely return them on rdmsr. They will always be 0
1219 until LBRV is implemented. */
1220 case MSR_IA32_DEBUGCTLMSR:
1221 *data = svm->vmcb->save.dbgctl;
1222 break;
1223 case MSR_IA32_LASTBRANCHFROMIP:
1224 *data = svm->vmcb->save.br_from;
1225 break;
1226 case MSR_IA32_LASTBRANCHTOIP:
1227 *data = svm->vmcb->save.br_to;
1228 break;
1229 case MSR_IA32_LASTINTFROMIP:
1230 *data = svm->vmcb->save.last_excp_from;
1231 break;
1232 case MSR_IA32_LASTINTTOIP:
1233 *data = svm->vmcb->save.last_excp_to;
1234 break;
1235 default:
1236 return kvm_get_msr_common(vcpu, ecx, data);
1237 }
1238 return 0;
1239 }
1240
1241 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1242 {
1243 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1244 u64 data;
1245
1246 if (svm_get_msr(&svm->vcpu, ecx, &data))
1247 kvm_inject_gp(&svm->vcpu, 0);
1248 else {
1249 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1250 (u32)(data >> 32), handler);
1251
1252 svm->vmcb->save.rax = data & 0xffffffff;
1253 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1254 svm->next_rip = svm->vmcb->save.rip + 2;
1255 skip_emulated_instruction(&svm->vcpu);
1256 }
1257 return 1;
1258 }
1259
1260 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1261 {
1262 struct vcpu_svm *svm = to_svm(vcpu);
1263
1264 switch (ecx) {
1265 case MSR_IA32_TIME_STAMP_COUNTER: {
1266 u64 tsc;
1267
1268 rdtscll(tsc);
1269 svm->vmcb->control.tsc_offset = data - tsc;
1270 break;
1271 }
1272 case MSR_K6_STAR:
1273 svm->vmcb->save.star = data;
1274 break;
1275 #ifdef CONFIG_X86_64
1276 case MSR_LSTAR:
1277 svm->vmcb->save.lstar = data;
1278 break;
1279 case MSR_CSTAR:
1280 svm->vmcb->save.cstar = data;
1281 break;
1282 case MSR_KERNEL_GS_BASE:
1283 svm->vmcb->save.kernel_gs_base = data;
1284 break;
1285 case MSR_SYSCALL_MASK:
1286 svm->vmcb->save.sfmask = data;
1287 break;
1288 #endif
1289 case MSR_IA32_SYSENTER_CS:
1290 svm->vmcb->save.sysenter_cs = data;
1291 break;
1292 case MSR_IA32_SYSENTER_EIP:
1293 svm->vmcb->save.sysenter_eip = data;
1294 break;
1295 case MSR_IA32_SYSENTER_ESP:
1296 svm->vmcb->save.sysenter_esp = data;
1297 break;
1298 case MSR_IA32_DEBUGCTLMSR:
1299 if (!svm_has(SVM_FEATURE_LBRV)) {
1300 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1301 __func__, data);
1302 break;
1303 }
1304 if (data & DEBUGCTL_RESERVED_BITS)
1305 return 1;
1306
1307 svm->vmcb->save.dbgctl = data;
1308 if (data & (1ULL<<0))
1309 svm_enable_lbrv(svm);
1310 else
1311 svm_disable_lbrv(svm);
1312 break;
1313 case MSR_K7_EVNTSEL0:
1314 case MSR_K7_EVNTSEL1:
1315 case MSR_K7_EVNTSEL2:
1316 case MSR_K7_EVNTSEL3:
1317 case MSR_K7_PERFCTR0:
1318 case MSR_K7_PERFCTR1:
1319 case MSR_K7_PERFCTR2:
1320 case MSR_K7_PERFCTR3:
1321 /*
1322 * Just discard all writes to the performance counters; this
1323 * should keep both older linux and windows 64-bit guests
1324 * happy
1325 */
1326 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1327
1328 break;
1329 default:
1330 return kvm_set_msr_common(vcpu, ecx, data);
1331 }
1332 return 0;
1333 }
1334
1335 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1336 {
1337 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1338 u64 data = (svm->vmcb->save.rax & -1u)
1339 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1340
1341 KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1342 handler);
1343
1344 svm->next_rip = svm->vmcb->save.rip + 2;
1345 if (svm_set_msr(&svm->vcpu, ecx, data))
1346 kvm_inject_gp(&svm->vcpu, 0);
1347 else
1348 skip_emulated_instruction(&svm->vcpu);
1349 return 1;
1350 }
1351
1352 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1353 {
1354 if (svm->vmcb->control.exit_info_1)
1355 return wrmsr_interception(svm, kvm_run);
1356 else
1357 return rdmsr_interception(svm, kvm_run);
1358 }
1359
1360 static int interrupt_window_interception(struct vcpu_svm *svm,
1361 struct kvm_run *kvm_run)
1362 {
1363 KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1364
1365 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1366 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1367 /*
1368 * If the user space waits to inject interrupts, exit as soon as
1369 * possible
1370 */
1371 if (kvm_run->request_interrupt_window &&
1372 !svm->vcpu.arch.irq_summary) {
1373 ++svm->vcpu.stat.irq_window_exits;
1374 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1375 return 0;
1376 }
1377
1378 return 1;
1379 }
1380
1381 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1382 struct kvm_run *kvm_run) = {
1383 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1384 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1385 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1386 [SVM_EXIT_READ_CR8] = emulate_on_interception,
1387 /* for now: */
1388 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1389 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1390 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1391 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
1392 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1393 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1394 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1395 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1396 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1397 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1398 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1399 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1400 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1401 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1402 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
1403 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1404 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1405 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
1406 [SVM_EXIT_INTR] = intr_interception,
1407 [SVM_EXIT_NMI] = nmi_interception,
1408 [SVM_EXIT_SMI] = nop_on_interception,
1409 [SVM_EXIT_INIT] = nop_on_interception,
1410 [SVM_EXIT_VINTR] = interrupt_window_interception,
1411 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1412 [SVM_EXIT_CPUID] = cpuid_interception,
1413 [SVM_EXIT_INVD] = emulate_on_interception,
1414 [SVM_EXIT_HLT] = halt_interception,
1415 [SVM_EXIT_INVLPG] = emulate_on_interception,
1416 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1417 [SVM_EXIT_IOIO] = io_interception,
1418 [SVM_EXIT_MSR] = msr_interception,
1419 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1420 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1421 [SVM_EXIT_VMRUN] = invalid_op_interception,
1422 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1423 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1424 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1425 [SVM_EXIT_STGI] = invalid_op_interception,
1426 [SVM_EXIT_CLGI] = invalid_op_interception,
1427 [SVM_EXIT_SKINIT] = invalid_op_interception,
1428 [SVM_EXIT_WBINVD] = emulate_on_interception,
1429 [SVM_EXIT_MONITOR] = invalid_op_interception,
1430 [SVM_EXIT_MWAIT] = invalid_op_interception,
1431 [SVM_EXIT_NPF] = pf_interception,
1432 };
1433
1434 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1435 {
1436 struct vcpu_svm *svm = to_svm(vcpu);
1437 u32 exit_code = svm->vmcb->control.exit_code;
1438
1439 KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1440 (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1441
1442 if (npt_enabled) {
1443 int mmu_reload = 0;
1444 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1445 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1446 mmu_reload = 1;
1447 }
1448 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1449 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1450 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1451 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1452 kvm_inject_gp(vcpu, 0);
1453 return 1;
1454 }
1455 }
1456 if (mmu_reload) {
1457 kvm_mmu_reset_context(vcpu);
1458 kvm_mmu_load(vcpu);
1459 }
1460 }
1461
1462 kvm_reput_irq(svm);
1463
1464 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1465 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1466 kvm_run->fail_entry.hardware_entry_failure_reason
1467 = svm->vmcb->control.exit_code;
1468 return 0;
1469 }
1470
1471 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1472 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1473 exit_code != SVM_EXIT_NPF)
1474 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1475 "exit_code 0x%x\n",
1476 __func__, svm->vmcb->control.exit_int_info,
1477 exit_code);
1478
1479 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1480 || !svm_exit_handlers[exit_code]) {
1481 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1482 kvm_run->hw.hardware_exit_reason = exit_code;
1483 return 0;
1484 }
1485
1486 return svm_exit_handlers[exit_code](svm, kvm_run);
1487 }
1488
1489 static void reload_tss(struct kvm_vcpu *vcpu)
1490 {
1491 int cpu = raw_smp_processor_id();
1492
1493 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1494 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1495 load_TR_desc();
1496 }
1497
1498 static void pre_svm_run(struct vcpu_svm *svm)
1499 {
1500 int cpu = raw_smp_processor_id();
1501
1502 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1503
1504 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1505 if (svm->vcpu.cpu != cpu ||
1506 svm->asid_generation != svm_data->asid_generation)
1507 new_asid(svm, svm_data);
1508 }
1509
1510
1511 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1512 {
1513 struct vmcb_control_area *control;
1514
1515 KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1516
1517 control = &svm->vmcb->control;
1518 control->int_vector = irq;
1519 control->int_ctl &= ~V_INTR_PRIO_MASK;
1520 control->int_ctl |= V_IRQ_MASK |
1521 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1522 }
1523
1524 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1525 {
1526 struct vcpu_svm *svm = to_svm(vcpu);
1527
1528 svm_inject_irq(svm, irq);
1529 }
1530
1531 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1532 {
1533 struct vcpu_svm *svm = to_svm(vcpu);
1534 struct vmcb *vmcb = svm->vmcb;
1535 int max_irr, tpr;
1536
1537 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1538 return;
1539
1540 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1541
1542 max_irr = kvm_lapic_find_highest_irr(vcpu);
1543 if (max_irr == -1)
1544 return;
1545
1546 tpr = kvm_lapic_get_cr8(vcpu) << 4;
1547
1548 if (tpr >= (max_irr & 0xf0))
1549 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1550 }
1551
1552 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1553 {
1554 struct vcpu_svm *svm = to_svm(vcpu);
1555 struct vmcb *vmcb = svm->vmcb;
1556 int intr_vector = -1;
1557
1558 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1559 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1560 intr_vector = vmcb->control.exit_int_info &
1561 SVM_EVTINJ_VEC_MASK;
1562 vmcb->control.exit_int_info = 0;
1563 svm_inject_irq(svm, intr_vector);
1564 goto out;
1565 }
1566
1567 if (vmcb->control.int_ctl & V_IRQ_MASK)
1568 goto out;
1569
1570 if (!kvm_cpu_has_interrupt(vcpu))
1571 goto out;
1572
1573 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1574 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1575 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1576 /* unable to deliver irq, set pending irq */
1577 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1578 svm_inject_irq(svm, 0x0);
1579 goto out;
1580 }
1581 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1582 intr_vector = kvm_cpu_get_interrupt(vcpu);
1583 svm_inject_irq(svm, intr_vector);
1584 kvm_timer_intr_post(vcpu, intr_vector);
1585 out:
1586 update_cr8_intercept(vcpu);
1587 }
1588
1589 static void kvm_reput_irq(struct vcpu_svm *svm)
1590 {
1591 struct vmcb_control_area *control = &svm->vmcb->control;
1592
1593 if ((control->int_ctl & V_IRQ_MASK)
1594 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1595 control->int_ctl &= ~V_IRQ_MASK;
1596 push_irq(&svm->vcpu, control->int_vector);
1597 }
1598
1599 svm->vcpu.arch.interrupt_window_open =
1600 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1601 }
1602
1603 static void svm_do_inject_vector(struct vcpu_svm *svm)
1604 {
1605 struct kvm_vcpu *vcpu = &svm->vcpu;
1606 int word_index = __ffs(vcpu->arch.irq_summary);
1607 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1608 int irq = word_index * BITS_PER_LONG + bit_index;
1609
1610 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1611 if (!vcpu->arch.irq_pending[word_index])
1612 clear_bit(word_index, &vcpu->arch.irq_summary);
1613 svm_inject_irq(svm, irq);
1614 }
1615
1616 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1617 struct kvm_run *kvm_run)
1618 {
1619 struct vcpu_svm *svm = to_svm(vcpu);
1620 struct vmcb_control_area *control = &svm->vmcb->control;
1621
1622 svm->vcpu.arch.interrupt_window_open =
1623 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1624 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1625
1626 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1627 /*
1628 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1629 */
1630 svm_do_inject_vector(svm);
1631
1632 /*
1633 * Interrupts blocked. Wait for unblock.
1634 */
1635 if (!svm->vcpu.arch.interrupt_window_open &&
1636 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1637 control->intercept |= 1ULL << INTERCEPT_VINTR;
1638 else
1639 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1640 }
1641
1642 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1643 {
1644 return 0;
1645 }
1646
1647 static void save_db_regs(unsigned long *db_regs)
1648 {
1649 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1650 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1651 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1652 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1653 }
1654
1655 static void load_db_regs(unsigned long *db_regs)
1656 {
1657 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1658 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1659 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1660 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1661 }
1662
1663 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1664 {
1665 force_new_asid(vcpu);
1666 }
1667
1668 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1669 {
1670 }
1671
1672 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1673 {
1674 struct vcpu_svm *svm = to_svm(vcpu);
1675
1676 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1677 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1678 kvm_lapic_set_tpr(vcpu, cr8);
1679 }
1680 }
1681
1682 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1683 {
1684 struct vcpu_svm *svm = to_svm(vcpu);
1685 u64 cr8;
1686
1687 if (!irqchip_in_kernel(vcpu->kvm))
1688 return;
1689
1690 cr8 = kvm_get_cr8(vcpu);
1691 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1692 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1693 }
1694
1695 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1696 {
1697 struct vcpu_svm *svm = to_svm(vcpu);
1698 u16 fs_selector;
1699 u16 gs_selector;
1700 u16 ldt_selector;
1701
1702 pre_svm_run(svm);
1703
1704 sync_lapic_to_cr8(vcpu);
1705
1706 save_host_msrs(vcpu);
1707 fs_selector = read_fs();
1708 gs_selector = read_gs();
1709 ldt_selector = read_ldt();
1710 svm->host_cr2 = kvm_read_cr2();
1711 svm->host_dr6 = read_dr6();
1712 svm->host_dr7 = read_dr7();
1713 svm->vmcb->save.cr2 = vcpu->arch.cr2;
1714 /* required for live migration with NPT */
1715 if (npt_enabled)
1716 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1717
1718 if (svm->vmcb->save.dr7 & 0xff) {
1719 write_dr7(0);
1720 save_db_regs(svm->host_db_regs);
1721 load_db_regs(svm->db_regs);
1722 }
1723
1724 clgi();
1725
1726 local_irq_enable();
1727
1728 asm volatile (
1729 #ifdef CONFIG_X86_64
1730 "push %%rbp; \n\t"
1731 #else
1732 "push %%ebp; \n\t"
1733 #endif
1734
1735 #ifdef CONFIG_X86_64
1736 "mov %c[rbx](%[svm]), %%rbx \n\t"
1737 "mov %c[rcx](%[svm]), %%rcx \n\t"
1738 "mov %c[rdx](%[svm]), %%rdx \n\t"
1739 "mov %c[rsi](%[svm]), %%rsi \n\t"
1740 "mov %c[rdi](%[svm]), %%rdi \n\t"
1741 "mov %c[rbp](%[svm]), %%rbp \n\t"
1742 "mov %c[r8](%[svm]), %%r8 \n\t"
1743 "mov %c[r9](%[svm]), %%r9 \n\t"
1744 "mov %c[r10](%[svm]), %%r10 \n\t"
1745 "mov %c[r11](%[svm]), %%r11 \n\t"
1746 "mov %c[r12](%[svm]), %%r12 \n\t"
1747 "mov %c[r13](%[svm]), %%r13 \n\t"
1748 "mov %c[r14](%[svm]), %%r14 \n\t"
1749 "mov %c[r15](%[svm]), %%r15 \n\t"
1750 #else
1751 "mov %c[rbx](%[svm]), %%ebx \n\t"
1752 "mov %c[rcx](%[svm]), %%ecx \n\t"
1753 "mov %c[rdx](%[svm]), %%edx \n\t"
1754 "mov %c[rsi](%[svm]), %%esi \n\t"
1755 "mov %c[rdi](%[svm]), %%edi \n\t"
1756 "mov %c[rbp](%[svm]), %%ebp \n\t"
1757 #endif
1758
1759 #ifdef CONFIG_X86_64
1760 /* Enter guest mode */
1761 "push %%rax \n\t"
1762 "mov %c[vmcb](%[svm]), %%rax \n\t"
1763 __ex(SVM_VMLOAD) "\n\t"
1764 __ex(SVM_VMRUN) "\n\t"
1765 __ex(SVM_VMSAVE) "\n\t"
1766 "pop %%rax \n\t"
1767 #else
1768 /* Enter guest mode */
1769 "push %%eax \n\t"
1770 "mov %c[vmcb](%[svm]), %%eax \n\t"
1771 __ex(SVM_VMLOAD) "\n\t"
1772 __ex(SVM_VMRUN) "\n\t"
1773 __ex(SVM_VMSAVE) "\n\t"
1774 "pop %%eax \n\t"
1775 #endif
1776
1777 /* Save guest registers, load host registers */
1778 #ifdef CONFIG_X86_64
1779 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1780 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1781 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1782 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1783 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1784 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1785 "mov %%r8, %c[r8](%[svm]) \n\t"
1786 "mov %%r9, %c[r9](%[svm]) \n\t"
1787 "mov %%r10, %c[r10](%[svm]) \n\t"
1788 "mov %%r11, %c[r11](%[svm]) \n\t"
1789 "mov %%r12, %c[r12](%[svm]) \n\t"
1790 "mov %%r13, %c[r13](%[svm]) \n\t"
1791 "mov %%r14, %c[r14](%[svm]) \n\t"
1792 "mov %%r15, %c[r15](%[svm]) \n\t"
1793
1794 "pop %%rbp; \n\t"
1795 #else
1796 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1797 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1798 "mov %%edx, %c[rdx](%[svm]) \n\t"
1799 "mov %%esi, %c[rsi](%[svm]) \n\t"
1800 "mov %%edi, %c[rdi](%[svm]) \n\t"
1801 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1802
1803 "pop %%ebp; \n\t"
1804 #endif
1805 :
1806 : [svm]"a"(svm),
1807 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1808 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1809 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1810 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1811 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1812 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1813 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1814 #ifdef CONFIG_X86_64
1815 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1816 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1817 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1818 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1819 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1820 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1821 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1822 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1823 #endif
1824 : "cc", "memory"
1825 #ifdef CONFIG_X86_64
1826 , "rbx", "rcx", "rdx", "rsi", "rdi"
1827 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1828 #else
1829 , "ebx", "ecx", "edx" , "esi", "edi"
1830 #endif
1831 );
1832
1833 if ((svm->vmcb->save.dr7 & 0xff))
1834 load_db_regs(svm->host_db_regs);
1835
1836 vcpu->arch.cr2 = svm->vmcb->save.cr2;
1837
1838 write_dr6(svm->host_dr6);
1839 write_dr7(svm->host_dr7);
1840 kvm_write_cr2(svm->host_cr2);
1841
1842 load_fs(fs_selector);
1843 load_gs(gs_selector);
1844 load_ldt(ldt_selector);
1845 load_host_msrs(vcpu);
1846
1847 reload_tss(vcpu);
1848
1849 local_irq_disable();
1850
1851 stgi();
1852
1853 sync_cr8_to_lapic(vcpu);
1854
1855 svm->next_rip = 0;
1856 }
1857
1858 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1859 {
1860 struct vcpu_svm *svm = to_svm(vcpu);
1861
1862 if (npt_enabled) {
1863 svm->vmcb->control.nested_cr3 = root;
1864 force_new_asid(vcpu);
1865 return;
1866 }
1867
1868 svm->vmcb->save.cr3 = root;
1869 force_new_asid(vcpu);
1870
1871 if (vcpu->fpu_active) {
1872 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1873 svm->vmcb->save.cr0 |= X86_CR0_TS;
1874 vcpu->fpu_active = 0;
1875 }
1876 }
1877
1878 static int is_disabled(void)
1879 {
1880 u64 vm_cr;
1881
1882 rdmsrl(MSR_VM_CR, vm_cr);
1883 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1884 return 1;
1885
1886 return 0;
1887 }
1888
1889 static void
1890 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1891 {
1892 /*
1893 * Patch in the VMMCALL instruction:
1894 */
1895 hypercall[0] = 0x0f;
1896 hypercall[1] = 0x01;
1897 hypercall[2] = 0xd9;
1898 }
1899
1900 static void svm_check_processor_compat(void *rtn)
1901 {
1902 *(int *)rtn = 0;
1903 }
1904
1905 static bool svm_cpu_has_accelerated_tpr(void)
1906 {
1907 return false;
1908 }
1909
1910 static int get_npt_level(void)
1911 {
1912 #ifdef CONFIG_X86_64
1913 return PT64_ROOT_LEVEL;
1914 #else
1915 return PT32E_ROOT_LEVEL;
1916 #endif
1917 }
1918
1919 static struct kvm_x86_ops svm_x86_ops = {
1920 .cpu_has_kvm_support = has_svm,
1921 .disabled_by_bios = is_disabled,
1922 .hardware_setup = svm_hardware_setup,
1923 .hardware_unsetup = svm_hardware_unsetup,
1924 .check_processor_compatibility = svm_check_processor_compat,
1925 .hardware_enable = svm_hardware_enable,
1926 .hardware_disable = svm_hardware_disable,
1927 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1928
1929 .vcpu_create = svm_create_vcpu,
1930 .vcpu_free = svm_free_vcpu,
1931 .vcpu_reset = svm_vcpu_reset,
1932
1933 .prepare_guest_switch = svm_prepare_guest_switch,
1934 .vcpu_load = svm_vcpu_load,
1935 .vcpu_put = svm_vcpu_put,
1936 .vcpu_decache = svm_vcpu_decache,
1937
1938 .set_guest_debug = svm_guest_debug,
1939 .get_msr = svm_get_msr,
1940 .set_msr = svm_set_msr,
1941 .get_segment_base = svm_get_segment_base,
1942 .get_segment = svm_get_segment,
1943 .set_segment = svm_set_segment,
1944 .get_cpl = svm_get_cpl,
1945 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1946 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1947 .set_cr0 = svm_set_cr0,
1948 .set_cr3 = svm_set_cr3,
1949 .set_cr4 = svm_set_cr4,
1950 .set_efer = svm_set_efer,
1951 .get_idt = svm_get_idt,
1952 .set_idt = svm_set_idt,
1953 .get_gdt = svm_get_gdt,
1954 .set_gdt = svm_set_gdt,
1955 .get_dr = svm_get_dr,
1956 .set_dr = svm_set_dr,
1957 .cache_regs = svm_cache_regs,
1958 .decache_regs = svm_decache_regs,
1959 .get_rflags = svm_get_rflags,
1960 .set_rflags = svm_set_rflags,
1961
1962 .tlb_flush = svm_flush_tlb,
1963
1964 .run = svm_vcpu_run,
1965 .handle_exit = handle_exit,
1966 .skip_emulated_instruction = skip_emulated_instruction,
1967 .patch_hypercall = svm_patch_hypercall,
1968 .get_irq = svm_get_irq,
1969 .set_irq = svm_set_irq,
1970 .queue_exception = svm_queue_exception,
1971 .exception_injected = svm_exception_injected,
1972 .inject_pending_irq = svm_intr_assist,
1973 .inject_pending_vectors = do_interrupt_requests,
1974
1975 .set_tss_addr = svm_set_tss_addr,
1976 .get_tdp_level = get_npt_level,
1977 };
1978
1979 static int __init svm_init(void)
1980 {
1981 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1982 THIS_MODULE);
1983 }
1984
1985 static void __exit svm_exit(void)
1986 {
1987 kvm_exit();
1988 }
1989
1990 module_init(svm_init)
1991 module_exit(svm_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree