?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
solos-pci: Fix race condition in tasklet RX handling
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / blackfin / mach-common / ints-priority.c
blob7ad8878bfa1815110a53220a1d96ab2c53df0476
1 /*
2 * Set up the interrupt priorities
3 *
4 * Copyright 2004-2009 Analog Devices Inc.
5 * 2003 Bas Vermeulen <bas@buyways.nl>
6 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
7 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 1996 Roman Zippel
10 *
11 * Licensed under the GPL-2
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/seq_file.h>
17 #include <linux/irq.h>
18 #ifdef CONFIG_IPIPE
19 #include <linux/ipipe.h>
20 #endif
21 #ifdef CONFIG_KGDB
22 #include <linux/kgdb.h>
23 #endif
24 #include <asm/traps.h>
25 #include <asm/blackfin.h>
26 #include <asm/gpio.h>
27 #include <asm/irq_handler.h>
28 #include <asm/dpmc.h>
29 #include <asm/bfin5xx_spi.h>
30 #include <asm/bfin_sport.h>
31 #include <asm/bfin_can.h>
32
33 #define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
34
35 #ifdef BF537_FAMILY
36 # define BF537_GENERIC_ERROR_INT_DEMUX
37 # define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
38 # define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
39 # define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
40 # define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
41 # define UART_ERR_MASK (0x6) /* UART_IIR */
42 # define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
43 #else
44 # undef BF537_GENERIC_ERROR_INT_DEMUX
45 #endif
46
47 /*
48 * NOTES:
49 * - we have separated the physical Hardware interrupt from the
50 * levels that the LINUX kernel sees (see the description in irq.h)
51 * -
52 */
53
54 #ifndef CONFIG_SMP
55 /* Initialize this to an actual value to force it into the .data
56 * section so that we know it is properly initialized at entry into
57 * the kernel but before bss is initialized to zero (which is where
58 * it would live otherwise). The 0x1f magic represents the IRQs we
59 * cannot actually mask out in hardware.
60 */
61 unsigned long bfin_irq_flags = 0x1f;
62 EXPORT_SYMBOL(bfin_irq_flags);
63 #endif
64
65 /* The number of spurious interrupts */
66 atomic_t num_spurious;
67
68 #ifdef CONFIG_PM
69 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
70 unsigned vr_wakeup;
71 #endif
72
73 struct ivgx {
74 /* irq number for request_irq, available in mach-bf5xx/irq.h */
75 unsigned int irqno;
76 /* corresponding bit in the SIC_ISR register */
77 unsigned int isrflag;
78 } ivg_table[NR_PERI_INTS];
79
80 struct ivg_slice {
81 /* position of first irq in ivg_table for given ivg */
82 struct ivgx *ifirst;
83 struct ivgx *istop;
84 } ivg7_13[IVG13 - IVG7 + 1];
85
86
87 /*
88 * Search SIC_IAR and fill tables with the irqvalues
89 * and their positions in the SIC_ISR register.
90 */
91 static void __init search_IAR(void)
92 {
93 unsigned ivg, irq_pos = 0;
94 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
95 int irqn;
96
97 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
98
99 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
100 int iar_shift = (irqn & 7) * 4;
101 if (ivg == (0xf &
102 #if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
103 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
104 bfin_read32((unsigned long *)SIC_IAR0 +
105 ((irqn % 32) >> 3) + ((irqn / 32) *
106 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
107 #else
108 bfin_read32((unsigned long *)SIC_IAR0 +
109 (irqn >> 3)) >> iar_shift)) {
110 #endif
111 ivg_table[irq_pos].irqno = IVG7 + irqn;
112 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
113 ivg7_13[ivg].istop++;
114 irq_pos++;
115 }
116 }
117 }
118 }
119
120 /*
121 * This is for core internal IRQs
122 */
123
124 static void bfin_ack_noop(unsigned int irq)
125 {
126 /* Dummy function. */
127 }
128
129 static void bfin_core_mask_irq(unsigned int irq)
130 {
131 bfin_irq_flags &= ~(1 << irq);
132 if (!irqs_disabled_hw())
133 local_irq_enable_hw();
134 }
135
136 static void bfin_core_unmask_irq(unsigned int irq)
137 {
138 bfin_irq_flags |= 1 << irq;
139 /*
140 * If interrupts are enabled, IMASK must contain the same value
141 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
142 * are currently disabled we need not do anything; one of the
143 * callers will take care of setting IMASK to the proper value
144 * when reenabling interrupts.
145 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
146 * what we need.
147 */
148 if (!irqs_disabled_hw())
149 local_irq_enable_hw();
150 return;
151 }
152
153 static void bfin_internal_mask_irq(unsigned int irq)
154 {
155 unsigned long flags;
156
157 #ifdef CONFIG_BF53x
158 local_irq_save_hw(flags);
159 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
160 ~(1 << SIC_SYSIRQ(irq)));
161 #else
162 unsigned mask_bank, mask_bit;
163 local_irq_save_hw(flags);
164 mask_bank = SIC_SYSIRQ(irq) / 32;
165 mask_bit = SIC_SYSIRQ(irq) % 32;
166 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
167 ~(1 << mask_bit));
168 #ifdef CONFIG_SMP
169 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
170 ~(1 << mask_bit));
171 #endif
172 #endif
173 local_irq_restore_hw(flags);
174 }
175
176 #ifdef CONFIG_SMP
177 static void bfin_internal_unmask_irq_affinity(unsigned int irq,
178 const struct cpumask *affinity)
179 #else
180 static void bfin_internal_unmask_irq(unsigned int irq)
181 #endif
182 {
183 unsigned long flags;
184
185 #ifdef CONFIG_BF53x
186 local_irq_save_hw(flags);
187 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
188 (1 << SIC_SYSIRQ(irq)));
189 #else
190 unsigned mask_bank, mask_bit;
191 local_irq_save_hw(flags);
192 mask_bank = SIC_SYSIRQ(irq) / 32;
193 mask_bit = SIC_SYSIRQ(irq) % 32;
194 #ifdef CONFIG_SMP
195 if (cpumask_test_cpu(0, affinity))
196 #endif
197 bfin_write_SIC_IMASK(mask_bank,
198 bfin_read_SIC_IMASK(mask_bank) |
199 (1 << mask_bit));
200 #ifdef CONFIG_SMP
201 if (cpumask_test_cpu(1, affinity))
202 bfin_write_SICB_IMASK(mask_bank,
203 bfin_read_SICB_IMASK(mask_bank) |
204 (1 << mask_bit));
205 #endif
206 #endif
207 local_irq_restore_hw(flags);
208 }
209
210 #ifdef CONFIG_SMP
211 static void bfin_internal_unmask_irq(unsigned int irq)
212 {
213 struct irq_desc *desc = irq_to_desc(irq);
214 bfin_internal_unmask_irq_affinity(irq, desc->affinity);
215 }
216
217 static int bfin_internal_set_affinity(unsigned int irq, const struct cpumask *mask)
218 {
219 bfin_internal_mask_irq(irq);
220 bfin_internal_unmask_irq_affinity(irq, mask);
221
222 return 0;
223 }
224 #endif
225
226 #ifdef CONFIG_PM
227 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
228 {
229 u32 bank, bit, wakeup = 0;
230 unsigned long flags;
231 bank = SIC_SYSIRQ(irq) / 32;
232 bit = SIC_SYSIRQ(irq) % 32;
233
234 switch (irq) {
235 #ifdef IRQ_RTC
236 case IRQ_RTC:
237 wakeup |= WAKE;
238 break;
239 #endif
240 #ifdef IRQ_CAN0_RX
241 case IRQ_CAN0_RX:
242 wakeup |= CANWE;
243 break;
244 #endif
245 #ifdef IRQ_CAN1_RX
246 case IRQ_CAN1_RX:
247 wakeup |= CANWE;
248 break;
249 #endif
250 #ifdef IRQ_USB_INT0
251 case IRQ_USB_INT0:
252 wakeup |= USBWE;
253 break;
254 #endif
255 #ifdef CONFIG_BF54x
256 case IRQ_CNT:
257 wakeup |= ROTWE;
258 break;
259 #endif
260 default:
261 break;
262 }
263
264 local_irq_save_hw(flags);
265
266 if (state) {
267 bfin_sic_iwr[bank] |= (1 << bit);
268 vr_wakeup |= wakeup;
269
270 } else {
271 bfin_sic_iwr[bank] &= ~(1 << bit);
272 vr_wakeup &= ~wakeup;
273 }
274
275 local_irq_restore_hw(flags);
276
277 return 0;
278 }
279 #endif
280
281 static struct irq_chip bfin_core_irqchip = {
282 .name = "CORE",
283 .ack = bfin_ack_noop,
284 .mask = bfin_core_mask_irq,
285 .unmask = bfin_core_unmask_irq,
286 };
287
288 static struct irq_chip bfin_internal_irqchip = {
289 .name = "INTN",
290 .ack = bfin_ack_noop,
291 .mask = bfin_internal_mask_irq,
292 .unmask = bfin_internal_unmask_irq,
293 .mask_ack = bfin_internal_mask_irq,
294 .disable = bfin_internal_mask_irq,
295 .enable = bfin_internal_unmask_irq,
296 #ifdef CONFIG_SMP
297 .set_affinity = bfin_internal_set_affinity,
298 #endif
299 #ifdef CONFIG_PM
300 .set_wake = bfin_internal_set_wake,
301 #endif
302 };
303
304 static void bfin_handle_irq(unsigned irq)
305 {
306 #ifdef CONFIG_IPIPE
307 struct pt_regs regs; /* Contents not used. */
308 ipipe_trace_irq_entry(irq);
309 __ipipe_handle_irq(irq, &regs);
310 ipipe_trace_irq_exit(irq);
311 #else /* !CONFIG_IPIPE */
312 struct irq_desc *desc = irq_desc + irq;
313 desc->handle_irq(irq, desc);
314 #endif /* !CONFIG_IPIPE */
315 }
316
317 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
318 static int error_int_mask;
319
320 static void bfin_generic_error_mask_irq(unsigned int irq)
321 {
322 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
323 if (!error_int_mask)
324 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
325 }
326
327 static void bfin_generic_error_unmask_irq(unsigned int irq)
328 {
329 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
330 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
331 }
332
333 static struct irq_chip bfin_generic_error_irqchip = {
334 .name = "ERROR",
335 .ack = bfin_ack_noop,
336 .mask_ack = bfin_generic_error_mask_irq,
337 .mask = bfin_generic_error_mask_irq,
338 .unmask = bfin_generic_error_unmask_irq,
339 };
340
341 static void bfin_demux_error_irq(unsigned int int_err_irq,
342 struct irq_desc *inta_desc)
343 {
344 int irq = 0;
345
346 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
347 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
348 irq = IRQ_MAC_ERROR;
349 else
350 #endif
351 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
352 irq = IRQ_SPORT0_ERROR;
353 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
354 irq = IRQ_SPORT1_ERROR;
355 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
356 irq = IRQ_PPI_ERROR;
357 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
358 irq = IRQ_CAN_ERROR;
359 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
360 irq = IRQ_SPI_ERROR;
361 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
362 irq = IRQ_UART0_ERROR;
363 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
364 irq = IRQ_UART1_ERROR;
365
366 if (irq) {
367 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
368 bfin_handle_irq(irq);
369 else {
370
371 switch (irq) {
372 case IRQ_PPI_ERROR:
373 bfin_write_PPI_STATUS(PPI_ERR_MASK);
374 break;
375 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
376 case IRQ_MAC_ERROR:
377 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
378 break;
379 #endif
380 case IRQ_SPORT0_ERROR:
381 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
382 break;
383
384 case IRQ_SPORT1_ERROR:
385 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
386 break;
387
388 case IRQ_CAN_ERROR:
389 bfin_write_CAN_GIS(CAN_ERR_MASK);
390 break;
391
392 case IRQ_SPI_ERROR:
393 bfin_write_SPI_STAT(SPI_ERR_MASK);
394 break;
395
396 default:
397 break;
398 }
399
400 pr_debug("IRQ %d:"
401 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
402 irq);
403 }
404 } else
405 printk(KERN_ERR
406 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
407 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
408 __func__, __FILE__, __LINE__);
409
410 }
411 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
412
413 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
414 static int mac_stat_int_mask;
415
416 static void bfin_mac_status_ack_irq(unsigned int irq)
417 {
418 switch (irq) {
419 case IRQ_MAC_MMCINT:
420 bfin_write_EMAC_MMC_TIRQS(
421 bfin_read_EMAC_MMC_TIRQE() &
422 bfin_read_EMAC_MMC_TIRQS());
423 bfin_write_EMAC_MMC_RIRQS(
424 bfin_read_EMAC_MMC_RIRQE() &
425 bfin_read_EMAC_MMC_RIRQS());
426 break;
427 case IRQ_MAC_RXFSINT:
428 bfin_write_EMAC_RX_STKY(
429 bfin_read_EMAC_RX_IRQE() &
430 bfin_read_EMAC_RX_STKY());
431 break;
432 case IRQ_MAC_TXFSINT:
433 bfin_write_EMAC_TX_STKY(
434 bfin_read_EMAC_TX_IRQE() &
435 bfin_read_EMAC_TX_STKY());
436 break;
437 case IRQ_MAC_WAKEDET:
438 bfin_write_EMAC_WKUP_CTL(
439 bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
440 break;
441 default:
442 /* These bits are W1C */
443 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
444 break;
445 }
446 }
447
448 static void bfin_mac_status_mask_irq(unsigned int irq)
449 {
450 mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
451 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
452 switch (irq) {
453 case IRQ_MAC_PHYINT:
454 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
455 break;
456 default:
457 break;
458 }
459 #else
460 if (!mac_stat_int_mask)
461 bfin_internal_mask_irq(IRQ_MAC_ERROR);
462 #endif
463 bfin_mac_status_ack_irq(irq);
464 }
465
466 static void bfin_mac_status_unmask_irq(unsigned int irq)
467 {
468 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
469 switch (irq) {
470 case IRQ_MAC_PHYINT:
471 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
472 break;
473 default:
474 break;
475 }
476 #else
477 if (!mac_stat_int_mask)
478 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
479 #endif
480 mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
481 }
482
483 #ifdef CONFIG_PM
484 int bfin_mac_status_set_wake(unsigned int irq, unsigned int state)
485 {
486 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
487 return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
488 #else
489 return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
490 #endif
491 }
492 #endif
493
494 static struct irq_chip bfin_mac_status_irqchip = {
495 .name = "MACST",
496 .ack = bfin_ack_noop,
497 .mask_ack = bfin_mac_status_mask_irq,
498 .mask = bfin_mac_status_mask_irq,
499 .unmask = bfin_mac_status_unmask_irq,
500 #ifdef CONFIG_PM
501 .set_wake = bfin_mac_status_set_wake,
502 #endif
503 };
504
505 static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
506 struct irq_desc *inta_desc)
507 {
508 int i, irq = 0;
509 u32 status = bfin_read_EMAC_SYSTAT();
510
511 for (i = 0; i < (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
512 if (status & (1L << i)) {
513 irq = IRQ_MAC_PHYINT + i;
514 break;
515 }
516
517 if (irq) {
518 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
519 bfin_handle_irq(irq);
520 } else {
521 bfin_mac_status_ack_irq(irq);
522 pr_debug("IRQ %d:"
523 " MASKED MAC ERROR INTERRUPT ASSERTED\n",
524 irq);
525 }
526 } else
527 printk(KERN_ERR
528 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
529 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
530 __func__, __FILE__, __LINE__);
531 }
532 #endif
533
534 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
535 {
536 #ifdef CONFIG_IPIPE
537 _set_irq_handler(irq, handle_level_irq);
538 #else
539 struct irq_desc *desc = irq_desc + irq;
540 /* May not call generic set_irq_handler() due to spinlock
541 recursion. */
542 desc->handle_irq = handle;
543 #endif
544 }
545
546 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
547 extern void bfin_gpio_irq_prepare(unsigned gpio);
548
549 #if !defined(CONFIG_BF54x)
550
551 static void bfin_gpio_ack_irq(unsigned int irq)
552 {
553 /* AFAIK ack_irq in case mask_ack is provided
554 * get's only called for edge sense irqs
555 */
556 set_gpio_data(irq_to_gpio(irq), 0);
557 }
558
559 static void bfin_gpio_mask_ack_irq(unsigned int irq)
560 {
561 struct irq_desc *desc = irq_desc + irq;
562 u32 gpionr = irq_to_gpio(irq);
563
564 if (desc->handle_irq == handle_edge_irq)
565 set_gpio_data(gpionr, 0);
566
567 set_gpio_maska(gpionr, 0);
568 }
569
570 static void bfin_gpio_mask_irq(unsigned int irq)
571 {
572 set_gpio_maska(irq_to_gpio(irq), 0);
573 }
574
575 static void bfin_gpio_unmask_irq(unsigned int irq)
576 {
577 set_gpio_maska(irq_to_gpio(irq), 1);
578 }
579
580 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
581 {
582 u32 gpionr = irq_to_gpio(irq);
583
584 if (__test_and_set_bit(gpionr, gpio_enabled))
585 bfin_gpio_irq_prepare(gpionr);
586
587 bfin_gpio_unmask_irq(irq);
588
589 return 0;
590 }
591
592 static void bfin_gpio_irq_shutdown(unsigned int irq)
593 {
594 u32 gpionr = irq_to_gpio(irq);
595
596 bfin_gpio_mask_irq(irq);
597 __clear_bit(gpionr, gpio_enabled);
598 bfin_gpio_irq_free(gpionr);
599 }
600
601 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
602 {
603 int ret;
604 char buf[16];
605 u32 gpionr = irq_to_gpio(irq);
606
607 if (type == IRQ_TYPE_PROBE) {
608 /* only probe unenabled GPIO interrupt lines */
609 if (test_bit(gpionr, gpio_enabled))
610 return 0;
611 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
612 }
613
614 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
615 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
616
617 snprintf(buf, 16, "gpio-irq%d", irq);
618 ret = bfin_gpio_irq_request(gpionr, buf);
619 if (ret)
620 return ret;
621
622 if (__test_and_set_bit(gpionr, gpio_enabled))
623 bfin_gpio_irq_prepare(gpionr);
624
625 } else {
626 __clear_bit(gpionr, gpio_enabled);
627 return 0;
628 }
629
630 set_gpio_inen(gpionr, 0);
631 set_gpio_dir(gpionr, 0);
632
633 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
634 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
635 set_gpio_both(gpionr, 1);
636 else
637 set_gpio_both(gpionr, 0);
638
639 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
640 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
641 else
642 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
643
644 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
645 set_gpio_edge(gpionr, 1);
646 set_gpio_inen(gpionr, 1);
647 set_gpio_data(gpionr, 0);
648
649 } else {
650 set_gpio_edge(gpionr, 0);
651 set_gpio_inen(gpionr, 1);
652 }
653
654 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
655 bfin_set_irq_handler(irq, handle_edge_irq);
656 else
657 bfin_set_irq_handler(irq, handle_level_irq);
658
659 return 0;
660 }
661
662 #ifdef CONFIG_PM
663 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
664 {
665 unsigned gpio = irq_to_gpio(irq);
666
667 if (state)
668 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
669 else
670 gpio_pm_wakeup_free(gpio);
671
672 return 0;
673 }
674 #endif
675
676 static void bfin_demux_gpio_irq(unsigned int inta_irq,
677 struct irq_desc *desc)
678 {
679 unsigned int i, gpio, mask, irq, search = 0;
680
681 switch (inta_irq) {
682 #if defined(CONFIG_BF53x)
683 case IRQ_PROG_INTA:
684 irq = IRQ_PF0;
685 search = 1;
686 break;
687 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
688 case IRQ_MAC_RX:
689 irq = IRQ_PH0;
690 break;
691 # endif
692 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
693 case IRQ_PORTF_INTA:
694 irq = IRQ_PF0;
695 break;
696 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
697 case IRQ_PORTF_INTA:
698 irq = IRQ_PF0;
699 break;
700 case IRQ_PORTG_INTA:
701 irq = IRQ_PG0;
702 break;
703 case IRQ_PORTH_INTA:
704 irq = IRQ_PH0;
705 break;
706 #elif defined(CONFIG_BF561)
707 case IRQ_PROG0_INTA:
708 irq = IRQ_PF0;
709 break;
710 case IRQ_PROG1_INTA:
711 irq = IRQ_PF16;
712 break;
713 case IRQ_PROG2_INTA:
714 irq = IRQ_PF32;
715 break;
716 #endif
717 default:
718 BUG();
719 return;
720 }
721
722 if (search) {
723 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
724 irq += i;
725
726 mask = get_gpiop_data(i) & get_gpiop_maska(i);
727
728 while (mask) {
729 if (mask & 1)
730 bfin_handle_irq(irq);
731 irq++;
732 mask >>= 1;
733 }
734 }
735 } else {
736 gpio = irq_to_gpio(irq);
737 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
738
739 do {
740 if (mask & 1)
741 bfin_handle_irq(irq);
742 irq++;
743 mask >>= 1;
744 } while (mask);
745 }
746
747 }
748
749 #else /* CONFIG_BF54x */
750
751 #define NR_PINT_SYS_IRQS 4
752 #define NR_PINT_BITS 32
753 #define NR_PINTS 160
754 #define IRQ_NOT_AVAIL 0xFF
755
756 #define PINT_2_BANK(x) ((x) >> 5)
757 #define PINT_2_BIT(x) ((x) & 0x1F)
758 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
759
760 static unsigned char irq2pint_lut[NR_PINTS];
761 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
762
763 struct pin_int_t {
764 unsigned int mask_set;
765 unsigned int mask_clear;
766 unsigned int request;
767 unsigned int assign;
768 unsigned int edge_set;
769 unsigned int edge_clear;
770 unsigned int invert_set;
771 unsigned int invert_clear;
772 unsigned int pinstate;
773 unsigned int latch;
774 };
775
776 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
777 (struct pin_int_t *)PINT0_MASK_SET,
778 (struct pin_int_t *)PINT1_MASK_SET,
779 (struct pin_int_t *)PINT2_MASK_SET,
780 (struct pin_int_t *)PINT3_MASK_SET,
781 };
782
783 inline unsigned int get_irq_base(u32 bank, u8 bmap)
784 {
785 unsigned int irq_base;
786
787 if (bank < 2) { /*PA-PB */
788 irq_base = IRQ_PA0 + bmap * 16;
789 } else { /*PC-PJ */
790 irq_base = IRQ_PC0 + bmap * 16;
791 }
792
793 return irq_base;
794 }
795
796 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
797 void init_pint_lut(void)
798 {
799 u16 bank, bit, irq_base, bit_pos;
800 u32 pint_assign;
801 u8 bmap;
802
803 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
804
805 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
806
807 pint_assign = pint[bank]->assign;
808
809 for (bit = 0; bit < NR_PINT_BITS; bit++) {
810
811 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
812
813 irq_base = get_irq_base(bank, bmap);
814
815 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
816 bit_pos = bit + bank * NR_PINT_BITS;
817
818 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
819 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
820 }
821 }
822 }
823
824 static void bfin_gpio_ack_irq(unsigned int irq)
825 {
826 struct irq_desc *desc = irq_desc + irq;
827 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
828 u32 pintbit = PINT_BIT(pint_val);
829 u32 bank = PINT_2_BANK(pint_val);
830
831 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
832 if (pint[bank]->invert_set & pintbit)
833 pint[bank]->invert_clear = pintbit;
834 else
835 pint[bank]->invert_set = pintbit;
836 }
837 pint[bank]->request = pintbit;
838
839 }
840
841 static void bfin_gpio_mask_ack_irq(unsigned int irq)
842 {
843 struct irq_desc *desc = irq_desc + irq;
844 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
845 u32 pintbit = PINT_BIT(pint_val);
846 u32 bank = PINT_2_BANK(pint_val);
847
848 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
849 if (pint[bank]->invert_set & pintbit)
850 pint[bank]->invert_clear = pintbit;
851 else
852 pint[bank]->invert_set = pintbit;
853 }
854
855 pint[bank]->request = pintbit;
856 pint[bank]->mask_clear = pintbit;
857 }
858
859 static void bfin_gpio_mask_irq(unsigned int irq)
860 {
861 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
862
863 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
864 }
865
866 static void bfin_gpio_unmask_irq(unsigned int irq)
867 {
868 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
869 u32 pintbit = PINT_BIT(pint_val);
870 u32 bank = PINT_2_BANK(pint_val);
871
872 pint[bank]->request = pintbit;
873 pint[bank]->mask_set = pintbit;
874 }
875
876 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
877 {
878 u32 gpionr = irq_to_gpio(irq);
879 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
880
881 if (pint_val == IRQ_NOT_AVAIL) {
882 printk(KERN_ERR
883 "GPIO IRQ %d :Not in PINT Assign table "
884 "Reconfigure Interrupt to Port Assignemt\n", irq);
885 return -ENODEV;
886 }
887
888 if (__test_and_set_bit(gpionr, gpio_enabled))
889 bfin_gpio_irq_prepare(gpionr);
890
891 bfin_gpio_unmask_irq(irq);
892
893 return 0;
894 }
895
896 static void bfin_gpio_irq_shutdown(unsigned int irq)
897 {
898 u32 gpionr = irq_to_gpio(irq);
899
900 bfin_gpio_mask_irq(irq);
901 __clear_bit(gpionr, gpio_enabled);
902 bfin_gpio_irq_free(gpionr);
903 }
904
905 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
906 {
907 int ret;
908 char buf[16];
909 u32 gpionr = irq_to_gpio(irq);
910 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
911 u32 pintbit = PINT_BIT(pint_val);
912 u32 bank = PINT_2_BANK(pint_val);
913
914 if (pint_val == IRQ_NOT_AVAIL)
915 return -ENODEV;
916
917 if (type == IRQ_TYPE_PROBE) {
918 /* only probe unenabled GPIO interrupt lines */
919 if (test_bit(gpionr, gpio_enabled))
920 return 0;
921 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
922 }
923
924 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
925 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
926
927 snprintf(buf, 16, "gpio-irq%d", irq);
928 ret = bfin_gpio_irq_request(gpionr, buf);
929 if (ret)
930 return ret;
931
932 if (__test_and_set_bit(gpionr, gpio_enabled))
933 bfin_gpio_irq_prepare(gpionr);
934
935 } else {
936 __clear_bit(gpionr, gpio_enabled);
937 return 0;
938 }
939
940 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
941 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
942 else
943 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
944
945 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
946 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
947 if (gpio_get_value(gpionr))
948 pint[bank]->invert_set = pintbit;
949 else
950 pint[bank]->invert_clear = pintbit;
951 }
952
953 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
954 pint[bank]->edge_set = pintbit;
955 bfin_set_irq_handler(irq, handle_edge_irq);
956 } else {
957 pint[bank]->edge_clear = pintbit;
958 bfin_set_irq_handler(irq, handle_level_irq);
959 }
960
961 return 0;
962 }
963
964 #ifdef CONFIG_PM
965 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
966 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
967
968 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
969 {
970 u32 pint_irq;
971 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
972 u32 bank = PINT_2_BANK(pint_val);
973 u32 pintbit = PINT_BIT(pint_val);
974
975 switch (bank) {
976 case 0:
977 pint_irq = IRQ_PINT0;
978 break;
979 case 2:
980 pint_irq = IRQ_PINT2;
981 break;
982 case 3:
983 pint_irq = IRQ_PINT3;
984 break;
985 case 1:
986 pint_irq = IRQ_PINT1;
987 break;
988 default:
989 return -EINVAL;
990 }
991
992 bfin_internal_set_wake(pint_irq, state);
993
994 if (state)
995 pint_wakeup_masks[bank] |= pintbit;
996 else
997 pint_wakeup_masks[bank] &= ~pintbit;
998
999 return 0;
1000 }
1001
1002 u32 bfin_pm_setup(void)
1003 {
1004 u32 val, i;
1005
1006 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1007 val = pint[i]->mask_clear;
1008 pint_saved_masks[i] = val;
1009 if (val ^ pint_wakeup_masks[i]) {
1010 pint[i]->mask_clear = val;
1011 pint[i]->mask_set = pint_wakeup_masks[i];
1012 }
1013 }
1014
1015 return 0;
1016 }
1017
1018 void bfin_pm_restore(void)
1019 {
1020 u32 i, val;
1021
1022 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
1023 val = pint_saved_masks[i];
1024 if (val ^ pint_wakeup_masks[i]) {
1025 pint[i]->mask_clear = pint[i]->mask_clear;
1026 pint[i]->mask_set = val;
1027 }
1028 }
1029 }
1030 #endif
1031
1032 static void bfin_demux_gpio_irq(unsigned int inta_irq,
1033 struct irq_desc *desc)
1034 {
1035 u32 bank, pint_val;
1036 u32 request, irq;
1037
1038 switch (inta_irq) {
1039 case IRQ_PINT0:
1040 bank = 0;
1041 break;
1042 case IRQ_PINT2:
1043 bank = 2;
1044 break;
1045 case IRQ_PINT3:
1046 bank = 3;
1047 break;
1048 case IRQ_PINT1:
1049 bank = 1;
1050 break;
1051 default:
1052 return;
1053 }
1054
1055 pint_val = bank * NR_PINT_BITS;
1056
1057 request = pint[bank]->request;
1058
1059 while (request) {
1060 if (request & 1) {
1061 irq = pint2irq_lut[pint_val] + SYS_IRQS;
1062 bfin_handle_irq(irq);
1063 }
1064 pint_val++;
1065 request >>= 1;
1066 }
1067
1068 }
1069 #endif
1070
1071 static struct irq_chip bfin_gpio_irqchip = {
1072 .name = "GPIO",
1073 .ack = bfin_gpio_ack_irq,
1074 .mask = bfin_gpio_mask_irq,
1075 .mask_ack = bfin_gpio_mask_ack_irq,
1076 .unmask = bfin_gpio_unmask_irq,
1077 .disable = bfin_gpio_mask_irq,
1078 .enable = bfin_gpio_unmask_irq,
1079 .set_type = bfin_gpio_irq_type,
1080 .startup = bfin_gpio_irq_startup,
1081 .shutdown = bfin_gpio_irq_shutdown,
1082 #ifdef CONFIG_PM
1083 .set_wake = bfin_gpio_set_wake,
1084 #endif
1085 };
1086
1087 void __cpuinit init_exception_vectors(void)
1088 {
1089 /* cannot program in software:
1090 * evt0 - emulation (jtag)
1091 * evt1 - reset
1092 */
1093 bfin_write_EVT2(evt_nmi);
1094 bfin_write_EVT3(trap);
1095 bfin_write_EVT5(evt_ivhw);
1096 bfin_write_EVT6(evt_timer);
1097 bfin_write_EVT7(evt_evt7);
1098 bfin_write_EVT8(evt_evt8);
1099 bfin_write_EVT9(evt_evt9);
1100 bfin_write_EVT10(evt_evt10);
1101 bfin_write_EVT11(evt_evt11);
1102 bfin_write_EVT12(evt_evt12);
1103 bfin_write_EVT13(evt_evt13);
1104 bfin_write_EVT14(evt_evt14);
1105 bfin_write_EVT15(evt_system_call);
1106 CSYNC();
1107 }
1108
1109 /*
1110 * This function should be called during kernel startup to initialize
1111 * the BFin IRQ handling routines.
1112 */
1113
1114 int __init init_arch_irq(void)
1115 {
1116 int irq;
1117 unsigned long ilat = 0;
1118 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
1119 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1120 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
1121 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
1122 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
1123 # ifdef CONFIG_BF54x
1124 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
1125 # endif
1126 # ifdef CONFIG_SMP
1127 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
1128 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
1129 # endif
1130 #else
1131 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
1132 #endif
1133
1134 local_irq_disable();
1135
1136 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
1137 /* Clear EMAC Interrupt Status bits so we can demux it later */
1138 bfin_write_EMAC_SYSTAT(-1);
1139 #endif
1140
1141 #ifdef CONFIG_BF54x
1142 # ifdef CONFIG_PINTx_REASSIGN
1143 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1144 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1145 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1146 pint[3]->assign = CONFIG_PINT3_ASSIGN;
1147 # endif
1148 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1149 init_pint_lut();
1150 #endif
1151
1152 for (irq = 0; irq <= SYS_IRQS; irq++) {
1153 if (irq <= IRQ_CORETMR)
1154 set_irq_chip(irq, &bfin_core_irqchip);
1155 else
1156 set_irq_chip(irq, &bfin_internal_irqchip);
1157
1158 switch (irq) {
1159 #if defined(CONFIG_BF53x)
1160 case IRQ_PROG_INTA:
1161 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1162 case IRQ_MAC_RX:
1163 # endif
1164 #elif defined(CONFIG_BF54x)
1165 case IRQ_PINT0:
1166 case IRQ_PINT1:
1167 case IRQ_PINT2:
1168 case IRQ_PINT3:
1169 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1170 case IRQ_PORTF_INTA:
1171 case IRQ_PORTG_INTA:
1172 case IRQ_PORTH_INTA:
1173 #elif defined(CONFIG_BF561)
1174 case IRQ_PROG0_INTA:
1175 case IRQ_PROG1_INTA:
1176 case IRQ_PROG2_INTA:
1177 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1178 case IRQ_PORTF_INTA:
1179 #endif
1180 set_irq_chained_handler(irq,
1181 bfin_demux_gpio_irq);
1182 break;
1183 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1184 case IRQ_GENERIC_ERROR:
1185 set_irq_chained_handler(irq, bfin_demux_error_irq);
1186 break;
1187 #endif
1188 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1189 case IRQ_MAC_ERROR:
1190 set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
1191 break;
1192 #endif
1193 #ifdef CONFIG_SMP
1194 case IRQ_SUPPLE_0:
1195 case IRQ_SUPPLE_1:
1196 set_irq_handler(irq, handle_percpu_irq);
1197 break;
1198 #endif
1199
1200 #ifdef CONFIG_TICKSOURCE_CORETMR
1201 case IRQ_CORETMR:
1202 # ifdef CONFIG_SMP
1203 set_irq_handler(irq, handle_percpu_irq);
1204 break;
1205 # else
1206 set_irq_handler(irq, handle_simple_irq);
1207 break;
1208 # endif
1209 #endif
1210
1211 #ifdef CONFIG_TICKSOURCE_GPTMR0
1212 case IRQ_TIMER0:
1213 set_irq_handler(irq, handle_simple_irq);
1214 break;
1215 #endif
1216
1217 #ifdef CONFIG_IPIPE
1218 default:
1219 set_irq_handler(irq, handle_level_irq);
1220 break;
1221 #else /* !CONFIG_IPIPE */
1222 default:
1223 set_irq_handler(irq, handle_simple_irq);
1224 break;
1225 #endif /* !CONFIG_IPIPE */
1226 }
1227 }
1228
1229 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1230 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1231 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1232 handle_level_irq);
1233 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1234 set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
1235 #endif
1236 #endif
1237
1238 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1239 for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1240 set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
1241 handle_level_irq);
1242 #endif
1243 /* if configured as edge, then will be changed to do_edge_IRQ */
1244 for (irq = GPIO_IRQ_BASE;
1245 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1246 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1247 handle_level_irq);
1248
1249 bfin_write_IMASK(0);
1250 CSYNC();
1251 ilat = bfin_read_ILAT();
1252 CSYNC();
1253 bfin_write_ILAT(ilat);
1254 CSYNC();
1255
1256 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1257 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1258 * local_irq_enable()
1259 */
1260 program_IAR();
1261 /* Therefore it's better to setup IARs before interrupts enabled */
1262 search_IAR();
1263
1264 /* Enable interrupts IVG7-15 */
1265 bfin_irq_flags |= IMASK_IVG15 |
1266 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1267 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1268
1269 /* This implicitly covers ANOMALY_05000171
1270 * Boot-ROM code modifies SICA_IWRx wakeup registers
1271 */
1272 #ifdef SIC_IWR0
1273 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1274 # ifdef SIC_IWR1
1275 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1276 * will screw up the bootrom as it relies on MDMA0/1 waking it
1277 * up from IDLE instructions. See this report for more info:
1278 * http://blackfin.uclinux.org/gf/tracker/4323
1279 */
1280 if (ANOMALY_05000435)
1281 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1282 else
1283 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1284 # endif
1285 # ifdef SIC_IWR2
1286 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1287 # endif
1288 #else
1289 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1290 #endif
1291
1292 return 0;
1293 }
1294
1295 #ifdef CONFIG_DO_IRQ_L1
1296 __attribute__((l1_text))
1297 #endif
1298 void do_irq(int vec, struct pt_regs *fp)
1299 {
1300 if (vec == EVT_IVTMR_P) {
1301 vec = IRQ_CORETMR;
1302 } else {
1303 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1304 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1305 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1306 unsigned long sic_status[3];
1307
1308 if (smp_processor_id()) {
1309 # ifdef SICB_ISR0
1310 /* This will be optimized out in UP mode. */
1311 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1312 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1313 # endif
1314 } else {
1315 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1316 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1317 }
1318 # ifdef SIC_ISR2
1319 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1320 # endif
1321 for (;; ivg++) {
1322 if (ivg >= ivg_stop) {
1323 atomic_inc(&num_spurious);
1324 return;
1325 }
1326 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1327 break;
1328 }
1329 #else
1330 unsigned long sic_status;
1331
1332 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1333
1334 for (;; ivg++) {
1335 if (ivg >= ivg_stop) {
1336 atomic_inc(&num_spurious);
1337 return;
1338 } else if (sic_status & ivg->isrflag)
1339 break;
1340 }
1341 #endif
1342 vec = ivg->irqno;
1343 }
1344 asm_do_IRQ(vec, fp);
1345 }
1346
1347 #ifdef CONFIG_IPIPE
1348
1349 int __ipipe_get_irq_priority(unsigned irq)
1350 {
1351 int ient, prio;
1352
1353 if (irq <= IRQ_CORETMR)
1354 return irq;
1355
1356 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1357 struct ivgx *ivg = ivg_table + ient;
1358 if (ivg->irqno == irq) {
1359 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1360 if (ivg7_13[prio].ifirst <= ivg &&
1361 ivg7_13[prio].istop > ivg)
1362 return IVG7 + prio;
1363 }
1364 }
1365 }
1366
1367 return IVG15;
1368 }
1369
1370 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1371 #ifdef CONFIG_DO_IRQ_L1
1372 __attribute__((l1_text))
1373 #endif
1374 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1375 {
1376 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1377 struct ipipe_domain *this_domain = __ipipe_current_domain;
1378 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1379 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1380 int irq, s;
1381
1382 if (likely(vec == EVT_IVTMR_P))
1383 irq = IRQ_CORETMR;
1384 else {
1385 #if defined(SIC_ISR0) || defined(SICA_ISR0)
1386 unsigned long sic_status[3];
1387
1388 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1389 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1390 # ifdef SIC_ISR2
1391 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1392 # endif
1393 for (;; ivg++) {
1394 if (ivg >= ivg_stop) {
1395 atomic_inc(&num_spurious);
1396 return 0;
1397 }
1398 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1399 break;
1400 }
1401 #else
1402 unsigned long sic_status;
1403
1404 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1405
1406 for (;; ivg++) {
1407 if (ivg >= ivg_stop) {
1408 atomic_inc(&num_spurious);
1409 return 0;
1410 } else if (sic_status & ivg->isrflag)
1411 break;
1412 }
1413 #endif
1414 irq = ivg->irqno;
1415 }
1416
1417 if (irq == IRQ_SYSTMR) {
1418 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1419 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1420 #endif
1421 /* This is basically what we need from the register frame. */
1422 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1423 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1424 if (this_domain != ipipe_root_domain)
1425 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1426 else
1427 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1428 }
1429
1430 if (this_domain == ipipe_root_domain) {
1431 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1432 barrier();
1433 }
1434
1435 ipipe_trace_irq_entry(irq);
1436 __ipipe_handle_irq(irq, regs);
1437 ipipe_trace_irq_exit(irq);
1438
1439 if (this_domain == ipipe_root_domain) {
1440 set_thread_flag(TIF_IRQ_SYNC);
1441 if (!s) {
1442 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1443 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1444 }
1445 }
1446
1447 return 0;
1448 }
1449
1450 #endif /* CONFIG_IPIPE */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree