2 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
4 * Licensed under the terms of the GNU GPL License version 2.
6 * Library for common functions for Intel SpeedStep v.1 and v.2 support
8 * BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/cpufreq.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
20 #include "speedstep-lib.h"
22 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-lib", msg)
24 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
25 static int relaxed_check
= 0;
27 #define relaxed_check 0
30 /*********************************************************************
31 * GET PROCESSOR CORE SPEED IN KHZ *
32 *********************************************************************/
34 static unsigned int pentium3_get_frequency (unsigned int processor
)
36 /* See table 14 of p3_ds.pdf and table 22 of 29834003.pdf */
38 unsigned int ratio
; /* Frequency Multiplier (x10) */
39 u8 bitmap
; /* power on configuration bits
40 [27, 25:22] (in MSR 0x2a) */
41 } msr_decode_mult
[] = {
56 { 0, 0xff } /* error or unknown value */
59 /* PIII(-M) FSB settings: see table b1-b of 24547206.pdf */
61 unsigned int value
; /* Front Side Bus speed in MHz */
62 u8 bitmap
; /* power on configuration bits [18: 19]
64 } msr_decode_fsb
[] = {
74 /* read MSR 0x2a - we only need the low 32 bits */
75 rdmsr(MSR_IA32_EBL_CR_POWERON
, msr_lo
, msr_tmp
);
76 dprintk("P3 - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo
, msr_tmp
);
82 while (msr_tmp
!= msr_decode_fsb
[i
].bitmap
) {
83 if (msr_decode_fsb
[i
].bitmap
== 0xff)
88 /* decode the multiplier */
89 if (processor
== SPEEDSTEP_PROCESSOR_PIII_C_EARLY
) {
90 dprintk("workaround for early PIIIs\n");
95 while (msr_lo
!= msr_decode_mult
[j
].bitmap
) {
96 if (msr_decode_mult
[j
].bitmap
== 0xff)
101 dprintk("speed is %u\n", (msr_decode_mult
[j
].ratio
* msr_decode_fsb
[i
].value
* 100));
103 return (msr_decode_mult
[j
].ratio
* msr_decode_fsb
[i
].value
* 100);
107 static unsigned int pentiumM_get_frequency(void)
111 rdmsr(MSR_IA32_EBL_CR_POWERON
, msr_lo
, msr_tmp
);
112 dprintk("PM - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo
, msr_tmp
);
114 /* see table B-2 of 24547212.pdf */
115 if (msr_lo
& 0x00040000) {
116 printk(KERN_DEBUG
"speedstep-lib: PM - invalid FSB: 0x%x 0x%x\n", msr_lo
, msr_tmp
);
120 msr_tmp
= (msr_lo
>> 22) & 0x1f;
121 dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp
, (msr_tmp
* 100 * 1000));
123 return (msr_tmp
* 100 * 1000);
126 static unsigned int pentium_core_get_frequency(void)
131 rdmsr(MSR_FSB_FREQ
, msr_lo
, msr_tmp
);
132 /* see table B-2 of 24547212.pdf */
133 switch (msr_lo
& 0x07) {
144 printk(KERN_ERR
"PCORE - MSR_FSB_FREQ undefined value");
147 rdmsr(MSR_IA32_EBL_CR_POWERON
, msr_lo
, msr_tmp
);
148 dprintk("PCORE - MSR_IA32_EBL_CR_POWERON: 0x%x 0x%x\n", msr_lo
, msr_tmp
);
150 msr_tmp
= (msr_lo
>> 22) & 0x1f;
151 dprintk("bits 22-26 are 0x%x, speed is %u\n", msr_tmp
, (msr_tmp
* fsb
* 1000));
153 return (msr_tmp
* fsb
* 1000);
157 static unsigned int pentium4_get_frequency(void)
159 struct cpuinfo_x86
*c
= &boot_cpu_data
;
160 u32 msr_lo
, msr_hi
, mult
;
161 unsigned int fsb
= 0;
163 rdmsr(0x2c, msr_lo
, msr_hi
);
165 dprintk("P4 - MSR_EBC_FREQUENCY_ID: 0x%x 0x%x\n", msr_lo
, msr_hi
);
167 /* decode the FSB: see IA-32 Intel (C) Architecture Software
168 * Developer's Manual, Volume 3: System Prgramming Guide,
169 * revision #12 in Table B-1: MSRs in the Pentium 4 and
170 * Intel Xeon Processors, on page B-4 and B-5.
172 if (c
->x86_model
< 2)
175 u8 fsb_code
= (msr_lo
>> 16) & 0x7;
190 printk(KERN_DEBUG
"speedstep-lib: couldn't detect FSB speed. Please send an e-mail to <linux@brodo.de>\n");
193 if (c
->x86_model
< 2)
198 dprintk("P4 - FSB %u kHz; Multiplier %u; Speed %u kHz\n", fsb
, mult
, (fsb
* mult
));
204 unsigned int speedstep_get_processor_frequency(unsigned int processor
)
207 case SPEEDSTEP_PROCESSOR_PCORE
:
208 return pentium_core_get_frequency();
209 case SPEEDSTEP_PROCESSOR_PM
:
210 return pentiumM_get_frequency();
211 case SPEEDSTEP_PROCESSOR_P4D
:
212 case SPEEDSTEP_PROCESSOR_P4M
:
213 return pentium4_get_frequency();
214 case SPEEDSTEP_PROCESSOR_PIII_T
:
215 case SPEEDSTEP_PROCESSOR_PIII_C
:
216 case SPEEDSTEP_PROCESSOR_PIII_C_EARLY
:
217 return pentium3_get_frequency(processor
);
223 EXPORT_SYMBOL_GPL(speedstep_get_processor_frequency
);
226 /*********************************************************************
227 * DETECT SPEEDSTEP-CAPABLE PROCESSOR *
228 *********************************************************************/
230 unsigned int speedstep_detect_processor (void)
232 struct cpuinfo_x86
*c
= cpu_data
;
233 u32 ebx
, msr_lo
, msr_hi
;
235 dprintk("x86: %x, model: %x\n", c
->x86
, c
->x86_model
);
237 if ((c
->x86_vendor
!= X86_VENDOR_INTEL
) ||
238 ((c
->x86
!= 6) && (c
->x86
!= 0xF)))
242 /* Intel Mobile Pentium 4-M
243 * or Intel Mobile Pentium 4 with 533 MHz FSB */
244 if (c
->x86_model
!= 2)
247 ebx
= cpuid_ebx(0x00000001);
250 dprintk("ebx value is %x, x86_mask is %x\n", ebx
, c
->x86_mask
);
252 switch (c
->x86_mask
) {
255 * B-stepping [M-P4-M]
256 * sample has ebx = 0x0f, production has 0x0e.
258 if ((ebx
== 0x0e) || (ebx
== 0x0f))
259 return SPEEDSTEP_PROCESSOR_P4M
;
263 * C-stepping [M-P4-M]
264 * needs to have ebx=0x0e, else it's a celeron:
265 * cf. 25130917.pdf / page 7, footnote 5 even
266 * though 25072120.pdf / page 7 doesn't say
267 * samples are only of B-stepping...
270 return SPEEDSTEP_PROCESSOR_P4M
;
274 * D-stepping [M-P4-M or M-P4/533]
276 * this is totally strange: CPUID 0x0F29 is
277 * used by M-P4-M, M-P4/533 and(!) Celeron CPUs.
278 * The latter need to be sorted out as they don't
280 * Celerons with CPUID 0x0F29 may have either
281 * ebx=0x8 or 0xf -- 25130917.pdf doesn't say anything
283 * M-P4-Ms may have either ebx=0xe or 0xf [see above]
284 * M-P4/533 have either ebx=0xe or 0xf. [25317607.pdf]
285 * also, M-P4M HTs have ebx=0x8, too
286 * For now, they are distinguished by the model_id string
288 if ((ebx
== 0x0e) || (strstr(c
->x86_model_id
,"Mobile Intel(R) Pentium(R) 4") != NULL
))
289 return SPEEDSTEP_PROCESSOR_P4M
;
297 switch (c
->x86_model
) {
298 case 0x0B: /* Intel PIII [Tualatin] */
299 /* cpuid_ebx(1) is 0x04 for desktop PIII, 0x06 for mobile PIII-M */
300 ebx
= cpuid_ebx(0x00000001);
301 dprintk("ebx is %x\n", ebx
);
308 /* So far all PIII-M processors support SpeedStep. See
309 * Intel's 24540640.pdf of June 2003
311 return SPEEDSTEP_PROCESSOR_PIII_T
;
313 case 0x08: /* Intel PIII [Coppermine] */
315 /* all mobile PIII Coppermines have FSB 100 MHz
316 * ==> sort out a few desktop PIIIs. */
317 rdmsr(MSR_IA32_EBL_CR_POWERON
, msr_lo
, msr_hi
);
318 dprintk("Coppermine: MSR_IA32_EBL_CR_POWERON is 0x%x, 0x%x\n", msr_lo
, msr_hi
);
320 if (msr_lo
!= 0x0080000)
324 * If the processor is a mobile version,
325 * platform ID has bit 50 set
326 * it has SpeedStep technology if either
327 * bit 56 or 57 is set
329 rdmsr(MSR_IA32_PLATFORM_ID
, msr_lo
, msr_hi
);
330 dprintk("Coppermine: MSR_IA32_PLATFORM ID is 0x%x, 0x%x\n", msr_lo
, msr_hi
);
331 if ((msr_hi
& (1<<18)) && (relaxed_check
? 1 : (msr_hi
& (3<<24)))) {
332 if (c
->x86_mask
== 0x01) {
333 dprintk("early PIII version\n");
334 return SPEEDSTEP_PROCESSOR_PIII_C_EARLY
;
336 return SPEEDSTEP_PROCESSOR_PIII_C
;
343 EXPORT_SYMBOL_GPL(speedstep_detect_processor
);
346 /*********************************************************************
347 * DETECT SPEEDSTEP SPEEDS *
348 *********************************************************************/
350 unsigned int speedstep_get_freqs(unsigned int processor
,
351 unsigned int *low_speed
,
352 unsigned int *high_speed
,
353 unsigned int *transition_latency
,
354 void (*set_state
) (unsigned int state
))
356 unsigned int prev_speed
;
357 unsigned int ret
= 0;
359 struct timeval tv1
, tv2
;
361 if ((!processor
) || (!low_speed
) || (!high_speed
) || (!set_state
))
364 dprintk("trying to determine both speeds\n");
366 /* get current speed */
367 prev_speed
= speedstep_get_processor_frequency(processor
);
371 dprintk("previous speed is %u\n", prev_speed
);
373 local_irq_save(flags
);
375 /* switch to low state */
376 set_state(SPEEDSTEP_LOW
);
377 *low_speed
= speedstep_get_processor_frequency(processor
);
383 dprintk("low speed is %u\n", *low_speed
);
385 /* start latency measurement */
386 if (transition_latency
)
387 do_gettimeofday(&tv1
);
389 /* switch to high state */
390 set_state(SPEEDSTEP_HIGH
);
392 /* end latency measurement */
393 if (transition_latency
)
394 do_gettimeofday(&tv2
);
396 *high_speed
= speedstep_get_processor_frequency(processor
);
402 dprintk("high speed is %u\n", *high_speed
);
404 if (*low_speed
== *high_speed
) {
409 /* switch to previous state, if necessary */
410 if (*high_speed
!= prev_speed
)
411 set_state(SPEEDSTEP_LOW
);
413 if (transition_latency
) {
414 *transition_latency
= (tv2
.tv_sec
- tv1
.tv_sec
) * USEC_PER_SEC
+
415 tv2
.tv_usec
- tv1
.tv_usec
;
416 dprintk("transition latency is %u uSec\n", *transition_latency
);
418 /* convert uSec to nSec and add 20% for safety reasons */
419 *transition_latency
*= 1200;
421 /* check if the latency measurement is too high or too low
422 * and set it to a safe value (500uSec) in that case
424 if (*transition_latency
> 10000000 || *transition_latency
< 50000) {
425 printk (KERN_WARNING
"speedstep: frequency transition measured seems out of "
426 "range (%u nSec), falling back to a safe one of %u nSec.\n",
427 *transition_latency
, 500000);
428 *transition_latency
= 500000;
433 local_irq_restore(flags
);
436 EXPORT_SYMBOL_GPL(speedstep_get_freqs
);
438 #ifdef CONFIG_X86_SPEEDSTEP_RELAXED_CAP_CHECK
439 module_param(relaxed_check
, int, 0444);
440 MODULE_PARM_DESC(relaxed_check
, "Don't do all checks for speedstep capability.");
443 MODULE_AUTHOR ("Dominik Brodowski <linux@brodo.de>");
444 MODULE_DESCRIPTION ("Library for Intel SpeedStep 1 or 2 cpufreq drivers.");
445 MODULE_LICENSE ("GPL");