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[media] IR/nuvoton: address all checkpatch.pl issues
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / media / IR / nuvoton-cir.c
blob2f0f78078b57a1de52fa7dc7b4730fedde32a630
1 /*
2 * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
3 *
4 * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
5 * Copyright (C) 2009 Nuvoton PS Team
6 *
7 * Special thanks to Nuvoton for providing hardware, spec sheets and
8 * sample code upon which portions of this driver are based. Indirect
9 * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
10 * modeled after.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
25 * USA
26 */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pnp.h>
31 #include <linux/io.h>
32 #include <linux/interrupt.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35 #include <linux/input.h>
36 #include <media/ir-core.h>
37 #include <linux/pci_ids.h>
38
39 #include "nuvoton-cir.h"
40
41 static char *chip_id = "w836x7hg";
42
43 /* write val to config reg */
44 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
45 {
46 outb(reg, nvt->cr_efir);
47 outb(val, nvt->cr_efdr);
48 }
49
50 /* read val from config reg */
51 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
52 {
53 outb(reg, nvt->cr_efir);
54 return inb(nvt->cr_efdr);
55 }
56
57 /* update config register bit without changing other bits */
58 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
59 {
60 u8 tmp = nvt_cr_read(nvt, reg) | val;
61 nvt_cr_write(nvt, tmp, reg);
62 }
63
64 /* clear config register bit without changing other bits */
65 static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
66 {
67 u8 tmp = nvt_cr_read(nvt, reg) & ~val;
68 nvt_cr_write(nvt, tmp, reg);
69 }
70
71 /* enter extended function mode */
72 static inline void nvt_efm_enable(struct nvt_dev *nvt)
73 {
74 /* Enabling Extended Function Mode explicitly requires writing 2x */
75 outb(EFER_EFM_ENABLE, nvt->cr_efir);
76 outb(EFER_EFM_ENABLE, nvt->cr_efir);
77 }
78
79 /* exit extended function mode */
80 static inline void nvt_efm_disable(struct nvt_dev *nvt)
81 {
82 outb(EFER_EFM_DISABLE, nvt->cr_efir);
83 }
84
85 /*
86 * When you want to address a specific logical device, write its logical
87 * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
88 * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
89 */
90 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
91 {
92 outb(CR_LOGICAL_DEV_SEL, nvt->cr_efir);
93 outb(ldev, nvt->cr_efdr);
94 }
95
96 /* write val to cir config register */
97 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
98 {
99 outb(val, nvt->cir_addr + offset);
100 }
101
102 /* read val from cir config register */
103 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
104 {
105 u8 val;
106
107 val = inb(nvt->cir_addr + offset);
108
109 return val;
110 }
111
112 /* write val to cir wake register */
113 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
114 u8 val, u8 offset)
115 {
116 outb(val, nvt->cir_wake_addr + offset);
117 }
118
119 /* read val from cir wake config register */
120 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
121 {
122 u8 val;
123
124 val = inb(nvt->cir_wake_addr + offset);
125
126 return val;
127 }
128
129 #define pr_reg(text, ...) \
130 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
131
132 /* dump current cir register contents */
133 static void cir_dump_regs(struct nvt_dev *nvt)
134 {
135 nvt_efm_enable(nvt);
136 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
137
138 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
139 pr_reg(" * CR CIR ACTIVE : 0x%x\n",
140 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
141 pr_reg(" * CR CIR BASE ADDR: 0x%x\n",
142 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
143 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
144 pr_reg(" * CR CIR IRQ NUM: 0x%x\n",
145 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
146
147 nvt_efm_disable(nvt);
148
149 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
150 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
151 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
152 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
153 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
154 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
155 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
156 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
157 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
158 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
159 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
160 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
161 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
162 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
163 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
164 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
165 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
166 }
167
168 /* dump current cir wake register contents */
169 static void cir_wake_dump_regs(struct nvt_dev *nvt)
170 {
171 u8 i, fifo_len;
172
173 nvt_efm_enable(nvt);
174 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
175
176 pr_reg("%s: Dump CIR WAKE logical device registers:\n",
177 NVT_DRIVER_NAME);
178 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n",
179 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
180 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n",
181 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
182 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
183 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n",
184 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
185
186 nvt_efm_disable(nvt);
187
188 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
189 pr_reg(" * IRCON: 0x%x\n",
190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
191 pr_reg(" * IRSTS: 0x%x\n",
192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
193 pr_reg(" * IREN: 0x%x\n",
194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
195 pr_reg(" * FIFO CMP DEEP: 0x%x\n",
196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
197 pr_reg(" * FIFO CMP TOL: 0x%x\n",
198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
199 pr_reg(" * FIFO COUNT: 0x%x\n",
200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
201 pr_reg(" * SLCH: 0x%x\n",
202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
203 pr_reg(" * SLCL: 0x%x\n",
204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
205 pr_reg(" * FIFOCON: 0x%x\n",
206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
207 pr_reg(" * SRXFSTS: 0x%x\n",
208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
209 pr_reg(" * SAMPLE RX FIFO: 0x%x\n",
210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
211 pr_reg(" * WR FIFO DATA: 0x%x\n",
212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
213 pr_reg(" * RD FIFO ONLY: 0x%x\n",
214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
215 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n",
216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
217 pr_reg(" * FIFO IGNORE: 0x%x\n",
218 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
219 pr_reg(" * IRFSM: 0x%x\n",
220 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
221
222 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
223 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
224 pr_reg("* Contents = ");
225 for (i = 0; i < fifo_len; i++)
226 printk(KERN_CONT "%02x ",
227 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
228 printk(KERN_CONT "\n");
229 }
230
231 /* detect hardware features */
232 static int nvt_hw_detect(struct nvt_dev *nvt)
233 {
234 unsigned long flags;
235 u8 chip_major, chip_minor;
236 int ret = 0;
237
238 nvt_efm_enable(nvt);
239
240 /* Check if we're wired for the alternate EFER setup */
241 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
242 if (chip_major == 0xff) {
243 nvt->cr_efir = CR_EFIR2;
244 nvt->cr_efdr = CR_EFDR2;
245 nvt_efm_enable(nvt);
246 chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
247 }
248
249 chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
250 nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
251
252 if (chip_major != CHIP_ID_HIGH &&
253 (chip_minor != CHIP_ID_LOW || chip_minor != CHIP_ID_LOW2))
254 ret = -ENODEV;
255
256 nvt_efm_disable(nvt);
257
258 spin_lock_irqsave(&nvt->nvt_lock, flags);
259 nvt->chip_major = chip_major;
260 nvt->chip_minor = chip_minor;
261 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
262
263 return ret;
264 }
265
266 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
267 {
268 u8 val;
269
270 /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
271 val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
272 val &= OUTPUT_PIN_SEL_MASK;
273 val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
274 nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
275
276 /* Select CIR logical device and enable */
277 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
278 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
279
280 nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
281 nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
282
283 nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
284
285 nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
286 nvt->cir_addr, nvt->cir_irq);
287 }
288
289 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
290 {
291 /* Select ACPI logical device, enable it and CIR Wake */
292 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
293 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
294
295 /* Enable CIR Wake via PSOUT# (Pin60) */
296 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
297
298 /* enable cir interrupt of mouse/keyboard IRQ event */
299 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
300
301 /* enable pme interrupt of cir wakeup event */
302 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
303
304 /* Select CIR Wake logical device and enable */
305 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
306 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
307
308 nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
309 nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
310
311 nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
312
313 nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
314 nvt->cir_wake_addr, nvt->cir_wake_irq);
315 }
316
317 /* clear out the hardware's cir rx fifo */
318 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
319 {
320 u8 val;
321
322 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
323 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
324 }
325
326 /* clear out the hardware's cir wake rx fifo */
327 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
328 {
329 u8 val;
330
331 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
332 nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
333 CIR_WAKE_FIFOCON);
334 }
335
336 /* clear out the hardware's cir tx fifo */
337 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
338 {
339 u8 val;
340
341 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
342 nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
343 }
344
345 /* enable RX Trigger Level Reach and Packet End interrupts */
346 static void nvt_set_cir_iren(struct nvt_dev *nvt)
347 {
348 u8 iren;
349
350 iren = CIR_IREN_RTR | CIR_IREN_PE;
351 nvt_cir_reg_write(nvt, iren, CIR_IREN);
352 }
353
354 static void nvt_cir_regs_init(struct nvt_dev *nvt)
355 {
356 /* set sample limit count (PE interrupt raised when reached) */
357 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
358 nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
359
360 /* set fifo irq trigger levels */
361 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
362 CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
363
364 /*
365 * Enable TX and RX, specify carrier on = low, off = high, and set
366 * sample period (currently 50us)
367 */
368 nvt_cir_reg_write(nvt,
369 CIR_IRCON_TXEN | CIR_IRCON_RXEN |
370 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
371 CIR_IRCON);
372
373 /* clear hardware rx and tx fifos */
374 nvt_clear_cir_fifo(nvt);
375 nvt_clear_tx_fifo(nvt);
376
377 /* clear any and all stray interrupts */
378 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
379
380 /* and finally, enable interrupts */
381 nvt_set_cir_iren(nvt);
382 }
383
384 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
385 {
386 /* set number of bytes needed for wake key comparison (default 67) */
387 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFO_LEN, CIR_WAKE_FIFO_CMP_DEEP);
388
389 /* set tolerance/variance allowed per byte during wake compare */
390 nvt_cir_wake_reg_write(nvt, CIR_WAKE_CMP_TOLERANCE,
391 CIR_WAKE_FIFO_CMP_TOL);
392
393 /* set sample limit count (PE interrupt raised when reached) */
394 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_WAKE_SLCH);
395 nvt_cir_wake_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_WAKE_SLCL);
396
397 /* set cir wake fifo rx trigger level (currently 67) */
398 nvt_cir_wake_reg_write(nvt, CIR_WAKE_FIFOCON_RX_TRIGGER_LEV,
399 CIR_WAKE_FIFOCON);
400
401 /*
402 * Enable TX and RX, specific carrier on = low, off = high, and set
403 * sample period (currently 50us)
404 */
405 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
406 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
407 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
408 CIR_WAKE_IRCON);
409
410 /* clear cir wake rx fifo */
411 nvt_clear_cir_wake_fifo(nvt);
412
413 /* clear any and all stray interrupts */
414 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
415 }
416
417 static void nvt_enable_wake(struct nvt_dev *nvt)
418 {
419 nvt_efm_enable(nvt);
420
421 nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
422 nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
423 nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
424 nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
425
426 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
427 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
428
429 nvt_efm_disable(nvt);
430
431 nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
432 CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
433 CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
434 CIR_WAKE_IRCON);
435 nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
436 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
437 }
438
439 /* rx carrier detect only works in learning mode, must be called w/nvt_lock */
440 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
441 {
442 u32 count, carrier, duration = 0;
443 int i;
444
445 count = nvt_cir_reg_read(nvt, CIR_FCCL) |
446 nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
447
448 for (i = 0; i < nvt->pkts; i++) {
449 if (nvt->buf[i] & BUF_PULSE_BIT)
450 duration += nvt->buf[i] & BUF_LEN_MASK;
451 }
452
453 duration *= SAMPLE_PERIOD;
454
455 if (!count || !duration) {
456 nvt_pr(KERN_NOTICE, "Unable to determine carrier! (c:%u, d:%u)",
457 count, duration);
458 return 0;
459 }
460
461 carrier = (count * 1000000) / duration;
462
463 if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
464 nvt_dbg("WTF? Carrier frequency out of range!");
465
466 nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
467 carrier, count, duration);
468
469 return carrier;
470 }
471
472 /*
473 * set carrier frequency
474 *
475 * set carrier on 2 registers: CP & CC
476 * always set CP as 0x81
477 * set CC by SPEC, CC = 3MHz/carrier - 1
478 */
479 static int nvt_set_tx_carrier(void *data, u32 carrier)
480 {
481 struct nvt_dev *nvt = data;
482 u16 val;
483
484 nvt_cir_reg_write(nvt, 1, CIR_CP);
485 val = 3000000 / (carrier) - 1;
486 nvt_cir_reg_write(nvt, val & 0xff, CIR_CC);
487
488 nvt_dbg("cp: 0x%x cc: 0x%x\n",
489 nvt_cir_reg_read(nvt, CIR_CP), nvt_cir_reg_read(nvt, CIR_CC));
490
491 return 0;
492 }
493
494 /*
495 * nvt_tx_ir
496 *
497 * 1) clean TX fifo first (handled by AP)
498 * 2) copy data from user space
499 * 3) disable RX interrupts, enable TX interrupts: TTR & TFU
500 * 4) send 9 packets to TX FIFO to open TTR
501 * in interrupt_handler:
502 * 5) send all data out
503 * go back to write():
504 * 6) disable TX interrupts, re-enable RX interupts
505 *
506 * The key problem of this function is user space data may larger than
507 * driver's data buf length. So nvt_tx_ir() will only copy TX_BUF_LEN data to
508 * buf, and keep current copied data buf num in cur_buf_num. But driver's buf
509 * number may larger than TXFCONT (0xff). So in interrupt_handler, it has to
510 * set TXFCONT as 0xff, until buf_count less than 0xff.
511 */
512 static int nvt_tx_ir(void *priv, int *txbuf, u32 n)
513 {
514 struct nvt_dev *nvt = priv;
515 unsigned long flags;
516 size_t cur_count;
517 unsigned int i;
518 u8 iren;
519 int ret;
520
521 spin_lock_irqsave(&nvt->tx.lock, flags);
522
523 if (n >= TX_BUF_LEN) {
524 nvt->tx.buf_count = cur_count = TX_BUF_LEN;
525 ret = TX_BUF_LEN;
526 } else {
527 nvt->tx.buf_count = cur_count = n;
528 ret = n;
529 }
530
531 memcpy(nvt->tx.buf, txbuf, nvt->tx.buf_count);
532
533 nvt->tx.cur_buf_num = 0;
534
535 /* save currently enabled interrupts */
536 iren = nvt_cir_reg_read(nvt, CIR_IREN);
537
538 /* now disable all interrupts, save TFU & TTR */
539 nvt_cir_reg_write(nvt, CIR_IREN_TFU | CIR_IREN_TTR, CIR_IREN);
540
541 nvt->tx.tx_state = ST_TX_REPLY;
542
543 nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV_8 |
544 CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
545
546 /* trigger TTR interrupt by writing out ones, (yes, it's ugly) */
547 for (i = 0; i < 9; i++)
548 nvt_cir_reg_write(nvt, 0x01, CIR_STXFIFO);
549
550 spin_unlock_irqrestore(&nvt->tx.lock, flags);
551
552 wait_event(nvt->tx.queue, nvt->tx.tx_state == ST_TX_REQUEST);
553
554 spin_lock_irqsave(&nvt->tx.lock, flags);
555 nvt->tx.tx_state = ST_TX_NONE;
556 spin_unlock_irqrestore(&nvt->tx.lock, flags);
557
558 /* restore enabled interrupts to prior state */
559 nvt_cir_reg_write(nvt, iren, CIR_IREN);
560
561 return ret;
562 }
563
564 /* dump contents of the last rx buffer we got from the hw rx fifo */
565 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
566 {
567 int i;
568
569 printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
570 for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
571 printk(KERN_CONT "0x%02x ", nvt->buf[i]);
572 printk(KERN_CONT "\n");
573 }
574
575 /*
576 * Process raw data in rx driver buffer, store it in raw IR event kfifo,
577 * trigger decode when appropriate.
578 *
579 * We get IR data samples one byte at a time. If the msb is set, its a pulse,
580 * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
581 * (default 50us) intervals for that pulse/space. A discrete signal is
582 * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
583 * to signal more IR coming (repeats) or end of IR, respectively. We store
584 * sample data in the raw event kfifo until we see 0x7<something> (except f)
585 * or 0x80, at which time, we trigger a decode operation.
586 */
587 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
588 {
589 struct ir_raw_event rawir = { .pulse = false, .duration = 0 };
590 unsigned int count;
591 u32 carrier;
592 u8 sample;
593 int i;
594
595 nvt_dbg_verbose("%s firing", __func__);
596
597 if (debug)
598 nvt_dump_rx_buf(nvt);
599
600 if (nvt->carrier_detect_enabled)
601 carrier = nvt_rx_carrier_detect(nvt);
602
603 count = nvt->pkts;
604 nvt_dbg_verbose("Processing buffer of len %d", count);
605
606 for (i = 0; i < count; i++) {
607 nvt->pkts--;
608 sample = nvt->buf[i];
609
610 rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
611 rawir.duration = (sample & BUF_LEN_MASK)
612 * SAMPLE_PERIOD * 1000;
613
614 if ((sample & BUF_LEN_MASK) == BUF_LEN_MASK) {
615 if (nvt->rawir.pulse == rawir.pulse)
616 nvt->rawir.duration += rawir.duration;
617 else {
618 nvt->rawir.duration = rawir.duration;
619 nvt->rawir.pulse = rawir.pulse;
620 }
621 continue;
622 }
623
624 rawir.duration += nvt->rawir.duration;
625 nvt->rawir.duration = 0;
626 nvt->rawir.pulse = rawir.pulse;
627
628 if (sample == BUF_PULSE_BIT)
629 rawir.pulse = false;
630
631 if (rawir.duration) {
632 nvt_dbg("Storing %s with duration %d",
633 rawir.pulse ? "pulse" : "space",
634 rawir.duration);
635
636 ir_raw_event_store(nvt->rdev, &rawir);
637 }
638
639 /*
640 * BUF_PULSE_BIT indicates end of IR data, BUF_REPEAT_BYTE
641 * indicates end of IR signal, but new data incoming. In both
642 * cases, it means we're ready to call ir_raw_event_handle
643 */
644 if (sample == BUF_PULSE_BIT || ((sample != BUF_LEN_MASK) &&
645 (sample & BUF_REPEAT_MASK) == BUF_REPEAT_BYTE))
646 ir_raw_event_handle(nvt->rdev);
647 }
648
649 if (nvt->pkts) {
650 nvt_dbg("Odd, pkts should be 0 now... (its %u)", nvt->pkts);
651 nvt->pkts = 0;
652 }
653
654 nvt_dbg_verbose("%s done", __func__);
655 }
656
657 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
658 {
659 nvt_pr(KERN_WARNING, "RX FIFO overrun detected, flushing data!");
660
661 nvt->pkts = 0;
662 nvt_clear_cir_fifo(nvt);
663 ir_raw_event_reset(nvt->rdev);
664 }
665
666 /* copy data from hardware rx fifo into driver buffer */
667 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
668 {
669 unsigned long flags;
670 u8 fifocount, val;
671 unsigned int b_idx;
672 bool overrun = false;
673 int i;
674
675 /* Get count of how many bytes to read from RX FIFO */
676 fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
677 /* if we get 0xff, probably means the logical dev is disabled */
678 if (fifocount == 0xff)
679 return;
680 /* watch out for a fifo overrun condition */
681 else if (fifocount > RX_BUF_LEN) {
682 overrun = true;
683 fifocount = RX_BUF_LEN;
684 }
685
686 nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
687
688 spin_lock_irqsave(&nvt->nvt_lock, flags);
689
690 b_idx = nvt->pkts;
691
692 /* This should never happen, but lets check anyway... */
693 if (b_idx + fifocount > RX_BUF_LEN) {
694 nvt_process_rx_ir_data(nvt);
695 b_idx = 0;
696 }
697
698 /* Read fifocount bytes from CIR Sample RX FIFO register */
699 for (i = 0; i < fifocount; i++) {
700 val = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
701 nvt->buf[b_idx + i] = val;
702 }
703
704 nvt->pkts += fifocount;
705 nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
706
707 nvt_process_rx_ir_data(nvt);
708
709 if (overrun)
710 nvt_handle_rx_fifo_overrun(nvt);
711
712 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
713 }
714
715 static void nvt_cir_log_irqs(u8 status, u8 iren)
716 {
717 nvt_pr(KERN_INFO, "IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
718 status, iren,
719 status & CIR_IRSTS_RDR ? " RDR" : "",
720 status & CIR_IRSTS_RTR ? " RTR" : "",
721 status & CIR_IRSTS_PE ? " PE" : "",
722 status & CIR_IRSTS_RFO ? " RFO" : "",
723 status & CIR_IRSTS_TE ? " TE" : "",
724 status & CIR_IRSTS_TTR ? " TTR" : "",
725 status & CIR_IRSTS_TFU ? " TFU" : "",
726 status & CIR_IRSTS_GH ? " GH" : "",
727 status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
728 CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
729 CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
730 }
731
732 static bool nvt_cir_tx_inactive(struct nvt_dev *nvt)
733 {
734 unsigned long flags;
735 bool tx_inactive;
736 u8 tx_state;
737
738 spin_lock_irqsave(&nvt->tx.lock, flags);
739 tx_state = nvt->tx.tx_state;
740 spin_unlock_irqrestore(&nvt->tx.lock, flags);
741
742 tx_inactive = (tx_state == ST_TX_NONE);
743
744 return tx_inactive;
745 }
746
747 /* interrupt service routine for incoming and outgoing CIR data */
748 static irqreturn_t nvt_cir_isr(int irq, void *data)
749 {
750 struct nvt_dev *nvt = data;
751 u8 status, iren, cur_state;
752 unsigned long flags;
753
754 nvt_dbg_verbose("%s firing", __func__);
755
756 nvt_efm_enable(nvt);
757 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
758 nvt_efm_disable(nvt);
759
760 /*
761 * Get IR Status register contents. Write 1 to ack/clear
762 *
763 * bit: reg name - description
764 * 7: CIR_IRSTS_RDR - RX Data Ready
765 * 6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
766 * 5: CIR_IRSTS_PE - Packet End
767 * 4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
768 * 3: CIR_IRSTS_TE - TX FIFO Empty
769 * 2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
770 * 1: CIR_IRSTS_TFU - TX FIFO Underrun
771 * 0: CIR_IRSTS_GH - Min Length Detected
772 */
773 status = nvt_cir_reg_read(nvt, CIR_IRSTS);
774 if (!status) {
775 nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
776 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
777 return IRQ_RETVAL(IRQ_NONE);
778 }
779
780 /* ack/clear all irq flags we've got */
781 nvt_cir_reg_write(nvt, status, CIR_IRSTS);
782 nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
783
784 /* Interrupt may be shared with CIR Wake, bail if CIR not enabled */
785 iren = nvt_cir_reg_read(nvt, CIR_IREN);
786 if (!iren) {
787 nvt_dbg_verbose("%s exiting, CIR not enabled", __func__);
788 return IRQ_RETVAL(IRQ_NONE);
789 }
790
791 if (debug)
792 nvt_cir_log_irqs(status, iren);
793
794 if (status & CIR_IRSTS_RTR) {
795 /* FIXME: add code for study/learn mode */
796 /* We only do rx if not tx'ing */
797 if (nvt_cir_tx_inactive(nvt))
798 nvt_get_rx_ir_data(nvt);
799 }
800
801 if (status & CIR_IRSTS_PE) {
802 if (nvt_cir_tx_inactive(nvt))
803 nvt_get_rx_ir_data(nvt);
804
805 spin_lock_irqsave(&nvt->nvt_lock, flags);
806
807 cur_state = nvt->study_state;
808
809 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
810
811 if (cur_state == ST_STUDY_NONE)
812 nvt_clear_cir_fifo(nvt);
813 }
814
815 if (status & CIR_IRSTS_TE)
816 nvt_clear_tx_fifo(nvt);
817
818 if (status & CIR_IRSTS_TTR) {
819 unsigned int pos, count;
820 u8 tmp;
821
822 spin_lock_irqsave(&nvt->tx.lock, flags);
823
824 pos = nvt->tx.cur_buf_num;
825 count = nvt->tx.buf_count;
826
827 /* Write data into the hardware tx fifo while pos < count */
828 if (pos < count) {
829 nvt_cir_reg_write(nvt, nvt->tx.buf[pos], CIR_STXFIFO);
830 nvt->tx.cur_buf_num++;
831 /* Disable TX FIFO Trigger Level Reach (TTR) interrupt */
832 } else {
833 tmp = nvt_cir_reg_read(nvt, CIR_IREN);
834 nvt_cir_reg_write(nvt, tmp & ~CIR_IREN_TTR, CIR_IREN);
835 }
836
837 spin_unlock_irqrestore(&nvt->tx.lock, flags);
838
839 }
840
841 if (status & CIR_IRSTS_TFU) {
842 spin_lock_irqsave(&nvt->tx.lock, flags);
843 if (nvt->tx.tx_state == ST_TX_REPLY) {
844 nvt->tx.tx_state = ST_TX_REQUEST;
845 wake_up(&nvt->tx.queue);
846 }
847 spin_unlock_irqrestore(&nvt->tx.lock, flags);
848 }
849
850 nvt_dbg_verbose("%s done", __func__);
851 return IRQ_RETVAL(IRQ_HANDLED);
852 }
853
854 /* Interrupt service routine for CIR Wake */
855 static irqreturn_t nvt_cir_wake_isr(int irq, void *data)
856 {
857 u8 status, iren, val;
858 struct nvt_dev *nvt = data;
859 unsigned long flags;
860
861 nvt_dbg_wake("%s firing", __func__);
862
863 status = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS);
864 if (!status)
865 return IRQ_RETVAL(IRQ_NONE);
866
867 if (status & CIR_WAKE_IRSTS_IR_PENDING)
868 nvt_clear_cir_wake_fifo(nvt);
869
870 nvt_cir_wake_reg_write(nvt, status, CIR_WAKE_IRSTS);
871 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IRSTS);
872
873 /* Interrupt may be shared with CIR, bail if Wake not enabled */
874 iren = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN);
875 if (!iren) {
876 nvt_dbg_wake("%s exiting, wake not enabled", __func__);
877 return IRQ_RETVAL(IRQ_HANDLED);
878 }
879
880 if ((status & CIR_WAKE_IRSTS_PE) &&
881 (nvt->wake_state == ST_WAKE_START)) {
882 while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)) {
883 val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
884 nvt_dbg("setting wake up key: 0x%x", val);
885 }
886
887 nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
888 spin_lock_irqsave(&nvt->nvt_lock, flags);
889 nvt->wake_state = ST_WAKE_FINISH;
890 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
891 }
892
893 nvt_dbg_wake("%s done", __func__);
894 return IRQ_RETVAL(IRQ_HANDLED);
895 }
896
897 static void nvt_enable_cir(struct nvt_dev *nvt)
898 {
899 /* set function enable flags */
900 nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
901 CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
902 CIR_IRCON);
903
904 nvt_efm_enable(nvt);
905
906 /* enable the CIR logical device */
907 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
908 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
909
910 nvt_efm_disable(nvt);
911
912 /* clear all pending interrupts */
913 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
914
915 /* enable interrupts */
916 nvt_set_cir_iren(nvt);
917 }
918
919 static void nvt_disable_cir(struct nvt_dev *nvt)
920 {
921 /* disable CIR interrupts */
922 nvt_cir_reg_write(nvt, 0, CIR_IREN);
923
924 /* clear any and all pending interrupts */
925 nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
926
927 /* clear all function enable flags */
928 nvt_cir_reg_write(nvt, 0, CIR_IRCON);
929
930 /* clear hardware rx and tx fifos */
931 nvt_clear_cir_fifo(nvt);
932 nvt_clear_tx_fifo(nvt);
933
934 nvt_efm_enable(nvt);
935
936 /* disable the CIR logical device */
937 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
938 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
939
940 nvt_efm_disable(nvt);
941 }
942
943 static int nvt_open(void *data)
944 {
945 struct nvt_dev *nvt = (struct nvt_dev *)data;
946 unsigned long flags;
947
948 spin_lock_irqsave(&nvt->nvt_lock, flags);
949 nvt->in_use = true;
950 nvt_enable_cir(nvt);
951 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
952
953 return 0;
954 }
955
956 static void nvt_close(void *data)
957 {
958 struct nvt_dev *nvt = (struct nvt_dev *)data;
959 unsigned long flags;
960
961 spin_lock_irqsave(&nvt->nvt_lock, flags);
962 nvt->in_use = false;
963 nvt_disable_cir(nvt);
964 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
965 }
966
967 /* Allocate memory, probe hardware, and initialize everything */
968 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
969 {
970 struct nvt_dev *nvt = NULL;
971 struct input_dev *rdev = NULL;
972 struct ir_dev_props *props = NULL;
973 int ret = -ENOMEM;
974
975 nvt = kzalloc(sizeof(struct nvt_dev), GFP_KERNEL);
976 if (!nvt)
977 return ret;
978
979 props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL);
980 if (!props)
981 goto failure;
982
983 /* input device for IR remote (and tx) */
984 rdev = input_allocate_device();
985 if (!rdev)
986 goto failure;
987
988 ret = -ENODEV;
989 /* validate pnp resources */
990 if (!pnp_port_valid(pdev, 0) ||
991 pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
992 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
993 goto failure;
994 }
995
996 if (!pnp_irq_valid(pdev, 0)) {
997 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
998 goto failure;
999 }
1000
1001 if (!pnp_port_valid(pdev, 1) ||
1002 pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
1003 dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
1004 goto failure;
1005 }
1006
1007 nvt->cir_addr = pnp_port_start(pdev, 0);
1008 nvt->cir_irq = pnp_irq(pdev, 0);
1009
1010 nvt->cir_wake_addr = pnp_port_start(pdev, 1);
1011 /* irq is always shared between cir and cir wake */
1012 nvt->cir_wake_irq = nvt->cir_irq;
1013
1014 nvt->cr_efir = CR_EFIR;
1015 nvt->cr_efdr = CR_EFDR;
1016
1017 spin_lock_init(&nvt->nvt_lock);
1018 spin_lock_init(&nvt->tx.lock);
1019
1020 ret = -EBUSY;
1021 /* now claim resources */
1022 if (!request_region(nvt->cir_addr,
1023 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1024 goto failure;
1025
1026 if (request_irq(nvt->cir_irq, nvt_cir_isr, IRQF_SHARED,
1027 NVT_DRIVER_NAME, (void *)nvt))
1028 goto failure;
1029
1030 if (!request_region(nvt->cir_wake_addr,
1031 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1032 goto failure;
1033
1034 if (request_irq(nvt->cir_wake_irq, nvt_cir_wake_isr, IRQF_SHARED,
1035 NVT_DRIVER_NAME, (void *)nvt))
1036 goto failure;
1037
1038 pnp_set_drvdata(pdev, nvt);
1039 nvt->pdev = pdev;
1040
1041 init_waitqueue_head(&nvt->tx.queue);
1042
1043 ret = nvt_hw_detect(nvt);
1044 if (ret)
1045 goto failure;
1046
1047 /* Initialize CIR & CIR Wake Logical Devices */
1048 nvt_efm_enable(nvt);
1049 nvt_cir_ldev_init(nvt);
1050 nvt_cir_wake_ldev_init(nvt);
1051 nvt_efm_disable(nvt);
1052
1053 /* Initialize CIR & CIR Wake Config Registers */
1054 nvt_cir_regs_init(nvt);
1055 nvt_cir_wake_regs_init(nvt);
1056
1057 /* Set up ir-core props */
1058 props->priv = nvt;
1059 props->driver_type = RC_DRIVER_IR_RAW;
1060 props->allowed_protos = IR_TYPE_ALL;
1061 props->open = nvt_open;
1062 props->close = nvt_close;
1063 #if 0
1064 props->min_timeout = XYZ;
1065 props->max_timeout = XYZ;
1066 props->timeout = XYZ;
1067 /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1068 props->rx_resolution = XYZ;
1069
1070 /* tx bits */
1071 props->tx_resolution = XYZ;
1072 #endif
1073 props->tx_ir = nvt_tx_ir;
1074 props->s_tx_carrier = nvt_set_tx_carrier;
1075
1076 rdev->name = "Nuvoton w836x7hg Infrared Remote Transceiver";
1077 rdev->id.bustype = BUS_HOST;
1078 rdev->id.vendor = PCI_VENDOR_ID_WINBOND2;
1079 rdev->id.product = nvt->chip_major;
1080 rdev->id.version = nvt->chip_minor;
1081
1082 nvt->props = props;
1083 nvt->rdev = rdev;
1084
1085 device_set_wakeup_capable(&pdev->dev, 1);
1086 device_set_wakeup_enable(&pdev->dev, 1);
1087
1088 ret = ir_input_register(rdev, RC_MAP_RC6_MCE, props, NVT_DRIVER_NAME);
1089 if (ret)
1090 goto failure;
1091
1092 nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1093 if (debug) {
1094 cir_dump_regs(nvt);
1095 cir_wake_dump_regs(nvt);
1096 }
1097
1098 return 0;
1099
1100 failure:
1101 if (nvt->cir_irq)
1102 free_irq(nvt->cir_irq, nvt);
1103 if (nvt->cir_addr)
1104 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1105
1106 if (nvt->cir_wake_irq)
1107 free_irq(nvt->cir_wake_irq, nvt);
1108 if (nvt->cir_wake_addr)
1109 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1110
1111 input_free_device(rdev);
1112 kfree(props);
1113 kfree(nvt);
1114
1115 return ret;
1116 }
1117
1118 static void __devexit nvt_remove(struct pnp_dev *pdev)
1119 {
1120 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1121 unsigned long flags;
1122
1123 spin_lock_irqsave(&nvt->nvt_lock, flags);
1124 /* disable CIR */
1125 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1126 nvt_disable_cir(nvt);
1127 /* enable CIR Wake (for IR power-on) */
1128 nvt_enable_wake(nvt);
1129 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1130
1131 /* free resources */
1132 free_irq(nvt->cir_irq, nvt);
1133 free_irq(nvt->cir_wake_irq, nvt);
1134 release_region(nvt->cir_addr, CIR_IOREG_LENGTH);
1135 release_region(nvt->cir_wake_addr, CIR_IOREG_LENGTH);
1136
1137 ir_input_unregister(nvt->rdev);
1138
1139 kfree(nvt->props);
1140 kfree(nvt);
1141 }
1142
1143 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1144 {
1145 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1146 unsigned long flags;
1147
1148 nvt_dbg("%s called", __func__);
1149
1150 /* zero out misc state tracking */
1151 spin_lock_irqsave(&nvt->nvt_lock, flags);
1152 nvt->study_state = ST_STUDY_NONE;
1153 nvt->wake_state = ST_WAKE_NONE;
1154 spin_unlock_irqrestore(&nvt->nvt_lock, flags);
1155
1156 spin_lock_irqsave(&nvt->tx.lock, flags);
1157 nvt->tx.tx_state = ST_TX_NONE;
1158 spin_unlock_irqrestore(&nvt->tx.lock, flags);
1159
1160 /* disable all CIR interrupts */
1161 nvt_cir_reg_write(nvt, 0, CIR_IREN);
1162
1163 nvt_efm_enable(nvt);
1164
1165 /* disable cir logical dev */
1166 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1167 nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
1168
1169 nvt_efm_disable(nvt);
1170
1171 /* make sure wake is enabled */
1172 nvt_enable_wake(nvt);
1173
1174 return 0;
1175 }
1176
1177 static int nvt_resume(struct pnp_dev *pdev)
1178 {
1179 int ret = 0;
1180 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1181
1182 nvt_dbg("%s called", __func__);
1183
1184 /* open interrupt */
1185 nvt_set_cir_iren(nvt);
1186
1187 /* Enable CIR logical device */
1188 nvt_efm_enable(nvt);
1189 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
1190 nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
1191
1192 nvt_efm_disable(nvt);
1193
1194 nvt_cir_regs_init(nvt);
1195 nvt_cir_wake_regs_init(nvt);
1196
1197 return ret;
1198 }
1199
1200 static void nvt_shutdown(struct pnp_dev *pdev)
1201 {
1202 struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1203 nvt_enable_wake(nvt);
1204 }
1205
1206 static const struct pnp_device_id nvt_ids[] = {
1207 { "WEC0530", 0 }, /* CIR */
1208 { "NTN0530", 0 }, /* CIR for new chip's pnp id*/
1209 { "", 0 },
1210 };
1211
1212 static struct pnp_driver nvt_driver = {
1213 .name = NVT_DRIVER_NAME,
1214 .id_table = nvt_ids,
1215 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1216 .probe = nvt_probe,
1217 .remove = __devexit_p(nvt_remove),
1218 .suspend = nvt_suspend,
1219 .resume = nvt_resume,
1220 .shutdown = nvt_shutdown,
1221 };
1222
1223 int nvt_init(void)
1224 {
1225 return pnp_register_driver(&nvt_driver);
1226 }
1227
1228 void nvt_exit(void)
1229 {
1230 pnp_unregister_driver(&nvt_driver);
1231 }
1232
1233 module_param(debug, int, S_IRUGO | S_IWUSR);
1234 MODULE_PARM_DESC(debug, "Enable debugging output");
1235
1236 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1237 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1238
1239 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1240 MODULE_LICENSE("GPL");
1241
1242 module_init(nvt_init);
1243 module_exit(nvt_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree