2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug
;
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
36 struct drm_display_mode
*mode
);
38 static uint32_t radeon_encoder_clones(struct drm_encoder
*encoder
)
40 struct drm_device
*dev
= encoder
->dev
;
41 struct radeon_device
*rdev
= dev
->dev_private
;
42 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
43 struct drm_encoder
*clone_encoder
;
44 uint32_t index_mask
= 0;
47 /* DIG routing gets problematic */
48 if (rdev
->family
>= CHIP_R600
)
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD_SUPPORT
)
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)
58 list_for_each_entry(clone_encoder
, &dev
->mode_config
.encoder_list
, head
) {
59 struct radeon_encoder
*radeon_clone
= to_radeon_encoder(clone_encoder
);
62 if (clone_encoder
== encoder
)
64 if (radeon_clone
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
66 if (radeon_clone
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)
69 index_mask
|= (1 << count
);
74 void radeon_setup_encoder_clones(struct drm_device
*dev
)
76 struct drm_encoder
*encoder
;
78 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
79 encoder
->possible_clones
= radeon_encoder_clones(encoder
);
84 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
, uint8_t dac
)
86 struct radeon_device
*rdev
= dev
->dev_private
;
89 switch (supported_device
) {
90 case ATOM_DEVICE_CRT1_SUPPORT
:
91 case ATOM_DEVICE_TV1_SUPPORT
:
92 case ATOM_DEVICE_TV2_SUPPORT
:
93 case ATOM_DEVICE_CRT2_SUPPORT
:
94 case ATOM_DEVICE_CV_SUPPORT
:
97 if ((rdev
->family
== CHIP_RS300
) ||
98 (rdev
->family
== CHIP_RS400
) ||
99 (rdev
->family
== CHIP_RS480
))
100 ret
= ENCODER_INTERNAL_DAC2_ENUM_ID1
;
101 else if (ASIC_IS_AVIVO(rdev
))
102 ret
= ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1
;
104 ret
= ENCODER_INTERNAL_DAC1_ENUM_ID1
;
107 if (ASIC_IS_AVIVO(rdev
))
108 ret
= ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1
;
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
113 ret
= ENCODER_INTERNAL_DAC2_ENUM_ID1
;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev
))
118 ret
= ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1
;
120 ret
= ENCODER_INTERNAL_DVO1_ENUM_ID1
;
124 case ATOM_DEVICE_LCD1_SUPPORT
:
125 if (ASIC_IS_AVIVO(rdev
))
126 ret
= ENCODER_INTERNAL_LVTM1_ENUM_ID1
;
128 ret
= ENCODER_INTERNAL_LVDS_ENUM_ID1
;
130 case ATOM_DEVICE_DFP1_SUPPORT
:
131 if ((rdev
->family
== CHIP_RS300
) ||
132 (rdev
->family
== CHIP_RS400
) ||
133 (rdev
->family
== CHIP_RS480
))
134 ret
= ENCODER_INTERNAL_DVO1_ENUM_ID1
;
135 else if (ASIC_IS_AVIVO(rdev
))
136 ret
= ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1
;
138 ret
= ENCODER_INTERNAL_TMDS1_ENUM_ID1
;
140 case ATOM_DEVICE_LCD2_SUPPORT
:
141 case ATOM_DEVICE_DFP2_SUPPORT
:
142 if ((rdev
->family
== CHIP_RS600
) ||
143 (rdev
->family
== CHIP_RS690
) ||
144 (rdev
->family
== CHIP_RS740
))
145 ret
= ENCODER_INTERNAL_DDI_ENUM_ID1
;
146 else if (ASIC_IS_AVIVO(rdev
))
147 ret
= ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1
;
149 ret
= ENCODER_INTERNAL_DVO1_ENUM_ID1
;
151 case ATOM_DEVICE_DFP3_SUPPORT
:
152 ret
= ENCODER_INTERNAL_LVTM1_ENUM_ID1
;
159 static inline bool radeon_encoder_is_digital(struct drm_encoder
*encoder
)
161 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
162 switch (radeon_encoder
->encoder_id
) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
181 radeon_link_encoder_connector(struct drm_device
*dev
)
183 struct drm_connector
*connector
;
184 struct radeon_connector
*radeon_connector
;
185 struct drm_encoder
*encoder
;
186 struct radeon_encoder
*radeon_encoder
;
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
190 radeon_connector
= to_radeon_connector(connector
);
191 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
192 radeon_encoder
= to_radeon_encoder(encoder
);
193 if (radeon_encoder
->devices
& radeon_connector
->devices
)
194 drm_mode_connector_attach_encoder(connector
, encoder
);
199 void radeon_encoder_set_active_device(struct drm_encoder
*encoder
)
201 struct drm_device
*dev
= encoder
->dev
;
202 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
203 struct drm_connector
*connector
;
205 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
206 if (connector
->encoder
== encoder
) {
207 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
208 radeon_encoder
->active_device
= radeon_encoder
->devices
& radeon_connector
->devices
;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder
->active_device
, radeon_encoder
->devices
,
211 radeon_connector
->devices
, encoder
->encoder_type
);
216 struct drm_connector
*
217 radeon_get_connector_for_encoder(struct drm_encoder
*encoder
)
219 struct drm_device
*dev
= encoder
->dev
;
220 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
221 struct drm_connector
*connector
;
222 struct radeon_connector
*radeon_connector
;
224 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
225 radeon_connector
= to_radeon_connector(connector
);
226 if (radeon_encoder
->active_device
& radeon_connector
->devices
)
232 struct drm_encoder
*radeon_atom_get_external_encoder(struct drm_encoder
*encoder
)
234 struct drm_device
*dev
= encoder
->dev
;
235 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
236 struct drm_encoder
*other_encoder
;
237 struct radeon_encoder
*other_radeon_encoder
;
239 if (radeon_encoder
->is_ext_encoder
)
242 list_for_each_entry(other_encoder
, &dev
->mode_config
.encoder_list
, head
) {
243 if (other_encoder
== encoder
)
245 other_radeon_encoder
= to_radeon_encoder(other_encoder
);
246 if (other_radeon_encoder
->is_ext_encoder
&&
247 (radeon_encoder
->devices
& other_radeon_encoder
->devices
))
248 return other_encoder
;
253 void radeon_panel_mode_fixup(struct drm_encoder
*encoder
,
254 struct drm_display_mode
*adjusted_mode
)
256 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
257 struct drm_device
*dev
= encoder
->dev
;
258 struct radeon_device
*rdev
= dev
->dev_private
;
259 struct drm_display_mode
*native_mode
= &radeon_encoder
->native_mode
;
260 unsigned hblank
= native_mode
->htotal
- native_mode
->hdisplay
;
261 unsigned vblank
= native_mode
->vtotal
- native_mode
->vdisplay
;
262 unsigned hover
= native_mode
->hsync_start
- native_mode
->hdisplay
;
263 unsigned vover
= native_mode
->vsync_start
- native_mode
->vdisplay
;
264 unsigned hsync_width
= native_mode
->hsync_end
- native_mode
->hsync_start
;
265 unsigned vsync_width
= native_mode
->vsync_end
- native_mode
->vsync_start
;
267 adjusted_mode
->clock
= native_mode
->clock
;
268 adjusted_mode
->flags
= native_mode
->flags
;
270 if (ASIC_IS_AVIVO(rdev
)) {
271 adjusted_mode
->hdisplay
= native_mode
->hdisplay
;
272 adjusted_mode
->vdisplay
= native_mode
->vdisplay
;
275 adjusted_mode
->htotal
= native_mode
->hdisplay
+ hblank
;
276 adjusted_mode
->hsync_start
= native_mode
->hdisplay
+ hover
;
277 adjusted_mode
->hsync_end
= adjusted_mode
->hsync_start
+ hsync_width
;
279 adjusted_mode
->vtotal
= native_mode
->vdisplay
+ vblank
;
280 adjusted_mode
->vsync_start
= native_mode
->vdisplay
+ vover
;
281 adjusted_mode
->vsync_end
= adjusted_mode
->vsync_start
+ vsync_width
;
283 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
285 if (ASIC_IS_AVIVO(rdev
)) {
286 adjusted_mode
->crtc_hdisplay
= native_mode
->hdisplay
;
287 adjusted_mode
->crtc_vdisplay
= native_mode
->vdisplay
;
290 adjusted_mode
->crtc_htotal
= adjusted_mode
->crtc_hdisplay
+ hblank
;
291 adjusted_mode
->crtc_hsync_start
= adjusted_mode
->crtc_hdisplay
+ hover
;
292 adjusted_mode
->crtc_hsync_end
= adjusted_mode
->crtc_hsync_start
+ hsync_width
;
294 adjusted_mode
->crtc_vtotal
= adjusted_mode
->crtc_vdisplay
+ vblank
;
295 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ vover
;
296 adjusted_mode
->crtc_vsync_end
= adjusted_mode
->crtc_vsync_start
+ vsync_width
;
300 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
301 struct drm_display_mode
*mode
,
302 struct drm_display_mode
*adjusted_mode
)
304 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
305 struct drm_device
*dev
= encoder
->dev
;
306 struct radeon_device
*rdev
= dev
->dev_private
;
308 /* set the active encoder to connector routing */
309 radeon_encoder_set_active_device(encoder
);
310 drm_mode_set_crtcinfo(adjusted_mode
, 0);
313 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
314 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
315 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
317 /* get the native mode for LVDS */
318 if (radeon_encoder
->active_device
& (ATOM_DEVICE_LCD_SUPPORT
))
319 radeon_panel_mode_fixup(encoder
, adjusted_mode
);
321 /* get the native mode for TV */
322 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)) {
323 struct radeon_encoder_atom_dac
*tv_dac
= radeon_encoder
->enc_priv
;
325 if (tv_dac
->tv_std
== TV_STD_NTSC
||
326 tv_dac
->tv_std
== TV_STD_NTSC_J
||
327 tv_dac
->tv_std
== TV_STD_PAL_M
)
328 radeon_atom_get_tv_timings(rdev
, 0, adjusted_mode
);
330 radeon_atom_get_tv_timings(rdev
, 1, adjusted_mode
);
334 if (ASIC_IS_DCE3(rdev
) &&
335 (radeon_encoder
->active_device
& (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
))) {
336 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
337 radeon_dp_set_link_config(connector
, mode
);
344 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
346 struct drm_device
*dev
= encoder
->dev
;
347 struct radeon_device
*rdev
= dev
->dev_private
;
348 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
349 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
351 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
353 memset(&args
, 0, sizeof(args
));
355 switch (radeon_encoder
->encoder_id
) {
356 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
358 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
360 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
362 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
366 args
.ucAction
= action
;
368 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
369 args
.ucDacStandard
= ATOM_DAC1_PS2
;
370 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
371 args
.ucDacStandard
= ATOM_DAC1_CV
;
373 switch (dac_info
->tv_std
) {
376 case TV_STD_SCART_PAL
:
379 args
.ucDacStandard
= ATOM_DAC1_PAL
;
385 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
389 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
391 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
396 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
398 struct drm_device
*dev
= encoder
->dev
;
399 struct radeon_device
*rdev
= dev
->dev_private
;
400 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
401 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
403 struct radeon_encoder_atom_dac
*dac_info
= radeon_encoder
->enc_priv
;
405 memset(&args
, 0, sizeof(args
));
407 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
409 args
.sTVEncoder
.ucAction
= action
;
411 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
412 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
414 switch (dac_info
->tv_std
) {
416 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
419 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
422 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
425 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
428 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
430 case TV_STD_SCART_PAL
:
431 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
434 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
437 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
440 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
445 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
447 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
451 union dvo_encoder_control
{
452 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds
;
453 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo
;
454 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3
;
458 atombios_dvo_setup(struct drm_encoder
*encoder
, int action
)
460 struct drm_device
*dev
= encoder
->dev
;
461 struct radeon_device
*rdev
= dev
->dev_private
;
462 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
463 union dvo_encoder_control args
;
464 int index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
466 memset(&args
, 0, sizeof(args
));
468 if (ASIC_IS_DCE3(rdev
)) {
470 args
.dvo_v3
.ucAction
= action
;
471 args
.dvo_v3
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
472 args
.dvo_v3
.ucDVOConfig
= 0; /* XXX */
473 } else if (ASIC_IS_DCE2(rdev
)) {
474 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
475 args
.dvo
.sDVOEncoder
.ucAction
= action
;
476 args
.dvo
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
477 /* DFP1, CRT1, TV1 depending on the type of port */
478 args
.dvo
.sDVOEncoder
.ucDeviceType
= ATOM_DEVICE_DFP1_INDEX
;
480 if (radeon_encoder
->pixel_clock
> 165000)
481 args
.dvo
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
|= PANEL_ENCODER_MISC_DUAL
;
484 args
.ext_tmds
.sXTmdsEncoder
.ucEnable
= action
;
486 if (radeon_encoder
->pixel_clock
> 165000)
487 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
489 /*if (pScrn->rgbBits == 8)*/
490 args
.ext_tmds
.sXTmdsEncoder
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
493 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
496 union lvds_encoder_control
{
497 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
498 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
502 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
504 struct drm_device
*dev
= encoder
->dev
;
505 struct radeon_device
*rdev
= dev
->dev_private
;
506 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
507 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
508 union lvds_encoder_control args
;
510 int hdmi_detected
= 0;
516 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
519 memset(&args
, 0, sizeof(args
));
521 switch (radeon_encoder
->encoder_id
) {
522 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
523 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
525 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
527 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
529 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
530 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
531 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
533 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
537 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
546 args
.v1
.ucAction
= action
;
548 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
549 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
550 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
551 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
552 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
553 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
554 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
557 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
558 if (radeon_encoder
->pixel_clock
> 165000)
559 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
560 /*if (pScrn->rgbBits == 8) */
561 args
.v1
.ucMisc
|= ATOM_PANEL_MISC_888RGB
;
567 args
.v2
.ucAction
= action
;
569 if (dig
->coherent_mode
)
570 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
573 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
574 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
575 args
.v2
.ucTruncate
= 0;
576 args
.v2
.ucSpatial
= 0;
577 args
.v2
.ucTemporal
= 0;
579 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
580 if (dig
->lcd_misc
& ATOM_PANEL_MISC_DUAL
)
581 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
582 if (dig
->lcd_misc
& ATOM_PANEL_MISC_SPATIAL
) {
583 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
584 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
585 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
587 if (dig
->lcd_misc
& ATOM_PANEL_MISC_TEMPORAL
) {
588 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
589 if (dig
->lcd_misc
& ATOM_PANEL_MISC_888RGB
)
590 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
591 if (((dig
->lcd_misc
>> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT
) & 0x3) == 2)
592 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
596 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
597 if (radeon_encoder
->pixel_clock
> 165000)
598 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
602 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
607 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
611 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
615 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
617 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
618 struct drm_device
*dev
= encoder
->dev
;
619 struct radeon_device
*rdev
= dev
->dev_private
;
620 struct drm_connector
*connector
;
621 struct radeon_connector
*radeon_connector
;
622 struct radeon_connector_atom_dig
*dig_connector
;
624 connector
= radeon_get_connector_for_encoder(encoder
);
626 switch (radeon_encoder
->encoder_id
) {
627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
632 return ATOM_ENCODER_MODE_DVI
;
633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
636 return ATOM_ENCODER_MODE_CRT
;
639 radeon_connector
= to_radeon_connector(connector
);
641 switch (connector
->connector_type
) {
642 case DRM_MODE_CONNECTOR_DVII
:
643 case DRM_MODE_CONNECTOR_HDMIB
: /* HDMI-B is basically DL-DVI; analog works fine */
644 if (drm_detect_monitor_audio(radeon_connector
->edid
) && radeon_audio
) {
646 if (ASIC_IS_DCE4(rdev
))
647 return ATOM_ENCODER_MODE_DVI
;
649 return ATOM_ENCODER_MODE_HDMI
;
650 } else if (radeon_connector
->use_digital
)
651 return ATOM_ENCODER_MODE_DVI
;
653 return ATOM_ENCODER_MODE_CRT
;
655 case DRM_MODE_CONNECTOR_DVID
:
656 case DRM_MODE_CONNECTOR_HDMIA
:
658 if (drm_detect_monitor_audio(radeon_connector
->edid
) && radeon_audio
) {
660 if (ASIC_IS_DCE4(rdev
))
661 return ATOM_ENCODER_MODE_DVI
;
663 return ATOM_ENCODER_MODE_HDMI
;
665 return ATOM_ENCODER_MODE_DVI
;
667 case DRM_MODE_CONNECTOR_LVDS
:
668 return ATOM_ENCODER_MODE_LVDS
;
670 case DRM_MODE_CONNECTOR_DisplayPort
:
671 dig_connector
= radeon_connector
->con_priv
;
672 if ((dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_DISPLAYPORT
) ||
673 (dig_connector
->dp_sink_type
== CONNECTOR_OBJECT_ID_eDP
))
674 return ATOM_ENCODER_MODE_DP
;
675 else if (drm_detect_monitor_audio(radeon_connector
->edid
) && radeon_audio
) {
677 if (ASIC_IS_DCE4(rdev
))
678 return ATOM_ENCODER_MODE_DVI
;
680 return ATOM_ENCODER_MODE_HDMI
;
682 return ATOM_ENCODER_MODE_DVI
;
684 case DRM_MODE_CONNECTOR_eDP
:
685 return ATOM_ENCODER_MODE_DP
;
686 case DRM_MODE_CONNECTOR_DVIA
:
687 case DRM_MODE_CONNECTOR_VGA
:
688 return ATOM_ENCODER_MODE_CRT
;
690 case DRM_MODE_CONNECTOR_Composite
:
691 case DRM_MODE_CONNECTOR_SVIDEO
:
692 case DRM_MODE_CONNECTOR_9PinDIN
:
694 return ATOM_ENCODER_MODE_TV
;
695 /*return ATOM_ENCODER_MODE_CV;*/
701 * DIG Encoder/Transmitter Setup
704 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
705 * Supports up to 3 digital outputs
706 * - 2 DIG encoder blocks.
707 * DIG1 can drive UNIPHY link A or link B
708 * DIG2 can drive UNIPHY link B or LVTMA
711 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
712 * Supports up to 5 digital outputs
713 * - 2 DIG encoder blocks.
714 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
717 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
718 * Supports up to 6 digital outputs
719 * - 6 DIG encoder blocks.
720 * - DIG to PHY mapping is hardcoded
721 * DIG1 drives UNIPHY0 link A, A+B
722 * DIG2 drives UNIPHY0 link B
723 * DIG3 drives UNIPHY1 link A, A+B
724 * DIG4 drives UNIPHY1 link B
725 * DIG5 drives UNIPHY2 link A, A+B
726 * DIG6 drives UNIPHY2 link B
729 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
730 * Supports up to 6 digital outputs
731 * - 2 DIG encoder blocks.
732 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
735 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
737 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
738 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
739 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
740 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
743 union dig_encoder_control
{
744 DIG_ENCODER_CONTROL_PS_ALLOCATION v1
;
745 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2
;
746 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3
;
747 DIG_ENCODER_CONTROL_PARAMETERS_V4 v4
;
751 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
)
753 struct drm_device
*dev
= encoder
->dev
;
754 struct radeon_device
*rdev
= dev
->dev_private
;
755 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
756 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
757 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
758 union dig_encoder_control args
;
762 int dp_lane_count
= 0;
763 int hpd_id
= RADEON_HPD_NONE
;
767 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
768 struct radeon_connector_atom_dig
*dig_connector
=
769 radeon_connector
->con_priv
;
771 dp_clock
= dig_connector
->dp_clock
;
772 dp_lane_count
= dig_connector
->dp_lane_count
;
773 hpd_id
= radeon_connector
->hpd
.hpd
;
774 bpc
= connector
->display_info
.bpc
;
777 /* no dig encoder assigned */
778 if (dig
->dig_encoder
== -1)
781 memset(&args
, 0, sizeof(args
));
783 if (ASIC_IS_DCE4(rdev
))
784 index
= GetIndexIntoMasterTable(COMMAND
, DIGxEncoderControl
);
786 if (dig
->dig_encoder
)
787 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
789 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
792 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
795 args
.v1
.ucAction
= action
;
796 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
797 args
.v1
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
799 if ((args
.v1
.ucEncoderMode
== ATOM_ENCODER_MODE_DP
) ||
800 (args
.v1
.ucEncoderMode
== ATOM_ENCODER_MODE_DP_MST
))
801 args
.v1
.ucLaneNum
= dp_lane_count
;
802 else if (radeon_encoder
->pixel_clock
> 165000)
803 args
.v1
.ucLaneNum
= 8;
805 args
.v1
.ucLaneNum
= 4;
807 if (ASIC_IS_DCE5(rdev
)) {
808 if ((args
.v1
.ucEncoderMode
== ATOM_ENCODER_MODE_DP
) ||
809 (args
.v1
.ucEncoderMode
== ATOM_ENCODER_MODE_DP_MST
)) {
810 if (dp_clock
== 270000)
811 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ
;
812 else if (dp_clock
== 540000)
813 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ
;
815 args
.v4
.acConfig
.ucDigSel
= dig
->dig_encoder
;
818 args
.v4
.ucBitPerColor
= PANEL_BPC_UNDEFINE
;
821 args
.v4
.ucBitPerColor
= PANEL_6BIT_PER_COLOR
;
825 args
.v4
.ucBitPerColor
= PANEL_8BIT_PER_COLOR
;
828 args
.v4
.ucBitPerColor
= PANEL_10BIT_PER_COLOR
;
831 args
.v4
.ucBitPerColor
= PANEL_12BIT_PER_COLOR
;
834 args
.v4
.ucBitPerColor
= PANEL_16BIT_PER_COLOR
;
837 if (hpd_id
== RADEON_HPD_NONE
)
838 args
.v4
.ucHPD_ID
= 0;
840 args
.v4
.ucHPD_ID
= hpd_id
+ 1;
841 } else if (ASIC_IS_DCE4(rdev
)) {
842 if ((args
.v1
.ucEncoderMode
== ATOM_ENCODER_MODE_DP
) && (dp_clock
== 270000))
843 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
844 args
.v3
.acConfig
.ucDigSel
= dig
->dig_encoder
;
847 args
.v3
.ucBitPerColor
= PANEL_BPC_UNDEFINE
;
850 args
.v3
.ucBitPerColor
= PANEL_6BIT_PER_COLOR
;
854 args
.v3
.ucBitPerColor
= PANEL_8BIT_PER_COLOR
;
857 args
.v3
.ucBitPerColor
= PANEL_10BIT_PER_COLOR
;
860 args
.v3
.ucBitPerColor
= PANEL_12BIT_PER_COLOR
;
863 args
.v3
.ucBitPerColor
= PANEL_16BIT_PER_COLOR
;
867 if ((args
.v1
.ucEncoderMode
== ATOM_ENCODER_MODE_DP
) && (dp_clock
== 270000))
868 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
869 switch (radeon_encoder
->encoder_id
) {
870 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
871 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
873 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
874 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
875 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
877 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
878 args
.v1
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
882 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
884 args
.v1
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
887 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
891 union dig_transmitter_control
{
892 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
893 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
894 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3
;
895 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4
;
899 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
, uint8_t lane_num
, uint8_t lane_set
)
901 struct drm_device
*dev
= encoder
->dev
;
902 struct radeon_device
*rdev
= dev
->dev_private
;
903 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
904 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
905 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
906 union dig_transmitter_control args
;
912 int dp_lane_count
= 0;
913 int connector_object_id
= 0;
914 int igp_lane_info
= 0;
917 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
918 struct radeon_connector_atom_dig
*dig_connector
=
919 radeon_connector
->con_priv
;
921 dp_clock
= dig_connector
->dp_clock
;
922 dp_lane_count
= dig_connector
->dp_lane_count
;
923 connector_object_id
=
924 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
925 igp_lane_info
= dig_connector
->igp_lane_info
;
928 /* no dig encoder assigned */
929 if (dig
->dig_encoder
== -1)
932 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_DP
)
935 memset(&args
, 0, sizeof(args
));
937 switch (radeon_encoder
->encoder_id
) {
938 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
939 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
942 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
943 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
944 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
946 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
947 index
= GetIndexIntoMasterTable(COMMAND
, LVTMATransmitterControl
);
951 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
954 args
.v1
.ucAction
= action
;
955 if (action
== ATOM_TRANSMITTER_ACTION_INIT
) {
956 args
.v1
.usInitInfo
= cpu_to_le16(connector_object_id
);
957 } else if (action
== ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH
) {
958 args
.v1
.asMode
.ucLaneSel
= lane_num
;
959 args
.v1
.asMode
.ucLaneSet
= lane_set
;
962 args
.v1
.usPixelClock
=
963 cpu_to_le16(dp_clock
/ 10);
964 else if (radeon_encoder
->pixel_clock
> 165000)
965 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
/ 2) / 10);
967 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
969 if (ASIC_IS_DCE4(rdev
)) {
971 args
.v3
.ucLaneNum
= dp_lane_count
;
972 else if (radeon_encoder
->pixel_clock
> 165000)
973 args
.v3
.ucLaneNum
= 8;
975 args
.v3
.ucLaneNum
= 4;
978 args
.v3
.acConfig
.ucLinkSel
= 1;
979 if (dig
->dig_encoder
& 1)
980 args
.v3
.acConfig
.ucEncoderSel
= 1;
982 /* Select the PLL for the PHY
983 * DP PHY should be clocked from external src if there is
987 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
988 pll_id
= radeon_crtc
->pll_id
;
991 if (ASIC_IS_DCE5(rdev
)) {
992 /* On DCE5 DCPLL usually generates the DP ref clock */
994 if (rdev
->clock
.dp_extclk
)
995 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_EXTCLK
;
997 args
.v4
.acConfig
.ucRefClkSource
= ENCODER_REFCLK_SRC_DCPLL
;
999 args
.v4
.acConfig
.ucRefClkSource
= pll_id
;
1001 /* On DCE4, if there is an external clock, it generates the DP ref clock */
1002 if (is_dp
&& rdev
->clock
.dp_extclk
)
1003 args
.v3
.acConfig
.ucRefClkSource
= 2; /* external src */
1005 args
.v3
.acConfig
.ucRefClkSource
= pll_id
;
1008 switch (radeon_encoder
->encoder_id
) {
1009 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1010 args
.v3
.acConfig
.ucTransmitterSel
= 0;
1012 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1013 args
.v3
.acConfig
.ucTransmitterSel
= 1;
1015 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1016 args
.v3
.acConfig
.ucTransmitterSel
= 2;
1021 args
.v3
.acConfig
.fCoherentMode
= 1; /* DP requires coherent */
1022 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1023 if (dig
->coherent_mode
)
1024 args
.v3
.acConfig
.fCoherentMode
= 1;
1025 if (radeon_encoder
->pixel_clock
> 165000)
1026 args
.v3
.acConfig
.fDualLinkConnector
= 1;
1028 } else if (ASIC_IS_DCE32(rdev
)) {
1029 args
.v2
.acConfig
.ucEncoderSel
= dig
->dig_encoder
;
1031 args
.v2
.acConfig
.ucLinkSel
= 1;
1033 switch (radeon_encoder
->encoder_id
) {
1034 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1035 args
.v2
.acConfig
.ucTransmitterSel
= 0;
1037 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1038 args
.v2
.acConfig
.ucTransmitterSel
= 1;
1040 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1041 args
.v2
.acConfig
.ucTransmitterSel
= 2;
1046 args
.v2
.acConfig
.fCoherentMode
= 1;
1047 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1048 if (dig
->coherent_mode
)
1049 args
.v2
.acConfig
.fCoherentMode
= 1;
1050 if (radeon_encoder
->pixel_clock
> 165000)
1051 args
.v2
.acConfig
.fDualLinkConnector
= 1;
1054 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
1056 if (dig
->dig_encoder
)
1057 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
1059 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
1061 if ((rdev
->flags
& RADEON_IS_IGP
) &&
1062 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_UNIPHY
)) {
1063 if (is_dp
|| (radeon_encoder
->pixel_clock
<= 165000)) {
1064 if (igp_lane_info
& 0x1)
1065 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
1066 else if (igp_lane_info
& 0x2)
1067 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
1068 else if (igp_lane_info
& 0x4)
1069 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
1070 else if (igp_lane_info
& 0x8)
1071 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
1073 if (igp_lane_info
& 0x3)
1074 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
1075 else if (igp_lane_info
& 0xc)
1076 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
1081 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
;
1083 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
1086 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1087 else if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
1088 if (dig
->coherent_mode
)
1089 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
1090 if (radeon_encoder
->pixel_clock
> 165000)
1091 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_8LANE_LINK
;
1095 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1099 atombios_set_edp_panel_power(struct drm_connector
*connector
, int action
)
1101 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1102 struct drm_device
*dev
= radeon_connector
->base
.dev
;
1103 struct radeon_device
*rdev
= dev
->dev_private
;
1104 union dig_transmitter_control args
;
1105 int index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
1108 if (connector
->connector_type
!= DRM_MODE_CONNECTOR_eDP
)
1111 if (!ASIC_IS_DCE4(rdev
))
1114 if ((action
!= ATOM_TRANSMITTER_ACTION_POWER_ON
) &&
1115 (action
!= ATOM_TRANSMITTER_ACTION_POWER_OFF
))
1118 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1121 memset(&args
, 0, sizeof(args
));
1123 args
.v1
.ucAction
= action
;
1125 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1127 /* wait for the panel to power up */
1128 if (action
== ATOM_TRANSMITTER_ACTION_POWER_ON
) {
1131 for (i
= 0; i
< 300; i
++) {
1132 if (radeon_hpd_sense(rdev
, radeon_connector
->hpd
.hpd
))
1142 union external_encoder_control
{
1143 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1
;
1144 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3
;
1148 atombios_external_encoder_setup(struct drm_encoder
*encoder
,
1149 struct drm_encoder
*ext_encoder
,
1152 struct drm_device
*dev
= encoder
->dev
;
1153 struct radeon_device
*rdev
= dev
->dev_private
;
1154 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1155 struct radeon_encoder
*ext_radeon_encoder
= to_radeon_encoder(ext_encoder
);
1156 union external_encoder_control args
;
1157 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1158 int index
= GetIndexIntoMasterTable(COMMAND
, ExternalEncoderControl
);
1161 int dp_lane_count
= 0;
1162 int connector_object_id
= 0;
1163 u32 ext_enum
= (ext_radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1167 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1168 struct radeon_connector_atom_dig
*dig_connector
=
1169 radeon_connector
->con_priv
;
1171 dp_clock
= dig_connector
->dp_clock
;
1172 dp_lane_count
= dig_connector
->dp_lane_count
;
1173 connector_object_id
=
1174 (radeon_connector
->connector_object_id
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
1175 bpc
= connector
->display_info
.bpc
;
1178 memset(&args
, 0, sizeof(args
));
1180 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1185 /* no params on frev 1 */
1191 args
.v1
.sDigEncoder
.ucAction
= action
;
1192 args
.v1
.sDigEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1193 args
.v1
.sDigEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1195 if (args
.v1
.sDigEncoder
.ucEncoderMode
== ATOM_ENCODER_MODE_DP
) {
1196 if (dp_clock
== 270000)
1197 args
.v1
.sDigEncoder
.ucConfig
|= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ
;
1198 args
.v1
.sDigEncoder
.ucLaneNum
= dp_lane_count
;
1199 } else if (radeon_encoder
->pixel_clock
> 165000)
1200 args
.v1
.sDigEncoder
.ucLaneNum
= 8;
1202 args
.v1
.sDigEncoder
.ucLaneNum
= 4;
1205 args
.v3
.sExtEncoder
.ucAction
= action
;
1206 if (action
== EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
)
1207 args
.v3
.sExtEncoder
.usConnectorId
= cpu_to_le16(connector_object_id
);
1209 args
.v3
.sExtEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
1210 args
.v3
.sExtEncoder
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
1212 if (args
.v3
.sExtEncoder
.ucEncoderMode
== ATOM_ENCODER_MODE_DP
) {
1213 if (dp_clock
== 270000)
1214 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ
;
1215 else if (dp_clock
== 540000)
1216 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ
;
1217 args
.v3
.sExtEncoder
.ucLaneNum
= dp_lane_count
;
1218 } else if (radeon_encoder
->pixel_clock
> 165000)
1219 args
.v3
.sExtEncoder
.ucLaneNum
= 8;
1221 args
.v3
.sExtEncoder
.ucLaneNum
= 4;
1223 case GRAPH_OBJECT_ENUM_ID1
:
1224 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1
;
1226 case GRAPH_OBJECT_ENUM_ID2
:
1227 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2
;
1229 case GRAPH_OBJECT_ENUM_ID3
:
1230 args
.v3
.sExtEncoder
.ucConfig
|= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3
;
1235 args
.v3
.sExtEncoder
.ucBitPerColor
= PANEL_BPC_UNDEFINE
;
1238 args
.v3
.sExtEncoder
.ucBitPerColor
= PANEL_6BIT_PER_COLOR
;
1242 args
.v3
.sExtEncoder
.ucBitPerColor
= PANEL_8BIT_PER_COLOR
;
1245 args
.v3
.sExtEncoder
.ucBitPerColor
= PANEL_10BIT_PER_COLOR
;
1248 args
.v3
.sExtEncoder
.ucBitPerColor
= PANEL_12BIT_PER_COLOR
;
1251 args
.v3
.sExtEncoder
.ucBitPerColor
= PANEL_16BIT_PER_COLOR
;
1256 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1261 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1264 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1268 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
1270 struct drm_device
*dev
= encoder
->dev
;
1271 struct radeon_device
*rdev
= dev
->dev_private
;
1272 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1273 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1274 ENABLE_YUV_PS_ALLOCATION args
;
1275 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
1278 memset(&args
, 0, sizeof(args
));
1280 if (rdev
->family
>= CHIP_R600
)
1281 reg
= R600_BIOS_3_SCRATCH
;
1283 reg
= RADEON_BIOS_3_SCRATCH
;
1285 /* XXX: fix up scratch reg handling */
1287 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1288 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
1289 (radeon_crtc
->crtc_id
<< 18)));
1290 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1291 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
1296 args
.ucEnable
= ATOM_ENABLE
;
1297 args
.ucCRTC
= radeon_crtc
->crtc_id
;
1299 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1305 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
1307 struct drm_device
*dev
= encoder
->dev
;
1308 struct radeon_device
*rdev
= dev
->dev_private
;
1309 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1310 struct drm_encoder
*ext_encoder
= radeon_atom_get_external_encoder(encoder
);
1311 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
1313 bool is_dig
= false;
1314 bool is_dce5_dac
= false;
1315 bool is_dce5_dvo
= false;
1317 memset(&args
, 0, sizeof(args
));
1319 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1320 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
1321 radeon_encoder
->active_device
);
1322 switch (radeon_encoder
->encoder_id
) {
1323 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1324 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1325 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
1327 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1328 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1329 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1330 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1333 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1334 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1335 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1337 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1338 if (ASIC_IS_DCE5(rdev
))
1340 else if (ASIC_IS_DCE3(rdev
))
1343 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
1345 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1346 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1348 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1349 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1350 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
1352 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
1354 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1355 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1356 if (ASIC_IS_DCE5(rdev
))
1359 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1360 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1361 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1362 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1364 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
1367 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1368 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1369 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1370 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
1371 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1372 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
1374 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
1380 case DRM_MODE_DPMS_ON
:
1381 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT
, 0, 0);
1382 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_DP
) {
1383 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1386 (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
1387 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1388 struct radeon_connector_atom_dig
*radeon_dig_connector
=
1389 radeon_connector
->con_priv
;
1390 atombios_set_edp_panel_power(connector
,
1391 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1392 radeon_dig_connector
->edp_on
= true;
1394 dp_link_train(encoder
, connector
);
1395 if (ASIC_IS_DCE4(rdev
))
1396 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_ON
);
1398 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1399 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLON
, 0, 0);
1401 case DRM_MODE_DPMS_STANDBY
:
1402 case DRM_MODE_DPMS_SUSPEND
:
1403 case DRM_MODE_DPMS_OFF
:
1404 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT
, 0, 0);
1405 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_DP
) {
1406 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1408 if (ASIC_IS_DCE4(rdev
))
1409 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_DP_VIDEO_OFF
);
1411 (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)) {
1412 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1413 struct radeon_connector_atom_dig
*radeon_dig_connector
=
1414 radeon_connector
->con_priv
;
1415 atombios_set_edp_panel_power(connector
,
1416 ATOM_TRANSMITTER_ACTION_POWER_OFF
);
1417 radeon_dig_connector
->edp_on
= false;
1420 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
1421 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_LCD_BLOFF
, 0, 0);
1424 } else if (is_dce5_dac
) {
1426 case DRM_MODE_DPMS_ON
:
1427 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1429 case DRM_MODE_DPMS_STANDBY
:
1430 case DRM_MODE_DPMS_SUSPEND
:
1431 case DRM_MODE_DPMS_OFF
:
1432 atombios_dac_setup(encoder
, ATOM_DISABLE
);
1435 } else if (is_dce5_dvo
) {
1437 case DRM_MODE_DPMS_ON
:
1438 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
1440 case DRM_MODE_DPMS_STANDBY
:
1441 case DRM_MODE_DPMS_SUSPEND
:
1442 case DRM_MODE_DPMS_OFF
:
1443 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
1448 case DRM_MODE_DPMS_ON
:
1449 args
.ucAction
= ATOM_ENABLE
;
1450 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1451 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1452 args
.ucAction
= ATOM_LCD_BLON
;
1453 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1456 case DRM_MODE_DPMS_STANDBY
:
1457 case DRM_MODE_DPMS_SUSPEND
:
1458 case DRM_MODE_DPMS_OFF
:
1459 args
.ucAction
= ATOM_DISABLE
;
1460 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1461 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1462 args
.ucAction
= ATOM_LCD_BLOFF
;
1463 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1473 case DRM_MODE_DPMS_ON
:
1475 if (ASIC_IS_DCE41(rdev
))
1476 action
= EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT
;
1478 action
= ATOM_ENABLE
;
1480 case DRM_MODE_DPMS_STANDBY
:
1481 case DRM_MODE_DPMS_SUSPEND
:
1482 case DRM_MODE_DPMS_OFF
:
1483 if (ASIC_IS_DCE41(rdev
))
1484 action
= EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT
;
1486 action
= ATOM_DISABLE
;
1489 atombios_external_encoder_setup(encoder
, ext_encoder
, action
);
1492 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
1496 union crtc_source_param
{
1497 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
1498 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
1502 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
1504 struct drm_device
*dev
= encoder
->dev
;
1505 struct radeon_device
*rdev
= dev
->dev_private
;
1506 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1507 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1508 union crtc_source_param args
;
1509 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
1511 struct radeon_encoder_atom_dig
*dig
;
1513 memset(&args
, 0, sizeof(args
));
1515 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1523 if (ASIC_IS_AVIVO(rdev
))
1524 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1526 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
1527 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
1529 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
1532 switch (radeon_encoder
->encoder_id
) {
1533 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1534 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1535 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
1537 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1538 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1539 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
1540 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1542 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1544 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1545 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1546 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1547 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1549 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1550 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1551 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1552 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1553 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1554 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1556 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1558 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1559 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1560 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1561 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1562 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1563 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1565 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1570 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1571 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1572 switch (radeon_encoder
->encoder_id
) {
1573 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1574 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1575 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1576 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1577 dig
= radeon_encoder
->enc_priv
;
1578 switch (dig
->dig_encoder
) {
1580 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1583 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1586 args
.v2
.ucEncoderID
= ASIC_INT_DIG3_ENCODER_ID
;
1589 args
.v2
.ucEncoderID
= ASIC_INT_DIG4_ENCODER_ID
;
1592 args
.v2
.ucEncoderID
= ASIC_INT_DIG5_ENCODER_ID
;
1595 args
.v2
.ucEncoderID
= ASIC_INT_DIG6_ENCODER_ID
;
1599 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1600 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1602 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1603 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1604 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1605 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1606 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1608 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1610 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1611 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1612 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1613 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1614 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1616 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1623 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1627 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1629 /* update scratch regs with new routing */
1630 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1634 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1635 struct drm_display_mode
*mode
)
1637 struct drm_device
*dev
= encoder
->dev
;
1638 struct radeon_device
*rdev
= dev
->dev_private
;
1639 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1640 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1642 /* Funky macbooks */
1643 if ((dev
->pdev
->device
== 0x71C5) &&
1644 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1645 (dev
->pdev
->subsystem_device
== 0x0080)) {
1646 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1647 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1649 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1650 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1652 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1656 /* set scaler clears this on some chips */
1657 if (ASIC_IS_AVIVO(rdev
) &&
1658 (!(radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
)))) {
1659 if (ASIC_IS_DCE4(rdev
)) {
1660 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1661 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1662 EVERGREEN_INTERLEAVE_EN
);
1664 WREG32(EVERGREEN_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1666 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
1667 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
,
1668 AVIVO_D1MODE_INTERLEAVE_EN
);
1670 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, 0);
1675 static int radeon_atom_pick_dig_encoder(struct drm_encoder
*encoder
)
1677 struct drm_device
*dev
= encoder
->dev
;
1678 struct radeon_device
*rdev
= dev
->dev_private
;
1679 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1680 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1681 struct drm_encoder
*test_encoder
;
1682 struct radeon_encoder_atom_dig
*dig
;
1683 uint32_t dig_enc_in_use
= 0;
1686 if (ASIC_IS_DCE4(rdev
)) {
1687 dig
= radeon_encoder
->enc_priv
;
1688 if (ASIC_IS_DCE41(rdev
))
1689 return radeon_crtc
->crtc_id
;
1691 switch (radeon_encoder
->encoder_id
) {
1692 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1698 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1704 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1714 /* on DCE32 and encoder can driver any block so just crtc id */
1715 if (ASIC_IS_DCE32(rdev
)) {
1716 return radeon_crtc
->crtc_id
;
1719 /* on DCE3 - LVTMA can only be driven by DIGB */
1720 list_for_each_entry(test_encoder
, &dev
->mode_config
.encoder_list
, head
) {
1721 struct radeon_encoder
*radeon_test_encoder
;
1723 if (encoder
== test_encoder
)
1726 if (!radeon_encoder_is_digital(test_encoder
))
1729 radeon_test_encoder
= to_radeon_encoder(test_encoder
);
1730 dig
= radeon_test_encoder
->enc_priv
;
1732 if (dig
->dig_encoder
>= 0)
1733 dig_enc_in_use
|= (1 << dig
->dig_encoder
);
1736 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
) {
1737 if (dig_enc_in_use
& 0x2)
1738 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1741 if (!(dig_enc_in_use
& 1))
1747 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
1748 struct drm_display_mode
*mode
,
1749 struct drm_display_mode
*adjusted_mode
)
1751 struct drm_device
*dev
= encoder
->dev
;
1752 struct radeon_device
*rdev
= dev
->dev_private
;
1753 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1754 struct drm_encoder
*ext_encoder
= radeon_atom_get_external_encoder(encoder
);
1756 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
1758 if (ASIC_IS_AVIVO(rdev
) && !ASIC_IS_DCE4(rdev
)) {
1759 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
1760 atombios_yuv_setup(encoder
, true);
1762 atombios_yuv_setup(encoder
, false);
1765 switch (radeon_encoder
->encoder_id
) {
1766 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1767 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1768 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1769 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1770 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
1772 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1773 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1774 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1775 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1776 if (ASIC_IS_DCE4(rdev
)) {
1777 /* disable the transmitter */
1778 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1779 /* setup and enable the encoder */
1780 atombios_dig_encoder_setup(encoder
, ATOM_ENCODER_CMD_SETUP
);
1782 /* init and enable the transmitter */
1783 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
1784 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1786 /* disable the encoder and transmitter */
1787 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
1788 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
);
1790 /* setup and enable the encoder and transmitter */
1791 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
);
1792 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_INIT
, 0, 0);
1793 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
, 0, 0);
1794 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
, 0, 0);
1797 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1798 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1799 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1800 atombios_dvo_setup(encoder
, ATOM_ENABLE
);
1802 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1803 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1804 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1805 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1806 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1807 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) {
1808 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
1809 atombios_tv_setup(encoder
, ATOM_ENABLE
);
1811 atombios_tv_setup(encoder
, ATOM_DISABLE
);
1817 if (ASIC_IS_DCE41(rdev
)) {
1818 atombios_external_encoder_setup(encoder
, ext_encoder
,
1819 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT
);
1820 atombios_external_encoder_setup(encoder
, ext_encoder
,
1821 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP
);
1823 atombios_external_encoder_setup(encoder
, ext_encoder
, ATOM_ENABLE
);
1826 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
1828 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
) {
1829 r600_hdmi_enable(encoder
);
1830 r600_hdmi_setmode(encoder
, adjusted_mode
);
1835 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1837 struct drm_device
*dev
= encoder
->dev
;
1838 struct radeon_device
*rdev
= dev
->dev_private
;
1839 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1840 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1842 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
1843 ATOM_DEVICE_CV_SUPPORT
|
1844 ATOM_DEVICE_CRT_SUPPORT
)) {
1845 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
1846 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
1849 memset(&args
, 0, sizeof(args
));
1851 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
1854 args
.sDacload
.ucMisc
= 0;
1856 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
1857 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
1858 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
1860 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
1862 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
1863 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
1864 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
1865 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
1866 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1867 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
1869 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1870 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1871 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
1873 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1876 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1883 static enum drm_connector_status
1884 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1886 struct drm_device
*dev
= encoder
->dev
;
1887 struct radeon_device
*rdev
= dev
->dev_private
;
1888 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1889 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1890 uint32_t bios_0_scratch
;
1892 if (!atombios_dac_load_detect(encoder
, connector
)) {
1893 DRM_DEBUG_KMS("detect returned false \n");
1894 return connector_status_unknown
;
1897 if (rdev
->family
>= CHIP_R600
)
1898 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1900 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1902 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
1903 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1904 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1905 return connector_status_connected
;
1907 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1908 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1909 return connector_status_connected
;
1911 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1912 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1913 return connector_status_connected
;
1915 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1916 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1917 return connector_status_connected
; /* CTV */
1918 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1919 return connector_status_connected
; /* STV */
1921 return connector_status_disconnected
;
1924 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
1926 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1927 struct drm_connector
*connector
= radeon_get_connector_for_encoder(encoder
);
1929 if (radeon_encoder
->active_device
&
1930 (ATOM_DEVICE_DFP_SUPPORT
| ATOM_DEVICE_LCD_SUPPORT
)) {
1931 struct radeon_encoder_atom_dig
*dig
= radeon_encoder
->enc_priv
;
1933 dig
->dig_encoder
= radeon_atom_pick_dig_encoder(encoder
);
1936 radeon_atom_output_lock(encoder
, true);
1937 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1940 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1942 /* select the clock/data port if it uses a router */
1943 if (radeon_connector
->router
.cd_valid
)
1944 radeon_router_select_cd_port(radeon_connector
);
1946 /* turn eDP panel on for mode set */
1947 if (connector
->connector_type
== DRM_MODE_CONNECTOR_eDP
)
1948 atombios_set_edp_panel_power(connector
,
1949 ATOM_TRANSMITTER_ACTION_POWER_ON
);
1952 /* this is needed for the pll/ss setup to work correctly in some cases */
1953 atombios_set_encoder_crtc_source(encoder
);
1956 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
1958 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
1959 radeon_atom_output_lock(encoder
, false);
1962 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
1964 struct drm_device
*dev
= encoder
->dev
;
1965 struct radeon_device
*rdev
= dev
->dev_private
;
1966 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1967 struct radeon_encoder_atom_dig
*dig
;
1969 /* check for pre-DCE3 cards with shared encoders;
1970 * can't really use the links individually, so don't disable
1971 * the encoder if it's in use by another connector
1973 if (!ASIC_IS_DCE3(rdev
)) {
1974 struct drm_encoder
*other_encoder
;
1975 struct radeon_encoder
*other_radeon_encoder
;
1977 list_for_each_entry(other_encoder
, &dev
->mode_config
.encoder_list
, head
) {
1978 other_radeon_encoder
= to_radeon_encoder(other_encoder
);
1979 if ((radeon_encoder
->encoder_id
== other_radeon_encoder
->encoder_id
) &&
1980 drm_helper_encoder_in_use(other_encoder
))
1985 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1987 switch (radeon_encoder
->encoder_id
) {
1988 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1989 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1990 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1991 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1992 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_DISABLE
);
1994 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1995 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1996 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1997 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1998 if (ASIC_IS_DCE4(rdev
))
1999 /* disable the transmitter */
2000 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
2002 /* disable the encoder and transmitter */
2003 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
, 0, 0);
2004 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
);
2007 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2008 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2009 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2010 atombios_dvo_setup(encoder
, ATOM_DISABLE
);
2012 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2013 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2014 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2015 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2016 atombios_dac_setup(encoder
, ATOM_DISABLE
);
2017 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
2018 atombios_tv_setup(encoder
, ATOM_DISABLE
);
2023 if (radeon_encoder_is_digital(encoder
)) {
2024 if (atombios_get_encoder_mode(encoder
) == ATOM_ENCODER_MODE_HDMI
)
2025 r600_hdmi_disable(encoder
);
2026 dig
= radeon_encoder
->enc_priv
;
2027 dig
->dig_encoder
= -1;
2029 radeon_encoder
->active_device
= 0;
2032 /* these are handled by the primary encoders */
2033 static void radeon_atom_ext_prepare(struct drm_encoder
*encoder
)
2038 static void radeon_atom_ext_commit(struct drm_encoder
*encoder
)
2044 radeon_atom_ext_mode_set(struct drm_encoder
*encoder
,
2045 struct drm_display_mode
*mode
,
2046 struct drm_display_mode
*adjusted_mode
)
2051 static void radeon_atom_ext_disable(struct drm_encoder
*encoder
)
2057 radeon_atom_ext_dpms(struct drm_encoder
*encoder
, int mode
)
2062 static bool radeon_atom_ext_mode_fixup(struct drm_encoder
*encoder
,
2063 struct drm_display_mode
*mode
,
2064 struct drm_display_mode
*adjusted_mode
)
2069 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs
= {
2070 .dpms
= radeon_atom_ext_dpms
,
2071 .mode_fixup
= radeon_atom_ext_mode_fixup
,
2072 .prepare
= radeon_atom_ext_prepare
,
2073 .mode_set
= radeon_atom_ext_mode_set
,
2074 .commit
= radeon_atom_ext_commit
,
2075 .disable
= radeon_atom_ext_disable
,
2076 /* no detect for TMDS/LVDS yet */
2079 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
2080 .dpms
= radeon_atom_encoder_dpms
,
2081 .mode_fixup
= radeon_atom_mode_fixup
,
2082 .prepare
= radeon_atom_encoder_prepare
,
2083 .mode_set
= radeon_atom_encoder_mode_set
,
2084 .commit
= radeon_atom_encoder_commit
,
2085 .disable
= radeon_atom_encoder_disable
,
2086 /* no detect for TMDS/LVDS yet */
2089 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
2090 .dpms
= radeon_atom_encoder_dpms
,
2091 .mode_fixup
= radeon_atom_mode_fixup
,
2092 .prepare
= radeon_atom_encoder_prepare
,
2093 .mode_set
= radeon_atom_encoder_mode_set
,
2094 .commit
= radeon_atom_encoder_commit
,
2095 .detect
= radeon_atom_dac_detect
,
2098 void radeon_enc_destroy(struct drm_encoder
*encoder
)
2100 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2101 kfree(radeon_encoder
->enc_priv
);
2102 drm_encoder_cleanup(encoder
);
2103 kfree(radeon_encoder
);
2106 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
2107 .destroy
= radeon_enc_destroy
,
2110 struct radeon_encoder_atom_dac
*
2111 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
2113 struct drm_device
*dev
= radeon_encoder
->base
.dev
;
2114 struct radeon_device
*rdev
= dev
->dev_private
;
2115 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
2120 dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
2124 struct radeon_encoder_atom_dig
*
2125 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
2127 int encoder_enum
= (radeon_encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
2128 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
2133 /* coherent mode by default */
2134 dig
->coherent_mode
= true;
2135 dig
->dig_encoder
= -1;
2137 if (encoder_enum
== 2)
2146 radeon_add_atom_encoder(struct drm_device
*dev
,
2147 uint32_t encoder_enum
,
2148 uint32_t supported_device
,
2151 struct radeon_device
*rdev
= dev
->dev_private
;
2152 struct drm_encoder
*encoder
;
2153 struct radeon_encoder
*radeon_encoder
;
2155 /* see if we already added it */
2156 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
2157 radeon_encoder
= to_radeon_encoder(encoder
);
2158 if (radeon_encoder
->encoder_enum
== encoder_enum
) {
2159 radeon_encoder
->devices
|= supported_device
;
2166 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
2167 if (!radeon_encoder
)
2170 encoder
= &radeon_encoder
->base
;
2171 switch (rdev
->num_crtc
) {
2173 encoder
->possible_crtcs
= 0x1;
2177 encoder
->possible_crtcs
= 0x3;
2180 encoder
->possible_crtcs
= 0x3f;
2184 radeon_encoder
->enc_priv
= NULL
;
2186 radeon_encoder
->encoder_enum
= encoder_enum
;
2187 radeon_encoder
->encoder_id
= (encoder_enum
& OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
2188 radeon_encoder
->devices
= supported_device
;
2189 radeon_encoder
->rmx_type
= RMX_OFF
;
2190 radeon_encoder
->underscan_type
= UNDERSCAN_OFF
;
2191 radeon_encoder
->is_ext_encoder
= false;
2192 radeon_encoder
->caps
= caps
;
2194 switch (radeon_encoder
->encoder_id
) {
2195 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
2196 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
2197 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
2198 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
2199 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2200 radeon_encoder
->rmx_type
= RMX_FULL
;
2201 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2202 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2204 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2205 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2207 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2209 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
2210 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2211 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2212 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2214 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
2215 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
2216 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
2217 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
2218 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
2219 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
2221 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
2222 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
2223 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
2224 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
2225 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
2226 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
2227 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
2228 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
2229 radeon_encoder
->rmx_type
= RMX_FULL
;
2230 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2231 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
2232 } else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
)) {
2233 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2234 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2236 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2237 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
2239 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
2241 case ENCODER_OBJECT_ID_SI170B
:
2242 case ENCODER_OBJECT_ID_CH7303
:
2243 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA
:
2244 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB
:
2245 case ENCODER_OBJECT_ID_TITFP513
:
2246 case ENCODER_OBJECT_ID_VT1623
:
2247 case ENCODER_OBJECT_ID_HDMI_SI1930
:
2248 case ENCODER_OBJECT_ID_TRAVIS
:
2249 case ENCODER_OBJECT_ID_NUTMEG
:
2250 /* these are handled by the primary encoders */
2251 radeon_encoder
->is_ext_encoder
= true;
2252 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
2253 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
2254 else if (radeon_encoder
->devices
& (ATOM_DEVICE_CRT_SUPPORT
))
2255 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
2257 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
2258 drm_encoder_helper_add(encoder
, &radeon_atom_ext_helper_funcs
);