2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2009 Cavium Networks
9 #include <linux/capability.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/if_vlan.h>
16 #include <linux/slab.h>
17 #include <linux/phy.h>
18 #include <linux/spinlock.h>
20 #include <asm/octeon/octeon.h>
21 #include <asm/octeon/cvmx-mixx-defs.h>
22 #include <asm/octeon/cvmx-agl-defs.h>
24 #define DRV_NAME "octeon_mgmt"
25 #define DRV_VERSION "2.0"
26 #define DRV_DESCRIPTION \
27 "Cavium Networks Octeon MII (management) port Network Driver"
29 #define OCTEON_MGMT_NAPI_WEIGHT 16
32 * Ring sizes that are powers of two allow for more efficient modulo
35 #define OCTEON_MGMT_RX_RING_SIZE 512
36 #define OCTEON_MGMT_TX_RING_SIZE 128
38 /* Allow 8 bytes for vlan and FCS. */
39 #define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
41 union mgmt_port_ring_entry
{
45 /* Length of the buffer/packet in bytes */
47 /* For TX, signals that the packet should be timestamped */
49 /* The RX error code */
51 #define RING_ENTRY_CODE_DONE 0xf
52 #define RING_ENTRY_CODE_MORE 0x10
53 /* Physical address of the buffer */
59 struct net_device
*netdev
;
63 dma_addr_t tx_ring_handle
;
65 unsigned int tx_next_clean
;
66 unsigned int tx_current_fill
;
67 /* The tx_list lock also protects the ring related variables */
68 struct sk_buff_head tx_list
;
70 /* RX variables only touched in napi_poll. No locking necessary. */
72 dma_addr_t rx_ring_handle
;
74 unsigned int rx_next_fill
;
75 unsigned int rx_current_fill
;
76 struct sk_buff_head rx_list
;
79 unsigned int last_duplex
;
80 unsigned int last_link
;
82 struct napi_struct napi
;
83 struct tasklet_struct tx_clean_tasklet
;
84 struct phy_device
*phydev
;
87 static void octeon_mgmt_set_rx_irq(struct octeon_mgmt
*p
, int enable
)
90 union cvmx_mixx_intena mix_intena
;
93 spin_lock_irqsave(&p
->lock
, flags
);
94 mix_intena
.u64
= cvmx_read_csr(CVMX_MIXX_INTENA(port
));
95 mix_intena
.s
.ithena
= enable
? 1 : 0;
96 cvmx_write_csr(CVMX_MIXX_INTENA(port
), mix_intena
.u64
);
97 spin_unlock_irqrestore(&p
->lock
, flags
);
100 static void octeon_mgmt_set_tx_irq(struct octeon_mgmt
*p
, int enable
)
103 union cvmx_mixx_intena mix_intena
;
106 spin_lock_irqsave(&p
->lock
, flags
);
107 mix_intena
.u64
= cvmx_read_csr(CVMX_MIXX_INTENA(port
));
108 mix_intena
.s
.othena
= enable
? 1 : 0;
109 cvmx_write_csr(CVMX_MIXX_INTENA(port
), mix_intena
.u64
);
110 spin_unlock_irqrestore(&p
->lock
, flags
);
113 static inline void octeon_mgmt_enable_rx_irq(struct octeon_mgmt
*p
)
115 octeon_mgmt_set_rx_irq(p
, 1);
118 static inline void octeon_mgmt_disable_rx_irq(struct octeon_mgmt
*p
)
120 octeon_mgmt_set_rx_irq(p
, 0);
123 static inline void octeon_mgmt_enable_tx_irq(struct octeon_mgmt
*p
)
125 octeon_mgmt_set_tx_irq(p
, 1);
128 static inline void octeon_mgmt_disable_tx_irq(struct octeon_mgmt
*p
)
130 octeon_mgmt_set_tx_irq(p
, 0);
133 static unsigned int ring_max_fill(unsigned int ring_size
)
135 return ring_size
- 8;
138 static unsigned int ring_size_to_bytes(unsigned int ring_size
)
140 return ring_size
* sizeof(union mgmt_port_ring_entry
);
143 static void octeon_mgmt_rx_fill_ring(struct net_device
*netdev
)
145 struct octeon_mgmt
*p
= netdev_priv(netdev
);
148 while (p
->rx_current_fill
< ring_max_fill(OCTEON_MGMT_RX_RING_SIZE
)) {
150 union mgmt_port_ring_entry re
;
153 /* CN56XX pass 1 needs 8 bytes of padding. */
154 size
= netdev
->mtu
+ OCTEON_MGMT_RX_HEADROOM
+ 8 + NET_IP_ALIGN
;
156 skb
= netdev_alloc_skb(netdev
, size
);
159 skb_reserve(skb
, NET_IP_ALIGN
);
160 __skb_queue_tail(&p
->rx_list
, skb
);
164 re
.s
.addr
= dma_map_single(p
->dev
, skb
->data
,
168 /* Put it in the ring. */
169 p
->rx_ring
[p
->rx_next_fill
] = re
.d64
;
170 dma_sync_single_for_device(p
->dev
, p
->rx_ring_handle
,
171 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE
),
174 (p
->rx_next_fill
+ 1) % OCTEON_MGMT_RX_RING_SIZE
;
175 p
->rx_current_fill
++;
177 cvmx_write_csr(CVMX_MIXX_IRING2(port
), 1);
181 static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt
*p
)
184 union cvmx_mixx_orcnt mix_orcnt
;
185 union mgmt_port_ring_entry re
;
190 mix_orcnt
.u64
= cvmx_read_csr(CVMX_MIXX_ORCNT(port
));
191 while (mix_orcnt
.s
.orcnt
) {
192 spin_lock_irqsave(&p
->tx_list
.lock
, flags
);
194 mix_orcnt
.u64
= cvmx_read_csr(CVMX_MIXX_ORCNT(port
));
196 if (mix_orcnt
.s
.orcnt
== 0) {
197 spin_unlock_irqrestore(&p
->tx_list
.lock
, flags
);
201 dma_sync_single_for_cpu(p
->dev
, p
->tx_ring_handle
,
202 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE
),
205 re
.d64
= p
->tx_ring
[p
->tx_next_clean
];
207 (p
->tx_next_clean
+ 1) % OCTEON_MGMT_TX_RING_SIZE
;
208 skb
= __skb_dequeue(&p
->tx_list
);
211 mix_orcnt
.s
.orcnt
= 1;
213 /* Acknowledge to hardware that we have the buffer. */
214 cvmx_write_csr(CVMX_MIXX_ORCNT(port
), mix_orcnt
.u64
);
215 p
->tx_current_fill
--;
217 spin_unlock_irqrestore(&p
->tx_list
.lock
, flags
);
219 dma_unmap_single(p
->dev
, re
.s
.addr
, re
.s
.len
,
221 dev_kfree_skb_any(skb
);
224 mix_orcnt
.u64
= cvmx_read_csr(CVMX_MIXX_ORCNT(port
));
227 if (cleaned
&& netif_queue_stopped(p
->netdev
))
228 netif_wake_queue(p
->netdev
);
231 static void octeon_mgmt_clean_tx_tasklet(unsigned long arg
)
233 struct octeon_mgmt
*p
= (struct octeon_mgmt
*)arg
;
234 octeon_mgmt_clean_tx_buffers(p
);
235 octeon_mgmt_enable_tx_irq(p
);
238 static void octeon_mgmt_update_rx_stats(struct net_device
*netdev
)
240 struct octeon_mgmt
*p
= netdev_priv(netdev
);
245 /* These reads also clear the count registers. */
246 drop
= cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port
));
247 bad
= cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port
));
250 /* Do an atomic update. */
251 spin_lock_irqsave(&p
->lock
, flags
);
252 netdev
->stats
.rx_errors
+= bad
;
253 netdev
->stats
.rx_dropped
+= drop
;
254 spin_unlock_irqrestore(&p
->lock
, flags
);
258 static void octeon_mgmt_update_tx_stats(struct net_device
*netdev
)
260 struct octeon_mgmt
*p
= netdev_priv(netdev
);
264 union cvmx_agl_gmx_txx_stat0 s0
;
265 union cvmx_agl_gmx_txx_stat1 s1
;
267 /* These reads also clear the count registers. */
268 s0
.u64
= cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port
));
269 s1
.u64
= cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port
));
271 if (s0
.s
.xsdef
|| s0
.s
.xscol
|| s1
.s
.scol
|| s1
.s
.mcol
) {
272 /* Do an atomic update. */
273 spin_lock_irqsave(&p
->lock
, flags
);
274 netdev
->stats
.tx_errors
+= s0
.s
.xsdef
+ s0
.s
.xscol
;
275 netdev
->stats
.collisions
+= s1
.s
.scol
+ s1
.s
.mcol
;
276 spin_unlock_irqrestore(&p
->lock
, flags
);
281 * Dequeue a receive skb and its corresponding ring entry. The ring
282 * entry is returned, *pskb is updated to point to the skb.
284 static u64
octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt
*p
,
285 struct sk_buff
**pskb
)
287 union mgmt_port_ring_entry re
;
289 dma_sync_single_for_cpu(p
->dev
, p
->rx_ring_handle
,
290 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE
),
293 re
.d64
= p
->rx_ring
[p
->rx_next
];
294 p
->rx_next
= (p
->rx_next
+ 1) % OCTEON_MGMT_RX_RING_SIZE
;
295 p
->rx_current_fill
--;
296 *pskb
= __skb_dequeue(&p
->rx_list
);
298 dma_unmap_single(p
->dev
, re
.s
.addr
,
299 ETH_FRAME_LEN
+ OCTEON_MGMT_RX_HEADROOM
,
306 static int octeon_mgmt_receive_one(struct octeon_mgmt
*p
)
309 struct net_device
*netdev
= p
->netdev
;
310 union cvmx_mixx_ircnt mix_ircnt
;
311 union mgmt_port_ring_entry re
;
313 struct sk_buff
*skb2
;
314 struct sk_buff
*skb_new
;
315 union mgmt_port_ring_entry re2
;
319 re
.d64
= octeon_mgmt_dequeue_rx_buffer(p
, &skb
);
320 if (likely(re
.s
.code
== RING_ENTRY_CODE_DONE
)) {
321 /* A good packet, send it up. */
322 skb_put(skb
, re
.s
.len
);
324 skb
->protocol
= eth_type_trans(skb
, netdev
);
325 netdev
->stats
.rx_packets
++;
326 netdev
->stats
.rx_bytes
+= skb
->len
;
327 netif_receive_skb(skb
);
329 } else if (re
.s
.code
== RING_ENTRY_CODE_MORE
) {
331 * Packet split across skbs. This can happen if we
332 * increase the MTU. Buffers that are already in the
333 * rx ring can then end up being too small. As the rx
334 * ring is refilled, buffers sized for the new MTU
335 * will be used and we should go back to the normal
338 skb_put(skb
, re
.s
.len
);
340 re2
.d64
= octeon_mgmt_dequeue_rx_buffer(p
, &skb2
);
341 if (re2
.s
.code
!= RING_ENTRY_CODE_MORE
342 && re2
.s
.code
!= RING_ENTRY_CODE_DONE
)
344 skb_put(skb2
, re2
.s
.len
);
345 skb_new
= skb_copy_expand(skb
, 0, skb2
->len
,
349 if (skb_copy_bits(skb2
, 0, skb_tail_pointer(skb_new
),
352 skb_put(skb_new
, skb2
->len
);
353 dev_kfree_skb_any(skb
);
354 dev_kfree_skb_any(skb2
);
356 } while (re2
.s
.code
== RING_ENTRY_CODE_MORE
);
359 /* Some other error, discard it. */
360 dev_kfree_skb_any(skb
);
362 * Error statistics are accumulated in
363 * octeon_mgmt_update_rx_stats.
368 /* Discard the whole mess. */
369 dev_kfree_skb_any(skb
);
370 dev_kfree_skb_any(skb2
);
371 while (re2
.s
.code
== RING_ENTRY_CODE_MORE
) {
372 re2
.d64
= octeon_mgmt_dequeue_rx_buffer(p
, &skb2
);
373 dev_kfree_skb_any(skb2
);
375 netdev
->stats
.rx_errors
++;
378 /* Tell the hardware we processed a packet. */
380 mix_ircnt
.s
.ircnt
= 1;
381 cvmx_write_csr(CVMX_MIXX_IRCNT(port
), mix_ircnt
.u64
);
386 static int octeon_mgmt_receive_packets(struct octeon_mgmt
*p
, int budget
)
389 unsigned int work_done
= 0;
390 union cvmx_mixx_ircnt mix_ircnt
;
394 mix_ircnt
.u64
= cvmx_read_csr(CVMX_MIXX_IRCNT(port
));
395 while (work_done
< budget
&& mix_ircnt
.s
.ircnt
) {
397 rc
= octeon_mgmt_receive_one(p
);
401 /* Check for more packets. */
402 mix_ircnt
.u64
= cvmx_read_csr(CVMX_MIXX_IRCNT(port
));
405 octeon_mgmt_rx_fill_ring(p
->netdev
);
410 static int octeon_mgmt_napi_poll(struct napi_struct
*napi
, int budget
)
412 struct octeon_mgmt
*p
= container_of(napi
, struct octeon_mgmt
, napi
);
413 struct net_device
*netdev
= p
->netdev
;
414 unsigned int work_done
= 0;
416 work_done
= octeon_mgmt_receive_packets(p
, budget
);
418 if (work_done
< budget
) {
419 /* We stopped because no more packets were available. */
421 octeon_mgmt_enable_rx_irq(p
);
423 octeon_mgmt_update_rx_stats(netdev
);
428 /* Reset the hardware to clean state. */
429 static void octeon_mgmt_reset_hw(struct octeon_mgmt
*p
)
431 union cvmx_mixx_ctl mix_ctl
;
432 union cvmx_mixx_bist mix_bist
;
433 union cvmx_agl_gmx_bist agl_gmx_bist
;
436 cvmx_write_csr(CVMX_MIXX_CTL(p
->port
), mix_ctl
.u64
);
438 mix_ctl
.u64
= cvmx_read_csr(CVMX_MIXX_CTL(p
->port
));
439 } while (mix_ctl
.s
.busy
);
441 cvmx_write_csr(CVMX_MIXX_CTL(p
->port
), mix_ctl
.u64
);
442 cvmx_read_csr(CVMX_MIXX_CTL(p
->port
));
445 mix_bist
.u64
= cvmx_read_csr(CVMX_MIXX_BIST(p
->port
));
447 dev_warn(p
->dev
, "MIX failed BIST (0x%016llx)\n",
448 (unsigned long long)mix_bist
.u64
);
450 agl_gmx_bist
.u64
= cvmx_read_csr(CVMX_AGL_GMX_BIST
);
451 if (agl_gmx_bist
.u64
)
452 dev_warn(p
->dev
, "AGL failed BIST (0x%016llx)\n",
453 (unsigned long long)agl_gmx_bist
.u64
);
456 struct octeon_mgmt_cam_state
{
462 static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state
*cs
,
467 for (i
= 0; i
< 6; i
++)
468 cs
->cam
[i
] |= (u64
)addr
[i
] << (8 * (cs
->cam_index
));
469 cs
->cam_mask
|= (1ULL << cs
->cam_index
);
473 static void octeon_mgmt_set_rx_filtering(struct net_device
*netdev
)
475 struct octeon_mgmt
*p
= netdev_priv(netdev
);
477 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl
;
478 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx
;
480 unsigned int prev_packet_enable
;
481 unsigned int cam_mode
= 1; /* 1 - Accept on CAM match */
482 unsigned int multicast_mode
= 1; /* 1 - Reject all multicast. */
483 struct octeon_mgmt_cam_state cam_state
;
484 struct netdev_hw_addr
*ha
;
485 int available_cam_entries
;
487 memset(&cam_state
, 0, sizeof(cam_state
));
489 if ((netdev
->flags
& IFF_PROMISC
) || netdev
->uc
.count
> 7) {
491 available_cam_entries
= 8;
494 * One CAM entry for the primary address, leaves seven
495 * for the secondary addresses.
497 available_cam_entries
= 7 - netdev
->uc
.count
;
500 if (netdev
->flags
& IFF_MULTICAST
) {
501 if (cam_mode
== 0 || (netdev
->flags
& IFF_ALLMULTI
) ||
502 netdev_mc_count(netdev
) > available_cam_entries
)
503 multicast_mode
= 2; /* 2 - Accept all multicast. */
505 multicast_mode
= 0; /* 0 - Use CAM. */
509 /* Add primary address. */
510 octeon_mgmt_cam_state_add(&cam_state
, netdev
->dev_addr
);
511 netdev_for_each_uc_addr(ha
, netdev
)
512 octeon_mgmt_cam_state_add(&cam_state
, ha
->addr
);
514 if (multicast_mode
== 0) {
515 netdev_for_each_mc_addr(ha
, netdev
)
516 octeon_mgmt_cam_state_add(&cam_state
, ha
->addr
);
520 spin_lock_irqsave(&p
->lock
, flags
);
522 /* Disable packet I/O. */
523 agl_gmx_prtx
.u64
= cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port
));
524 prev_packet_enable
= agl_gmx_prtx
.s
.en
;
525 agl_gmx_prtx
.s
.en
= 0;
526 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port
), agl_gmx_prtx
.u64
);
530 adr_ctl
.s
.cam_mode
= cam_mode
;
531 adr_ctl
.s
.mcst
= multicast_mode
;
532 adr_ctl
.s
.bcst
= 1; /* Allow broadcast */
534 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port
), adr_ctl
.u64
);
536 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port
), cam_state
.cam
[0]);
537 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port
), cam_state
.cam
[1]);
538 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port
), cam_state
.cam
[2]);
539 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port
), cam_state
.cam
[3]);
540 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port
), cam_state
.cam
[4]);
541 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port
), cam_state
.cam
[5]);
542 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port
), cam_state
.cam_mask
);
544 /* Restore packet I/O. */
545 agl_gmx_prtx
.s
.en
= prev_packet_enable
;
546 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port
), agl_gmx_prtx
.u64
);
548 spin_unlock_irqrestore(&p
->lock
, flags
);
551 static int octeon_mgmt_set_mac_address(struct net_device
*netdev
, void *addr
)
553 struct sockaddr
*sa
= addr
;
555 if (!is_valid_ether_addr(sa
->sa_data
))
556 return -EADDRNOTAVAIL
;
558 memcpy(netdev
->dev_addr
, sa
->sa_data
, ETH_ALEN
);
560 octeon_mgmt_set_rx_filtering(netdev
);
565 static int octeon_mgmt_change_mtu(struct net_device
*netdev
, int new_mtu
)
567 struct octeon_mgmt
*p
= netdev_priv(netdev
);
569 int size_without_fcs
= new_mtu
+ OCTEON_MGMT_RX_HEADROOM
;
572 * Limit the MTU to make sure the ethernet packets are between
573 * 64 bytes and 16383 bytes.
575 if (size_without_fcs
< 64 || size_without_fcs
> 16383) {
576 dev_warn(p
->dev
, "MTU must be between %d and %d.\n",
577 64 - OCTEON_MGMT_RX_HEADROOM
,
578 16383 - OCTEON_MGMT_RX_HEADROOM
);
582 netdev
->mtu
= new_mtu
;
584 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port
), size_without_fcs
);
585 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port
),
586 (size_without_fcs
+ 7) & 0xfff8);
591 static irqreturn_t
octeon_mgmt_interrupt(int cpl
, void *dev_id
)
593 struct net_device
*netdev
= dev_id
;
594 struct octeon_mgmt
*p
= netdev_priv(netdev
);
596 union cvmx_mixx_isr mixx_isr
;
598 mixx_isr
.u64
= cvmx_read_csr(CVMX_MIXX_ISR(port
));
600 /* Clear any pending interrupts */
601 cvmx_write_csr(CVMX_MIXX_ISR(port
), mixx_isr
.u64
);
602 cvmx_read_csr(CVMX_MIXX_ISR(port
));
604 if (mixx_isr
.s
.irthresh
) {
605 octeon_mgmt_disable_rx_irq(p
);
606 napi_schedule(&p
->napi
);
608 if (mixx_isr
.s
.orthresh
) {
609 octeon_mgmt_disable_tx_irq(p
);
610 tasklet_schedule(&p
->tx_clean_tasklet
);
616 static int octeon_mgmt_ioctl(struct net_device
*netdev
,
617 struct ifreq
*rq
, int cmd
)
619 struct octeon_mgmt
*p
= netdev_priv(netdev
);
621 if (!netif_running(netdev
))
627 return phy_mii_ioctl(p
->phydev
, if_mii(rq
), cmd
);
630 static void octeon_mgmt_adjust_link(struct net_device
*netdev
)
632 struct octeon_mgmt
*p
= netdev_priv(netdev
);
634 union cvmx_agl_gmx_prtx_cfg prtx_cfg
;
636 int link_changed
= 0;
638 spin_lock_irqsave(&p
->lock
, flags
);
639 if (p
->phydev
->link
) {
642 if (p
->last_duplex
!= p
->phydev
->duplex
) {
643 p
->last_duplex
= p
->phydev
->duplex
;
645 cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port
));
646 prtx_cfg
.s
.duplex
= p
->phydev
->duplex
;
647 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port
),
654 p
->last_link
= p
->phydev
->link
;
655 spin_unlock_irqrestore(&p
->lock
, flags
);
657 if (link_changed
!= 0) {
658 if (link_changed
> 0) {
659 netif_carrier_on(netdev
);
660 pr_info("%s: Link is up - %d/%s\n", netdev
->name
,
662 DUPLEX_FULL
== p
->phydev
->duplex
?
665 netif_carrier_off(netdev
);
666 pr_info("%s: Link is down\n", netdev
->name
);
671 static int octeon_mgmt_init_phy(struct net_device
*netdev
)
673 struct octeon_mgmt
*p
= netdev_priv(netdev
);
676 if (octeon_is_simulation()) {
677 /* No PHYs in the simulator. */
678 netif_carrier_on(netdev
);
682 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
, "0", p
->port
);
684 p
->phydev
= phy_connect(netdev
, phy_id
, octeon_mgmt_adjust_link
, 0,
685 PHY_INTERFACE_MODE_MII
);
687 if (IS_ERR(p
->phydev
)) {
692 phy_start_aneg(p
->phydev
);
697 static int octeon_mgmt_open(struct net_device
*netdev
)
699 struct octeon_mgmt
*p
= netdev_priv(netdev
);
701 union cvmx_mixx_ctl mix_ctl
;
702 union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode
;
703 union cvmx_mixx_oring1 oring1
;
704 union cvmx_mixx_iring1 iring1
;
705 union cvmx_agl_gmx_prtx_cfg prtx_cfg
;
706 union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl
;
707 union cvmx_mixx_irhwm mix_irhwm
;
708 union cvmx_mixx_orhwm mix_orhwm
;
709 union cvmx_mixx_intena mix_intena
;
712 /* Allocate ring buffers. */
713 p
->tx_ring
= kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE
),
718 dma_map_single(p
->dev
, p
->tx_ring
,
719 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE
),
722 p
->tx_next_clean
= 0;
723 p
->tx_current_fill
= 0;
726 p
->rx_ring
= kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE
),
731 dma_map_single(p
->dev
, p
->rx_ring
,
732 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE
),
737 p
->rx_current_fill
= 0;
739 octeon_mgmt_reset_hw(p
);
741 mix_ctl
.u64
= cvmx_read_csr(CVMX_MIXX_CTL(port
));
743 /* Bring it out of reset if needed. */
744 if (mix_ctl
.s
.reset
) {
746 cvmx_write_csr(CVMX_MIXX_CTL(port
), mix_ctl
.u64
);
748 mix_ctl
.u64
= cvmx_read_csr(CVMX_MIXX_CTL(port
));
749 } while (mix_ctl
.s
.reset
);
752 agl_gmx_inf_mode
.u64
= 0;
753 agl_gmx_inf_mode
.s
.en
= 1;
754 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE
, agl_gmx_inf_mode
.u64
);
757 oring1
.s
.obase
= p
->tx_ring_handle
>> 3;
758 oring1
.s
.osize
= OCTEON_MGMT_TX_RING_SIZE
;
759 cvmx_write_csr(CVMX_MIXX_ORING1(port
), oring1
.u64
);
762 iring1
.s
.ibase
= p
->rx_ring_handle
>> 3;
763 iring1
.s
.isize
= OCTEON_MGMT_RX_RING_SIZE
;
764 cvmx_write_csr(CVMX_MIXX_IRING1(port
), iring1
.u64
);
766 /* Disable packet I/O. */
767 prtx_cfg
.u64
= cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port
));
769 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port
), prtx_cfg
.u64
);
771 memcpy(sa
.sa_data
, netdev
->dev_addr
, ETH_ALEN
);
772 octeon_mgmt_set_mac_address(netdev
, &sa
);
774 octeon_mgmt_change_mtu(netdev
, netdev
->mtu
);
777 * Enable the port HW. Packets are not allowed until
778 * cvmx_mgmt_port_enable() is called.
781 mix_ctl
.s
.crc_strip
= 1; /* Strip the ending CRC */
782 mix_ctl
.s
.en
= 1; /* Enable the port */
783 mix_ctl
.s
.nbtarb
= 0; /* Arbitration mode */
784 /* MII CB-request FIFO programmable high watermark */
785 mix_ctl
.s
.mrq_hwm
= 1;
786 cvmx_write_csr(CVMX_MIXX_CTL(port
), mix_ctl
.u64
);
788 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X
)
789 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X
)) {
791 * Force compensation values, as they are not
792 * determined properly by HW
794 union cvmx_agl_gmx_drv_ctl drv_ctl
;
796 drv_ctl
.u64
= cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL
);
798 drv_ctl
.s
.byp_en1
= 1;
802 drv_ctl
.s
.byp_en
= 1;
806 cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL
, drv_ctl
.u64
);
809 octeon_mgmt_rx_fill_ring(netdev
);
811 /* Clear statistics. */
813 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port
), 1);
814 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port
), 0);
815 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port
), 0);
817 cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port
), 1);
818 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port
), 0);
819 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port
), 0);
821 /* Clear any pending interrupts */
822 cvmx_write_csr(CVMX_MIXX_ISR(port
), cvmx_read_csr(CVMX_MIXX_ISR(port
)));
824 if (request_irq(p
->irq
, octeon_mgmt_interrupt
, 0, netdev
->name
,
826 dev_err(p
->dev
, "request_irq(%d) failed.\n", p
->irq
);
830 /* Interrupt every single RX packet */
832 mix_irhwm
.s
.irhwm
= 0;
833 cvmx_write_csr(CVMX_MIXX_IRHWM(port
), mix_irhwm
.u64
);
835 /* Interrupt when we have 1 or more packets to clean. */
837 mix_orhwm
.s
.orhwm
= 1;
838 cvmx_write_csr(CVMX_MIXX_ORHWM(port
), mix_orhwm
.u64
);
840 /* Enable receive and transmit interrupts */
842 mix_intena
.s
.ithena
= 1;
843 mix_intena
.s
.othena
= 1;
844 cvmx_write_csr(CVMX_MIXX_INTENA(port
), mix_intena
.u64
);
847 /* Enable packet I/O. */
850 rxx_frm_ctl
.s
.pre_align
= 1;
852 * When set, disables the length check for non-min sized pkts
853 * with padding in the client data.
855 rxx_frm_ctl
.s
.pad_len
= 1;
856 /* When set, disables the length check for VLAN pkts */
857 rxx_frm_ctl
.s
.vlan_len
= 1;
858 /* When set, PREAMBLE checking is less strict */
859 rxx_frm_ctl
.s
.pre_free
= 1;
860 /* Control Pause Frames can match station SMAC */
861 rxx_frm_ctl
.s
.ctl_smac
= 0;
862 /* Control Pause Frames can match globally assign Multicast address */
863 rxx_frm_ctl
.s
.ctl_mcst
= 1;
864 /* Forward pause information to TX block */
865 rxx_frm_ctl
.s
.ctl_bck
= 1;
866 /* Drop Control Pause Frames */
867 rxx_frm_ctl
.s
.ctl_drp
= 1;
868 /* Strip off the preamble */
869 rxx_frm_ctl
.s
.pre_strp
= 1;
871 * This port is configured to send PREAMBLE+SFD to begin every
872 * frame. GMX checks that the PREAMBLE is sent correctly.
874 rxx_frm_ctl
.s
.pre_chk
= 1;
875 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port
), rxx_frm_ctl
.u64
);
877 /* Enable the AGL block */
878 agl_gmx_inf_mode
.u64
= 0;
879 agl_gmx_inf_mode
.s
.en
= 1;
880 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE
, agl_gmx_inf_mode
.u64
);
882 /* Configure the port duplex and enables */
883 prtx_cfg
.u64
= cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port
));
884 prtx_cfg
.s
.tx_en
= 1;
885 prtx_cfg
.s
.rx_en
= 1;
888 prtx_cfg
.s
.duplex
= p
->last_duplex
;
889 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port
), prtx_cfg
.u64
);
892 netif_carrier_off(netdev
);
894 if (octeon_mgmt_init_phy(netdev
)) {
895 dev_err(p
->dev
, "Cannot initialize PHY.\n");
899 netif_wake_queue(netdev
);
900 napi_enable(&p
->napi
);
904 octeon_mgmt_reset_hw(p
);
905 dma_unmap_single(p
->dev
, p
->rx_ring_handle
,
906 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE
),
910 dma_unmap_single(p
->dev
, p
->tx_ring_handle
,
911 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE
),
917 static int octeon_mgmt_stop(struct net_device
*netdev
)
919 struct octeon_mgmt
*p
= netdev_priv(netdev
);
921 napi_disable(&p
->napi
);
922 netif_stop_queue(netdev
);
925 phy_disconnect(p
->phydev
);
927 netif_carrier_off(netdev
);
929 octeon_mgmt_reset_hw(p
);
932 free_irq(p
->irq
, netdev
);
934 /* dma_unmap is a nop on Octeon, so just free everything. */
935 skb_queue_purge(&p
->tx_list
);
936 skb_queue_purge(&p
->rx_list
);
938 dma_unmap_single(p
->dev
, p
->rx_ring_handle
,
939 ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE
),
943 dma_unmap_single(p
->dev
, p
->tx_ring_handle
,
944 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE
),
952 static int octeon_mgmt_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
954 struct octeon_mgmt
*p
= netdev_priv(netdev
);
956 union mgmt_port_ring_entry re
;
958 int rv
= NETDEV_TX_BUSY
;
962 re
.s
.addr
= dma_map_single(p
->dev
, skb
->data
,
966 spin_lock_irqsave(&p
->tx_list
.lock
, flags
);
968 if (unlikely(p
->tx_current_fill
>= ring_max_fill(OCTEON_MGMT_TX_RING_SIZE
) - 1)) {
969 spin_unlock_irqrestore(&p
->tx_list
.lock
, flags
);
970 netif_stop_queue(netdev
);
971 spin_lock_irqsave(&p
->tx_list
.lock
, flags
);
974 if (unlikely(p
->tx_current_fill
>=
975 ring_max_fill(OCTEON_MGMT_TX_RING_SIZE
))) {
976 spin_unlock_irqrestore(&p
->tx_list
.lock
, flags
);
977 dma_unmap_single(p
->dev
, re
.s
.addr
, re
.s
.len
,
982 __skb_queue_tail(&p
->tx_list
, skb
);
984 /* Put it in the ring. */
985 p
->tx_ring
[p
->tx_next
] = re
.d64
;
986 p
->tx_next
= (p
->tx_next
+ 1) % OCTEON_MGMT_TX_RING_SIZE
;
987 p
->tx_current_fill
++;
989 spin_unlock_irqrestore(&p
->tx_list
.lock
, flags
);
991 dma_sync_single_for_device(p
->dev
, p
->tx_ring_handle
,
992 ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE
),
995 netdev
->stats
.tx_packets
++;
996 netdev
->stats
.tx_bytes
+= skb
->len
;
999 cvmx_write_csr(CVMX_MIXX_ORING2(port
), 1);
1001 netdev
->trans_start
= jiffies
;
1004 octeon_mgmt_update_tx_stats(netdev
);
1008 #ifdef CONFIG_NET_POLL_CONTROLLER
1009 static void octeon_mgmt_poll_controller(struct net_device
*netdev
)
1011 struct octeon_mgmt
*p
= netdev_priv(netdev
);
1013 octeon_mgmt_receive_packets(p
, 16);
1014 octeon_mgmt_update_rx_stats(netdev
);
1019 static void octeon_mgmt_get_drvinfo(struct net_device
*netdev
,
1020 struct ethtool_drvinfo
*info
)
1022 strncpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
1023 strncpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
1024 strncpy(info
->fw_version
, "N/A", sizeof(info
->fw_version
));
1025 strncpy(info
->bus_info
, "N/A", sizeof(info
->bus_info
));
1027 info
->testinfo_len
= 0;
1028 info
->regdump_len
= 0;
1029 info
->eedump_len
= 0;
1032 static int octeon_mgmt_get_settings(struct net_device
*netdev
,
1033 struct ethtool_cmd
*cmd
)
1035 struct octeon_mgmt
*p
= netdev_priv(netdev
);
1038 return phy_ethtool_gset(p
->phydev
, cmd
);
1043 static int octeon_mgmt_set_settings(struct net_device
*netdev
,
1044 struct ethtool_cmd
*cmd
)
1046 struct octeon_mgmt
*p
= netdev_priv(netdev
);
1048 if (!capable(CAP_NET_ADMIN
))
1052 return phy_ethtool_sset(p
->phydev
, cmd
);
1057 static const struct ethtool_ops octeon_mgmt_ethtool_ops
= {
1058 .get_drvinfo
= octeon_mgmt_get_drvinfo
,
1059 .get_link
= ethtool_op_get_link
,
1060 .get_settings
= octeon_mgmt_get_settings
,
1061 .set_settings
= octeon_mgmt_set_settings
1064 static const struct net_device_ops octeon_mgmt_ops
= {
1065 .ndo_open
= octeon_mgmt_open
,
1066 .ndo_stop
= octeon_mgmt_stop
,
1067 .ndo_start_xmit
= octeon_mgmt_xmit
,
1068 .ndo_set_rx_mode
= octeon_mgmt_set_rx_filtering
,
1069 .ndo_set_multicast_list
= octeon_mgmt_set_rx_filtering
,
1070 .ndo_set_mac_address
= octeon_mgmt_set_mac_address
,
1071 .ndo_do_ioctl
= octeon_mgmt_ioctl
,
1072 .ndo_change_mtu
= octeon_mgmt_change_mtu
,
1073 #ifdef CONFIG_NET_POLL_CONTROLLER
1074 .ndo_poll_controller
= octeon_mgmt_poll_controller
,
1078 static int __init
octeon_mgmt_probe(struct platform_device
*pdev
)
1080 struct resource
*res_irq
;
1081 struct net_device
*netdev
;
1082 struct octeon_mgmt
*p
;
1085 netdev
= alloc_etherdev(sizeof(struct octeon_mgmt
));
1089 dev_set_drvdata(&pdev
->dev
, netdev
);
1090 p
= netdev_priv(netdev
);
1091 netif_napi_add(netdev
, &p
->napi
, octeon_mgmt_napi_poll
,
1092 OCTEON_MGMT_NAPI_WEIGHT
);
1095 p
->dev
= &pdev
->dev
;
1098 snprintf(netdev
->name
, IFNAMSIZ
, "mgmt%d", p
->port
);
1100 res_irq
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1104 p
->irq
= res_irq
->start
;
1105 spin_lock_init(&p
->lock
);
1107 skb_queue_head_init(&p
->tx_list
);
1108 skb_queue_head_init(&p
->rx_list
);
1109 tasklet_init(&p
->tx_clean_tasklet
,
1110 octeon_mgmt_clean_tx_tasklet
, (unsigned long)p
);
1112 netdev
->netdev_ops
= &octeon_mgmt_ops
;
1113 netdev
->ethtool_ops
= &octeon_mgmt_ethtool_ops
;
1116 /* The mgmt ports get the first N MACs. */
1117 for (i
= 0; i
< 6; i
++)
1118 netdev
->dev_addr
[i
] = octeon_bootinfo
->mac_addr_base
[i
];
1119 netdev
->dev_addr
[5] += p
->port
;
1121 if (p
->port
>= octeon_bootinfo
->mac_addr_count
)
1123 "Error %s: Using MAC outside of the assigned range: %pM\n",
1124 netdev
->name
, netdev
->dev_addr
);
1126 if (register_netdev(netdev
))
1129 dev_info(&pdev
->dev
, "Version " DRV_VERSION
"\n");
1132 free_netdev(netdev
);
1136 static int __exit
octeon_mgmt_remove(struct platform_device
*pdev
)
1138 struct net_device
*netdev
= dev_get_drvdata(&pdev
->dev
);
1140 unregister_netdev(netdev
);
1141 free_netdev(netdev
);
1145 static struct platform_driver octeon_mgmt_driver
= {
1147 .name
= "octeon_mgmt",
1148 .owner
= THIS_MODULE
,
1150 .probe
= octeon_mgmt_probe
,
1151 .remove
= __exit_p(octeon_mgmt_remove
),
1154 extern void octeon_mdiobus_force_mod_depencency(void);
1156 static int __init
octeon_mgmt_mod_init(void)
1158 /* Force our mdiobus driver module to be loaded first. */
1159 octeon_mdiobus_force_mod_depencency();
1160 return platform_driver_register(&octeon_mgmt_driver
);
1163 static void __exit
octeon_mgmt_mod_exit(void)
1165 platform_driver_unregister(&octeon_mgmt_driver
);
1168 module_init(octeon_mgmt_mod_init
);
1169 module_exit(octeon_mgmt_mod_exit
);
1171 MODULE_DESCRIPTION(DRV_DESCRIPTION
);
1172 MODULE_AUTHOR("David Daney");
1173 MODULE_LICENSE("GPL");
1174 MODULE_VERSION(DRV_VERSION
);