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drm/i915: don't unlock panel regs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
blob103a60b3cad4775d5db338ca682e552534953d48
1 /*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE 9
44
45 #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46 #define IS_PCH_eDP(i) ((i)->is_pch_edp)
47
48 struct intel_dp {
49 struct intel_encoder base;
50 uint32_t output_reg;
51 uint32_t DP;
52 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
53 bool has_audio;
54 int dpms_mode;
55 uint8_t link_bw;
56 uint8_t lane_count;
57 uint8_t dpcd[4];
58 struct i2c_adapter adapter;
59 struct i2c_algo_dp_aux_data algo;
60 bool is_pch_edp;
61 uint8_t train_set[4];
62 uint8_t link_status[DP_LINK_STATUS_SIZE];
63 };
64
65 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
66 {
67 return container_of(encoder, struct intel_dp, base.base);
68 }
69
70 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
71 {
72 return container_of(intel_attached_encoder(connector),
73 struct intel_dp, base);
74 }
75
76 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
77 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
78 static void intel_dp_link_down(struct intel_dp *intel_dp);
79
80 void
81 intel_edp_link_config (struct intel_encoder *intel_encoder,
82 int *lane_num, int *link_bw)
83 {
84 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
85
86 *lane_num = intel_dp->lane_count;
87 if (intel_dp->link_bw == DP_LINK_BW_1_62)
88 *link_bw = 162000;
89 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
90 *link_bw = 270000;
91 }
92
93 static int
94 intel_dp_max_lane_count(struct intel_dp *intel_dp)
95 {
96 int max_lane_count = 4;
97
98 if (intel_dp->dpcd[0] >= 0x11) {
99 max_lane_count = intel_dp->dpcd[2] & 0x1f;
100 switch (max_lane_count) {
101 case 1: case 2: case 4:
102 break;
103 default:
104 max_lane_count = 4;
105 }
106 }
107 return max_lane_count;
108 }
109
110 static int
111 intel_dp_max_link_bw(struct intel_dp *intel_dp)
112 {
113 int max_link_bw = intel_dp->dpcd[1];
114
115 switch (max_link_bw) {
116 case DP_LINK_BW_1_62:
117 case DP_LINK_BW_2_7:
118 break;
119 default:
120 max_link_bw = DP_LINK_BW_1_62;
121 break;
122 }
123 return max_link_bw;
124 }
125
126 static int
127 intel_dp_link_clock(uint8_t link_bw)
128 {
129 if (link_bw == DP_LINK_BW_2_7)
130 return 270000;
131 else
132 return 162000;
133 }
134
135 /* I think this is a fiction */
136 static int
137 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
138 {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140
141 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
142 return (pixel_clock * dev_priv->edp_bpp) / 8;
143 else
144 return pixel_clock * 3;
145 }
146
147 static int
148 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
149 {
150 return (max_link_clock * max_lanes * 8) / 10;
151 }
152
153 static int
154 intel_dp_mode_valid(struct drm_connector *connector,
155 struct drm_display_mode *mode)
156 {
157 struct intel_dp *intel_dp = intel_attached_dp(connector);
158 struct drm_device *dev = connector->dev;
159 struct drm_i915_private *dev_priv = dev->dev_private;
160 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
161 int max_lanes = intel_dp_max_lane_count(intel_dp);
162
163 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
164 dev_priv->panel_fixed_mode) {
165 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
166 return MODE_PANEL;
167
168 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
169 return MODE_PANEL;
170 }
171
172 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
173 which are outside spec tolerances but somehow work by magic */
174 if (!IS_eDP(intel_dp) &&
175 (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
176 > intel_dp_max_data_rate(max_link_clock, max_lanes)))
177 return MODE_CLOCK_HIGH;
178
179 if (mode->clock < 10000)
180 return MODE_CLOCK_LOW;
181
182 return MODE_OK;
183 }
184
185 static uint32_t
186 pack_aux(uint8_t *src, int src_bytes)
187 {
188 int i;
189 uint32_t v = 0;
190
191 if (src_bytes > 4)
192 src_bytes = 4;
193 for (i = 0; i < src_bytes; i++)
194 v |= ((uint32_t) src[i]) << ((3-i) * 8);
195 return v;
196 }
197
198 static void
199 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
200 {
201 int i;
202 if (dst_bytes > 4)
203 dst_bytes = 4;
204 for (i = 0; i < dst_bytes; i++)
205 dst[i] = src >> ((3-i) * 8);
206 }
207
208 /* hrawclock is 1/4 the FSB frequency */
209 static int
210 intel_hrawclk(struct drm_device *dev)
211 {
212 struct drm_i915_private *dev_priv = dev->dev_private;
213 uint32_t clkcfg;
214
215 clkcfg = I915_READ(CLKCFG);
216 switch (clkcfg & CLKCFG_FSB_MASK) {
217 case CLKCFG_FSB_400:
218 return 100;
219 case CLKCFG_FSB_533:
220 return 133;
221 case CLKCFG_FSB_667:
222 return 166;
223 case CLKCFG_FSB_800:
224 return 200;
225 case CLKCFG_FSB_1067:
226 return 266;
227 case CLKCFG_FSB_1333:
228 return 333;
229 /* these two are just a guess; one of them might be right */
230 case CLKCFG_FSB_1600:
231 case CLKCFG_FSB_1600_ALT:
232 return 400;
233 default:
234 return 133;
235 }
236 }
237
238 static int
239 intel_dp_aux_ch(struct intel_dp *intel_dp,
240 uint8_t *send, int send_bytes,
241 uint8_t *recv, int recv_size)
242 {
243 uint32_t output_reg = intel_dp->output_reg;
244 struct drm_device *dev = intel_dp->base.base.dev;
245 struct drm_i915_private *dev_priv = dev->dev_private;
246 uint32_t ch_ctl = output_reg + 0x10;
247 uint32_t ch_data = ch_ctl + 4;
248 int i;
249 int recv_bytes;
250 uint32_t status;
251 uint32_t aux_clock_divider;
252 int try, precharge;
253
254 /* The clock divider is based off the hrawclk,
255 * and would like to run at 2MHz. So, take the
256 * hrawclk value and divide by 2 and use that
257 *
258 * Note that PCH attached eDP panels should use a 125MHz input
259 * clock divider.
260 */
261 if (IS_eDP(intel_dp) && !IS_PCH_eDP(intel_dp)) {
262 if (IS_GEN6(dev))
263 aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
264 else
265 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
266 } else if (HAS_PCH_SPLIT(dev))
267 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
268 else
269 aux_clock_divider = intel_hrawclk(dev) / 2;
270
271 if (IS_GEN6(dev))
272 precharge = 3;
273 else
274 precharge = 5;
275
276 if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
277 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
278 I915_READ(ch_ctl));
279 return -EBUSY;
280 }
281
282 /* Must try at least 3 times according to DP spec */
283 for (try = 0; try < 5; try++) {
284 /* Load the send data into the aux channel data registers */
285 for (i = 0; i < send_bytes; i += 4)
286 I915_WRITE(ch_data + i,
287 pack_aux(send + i, send_bytes - i));
288
289 /* Send the command and wait for it to complete */
290 I915_WRITE(ch_ctl,
291 DP_AUX_CH_CTL_SEND_BUSY |
292 DP_AUX_CH_CTL_TIME_OUT_400us |
293 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
294 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
295 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
296 DP_AUX_CH_CTL_DONE |
297 DP_AUX_CH_CTL_TIME_OUT_ERROR |
298 DP_AUX_CH_CTL_RECEIVE_ERROR);
299 for (;;) {
300 status = I915_READ(ch_ctl);
301 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
302 break;
303 udelay(100);
304 }
305
306 /* Clear done status and any errors */
307 I915_WRITE(ch_ctl,
308 status |
309 DP_AUX_CH_CTL_DONE |
310 DP_AUX_CH_CTL_TIME_OUT_ERROR |
311 DP_AUX_CH_CTL_RECEIVE_ERROR);
312 if (status & DP_AUX_CH_CTL_DONE)
313 break;
314 }
315
316 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
317 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
318 return -EBUSY;
319 }
320
321 /* Check for timeout or receive error.
322 * Timeouts occur when the sink is not connected
323 */
324 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
325 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
326 return -EIO;
327 }
328
329 /* Timeouts occur when the device isn't connected, so they're
330 * "normal" -- don't fill the kernel log with these */
331 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
332 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
333 return -ETIMEDOUT;
334 }
335
336 /* Unload any bytes sent back from the other side */
337 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
338 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
339 if (recv_bytes > recv_size)
340 recv_bytes = recv_size;
341
342 for (i = 0; i < recv_bytes; i += 4)
343 unpack_aux(I915_READ(ch_data + i),
344 recv + i, recv_bytes - i);
345
346 return recv_bytes;
347 }
348
349 /* Write data to the aux channel in native mode */
350 static int
351 intel_dp_aux_native_write(struct intel_dp *intel_dp,
352 uint16_t address, uint8_t *send, int send_bytes)
353 {
354 int ret;
355 uint8_t msg[20];
356 int msg_bytes;
357 uint8_t ack;
358
359 if (send_bytes > 16)
360 return -1;
361 msg[0] = AUX_NATIVE_WRITE << 4;
362 msg[1] = address >> 8;
363 msg[2] = address & 0xff;
364 msg[3] = send_bytes - 1;
365 memcpy(&msg[4], send, send_bytes);
366 msg_bytes = send_bytes + 4;
367 for (;;) {
368 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
369 if (ret < 0)
370 return ret;
371 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
372 break;
373 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
374 udelay(100);
375 else
376 return -EIO;
377 }
378 return send_bytes;
379 }
380
381 /* Write a single byte to the aux channel in native mode */
382 static int
383 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
384 uint16_t address, uint8_t byte)
385 {
386 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
387 }
388
389 /* read bytes from a native aux channel */
390 static int
391 intel_dp_aux_native_read(struct intel_dp *intel_dp,
392 uint16_t address, uint8_t *recv, int recv_bytes)
393 {
394 uint8_t msg[4];
395 int msg_bytes;
396 uint8_t reply[20];
397 int reply_bytes;
398 uint8_t ack;
399 int ret;
400
401 msg[0] = AUX_NATIVE_READ << 4;
402 msg[1] = address >> 8;
403 msg[2] = address & 0xff;
404 msg[3] = recv_bytes - 1;
405
406 msg_bytes = 4;
407 reply_bytes = recv_bytes + 1;
408
409 for (;;) {
410 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
411 reply, reply_bytes);
412 if (ret == 0)
413 return -EPROTO;
414 if (ret < 0)
415 return ret;
416 ack = reply[0];
417 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
418 memcpy(recv, reply + 1, ret - 1);
419 return ret - 1;
420 }
421 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
422 udelay(100);
423 else
424 return -EIO;
425 }
426 }
427
428 static int
429 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
430 uint8_t write_byte, uint8_t *read_byte)
431 {
432 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
433 struct intel_dp *intel_dp = container_of(adapter,
434 struct intel_dp,
435 adapter);
436 uint16_t address = algo_data->address;
437 uint8_t msg[5];
438 uint8_t reply[2];
439 int msg_bytes;
440 int reply_bytes;
441 int ret;
442
443 /* Set up the command byte */
444 if (mode & MODE_I2C_READ)
445 msg[0] = AUX_I2C_READ << 4;
446 else
447 msg[0] = AUX_I2C_WRITE << 4;
448
449 if (!(mode & MODE_I2C_STOP))
450 msg[0] |= AUX_I2C_MOT << 4;
451
452 msg[1] = address >> 8;
453 msg[2] = address;
454
455 switch (mode) {
456 case MODE_I2C_WRITE:
457 msg[3] = 0;
458 msg[4] = write_byte;
459 msg_bytes = 5;
460 reply_bytes = 1;
461 break;
462 case MODE_I2C_READ:
463 msg[3] = 0;
464 msg_bytes = 4;
465 reply_bytes = 2;
466 break;
467 default:
468 msg_bytes = 3;
469 reply_bytes = 1;
470 break;
471 }
472
473 for (;;) {
474 ret = intel_dp_aux_ch(intel_dp,
475 msg, msg_bytes,
476 reply, reply_bytes);
477 if (ret < 0) {
478 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
479 return ret;
480 }
481 switch (reply[0] & AUX_I2C_REPLY_MASK) {
482 case AUX_I2C_REPLY_ACK:
483 if (mode == MODE_I2C_READ) {
484 *read_byte = reply[1];
485 }
486 return reply_bytes - 1;
487 case AUX_I2C_REPLY_NACK:
488 DRM_DEBUG_KMS("aux_ch nack\n");
489 return -EREMOTEIO;
490 case AUX_I2C_REPLY_DEFER:
491 DRM_DEBUG_KMS("aux_ch defer\n");
492 udelay(100);
493 break;
494 default:
495 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
496 return -EREMOTEIO;
497 }
498 }
499 }
500
501 static int
502 intel_dp_i2c_init(struct intel_dp *intel_dp,
503 struct intel_connector *intel_connector, const char *name)
504 {
505 DRM_DEBUG_KMS("i2c_init %s\n", name);
506 intel_dp->algo.running = false;
507 intel_dp->algo.address = 0;
508 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
509
510 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
511 intel_dp->adapter.owner = THIS_MODULE;
512 intel_dp->adapter.class = I2C_CLASS_DDC;
513 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
514 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
515 intel_dp->adapter.algo_data = &intel_dp->algo;
516 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
517
518 return i2c_dp_aux_add_bus(&intel_dp->adapter);
519 }
520
521 static bool
522 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
523 struct drm_display_mode *adjusted_mode)
524 {
525 struct drm_device *dev = encoder->dev;
526 struct drm_i915_private *dev_priv = dev->dev_private;
527 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
528 int lane_count, clock;
529 int max_lane_count = intel_dp_max_lane_count(intel_dp);
530 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
531 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
532
533 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
534 dev_priv->panel_fixed_mode) {
535 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
536 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
537 mode, adjusted_mode);
538 /*
539 * the mode->clock is used to calculate the Data&Link M/N
540 * of the pipe. For the eDP the fixed clock should be used.
541 */
542 mode->clock = dev_priv->panel_fixed_mode->clock;
543 }
544
545 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
546 for (clock = 0; clock <= max_clock; clock++) {
547 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
548
549 if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
550 <= link_avail) {
551 intel_dp->link_bw = bws[clock];
552 intel_dp->lane_count = lane_count;
553 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
554 DRM_DEBUG_KMS("Display port link bw %02x lane "
555 "count %d clock %d\n",
556 intel_dp->link_bw, intel_dp->lane_count,
557 adjusted_mode->clock);
558 return true;
559 }
560 }
561 }
562
563 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
564 /* okay we failed just pick the highest */
565 intel_dp->lane_count = max_lane_count;
566 intel_dp->link_bw = bws[max_clock];
567 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
568 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
569 "count %d clock %d\n",
570 intel_dp->link_bw, intel_dp->lane_count,
571 adjusted_mode->clock);
572
573 return true;
574 }
575
576 return false;
577 }
578
579 struct intel_dp_m_n {
580 uint32_t tu;
581 uint32_t gmch_m;
582 uint32_t gmch_n;
583 uint32_t link_m;
584 uint32_t link_n;
585 };
586
587 static void
588 intel_reduce_ratio(uint32_t *num, uint32_t *den)
589 {
590 while (*num > 0xffffff || *den > 0xffffff) {
591 *num >>= 1;
592 *den >>= 1;
593 }
594 }
595
596 static void
597 intel_dp_compute_m_n(int bpp,
598 int nlanes,
599 int pixel_clock,
600 int link_clock,
601 struct intel_dp_m_n *m_n)
602 {
603 m_n->tu = 64;
604 m_n->gmch_m = (pixel_clock * bpp) >> 3;
605 m_n->gmch_n = link_clock * nlanes;
606 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
607 m_n->link_m = pixel_clock;
608 m_n->link_n = link_clock;
609 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
610 }
611
612 bool intel_pch_has_edp(struct drm_crtc *crtc)
613 {
614 struct drm_device *dev = crtc->dev;
615 struct drm_mode_config *mode_config = &dev->mode_config;
616 struct drm_encoder *encoder;
617
618 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
619 struct intel_dp *intel_dp;
620
621 if (encoder->crtc != crtc)
622 continue;
623
624 intel_dp = enc_to_intel_dp(encoder);
625 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
626 return intel_dp->is_pch_edp;
627 }
628 return false;
629 }
630
631 void
632 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
633 struct drm_display_mode *adjusted_mode)
634 {
635 struct drm_device *dev = crtc->dev;
636 struct drm_mode_config *mode_config = &dev->mode_config;
637 struct drm_encoder *encoder;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
640 int lane_count = 4, bpp = 24;
641 struct intel_dp_m_n m_n;
642
643 /*
644 * Find the lane count in the intel_encoder private
645 */
646 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
647 struct intel_dp *intel_dp;
648
649 if (encoder->crtc != crtc)
650 continue;
651
652 intel_dp = enc_to_intel_dp(encoder);
653 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
654 lane_count = intel_dp->lane_count;
655 if (IS_PCH_eDP(intel_dp))
656 bpp = dev_priv->edp_bpp;
657 break;
658 }
659 }
660
661 /*
662 * Compute the GMCH and Link ratios. The '3' here is
663 * the number of bytes_per_pixel post-LUT, which we always
664 * set up for 8-bits of R/G/B, or 3 bytes total.
665 */
666 intel_dp_compute_m_n(bpp, lane_count,
667 mode->clock, adjusted_mode->clock, &m_n);
668
669 if (HAS_PCH_SPLIT(dev)) {
670 if (intel_crtc->pipe == 0) {
671 I915_WRITE(TRANSA_DATA_M1,
672 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
673 m_n.gmch_m);
674 I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
675 I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
676 I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
677 } else {
678 I915_WRITE(TRANSB_DATA_M1,
679 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
680 m_n.gmch_m);
681 I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
682 I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
683 I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
684 }
685 } else {
686 if (intel_crtc->pipe == 0) {
687 I915_WRITE(PIPEA_GMCH_DATA_M,
688 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
689 m_n.gmch_m);
690 I915_WRITE(PIPEA_GMCH_DATA_N,
691 m_n.gmch_n);
692 I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
693 I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
694 } else {
695 I915_WRITE(PIPEB_GMCH_DATA_M,
696 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
697 m_n.gmch_m);
698 I915_WRITE(PIPEB_GMCH_DATA_N,
699 m_n.gmch_n);
700 I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
701 I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
702 }
703 }
704 }
705
706 static void
707 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
708 struct drm_display_mode *adjusted_mode)
709 {
710 struct drm_device *dev = encoder->dev;
711 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
712 struct drm_crtc *crtc = intel_dp->base.base.crtc;
713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
714
715 intel_dp->DP = (DP_VOLTAGE_0_4 |
716 DP_PRE_EMPHASIS_0);
717
718 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
719 intel_dp->DP |= DP_SYNC_HS_HIGH;
720 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
721 intel_dp->DP |= DP_SYNC_VS_HIGH;
722
723 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
724 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
725 else
726 intel_dp->DP |= DP_LINK_TRAIN_OFF;
727
728 switch (intel_dp->lane_count) {
729 case 1:
730 intel_dp->DP |= DP_PORT_WIDTH_1;
731 break;
732 case 2:
733 intel_dp->DP |= DP_PORT_WIDTH_2;
734 break;
735 case 4:
736 intel_dp->DP |= DP_PORT_WIDTH_4;
737 break;
738 }
739 if (intel_dp->has_audio)
740 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
741
742 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
743 intel_dp->link_configuration[0] = intel_dp->link_bw;
744 intel_dp->link_configuration[1] = intel_dp->lane_count;
745
746 /*
747 * Check for DPCD version > 1.1 and enhanced framing support
748 */
749 if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
750 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
751 intel_dp->DP |= DP_ENHANCED_FRAMING;
752 }
753
754 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
755 if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
756 intel_dp->DP |= DP_PIPEB_SELECT;
757
758 if (IS_eDP(intel_dp)) {
759 /* don't miss out required setting for eDP */
760 intel_dp->DP |= DP_PLL_ENABLE;
761 if (adjusted_mode->clock < 200000)
762 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
763 else
764 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
765 }
766 }
767
768 /* Returns true if the panel was already on when called */
769 static bool ironlake_edp_panel_on (struct drm_device *dev)
770 {
771 struct drm_i915_private *dev_priv = dev->dev_private;
772 u32 pp;
773
774 if (I915_READ(PCH_PP_STATUS) & PP_ON)
775 return true;
776
777 pp = I915_READ(PCH_PP_CONTROL);
778
779 /* ILK workaround: disable reset around power sequence */
780 pp &= ~PANEL_POWER_RESET;
781 I915_WRITE(PCH_PP_CONTROL, pp);
782 POSTING_READ(PCH_PP_CONTROL);
783
784 pp |= POWER_TARGET_ON;
785 I915_WRITE(PCH_PP_CONTROL, pp);
786
787 if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000))
788 DRM_ERROR("panel on wait timed out: 0x%08x\n",
789 I915_READ(PCH_PP_STATUS));
790
791 pp &= ~(PANEL_UNLOCK_REGS);
792 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
793 I915_WRITE(PCH_PP_CONTROL, pp);
794 POSTING_READ(PCH_PP_CONTROL);
795
796 return false;
797 }
798
799 static void ironlake_edp_panel_off (struct drm_device *dev)
800 {
801 struct drm_i915_private *dev_priv = dev->dev_private;
802 u32 pp;
803
804 pp = I915_READ(PCH_PP_CONTROL);
805
806 /* ILK workaround: disable reset around power sequence */
807 pp &= ~PANEL_POWER_RESET;
808 I915_WRITE(PCH_PP_CONTROL, pp);
809 POSTING_READ(PCH_PP_CONTROL);
810
811 pp &= ~POWER_TARGET_ON;
812 I915_WRITE(PCH_PP_CONTROL, pp);
813
814 if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000))
815 DRM_ERROR("panel off wait timed out: 0x%08x\n",
816 I915_READ(PCH_PP_STATUS));
817
818 /* Make sure VDD is enabled so DP AUX will work */
819 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
820 I915_WRITE(PCH_PP_CONTROL, pp);
821 POSTING_READ(PCH_PP_CONTROL);
822 }
823
824 static void ironlake_edp_panel_vdd_on(struct drm_device *dev)
825 {
826 struct drm_i915_private *dev_priv = dev->dev_private;
827 u32 pp;
828
829 pp = I915_READ(PCH_PP_CONTROL);
830 pp |= EDP_FORCE_VDD;
831 I915_WRITE(PCH_PP_CONTROL, pp);
832 POSTING_READ(PCH_PP_CONTROL);
833 msleep(300);
834 }
835
836 static void ironlake_edp_panel_vdd_off(struct drm_device *dev)
837 {
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 u32 pp;
840
841 pp = I915_READ(PCH_PP_CONTROL);
842 pp &= ~EDP_FORCE_VDD;
843 I915_WRITE(PCH_PP_CONTROL, pp);
844 POSTING_READ(PCH_PP_CONTROL);
845 msleep(300);
846 }
847
848 static void ironlake_edp_backlight_on (struct drm_device *dev)
849 {
850 struct drm_i915_private *dev_priv = dev->dev_private;
851 u32 pp;
852
853 DRM_DEBUG_KMS("\n");
854 pp = I915_READ(PCH_PP_CONTROL);
855 pp |= EDP_BLC_ENABLE;
856 I915_WRITE(PCH_PP_CONTROL, pp);
857 }
858
859 static void ironlake_edp_backlight_off (struct drm_device *dev)
860 {
861 struct drm_i915_private *dev_priv = dev->dev_private;
862 u32 pp;
863
864 DRM_DEBUG_KMS("\n");
865 pp = I915_READ(PCH_PP_CONTROL);
866 pp &= ~EDP_BLC_ENABLE;
867 I915_WRITE(PCH_PP_CONTROL, pp);
868 }
869
870 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
871 {
872 struct drm_device *dev = encoder->dev;
873 struct drm_i915_private *dev_priv = dev->dev_private;
874 u32 dpa_ctl;
875
876 DRM_DEBUG_KMS("\n");
877 dpa_ctl = I915_READ(DP_A);
878 dpa_ctl &= ~DP_PLL_ENABLE;
879 I915_WRITE(DP_A, dpa_ctl);
880 }
881
882 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
883 {
884 struct drm_device *dev = encoder->dev;
885 struct drm_i915_private *dev_priv = dev->dev_private;
886 u32 dpa_ctl;
887
888 dpa_ctl = I915_READ(DP_A);
889 dpa_ctl |= DP_PLL_ENABLE;
890 I915_WRITE(DP_A, dpa_ctl);
891 POSTING_READ(DP_A);
892 udelay(200);
893 }
894
895 static void intel_dp_prepare(struct drm_encoder *encoder)
896 {
897 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
898 struct drm_device *dev = encoder->dev;
899 struct drm_i915_private *dev_priv = dev->dev_private;
900 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
901
902 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
903 ironlake_edp_panel_off(dev);
904 ironlake_edp_backlight_off(dev);
905 ironlake_edp_panel_vdd_on(dev);
906 ironlake_edp_pll_on(encoder);
907 }
908 if (dp_reg & DP_PORT_EN)
909 intel_dp_link_down(intel_dp);
910 }
911
912 static void intel_dp_commit(struct drm_encoder *encoder)
913 {
914 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
915 struct drm_device *dev = encoder->dev;
916
917 intel_dp_start_link_train(intel_dp);
918
919 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
920 ironlake_edp_panel_on(dev);
921
922 intel_dp_complete_link_train(intel_dp);
923
924 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
925 ironlake_edp_backlight_on(dev);
926 }
927
928 static void
929 intel_dp_dpms(struct drm_encoder *encoder, int mode)
930 {
931 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
932 struct drm_device *dev = encoder->dev;
933 struct drm_i915_private *dev_priv = dev->dev_private;
934 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
935
936 if (mode != DRM_MODE_DPMS_ON) {
937 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
938 ironlake_edp_backlight_off(dev);
939 ironlake_edp_panel_off(dev);
940 }
941 if (dp_reg & DP_PORT_EN)
942 intel_dp_link_down(intel_dp);
943 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
944 ironlake_edp_pll_off(encoder);
945 } else {
946 if (!(dp_reg & DP_PORT_EN)) {
947 intel_dp_start_link_train(intel_dp);
948 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
949 ironlake_edp_panel_on(dev);
950 intel_dp_complete_link_train(intel_dp);
951 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
952 ironlake_edp_backlight_on(dev);
953 }
954 }
955 intel_dp->dpms_mode = mode;
956 }
957
958 /*
959 * Fetch AUX CH registers 0x202 - 0x207 which contain
960 * link status information
961 */
962 static bool
963 intel_dp_get_link_status(struct intel_dp *intel_dp)
964 {
965 int ret;
966
967 ret = intel_dp_aux_native_read(intel_dp,
968 DP_LANE0_1_STATUS,
969 intel_dp->link_status, DP_LINK_STATUS_SIZE);
970 if (ret != DP_LINK_STATUS_SIZE)
971 return false;
972 return true;
973 }
974
975 static uint8_t
976 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
977 int r)
978 {
979 return link_status[r - DP_LANE0_1_STATUS];
980 }
981
982 static uint8_t
983 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
984 int lane)
985 {
986 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
987 int s = ((lane & 1) ?
988 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
989 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
990 uint8_t l = intel_dp_link_status(link_status, i);
991
992 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
993 }
994
995 static uint8_t
996 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
997 int lane)
998 {
999 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1000 int s = ((lane & 1) ?
1001 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1002 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1003 uint8_t l = intel_dp_link_status(link_status, i);
1004
1005 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1006 }
1007
1008
1009 #if 0
1010 static char *voltage_names[] = {
1011 "0.4V", "0.6V", "0.8V", "1.2V"
1012 };
1013 static char *pre_emph_names[] = {
1014 "0dB", "3.5dB", "6dB", "9.5dB"
1015 };
1016 static char *link_train_names[] = {
1017 "pattern 1", "pattern 2", "idle", "off"
1018 };
1019 #endif
1020
1021 /*
1022 * These are source-specific values; current Intel hardware supports
1023 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1024 */
1025 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1026
1027 static uint8_t
1028 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1029 {
1030 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1031 case DP_TRAIN_VOLTAGE_SWING_400:
1032 return DP_TRAIN_PRE_EMPHASIS_6;
1033 case DP_TRAIN_VOLTAGE_SWING_600:
1034 return DP_TRAIN_PRE_EMPHASIS_6;
1035 case DP_TRAIN_VOLTAGE_SWING_800:
1036 return DP_TRAIN_PRE_EMPHASIS_3_5;
1037 case DP_TRAIN_VOLTAGE_SWING_1200:
1038 default:
1039 return DP_TRAIN_PRE_EMPHASIS_0;
1040 }
1041 }
1042
1043 static void
1044 intel_get_adjust_train(struct intel_dp *intel_dp)
1045 {
1046 uint8_t v = 0;
1047 uint8_t p = 0;
1048 int lane;
1049
1050 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1051 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1052 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1053
1054 if (this_v > v)
1055 v = this_v;
1056 if (this_p > p)
1057 p = this_p;
1058 }
1059
1060 if (v >= I830_DP_VOLTAGE_MAX)
1061 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1062
1063 if (p >= intel_dp_pre_emphasis_max(v))
1064 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1065
1066 for (lane = 0; lane < 4; lane++)
1067 intel_dp->train_set[lane] = v | p;
1068 }
1069
1070 static uint32_t
1071 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1072 {
1073 uint32_t signal_levels = 0;
1074
1075 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1076 case DP_TRAIN_VOLTAGE_SWING_400:
1077 default:
1078 signal_levels |= DP_VOLTAGE_0_4;
1079 break;
1080 case DP_TRAIN_VOLTAGE_SWING_600:
1081 signal_levels |= DP_VOLTAGE_0_6;
1082 break;
1083 case DP_TRAIN_VOLTAGE_SWING_800:
1084 signal_levels |= DP_VOLTAGE_0_8;
1085 break;
1086 case DP_TRAIN_VOLTAGE_SWING_1200:
1087 signal_levels |= DP_VOLTAGE_1_2;
1088 break;
1089 }
1090 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1091 case DP_TRAIN_PRE_EMPHASIS_0:
1092 default:
1093 signal_levels |= DP_PRE_EMPHASIS_0;
1094 break;
1095 case DP_TRAIN_PRE_EMPHASIS_3_5:
1096 signal_levels |= DP_PRE_EMPHASIS_3_5;
1097 break;
1098 case DP_TRAIN_PRE_EMPHASIS_6:
1099 signal_levels |= DP_PRE_EMPHASIS_6;
1100 break;
1101 case DP_TRAIN_PRE_EMPHASIS_9_5:
1102 signal_levels |= DP_PRE_EMPHASIS_9_5;
1103 break;
1104 }
1105 return signal_levels;
1106 }
1107
1108 /* Gen6's DP voltage swing and pre-emphasis control */
1109 static uint32_t
1110 intel_gen6_edp_signal_levels(uint8_t train_set)
1111 {
1112 switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1113 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1114 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1115 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1116 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1117 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1118 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1119 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1120 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1121 default:
1122 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1123 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1124 }
1125 }
1126
1127 static uint8_t
1128 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1129 int lane)
1130 {
1131 int i = DP_LANE0_1_STATUS + (lane >> 1);
1132 int s = (lane & 1) * 4;
1133 uint8_t l = intel_dp_link_status(link_status, i);
1134
1135 return (l >> s) & 0xf;
1136 }
1137
1138 /* Check for clock recovery is done on all channels */
1139 static bool
1140 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1141 {
1142 int lane;
1143 uint8_t lane_status;
1144
1145 for (lane = 0; lane < lane_count; lane++) {
1146 lane_status = intel_get_lane_status(link_status, lane);
1147 if ((lane_status & DP_LANE_CR_DONE) == 0)
1148 return false;
1149 }
1150 return true;
1151 }
1152
1153 /* Check to see if channel eq is done on all channels */
1154 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1155 DP_LANE_CHANNEL_EQ_DONE|\
1156 DP_LANE_SYMBOL_LOCKED)
1157 static bool
1158 intel_channel_eq_ok(struct intel_dp *intel_dp)
1159 {
1160 uint8_t lane_align;
1161 uint8_t lane_status;
1162 int lane;
1163
1164 lane_align = intel_dp_link_status(intel_dp->link_status,
1165 DP_LANE_ALIGN_STATUS_UPDATED);
1166 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1167 return false;
1168 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1169 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1170 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1171 return false;
1172 }
1173 return true;
1174 }
1175
1176 static bool
1177 intel_dp_set_link_train(struct intel_dp *intel_dp,
1178 uint32_t dp_reg_value,
1179 uint8_t dp_train_pat,
1180 bool first)
1181 {
1182 struct drm_device *dev = intel_dp->base.base.dev;
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1185 int ret;
1186
1187 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1188 POSTING_READ(intel_dp->output_reg);
1189 if (first)
1190 intel_wait_for_vblank(dev, intel_crtc->pipe);
1191
1192 intel_dp_aux_native_write_1(intel_dp,
1193 DP_TRAINING_PATTERN_SET,
1194 dp_train_pat);
1195
1196 ret = intel_dp_aux_native_write(intel_dp,
1197 DP_TRAINING_LANE0_SET, intel_dp->train_set, 4);
1198 if (ret != 4)
1199 return false;
1200
1201 return true;
1202 }
1203
1204 /* Enable corresponding port and start training pattern 1 */
1205 static void
1206 intel_dp_start_link_train(struct intel_dp *intel_dp)
1207 {
1208 struct drm_device *dev = intel_dp->base.base.dev;
1209 int i;
1210 uint8_t voltage;
1211 bool clock_recovery = false;
1212 bool first = true;
1213 int tries;
1214 u32 reg;
1215 uint32_t DP = intel_dp->DP;
1216
1217 /* Write the link configuration data */
1218 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1219 intel_dp->link_configuration,
1220 DP_LINK_CONFIGURATION_SIZE);
1221
1222 DP |= DP_PORT_EN;
1223 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1224 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1225 else
1226 DP &= ~DP_LINK_TRAIN_MASK;
1227 memset(intel_dp->train_set, 0, 4);
1228 voltage = 0xff;
1229 tries = 0;
1230 clock_recovery = false;
1231 for (;;) {
1232 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1233 uint32_t signal_levels;
1234 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1235 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1236 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1237 } else {
1238 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1239 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1240 }
1241
1242 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1243 reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1244 else
1245 reg = DP | DP_LINK_TRAIN_PAT_1;
1246
1247 if (!intel_dp_set_link_train(intel_dp, reg,
1248 DP_TRAINING_PATTERN_1, first))
1249 break;
1250 first = false;
1251 /* Set training pattern 1 */
1252
1253 udelay(100);
1254 if (!intel_dp_get_link_status(intel_dp))
1255 break;
1256
1257 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1258 clock_recovery = true;
1259 break;
1260 }
1261
1262 /* Check to see if we've tried the max voltage */
1263 for (i = 0; i < intel_dp->lane_count; i++)
1264 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1265 break;
1266 if (i == intel_dp->lane_count)
1267 break;
1268
1269 /* Check to see if we've tried the same voltage 5 times */
1270 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1271 ++tries;
1272 if (tries == 5)
1273 break;
1274 } else
1275 tries = 0;
1276 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1277
1278 /* Compute new intel_dp->train_set as requested by target */
1279 intel_get_adjust_train(intel_dp);
1280 }
1281
1282 intel_dp->DP = DP;
1283 }
1284
1285 static void
1286 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1287 {
1288 struct drm_device *dev = intel_dp->base.base.dev;
1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 bool channel_eq = false;
1291 int tries;
1292 u32 reg;
1293 uint32_t DP = intel_dp->DP;
1294
1295 /* channel equalization */
1296 tries = 0;
1297 channel_eq = false;
1298 for (;;) {
1299 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1300 uint32_t signal_levels;
1301
1302 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1303 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1304 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1305 } else {
1306 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1307 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1308 }
1309
1310 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1311 reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1312 else
1313 reg = DP | DP_LINK_TRAIN_PAT_2;
1314
1315 /* channel eq pattern */
1316 if (!intel_dp_set_link_train(intel_dp, reg,
1317 DP_TRAINING_PATTERN_2,
1318 false))
1319 break;
1320
1321 udelay(400);
1322 if (!intel_dp_get_link_status(intel_dp))
1323 break;
1324
1325 if (intel_channel_eq_ok(intel_dp)) {
1326 channel_eq = true;
1327 break;
1328 }
1329
1330 /* Try 5 times */
1331 if (tries > 5)
1332 break;
1333
1334 /* Compute new intel_dp->train_set as requested by target */
1335 intel_get_adjust_train(intel_dp);
1336 ++tries;
1337 }
1338
1339 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1340 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1341 else
1342 reg = DP | DP_LINK_TRAIN_OFF;
1343
1344 I915_WRITE(intel_dp->output_reg, reg);
1345 POSTING_READ(intel_dp->output_reg);
1346 intel_dp_aux_native_write_1(intel_dp,
1347 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1348 }
1349
1350 static void
1351 intel_dp_link_down(struct intel_dp *intel_dp)
1352 {
1353 struct drm_device *dev = intel_dp->base.base.dev;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 uint32_t DP = intel_dp->DP;
1356
1357 DRM_DEBUG_KMS("\n");
1358
1359 if (IS_eDP(intel_dp)) {
1360 DP &= ~DP_PLL_ENABLE;
1361 I915_WRITE(intel_dp->output_reg, DP);
1362 POSTING_READ(intel_dp->output_reg);
1363 udelay(100);
1364 }
1365
1366 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
1367 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1368 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1369 POSTING_READ(intel_dp->output_reg);
1370 } else {
1371 DP &= ~DP_LINK_TRAIN_MASK;
1372 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1373 POSTING_READ(intel_dp->output_reg);
1374 }
1375
1376 udelay(17000);
1377
1378 if (IS_eDP(intel_dp))
1379 DP |= DP_LINK_TRAIN_OFF;
1380 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1381 POSTING_READ(intel_dp->output_reg);
1382 }
1383
1384 /*
1385 * According to DP spec
1386 * 5.1.2:
1387 * 1. Read DPCD
1388 * 2. Configure link according to Receiver Capabilities
1389 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1390 * 4. Check link status on receipt of hot-plug interrupt
1391 */
1392
1393 static void
1394 intel_dp_check_link_status(struct intel_dp *intel_dp)
1395 {
1396 if (!intel_dp->base.base.crtc)
1397 return;
1398
1399 if (!intel_dp_get_link_status(intel_dp)) {
1400 intel_dp_link_down(intel_dp);
1401 return;
1402 }
1403
1404 if (!intel_channel_eq_ok(intel_dp)) {
1405 intel_dp_start_link_train(intel_dp);
1406 intel_dp_complete_link_train(intel_dp);
1407 }
1408 }
1409
1410 static enum drm_connector_status
1411 ironlake_dp_detect(struct drm_connector *connector)
1412 {
1413 struct intel_dp *intel_dp = intel_attached_dp(connector);
1414 enum drm_connector_status status;
1415
1416 /* Panel needs power for AUX to work */
1417 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
1418 ironlake_edp_panel_vdd_on(connector->dev);
1419 status = connector_status_disconnected;
1420 if (intel_dp_aux_native_read(intel_dp,
1421 0x000, intel_dp->dpcd,
1422 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1423 {
1424 if (intel_dp->dpcd[0] != 0)
1425 status = connector_status_connected;
1426 }
1427 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1428 intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1429 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
1430 ironlake_edp_panel_vdd_off(connector->dev);
1431 return status;
1432 }
1433
1434 /**
1435 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1436 *
1437 * \return true if DP port is connected.
1438 * \return false if DP port is disconnected.
1439 */
1440 static enum drm_connector_status
1441 intel_dp_detect(struct drm_connector *connector)
1442 {
1443 struct intel_dp *intel_dp = intel_attached_dp(connector);
1444 struct drm_device *dev = intel_dp->base.base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
1446 uint32_t temp, bit;
1447 enum drm_connector_status status;
1448
1449 intel_dp->has_audio = false;
1450
1451 if (HAS_PCH_SPLIT(dev))
1452 return ironlake_dp_detect(connector);
1453
1454 switch (intel_dp->output_reg) {
1455 case DP_B:
1456 bit = DPB_HOTPLUG_INT_STATUS;
1457 break;
1458 case DP_C:
1459 bit = DPC_HOTPLUG_INT_STATUS;
1460 break;
1461 case DP_D:
1462 bit = DPD_HOTPLUG_INT_STATUS;
1463 break;
1464 default:
1465 return connector_status_unknown;
1466 }
1467
1468 temp = I915_READ(PORT_HOTPLUG_STAT);
1469
1470 if ((temp & bit) == 0)
1471 return connector_status_disconnected;
1472
1473 status = connector_status_disconnected;
1474 if (intel_dp_aux_native_read(intel_dp,
1475 0x000, intel_dp->dpcd,
1476 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1477 {
1478 if (intel_dp->dpcd[0] != 0)
1479 status = connector_status_connected;
1480 }
1481 return status;
1482 }
1483
1484 static int intel_dp_get_modes(struct drm_connector *connector)
1485 {
1486 struct intel_dp *intel_dp = intel_attached_dp(connector);
1487 struct drm_device *dev = intel_dp->base.base.dev;
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 int ret;
1490
1491 /* We should parse the EDID data and find out if it has an audio sink
1492 */
1493
1494 ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
1495 if (ret) {
1496 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
1497 !dev_priv->panel_fixed_mode) {
1498 struct drm_display_mode *newmode;
1499 list_for_each_entry(newmode, &connector->probed_modes,
1500 head) {
1501 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1502 dev_priv->panel_fixed_mode =
1503 drm_mode_duplicate(dev, newmode);
1504 break;
1505 }
1506 }
1507 }
1508
1509 return ret;
1510 }
1511
1512 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1513 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
1514 if (dev_priv->panel_fixed_mode != NULL) {
1515 struct drm_display_mode *mode;
1516 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1517 drm_mode_probed_add(connector, mode);
1518 return 1;
1519 }
1520 }
1521 return 0;
1522 }
1523
1524 static void
1525 intel_dp_destroy (struct drm_connector *connector)
1526 {
1527 drm_sysfs_connector_remove(connector);
1528 drm_connector_cleanup(connector);
1529 kfree(connector);
1530 }
1531
1532 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1533 {
1534 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1535
1536 i2c_del_adapter(&intel_dp->adapter);
1537 drm_encoder_cleanup(encoder);
1538 kfree(intel_dp);
1539 }
1540
1541 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1542 .dpms = intel_dp_dpms,
1543 .mode_fixup = intel_dp_mode_fixup,
1544 .prepare = intel_dp_prepare,
1545 .mode_set = intel_dp_mode_set,
1546 .commit = intel_dp_commit,
1547 };
1548
1549 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1550 .dpms = drm_helper_connector_dpms,
1551 .detect = intel_dp_detect,
1552 .fill_modes = drm_helper_probe_single_connector_modes,
1553 .destroy = intel_dp_destroy,
1554 };
1555
1556 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1557 .get_modes = intel_dp_get_modes,
1558 .mode_valid = intel_dp_mode_valid,
1559 .best_encoder = intel_best_encoder,
1560 };
1561
1562 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1563 .destroy = intel_dp_encoder_destroy,
1564 };
1565
1566 static void
1567 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1568 {
1569 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1570
1571 if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1572 intel_dp_check_link_status(intel_dp);
1573 }
1574
1575 /* Return which DP Port should be selected for Transcoder DP control */
1576 int
1577 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1578 {
1579 struct drm_device *dev = crtc->dev;
1580 struct drm_mode_config *mode_config = &dev->mode_config;
1581 struct drm_encoder *encoder;
1582
1583 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1584 struct intel_dp *intel_dp;
1585
1586 if (encoder->crtc != crtc)
1587 continue;
1588
1589 intel_dp = enc_to_intel_dp(encoder);
1590 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1591 return intel_dp->output_reg;
1592 }
1593
1594 return -1;
1595 }
1596
1597 /* check the VBT to see whether the eDP is on DP-D port */
1598 bool intel_dpd_is_edp(struct drm_device *dev)
1599 {
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 struct child_device_config *p_child;
1602 int i;
1603
1604 if (!dev_priv->child_dev_num)
1605 return false;
1606
1607 for (i = 0; i < dev_priv->child_dev_num; i++) {
1608 p_child = dev_priv->child_dev + i;
1609
1610 if (p_child->dvo_port == PORT_IDPD &&
1611 p_child->device_type == DEVICE_TYPE_eDP)
1612 return true;
1613 }
1614 return false;
1615 }
1616
1617 void
1618 intel_dp_init(struct drm_device *dev, int output_reg)
1619 {
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621 struct drm_connector *connector;
1622 struct intel_dp *intel_dp;
1623 struct intel_encoder *intel_encoder;
1624 struct intel_connector *intel_connector;
1625 const char *name = NULL;
1626 int type;
1627
1628 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1629 if (!intel_dp)
1630 return;
1631
1632 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1633 if (!intel_connector) {
1634 kfree(intel_dp);
1635 return;
1636 }
1637 intel_encoder = &intel_dp->base;
1638
1639 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1640 if (intel_dpd_is_edp(dev))
1641 intel_dp->is_pch_edp = true;
1642
1643 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1644 type = DRM_MODE_CONNECTOR_eDP;
1645 intel_encoder->type = INTEL_OUTPUT_EDP;
1646 } else {
1647 type = DRM_MODE_CONNECTOR_DisplayPort;
1648 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1649 }
1650
1651 connector = &intel_connector->base;
1652 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1653 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1654
1655 connector->polled = DRM_CONNECTOR_POLL_HPD;
1656
1657 if (output_reg == DP_B || output_reg == PCH_DP_B)
1658 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1659 else if (output_reg == DP_C || output_reg == PCH_DP_C)
1660 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1661 else if (output_reg == DP_D || output_reg == PCH_DP_D)
1662 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1663
1664 if (IS_eDP(intel_dp))
1665 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1666
1667 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1668 connector->interlace_allowed = true;
1669 connector->doublescan_allowed = 0;
1670
1671 intel_dp->output_reg = output_reg;
1672 intel_dp->has_audio = false;
1673 intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1674
1675 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1676 DRM_MODE_ENCODER_TMDS);
1677 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1678
1679 intel_connector_attach_encoder(intel_connector, intel_encoder);
1680 drm_sysfs_connector_add(connector);
1681
1682 /* Set up the DDC bus. */
1683 switch (output_reg) {
1684 case DP_A:
1685 name = "DPDDC-A";
1686 break;
1687 case DP_B:
1688 case PCH_DP_B:
1689 dev_priv->hotplug_supported_mask |=
1690 HDMIB_HOTPLUG_INT_STATUS;
1691 name = "DPDDC-B";
1692 break;
1693 case DP_C:
1694 case PCH_DP_C:
1695 dev_priv->hotplug_supported_mask |=
1696 HDMIC_HOTPLUG_INT_STATUS;
1697 name = "DPDDC-C";
1698 break;
1699 case DP_D:
1700 case PCH_DP_D:
1701 dev_priv->hotplug_supported_mask |=
1702 HDMID_HOTPLUG_INT_STATUS;
1703 name = "DPDDC-D";
1704 break;
1705 }
1706
1707 intel_dp_i2c_init(intel_dp, intel_connector, name);
1708
1709 intel_encoder->ddc_bus = &intel_dp->adapter;
1710 intel_encoder->hot_plug = intel_dp_hot_plug;
1711
1712 if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1713 /* initialize panel mode from VBT if available for eDP */
1714 if (dev_priv->lfp_lvds_vbt_mode) {
1715 dev_priv->panel_fixed_mode =
1716 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1717 if (dev_priv->panel_fixed_mode) {
1718 dev_priv->panel_fixed_mode->type |=
1719 DRM_MODE_TYPE_PREFERRED;
1720 }
1721 }
1722 }
1723
1724 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1725 * 0xd. Failure to do so will result in spurious interrupts being
1726 * generated on the port when a cable is not attached.
1727 */
1728 if (IS_G4X(dev) && !IS_GM45(dev)) {
1729 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1730 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1731 }
1732 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree