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drm/radeon/kms: add initial radeon tv-out support.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / rv515.c
blob97965c430c1f251fa1366f51ed6e249998480c31
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "rv515r.h"
31 #include "radeon.h"
32 #include "radeon_share.h"
33
34 #include "rv515_reg_safe.h"
35 /* rv515 depends on : */
36 void r100_hdp_reset(struct radeon_device *rdev);
37 int r100_cp_reset(struct radeon_device *rdev);
38 int r100_rb2d_reset(struct radeon_device *rdev);
39 int r100_gui_wait_for_idle(struct radeon_device *rdev);
40 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
41 int rv370_pcie_gart_enable(struct radeon_device *rdev);
42 void rv370_pcie_gart_disable(struct radeon_device *rdev);
43 void r420_pipes_init(struct radeon_device *rdev);
44 void rs600_mc_disable_clients(struct radeon_device *rdev);
45 void rs600_disable_vga(struct radeon_device *rdev);
46
47 /* This files gather functions specifics to:
48 * rv515
49 *
50 * Some of these functions might be used by newer ASICs.
51 */
52 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
53 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
54 void rv515_gpu_init(struct radeon_device *rdev);
55 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
56
57
58 /*
59 * MC
60 */
61 int rv515_mc_init(struct radeon_device *rdev)
62 {
63 uint32_t tmp;
64 int r;
65
66 if (r100_debugfs_rbbm_init(rdev)) {
67 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
68 }
69 if (rv515_debugfs_pipes_info_init(rdev)) {
70 DRM_ERROR("Failed to register debugfs file for pipes !\n");
71 }
72 if (rv515_debugfs_ga_info_init(rdev)) {
73 DRM_ERROR("Failed to register debugfs file for pipes !\n");
74 }
75
76 rv515_gpu_init(rdev);
77 rv370_pcie_gart_disable(rdev);
78
79 /* Setup GPU memory space */
80 rdev->mc.vram_location = 0xFFFFFFFFUL;
81 rdev->mc.gtt_location = 0xFFFFFFFFUL;
82 if (rdev->flags & RADEON_IS_AGP) {
83 r = radeon_agp_init(rdev);
84 if (r) {
85 printk(KERN_WARNING "[drm] Disabling AGP\n");
86 rdev->flags &= ~RADEON_IS_AGP;
87 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
88 } else {
89 rdev->mc.gtt_location = rdev->mc.agp_base;
90 }
91 }
92 r = radeon_mc_setup(rdev);
93 if (r) {
94 return r;
95 }
96
97 /* Program GPU memory space */
98 rs600_mc_disable_clients(rdev);
99 if (rv515_mc_wait_for_idle(rdev)) {
100 printk(KERN_WARNING "Failed to wait MC idle while "
101 "programming pipes. Bad things might happen.\n");
102 }
103 /* Write VRAM size in case we are limiting it */
104 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
105 tmp = REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
106 WREG32(0x134, tmp);
107 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1;
108 tmp = REG_SET(MC_FB_TOP, tmp >> 16);
109 tmp |= REG_SET(MC_FB_START, rdev->mc.vram_location >> 16);
110 WREG32_MC(MC_FB_LOCATION, tmp);
111 WREG32(HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
112 WREG32(0x310, rdev->mc.vram_location);
113 if (rdev->flags & RADEON_IS_AGP) {
114 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
115 tmp = REG_SET(MC_AGP_TOP, tmp >> 16);
116 tmp |= REG_SET(MC_AGP_START, rdev->mc.gtt_location >> 16);
117 WREG32_MC(MC_AGP_LOCATION, tmp);
118 WREG32_MC(MC_AGP_BASE, rdev->mc.agp_base);
119 WREG32_MC(MC_AGP_BASE_2, 0);
120 } else {
121 WREG32_MC(MC_AGP_LOCATION, 0x0FFFFFFF);
122 WREG32_MC(MC_AGP_BASE, 0);
123 WREG32_MC(MC_AGP_BASE_2, 0);
124 }
125 return 0;
126 }
127
128 void rv515_mc_fini(struct radeon_device *rdev)
129 {
130 rv370_pcie_gart_disable(rdev);
131 radeon_gart_table_vram_free(rdev);
132 radeon_gart_fini(rdev);
133 }
134
135
136 /*
137 * Global GPU functions
138 */
139 void rv515_ring_start(struct radeon_device *rdev)
140 {
141 int r;
142
143 r = radeon_ring_lock(rdev, 64);
144 if (r) {
145 return;
146 }
147 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
148 radeon_ring_write(rdev,
149 ISYNC_ANY2D_IDLE3D |
150 ISYNC_ANY3D_IDLE2D |
151 ISYNC_WAIT_IDLEGUI |
152 ISYNC_CPSCRATCH_IDLEGUI);
153 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
154 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
155 radeon_ring_write(rdev, PACKET0(0x170C, 0));
156 radeon_ring_write(rdev, 1 << 31);
157 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
158 radeon_ring_write(rdev, 0);
159 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
160 radeon_ring_write(rdev, 0);
161 radeon_ring_write(rdev, PACKET0(0x42C8, 0));
162 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
163 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
164 radeon_ring_write(rdev, 0);
165 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
166 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
167 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
168 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
169 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
170 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
171 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
172 radeon_ring_write(rdev, 0);
173 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
174 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
175 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
176 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
177 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
178 radeon_ring_write(rdev,
179 ((6 << MS_X0_SHIFT) |
180 (6 << MS_Y0_SHIFT) |
181 (6 << MS_X1_SHIFT) |
182 (6 << MS_Y1_SHIFT) |
183 (6 << MS_X2_SHIFT) |
184 (6 << MS_Y2_SHIFT) |
185 (6 << MSBD0_Y_SHIFT) |
186 (6 << MSBD0_X_SHIFT)));
187 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
188 radeon_ring_write(rdev,
189 ((6 << MS_X3_SHIFT) |
190 (6 << MS_Y3_SHIFT) |
191 (6 << MS_X4_SHIFT) |
192 (6 << MS_Y4_SHIFT) |
193 (6 << MS_X5_SHIFT) |
194 (6 << MS_Y5_SHIFT) |
195 (6 << MSBD1_SHIFT)));
196 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
197 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
198 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
199 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
200 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
201 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
202 radeon_ring_write(rdev, PACKET0(0x20C8, 0));
203 radeon_ring_write(rdev, 0);
204 radeon_ring_unlock_commit(rdev);
205 }
206
207 void rv515_errata(struct radeon_device *rdev)
208 {
209 rdev->pll_errata = 0;
210 }
211
212 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
213 {
214 unsigned i;
215 uint32_t tmp;
216
217 for (i = 0; i < rdev->usec_timeout; i++) {
218 /* read MC_STATUS */
219 tmp = RREG32_MC(MC_STATUS);
220 if (tmp & MC_STATUS_IDLE) {
221 return 0;
222 }
223 DRM_UDELAY(1);
224 }
225 return -1;
226 }
227
228 void rv515_gpu_init(struct radeon_device *rdev)
229 {
230 unsigned pipe_select_current, gb_pipe_select, tmp;
231
232 r100_hdp_reset(rdev);
233 r100_rb2d_reset(rdev);
234
235 if (r100_gui_wait_for_idle(rdev)) {
236 printk(KERN_WARNING "Failed to wait GUI idle while "
237 "reseting GPU. Bad things might happen.\n");
238 }
239
240 rs600_disable_vga(rdev);
241
242 r420_pipes_init(rdev);
243 gb_pipe_select = RREG32(0x402C);
244 tmp = RREG32(0x170C);
245 pipe_select_current = (tmp >> 2) & 3;
246 tmp = (1 << pipe_select_current) |
247 (((gb_pipe_select >> 8) & 0xF) << 4);
248 WREG32_PLL(0x000D, tmp);
249 if (r100_gui_wait_for_idle(rdev)) {
250 printk(KERN_WARNING "Failed to wait GUI idle while "
251 "reseting GPU. Bad things might happen.\n");
252 }
253 if (rv515_mc_wait_for_idle(rdev)) {
254 printk(KERN_WARNING "Failed to wait MC idle while "
255 "programming pipes. Bad things might happen.\n");
256 }
257 }
258
259 int rv515_ga_reset(struct radeon_device *rdev)
260 {
261 uint32_t tmp;
262 bool reinit_cp;
263 int i;
264
265 reinit_cp = rdev->cp.ready;
266 rdev->cp.ready = false;
267 for (i = 0; i < rdev->usec_timeout; i++) {
268 WREG32(CP_CSQ_MODE, 0);
269 WREG32(CP_CSQ_CNTL, 0);
270 WREG32(RBBM_SOFT_RESET, 0x32005);
271 (void)RREG32(RBBM_SOFT_RESET);
272 udelay(200);
273 WREG32(RBBM_SOFT_RESET, 0);
274 /* Wait to prevent race in RBBM_STATUS */
275 mdelay(1);
276 tmp = RREG32(RBBM_STATUS);
277 if (tmp & ((1 << 20) | (1 << 26))) {
278 DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
279 /* GA still busy soft reset it */
280 WREG32(0x429C, 0x200);
281 WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
282 WREG32(0x43E0, 0);
283 WREG32(0x43E4, 0);
284 WREG32(0x24AC, 0);
285 }
286 /* Wait to prevent race in RBBM_STATUS */
287 mdelay(1);
288 tmp = RREG32(RBBM_STATUS);
289 if (!(tmp & ((1 << 20) | (1 << 26)))) {
290 break;
291 }
292 }
293 for (i = 0; i < rdev->usec_timeout; i++) {
294 tmp = RREG32(RBBM_STATUS);
295 if (!(tmp & ((1 << 20) | (1 << 26)))) {
296 DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
297 tmp);
298 DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
299 DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
300 DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
301 if (reinit_cp) {
302 return r100_cp_init(rdev, rdev->cp.ring_size);
303 }
304 return 0;
305 }
306 DRM_UDELAY(1);
307 }
308 tmp = RREG32(RBBM_STATUS);
309 DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
310 return -1;
311 }
312
313 int rv515_gpu_reset(struct radeon_device *rdev)
314 {
315 uint32_t status;
316
317 /* reset order likely matter */
318 status = RREG32(RBBM_STATUS);
319 /* reset HDP */
320 r100_hdp_reset(rdev);
321 /* reset rb2d */
322 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
323 r100_rb2d_reset(rdev);
324 }
325 /* reset GA */
326 if (status & ((1 << 20) | (1 << 26))) {
327 rv515_ga_reset(rdev);
328 }
329 /* reset CP */
330 status = RREG32(RBBM_STATUS);
331 if (status & (1 << 16)) {
332 r100_cp_reset(rdev);
333 }
334 /* Check if GPU is idle */
335 status = RREG32(RBBM_STATUS);
336 if (status & (1 << 31)) {
337 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
338 return -1;
339 }
340 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
341 return 0;
342 }
343
344
345 /*
346 * VRAM info
347 */
348 static void rv515_vram_get_type(struct radeon_device *rdev)
349 {
350 uint32_t tmp;
351
352 rdev->mc.vram_width = 128;
353 rdev->mc.vram_is_ddr = true;
354 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
355 switch (tmp) {
356 case 0:
357 rdev->mc.vram_width = 64;
358 break;
359 case 1:
360 rdev->mc.vram_width = 128;
361 break;
362 default:
363 rdev->mc.vram_width = 128;
364 break;
365 }
366 }
367
368 void rv515_vram_info(struct radeon_device *rdev)
369 {
370 fixed20_12 a;
371
372 rv515_vram_get_type(rdev);
373
374 r100_vram_init_sizes(rdev);
375 /* FIXME: we should enforce default clock in case GPU is not in
376 * default setup
377 */
378 a.full = rfixed_const(100);
379 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
380 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
381 }
382
383
384 /*
385 * Indirect registers accessor
386 */
387 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
388 {
389 uint32_t r;
390
391 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
392 r = RREG32(MC_IND_DATA);
393 WREG32(MC_IND_INDEX, 0);
394 return r;
395 }
396
397 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
398 {
399 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
400 WREG32(MC_IND_DATA, (v));
401 WREG32(MC_IND_INDEX, 0);
402 }
403
404 /*
405 * Debugfs info
406 */
407 #if defined(CONFIG_DEBUG_FS)
408 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
409 {
410 struct drm_info_node *node = (struct drm_info_node *) m->private;
411 struct drm_device *dev = node->minor->dev;
412 struct radeon_device *rdev = dev->dev_private;
413 uint32_t tmp;
414
415 tmp = RREG32(GB_PIPE_SELECT);
416 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
417 tmp = RREG32(SU_REG_DEST);
418 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
419 tmp = RREG32(GB_TILE_CONFIG);
420 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
421 tmp = RREG32(DST_PIPE_CONFIG);
422 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
423 return 0;
424 }
425
426 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
427 {
428 struct drm_info_node *node = (struct drm_info_node *) m->private;
429 struct drm_device *dev = node->minor->dev;
430 struct radeon_device *rdev = dev->dev_private;
431 uint32_t tmp;
432
433 tmp = RREG32(0x2140);
434 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
435 radeon_gpu_reset(rdev);
436 tmp = RREG32(0x425C);
437 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
438 return 0;
439 }
440
441 static struct drm_info_list rv515_pipes_info_list[] = {
442 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
443 };
444
445 static struct drm_info_list rv515_ga_info_list[] = {
446 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
447 };
448 #endif
449
450 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
451 {
452 #if defined(CONFIG_DEBUG_FS)
453 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
454 #else
455 return 0;
456 #endif
457 }
458
459 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
460 {
461 #if defined(CONFIG_DEBUG_FS)
462 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
463 #else
464 return 0;
465 #endif
466 }
467
468 /*
469 * Asic initialization
470 */
471 int rv515_init(struct radeon_device *rdev)
472 {
473 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
474 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
475 return 0;
476 }
477
478 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
479 {
480 int index_reg = 0x6578 + crtc->crtc_offset;
481 int data_reg = 0x657c + crtc->crtc_offset;
482
483 WREG32(0x659C + crtc->crtc_offset, 0x0);
484 WREG32(0x6594 + crtc->crtc_offset, 0x705);
485 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
486 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
487 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
488 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
489 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
490 WREG32(index_reg, 0x0);
491 WREG32(data_reg, 0x841880A8);
492 WREG32(index_reg, 0x1);
493 WREG32(data_reg, 0x84208680);
494 WREG32(index_reg, 0x2);
495 WREG32(data_reg, 0xBFF880B0);
496 WREG32(index_reg, 0x100);
497 WREG32(data_reg, 0x83D88088);
498 WREG32(index_reg, 0x101);
499 WREG32(data_reg, 0x84608680);
500 WREG32(index_reg, 0x102);
501 WREG32(data_reg, 0xBFF080D0);
502 WREG32(index_reg, 0x200);
503 WREG32(data_reg, 0x83988068);
504 WREG32(index_reg, 0x201);
505 WREG32(data_reg, 0x84A08680);
506 WREG32(index_reg, 0x202);
507 WREG32(data_reg, 0xBFF080F8);
508 WREG32(index_reg, 0x300);
509 WREG32(data_reg, 0x83588058);
510 WREG32(index_reg, 0x301);
511 WREG32(data_reg, 0x84E08660);
512 WREG32(index_reg, 0x302);
513 WREG32(data_reg, 0xBFF88120);
514 WREG32(index_reg, 0x400);
515 WREG32(data_reg, 0x83188040);
516 WREG32(index_reg, 0x401);
517 WREG32(data_reg, 0x85008660);
518 WREG32(index_reg, 0x402);
519 WREG32(data_reg, 0xBFF88150);
520 WREG32(index_reg, 0x500);
521 WREG32(data_reg, 0x82D88030);
522 WREG32(index_reg, 0x501);
523 WREG32(data_reg, 0x85408640);
524 WREG32(index_reg, 0x502);
525 WREG32(data_reg, 0xBFF88180);
526 WREG32(index_reg, 0x600);
527 WREG32(data_reg, 0x82A08018);
528 WREG32(index_reg, 0x601);
529 WREG32(data_reg, 0x85808620);
530 WREG32(index_reg, 0x602);
531 WREG32(data_reg, 0xBFF081B8);
532 WREG32(index_reg, 0x700);
533 WREG32(data_reg, 0x82608010);
534 WREG32(index_reg, 0x701);
535 WREG32(data_reg, 0x85A08600);
536 WREG32(index_reg, 0x702);
537 WREG32(data_reg, 0x800081F0);
538 WREG32(index_reg, 0x800);
539 WREG32(data_reg, 0x8228BFF8);
540 WREG32(index_reg, 0x801);
541 WREG32(data_reg, 0x85E085E0);
542 WREG32(index_reg, 0x802);
543 WREG32(data_reg, 0xBFF88228);
544 WREG32(index_reg, 0x10000);
545 WREG32(data_reg, 0x82A8BF00);
546 WREG32(index_reg, 0x10001);
547 WREG32(data_reg, 0x82A08CC0);
548 WREG32(index_reg, 0x10002);
549 WREG32(data_reg, 0x8008BEF8);
550 WREG32(index_reg, 0x10100);
551 WREG32(data_reg, 0x81F0BF28);
552 WREG32(index_reg, 0x10101);
553 WREG32(data_reg, 0x83608CA0);
554 WREG32(index_reg, 0x10102);
555 WREG32(data_reg, 0x8018BED0);
556 WREG32(index_reg, 0x10200);
557 WREG32(data_reg, 0x8148BF38);
558 WREG32(index_reg, 0x10201);
559 WREG32(data_reg, 0x84408C80);
560 WREG32(index_reg, 0x10202);
561 WREG32(data_reg, 0x8008BEB8);
562 WREG32(index_reg, 0x10300);
563 WREG32(data_reg, 0x80B0BF78);
564 WREG32(index_reg, 0x10301);
565 WREG32(data_reg, 0x85008C20);
566 WREG32(index_reg, 0x10302);
567 WREG32(data_reg, 0x8020BEA0);
568 WREG32(index_reg, 0x10400);
569 WREG32(data_reg, 0x8028BF90);
570 WREG32(index_reg, 0x10401);
571 WREG32(data_reg, 0x85E08BC0);
572 WREG32(index_reg, 0x10402);
573 WREG32(data_reg, 0x8018BE90);
574 WREG32(index_reg, 0x10500);
575 WREG32(data_reg, 0xBFB8BFB0);
576 WREG32(index_reg, 0x10501);
577 WREG32(data_reg, 0x86C08B40);
578 WREG32(index_reg, 0x10502);
579 WREG32(data_reg, 0x8010BE90);
580 WREG32(index_reg, 0x10600);
581 WREG32(data_reg, 0xBF58BFC8);
582 WREG32(index_reg, 0x10601);
583 WREG32(data_reg, 0x87A08AA0);
584 WREG32(index_reg, 0x10602);
585 WREG32(data_reg, 0x8010BE98);
586 WREG32(index_reg, 0x10700);
587 WREG32(data_reg, 0xBF10BFF0);
588 WREG32(index_reg, 0x10701);
589 WREG32(data_reg, 0x886089E0);
590 WREG32(index_reg, 0x10702);
591 WREG32(data_reg, 0x8018BEB0);
592 WREG32(index_reg, 0x10800);
593 WREG32(data_reg, 0xBED8BFE8);
594 WREG32(index_reg, 0x10801);
595 WREG32(data_reg, 0x89408940);
596 WREG32(index_reg, 0x10802);
597 WREG32(data_reg, 0xBFE8BED8);
598 WREG32(index_reg, 0x20000);
599 WREG32(data_reg, 0x80008000);
600 WREG32(index_reg, 0x20001);
601 WREG32(data_reg, 0x90008000);
602 WREG32(index_reg, 0x20002);
603 WREG32(data_reg, 0x80008000);
604 WREG32(index_reg, 0x20003);
605 WREG32(data_reg, 0x80008000);
606 WREG32(index_reg, 0x20100);
607 WREG32(data_reg, 0x80108000);
608 WREG32(index_reg, 0x20101);
609 WREG32(data_reg, 0x8FE0BF70);
610 WREG32(index_reg, 0x20102);
611 WREG32(data_reg, 0xBFE880C0);
612 WREG32(index_reg, 0x20103);
613 WREG32(data_reg, 0x80008000);
614 WREG32(index_reg, 0x20200);
615 WREG32(data_reg, 0x8018BFF8);
616 WREG32(index_reg, 0x20201);
617 WREG32(data_reg, 0x8F80BF08);
618 WREG32(index_reg, 0x20202);
619 WREG32(data_reg, 0xBFD081A0);
620 WREG32(index_reg, 0x20203);
621 WREG32(data_reg, 0xBFF88000);
622 WREG32(index_reg, 0x20300);
623 WREG32(data_reg, 0x80188000);
624 WREG32(index_reg, 0x20301);
625 WREG32(data_reg, 0x8EE0BEC0);
626 WREG32(index_reg, 0x20302);
627 WREG32(data_reg, 0xBFB082A0);
628 WREG32(index_reg, 0x20303);
629 WREG32(data_reg, 0x80008000);
630 WREG32(index_reg, 0x20400);
631 WREG32(data_reg, 0x80188000);
632 WREG32(index_reg, 0x20401);
633 WREG32(data_reg, 0x8E00BEA0);
634 WREG32(index_reg, 0x20402);
635 WREG32(data_reg, 0xBF8883C0);
636 WREG32(index_reg, 0x20403);
637 WREG32(data_reg, 0x80008000);
638 WREG32(index_reg, 0x20500);
639 WREG32(data_reg, 0x80188000);
640 WREG32(index_reg, 0x20501);
641 WREG32(data_reg, 0x8D00BE90);
642 WREG32(index_reg, 0x20502);
643 WREG32(data_reg, 0xBF588500);
644 WREG32(index_reg, 0x20503);
645 WREG32(data_reg, 0x80008008);
646 WREG32(index_reg, 0x20600);
647 WREG32(data_reg, 0x80188000);
648 WREG32(index_reg, 0x20601);
649 WREG32(data_reg, 0x8BC0BE98);
650 WREG32(index_reg, 0x20602);
651 WREG32(data_reg, 0xBF308660);
652 WREG32(index_reg, 0x20603);
653 WREG32(data_reg, 0x80008008);
654 WREG32(index_reg, 0x20700);
655 WREG32(data_reg, 0x80108000);
656 WREG32(index_reg, 0x20701);
657 WREG32(data_reg, 0x8A80BEB0);
658 WREG32(index_reg, 0x20702);
659 WREG32(data_reg, 0xBF0087C0);
660 WREG32(index_reg, 0x20703);
661 WREG32(data_reg, 0x80008008);
662 WREG32(index_reg, 0x20800);
663 WREG32(data_reg, 0x80108000);
664 WREG32(index_reg, 0x20801);
665 WREG32(data_reg, 0x8920BED0);
666 WREG32(index_reg, 0x20802);
667 WREG32(data_reg, 0xBED08920);
668 WREG32(index_reg, 0x20803);
669 WREG32(data_reg, 0x80008010);
670 WREG32(index_reg, 0x30000);
671 WREG32(data_reg, 0x90008000);
672 WREG32(index_reg, 0x30001);
673 WREG32(data_reg, 0x80008000);
674 WREG32(index_reg, 0x30100);
675 WREG32(data_reg, 0x8FE0BF90);
676 WREG32(index_reg, 0x30101);
677 WREG32(data_reg, 0xBFF880A0);
678 WREG32(index_reg, 0x30200);
679 WREG32(data_reg, 0x8F60BF40);
680 WREG32(index_reg, 0x30201);
681 WREG32(data_reg, 0xBFE88180);
682 WREG32(index_reg, 0x30300);
683 WREG32(data_reg, 0x8EC0BF00);
684 WREG32(index_reg, 0x30301);
685 WREG32(data_reg, 0xBFC88280);
686 WREG32(index_reg, 0x30400);
687 WREG32(data_reg, 0x8DE0BEE0);
688 WREG32(index_reg, 0x30401);
689 WREG32(data_reg, 0xBFA083A0);
690 WREG32(index_reg, 0x30500);
691 WREG32(data_reg, 0x8CE0BED0);
692 WREG32(index_reg, 0x30501);
693 WREG32(data_reg, 0xBF7884E0);
694 WREG32(index_reg, 0x30600);
695 WREG32(data_reg, 0x8BA0BED8);
696 WREG32(index_reg, 0x30601);
697 WREG32(data_reg, 0xBF508640);
698 WREG32(index_reg, 0x30700);
699 WREG32(data_reg, 0x8A60BEE8);
700 WREG32(index_reg, 0x30701);
701 WREG32(data_reg, 0xBF2087A0);
702 WREG32(index_reg, 0x30800);
703 WREG32(data_reg, 0x8900BF00);
704 WREG32(index_reg, 0x30801);
705 WREG32(data_reg, 0xBF008900);
706 }
707
708 struct rv515_watermark {
709 u32 lb_request_fifo_depth;
710 fixed20_12 num_line_pair;
711 fixed20_12 estimated_width;
712 fixed20_12 worst_case_latency;
713 fixed20_12 consumption_rate;
714 fixed20_12 active_time;
715 fixed20_12 dbpp;
716 fixed20_12 priority_mark_max;
717 fixed20_12 priority_mark;
718 fixed20_12 sclk;
719 };
720
721 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
722 struct radeon_crtc *crtc,
723 struct rv515_watermark *wm)
724 {
725 struct drm_display_mode *mode = &crtc->base.mode;
726 fixed20_12 a, b, c;
727 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
728 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
729
730 if (!crtc->base.enabled) {
731 /* FIXME: wouldn't it better to set priority mark to maximum */
732 wm->lb_request_fifo_depth = 4;
733 return;
734 }
735
736 if (crtc->vsc.full > rfixed_const(2))
737 wm->num_line_pair.full = rfixed_const(2);
738 else
739 wm->num_line_pair.full = rfixed_const(1);
740
741 b.full = rfixed_const(mode->crtc_hdisplay);
742 c.full = rfixed_const(256);
743 a.full = rfixed_mul(wm->num_line_pair, b);
744 request_fifo_depth.full = rfixed_div(a, c);
745 if (a.full < rfixed_const(4)) {
746 wm->lb_request_fifo_depth = 4;
747 } else {
748 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
749 }
750
751 /* Determine consumption rate
752 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
753 * vtaps = number of vertical taps,
754 * vsc = vertical scaling ratio, defined as source/destination
755 * hsc = horizontal scaling ration, defined as source/destination
756 */
757 a.full = rfixed_const(mode->clock);
758 b.full = rfixed_const(1000);
759 a.full = rfixed_div(a, b);
760 pclk.full = rfixed_div(b, a);
761 if (crtc->rmx_type != RMX_OFF) {
762 b.full = rfixed_const(2);
763 if (crtc->vsc.full > b.full)
764 b.full = crtc->vsc.full;
765 b.full = rfixed_mul(b, crtc->hsc);
766 c.full = rfixed_const(2);
767 b.full = rfixed_div(b, c);
768 consumption_time.full = rfixed_div(pclk, b);
769 } else {
770 consumption_time.full = pclk.full;
771 }
772 a.full = rfixed_const(1);
773 wm->consumption_rate.full = rfixed_div(a, consumption_time);
774
775
776 /* Determine line time
777 * LineTime = total time for one line of displayhtotal
778 * LineTime = total number of horizontal pixels
779 * pclk = pixel clock period(ns)
780 */
781 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
782 line_time.full = rfixed_mul(a, pclk);
783
784 /* Determine active time
785 * ActiveTime = time of active region of display within one line,
786 * hactive = total number of horizontal active pixels
787 * htotal = total number of horizontal pixels
788 */
789 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
790 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
791 wm->active_time.full = rfixed_mul(line_time, b);
792 wm->active_time.full = rfixed_div(wm->active_time, a);
793
794 /* Determine chunk time
795 * ChunkTime = the time it takes the DCP to send one chunk of data
796 * to the LB which consists of pipeline delay and inter chunk gap
797 * sclk = system clock(Mhz)
798 */
799 a.full = rfixed_const(600 * 1000);
800 chunk_time.full = rfixed_div(a, rdev->pm.sclk);
801 read_delay_latency.full = rfixed_const(1000);
802
803 /* Determine the worst case latency
804 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
805 * WorstCaseLatency = worst case time from urgent to when the MC starts
806 * to return data
807 * READ_DELAY_IDLE_MAX = constant of 1us
808 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
809 * which consists of pipeline delay and inter chunk gap
810 */
811 if (rfixed_trunc(wm->num_line_pair) > 1) {
812 a.full = rfixed_const(3);
813 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
814 wm->worst_case_latency.full += read_delay_latency.full;
815 } else {
816 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
817 }
818
819 /* Determine the tolerable latency
820 * TolerableLatency = Any given request has only 1 line time
821 * for the data to be returned
822 * LBRequestFifoDepth = Number of chunk requests the LB can
823 * put into the request FIFO for a display
824 * LineTime = total time for one line of display
825 * ChunkTime = the time it takes the DCP to send one chunk
826 * of data to the LB which consists of
827 * pipeline delay and inter chunk gap
828 */
829 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
830 tolerable_latency.full = line_time.full;
831 } else {
832 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
833 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
834 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
835 tolerable_latency.full = line_time.full - tolerable_latency.full;
836 }
837 /* We assume worst case 32bits (4 bytes) */
838 wm->dbpp.full = rfixed_const(2 * 16);
839
840 /* Determine the maximum priority mark
841 * width = viewport width in pixels
842 */
843 a.full = rfixed_const(16);
844 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
845 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
846
847 /* Determine estimated width */
848 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
849 estimated_width.full = rfixed_div(estimated_width, consumption_time);
850 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
851 wm->priority_mark.full = rfixed_const(10);
852 } else {
853 a.full = rfixed_const(16);
854 wm->priority_mark.full = rfixed_div(estimated_width, a);
855 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
856 }
857 }
858
859 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
860 {
861 struct drm_display_mode *mode0 = NULL;
862 struct drm_display_mode *mode1 = NULL;
863 struct rv515_watermark wm0;
864 struct rv515_watermark wm1;
865 u32 tmp;
866 fixed20_12 priority_mark02, priority_mark12, fill_rate;
867 fixed20_12 a, b;
868
869 if (rdev->mode_info.crtcs[0]->base.enabled)
870 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
871 if (rdev->mode_info.crtcs[1]->base.enabled)
872 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
873 rs690_line_buffer_adjust(rdev, mode0, mode1);
874
875 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
876 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
877
878 tmp = wm0.lb_request_fifo_depth;
879 tmp |= wm1.lb_request_fifo_depth << 16;
880 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
881
882 if (mode0 && mode1) {
883 if (rfixed_trunc(wm0.dbpp) > 64)
884 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
885 else
886 a.full = wm0.num_line_pair.full;
887 if (rfixed_trunc(wm1.dbpp) > 64)
888 b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
889 else
890 b.full = wm1.num_line_pair.full;
891 a.full += b.full;
892 fill_rate.full = rfixed_div(wm0.sclk, a);
893 if (wm0.consumption_rate.full > fill_rate.full) {
894 b.full = wm0.consumption_rate.full - fill_rate.full;
895 b.full = rfixed_mul(b, wm0.active_time);
896 a.full = rfixed_const(16);
897 b.full = rfixed_div(b, a);
898 a.full = rfixed_mul(wm0.worst_case_latency,
899 wm0.consumption_rate);
900 priority_mark02.full = a.full + b.full;
901 } else {
902 a.full = rfixed_mul(wm0.worst_case_latency,
903 wm0.consumption_rate);
904 b.full = rfixed_const(16 * 1000);
905 priority_mark02.full = rfixed_div(a, b);
906 }
907 if (wm1.consumption_rate.full > fill_rate.full) {
908 b.full = wm1.consumption_rate.full - fill_rate.full;
909 b.full = rfixed_mul(b, wm1.active_time);
910 a.full = rfixed_const(16);
911 b.full = rfixed_div(b, a);
912 a.full = rfixed_mul(wm1.worst_case_latency,
913 wm1.consumption_rate);
914 priority_mark12.full = a.full + b.full;
915 } else {
916 a.full = rfixed_mul(wm1.worst_case_latency,
917 wm1.consumption_rate);
918 b.full = rfixed_const(16 * 1000);
919 priority_mark12.full = rfixed_div(a, b);
920 }
921 if (wm0.priority_mark.full > priority_mark02.full)
922 priority_mark02.full = wm0.priority_mark.full;
923 if (rfixed_trunc(priority_mark02) < 0)
924 priority_mark02.full = 0;
925 if (wm0.priority_mark_max.full > priority_mark02.full)
926 priority_mark02.full = wm0.priority_mark_max.full;
927 if (wm1.priority_mark.full > priority_mark12.full)
928 priority_mark12.full = wm1.priority_mark.full;
929 if (rfixed_trunc(priority_mark12) < 0)
930 priority_mark12.full = 0;
931 if (wm1.priority_mark_max.full > priority_mark12.full)
932 priority_mark12.full = wm1.priority_mark_max.full;
933 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
934 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
935 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
936 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
937 } else if (mode0) {
938 if (rfixed_trunc(wm0.dbpp) > 64)
939 a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
940 else
941 a.full = wm0.num_line_pair.full;
942 fill_rate.full = rfixed_div(wm0.sclk, a);
943 if (wm0.consumption_rate.full > fill_rate.full) {
944 b.full = wm0.consumption_rate.full - fill_rate.full;
945 b.full = rfixed_mul(b, wm0.active_time);
946 a.full = rfixed_const(16);
947 b.full = rfixed_div(b, a);
948 a.full = rfixed_mul(wm0.worst_case_latency,
949 wm0.consumption_rate);
950 priority_mark02.full = a.full + b.full;
951 } else {
952 a.full = rfixed_mul(wm0.worst_case_latency,
953 wm0.consumption_rate);
954 b.full = rfixed_const(16);
955 priority_mark02.full = rfixed_div(a, b);
956 }
957 if (wm0.priority_mark.full > priority_mark02.full)
958 priority_mark02.full = wm0.priority_mark.full;
959 if (rfixed_trunc(priority_mark02) < 0)
960 priority_mark02.full = 0;
961 if (wm0.priority_mark_max.full > priority_mark02.full)
962 priority_mark02.full = wm0.priority_mark_max.full;
963 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
964 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
965 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
966 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
967 } else {
968 if (rfixed_trunc(wm1.dbpp) > 64)
969 a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
970 else
971 a.full = wm1.num_line_pair.full;
972 fill_rate.full = rfixed_div(wm1.sclk, a);
973 if (wm1.consumption_rate.full > fill_rate.full) {
974 b.full = wm1.consumption_rate.full - fill_rate.full;
975 b.full = rfixed_mul(b, wm1.active_time);
976 a.full = rfixed_const(16);
977 b.full = rfixed_div(b, a);
978 a.full = rfixed_mul(wm1.worst_case_latency,
979 wm1.consumption_rate);
980 priority_mark12.full = a.full + b.full;
981 } else {
982 a.full = rfixed_mul(wm1.worst_case_latency,
983 wm1.consumption_rate);
984 b.full = rfixed_const(16 * 1000);
985 priority_mark12.full = rfixed_div(a, b);
986 }
987 if (wm1.priority_mark.full > priority_mark12.full)
988 priority_mark12.full = wm1.priority_mark.full;
989 if (rfixed_trunc(priority_mark12) < 0)
990 priority_mark12.full = 0;
991 if (wm1.priority_mark_max.full > priority_mark12.full)
992 priority_mark12.full = wm1.priority_mark_max.full;
993 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
994 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
995 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
996 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
997 }
998 }
999
1000 void rv515_bandwidth_update(struct radeon_device *rdev)
1001 {
1002 uint32_t tmp;
1003 struct drm_display_mode *mode0 = NULL;
1004 struct drm_display_mode *mode1 = NULL;
1005
1006 if (rdev->mode_info.crtcs[0]->base.enabled)
1007 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1008 if (rdev->mode_info.crtcs[1]->base.enabled)
1009 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1010 /*
1011 * Set display0/1 priority up in the memory controller for
1012 * modes if the user specifies HIGH for displaypriority
1013 * option.
1014 */
1015 if (rdev->disp_priority == 2) {
1016 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1017 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1018 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1019 if (mode1)
1020 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1021 if (mode0)
1022 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1023 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1024 }
1025 rv515_bandwidth_avivo_update(rdev);
1026 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree