drivers/hwmon/coretemp.c

   1 /*
   2  * coretemp.c - Linux kernel module for hardware monitoring
   3  *
   4  * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
   5  *
   6  * Inspired from many hwmon drivers
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301 USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/slab.h>
  27 #include <linux/jiffies.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/sysfs.h>
  30 #include <linux/hwmon-sysfs.h>
  31 #include <linux/err.h>
  32 #include <linux/mutex.h>
  33 #include <linux/list.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/cpu.h>
  36 #include <linux/pci.h>
  37 #include <asm/msr.h>
  38 #include <asm/processor.h>
  39
  40 #define DRVNAME "coretemp"
  41
  42 typedef enum { SHOW_TEMP, SHOW_TJMAX, SHOW_TTARGET, SHOW_LABEL,
  43                 SHOW_NAME } SHOW;
  44
  45 /*
  46  * Functions declaration
  47  */
  48
  49 static struct coretemp_data *coretemp_update_device(struct device *dev);
  50
  51 struct coretemp_data {
  52         struct device *hwmon_dev;
  53         struct mutex update_lock;
  54         const char *name;
  55         u32 id;
  56         u16 core_id;
  57         char valid;             /* zero until following fields are valid */
  58         unsigned long last_updated;     /* in jiffies */
  59         int temp;
  60         int tjmax;
  61         int ttarget;
  62         u8 alarm;
  63 };
  64
  65 /*
  66  * Sysfs stuff
  67  */
  68
  69 static ssize_t show_name(struct device *dev, struct device_attribute
  70                           *devattr, char *buf)
  71 {
  72         int ret;
  73         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  74         struct coretemp_data *data = dev_get_drvdata(dev);
  75
  76         if (attr->index == SHOW_NAME)
  77                 ret = sprintf(buf, "%s\n", data->name);
  78         else    /* show label */
  79                 ret = sprintf(buf, "Core %d\n", data->core_id);
  80         return ret;
  81 }
  82
  83 static ssize_t show_alarm(struct device *dev, struct device_attribute
  84                           *devattr, char *buf)
  85 {
  86         struct coretemp_data *data = coretemp_update_device(dev);
  87         /* read the Out-of-spec log, never clear */
  88         return sprintf(buf, "%d\n", data->alarm);
  89 }
  90
  91 static ssize_t show_temp(struct device *dev,
  92                          struct device_attribute *devattr, char *buf)
  93 {
  94         struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  95         struct coretemp_data *data = coretemp_update_device(dev);
  96         int err;
  97
  98         if (attr->index == SHOW_TEMP)
  99                 err = data->valid ? sprintf(buf, "%d\n", data->temp) : -EAGAIN;
 100         else if (attr->index == SHOW_TJMAX)
 101                 err = sprintf(buf, "%d\n", data->tjmax);
 102         else
 103                 err = sprintf(buf, "%d\n", data->ttarget);
 104         return err;
 105 }
 106
 107 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL,
 108                           SHOW_TEMP);
 109 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, NULL,
 110                           SHOW_TJMAX);
 111 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, NULL,
 112                           SHOW_TTARGET);
 113 static DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL);
 114 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, show_name, NULL, SHOW_LABEL);
 115 static SENSOR_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, SHOW_NAME);
 116
 117 static struct attribute *coretemp_attributes[] = {
 118         &sensor_dev_attr_name.dev_attr.attr,
 119         &sensor_dev_attr_temp1_label.dev_attr.attr,
 120         &dev_attr_temp1_crit_alarm.attr,
 121         &sensor_dev_attr_temp1_input.dev_attr.attr,
 122         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 123         NULL
 124 };
 125
 126 static const struct attribute_group coretemp_group = {
 127         .attrs = coretemp_attributes,
 128 };
 129
 130 static struct coretemp_data *coretemp_update_device(struct device *dev)
 131 {
 132         struct coretemp_data *data = dev_get_drvdata(dev);
 133
 134         mutex_lock(&data->update_lock);
 135
 136         if (!data->valid || time_after(jiffies, data->last_updated + HZ)) {
 137                 u32 eax, edx;
 138
 139                 data->valid = 0;
 140                 rdmsr_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 141                 data->alarm = (eax >> 5) & 1;
 142                 /* update only if data has been valid */
 143                 if (eax & 0x80000000) {
 144                         data->temp = data->tjmax - (((eax >> 16)
 145                                                         & 0x7f) * 1000);
 146                         data->valid = 1;
 147                 } else {
 148                         dev_dbg(dev, "Temperature data invalid (0x%x)\n", eax);
 149                 }
 150                 data->last_updated = jiffies;
 151         }
 152
 153         mutex_unlock(&data->update_lock);
 154         return data;
 155 }
 156
 157 static int __devinit adjust_tjmax(struct cpuinfo_x86 *c, u32 id, struct device *dev)
 158 {
 159         /* The 100C is default for both mobile and non mobile CPUs */
 160
 161         int tjmax = 100000;
 162         int tjmax_ee = 85000;
 163         int usemsr_ee = 1;
 164         int err;
 165         u32 eax, edx;
 166         struct pci_dev *host_bridge;
 167
 168         /* Early chips have no MSR for TjMax */
 169
 170         if ((c->x86_model == 0xf) && (c->x86_mask < 4)) {
 171                 usemsr_ee = 0;
 172         }
 173
 174         /* Atom CPUs */
 175
 176         if (c->x86_model == 0x1c) {
 177                 usemsr_ee = 0;
 178
 179                 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 180
 181                 if (host_bridge && host_bridge->vendor == PCI_VENDOR_ID_INTEL
 182                     && (host_bridge->device == 0xa000   /* NM10 based nettop */
 183                     || host_bridge->device == 0xa010))  /* NM10 based netbook */
 184                         tjmax = 100000;
 185                 else
 186                         tjmax = 90000;
 187
 188                 pci_dev_put(host_bridge);
 189         }
 190
 191         if ((c->x86_model > 0xe) && (usemsr_ee)) {
 192                 u8 platform_id;
 193
 194                 /* Now we can detect the mobile CPU using Intel provided table
 195                    http://softwarecommunity.intel.com/Wiki/Mobility/720.htm
 196                    For Core2 cores, check MSR 0x17, bit 28 1 = Mobile CPU
 197                 */
 198
 199                 err = rdmsr_safe_on_cpu(id, 0x17, &eax, &edx);
 200                 if (err) {
 201                         dev_warn(dev,
 202                                  "Unable to access MSR 0x17, assuming desktop"
 203                                  " CPU\n");
 204                         usemsr_ee = 0;
 205                 } else if (c->x86_model < 0x17 && !(eax & 0x10000000)) {
 206                         /* Trust bit 28 up to Penryn, I could not find any
 207                            documentation on that; if you happen to know
 208                            someone at Intel please ask */
 209                         usemsr_ee = 0;
 210                 } else {
 211                         /* Platform ID bits 52:50 (EDX starts at bit 32) */
 212                         platform_id = (edx >> 18) & 0x7;
 213
 214                         /* Mobile Penryn CPU seems to be platform ID 7 or 5
 215                           (guesswork) */
 216                         if ((c->x86_model == 0x17) &&
 217                             ((platform_id == 5) || (platform_id == 7))) {
 218                                 /* If MSR EE bit is set, set it to 90 degrees C,
 219                                    otherwise 105 degrees C */
 220                                 tjmax_ee = 90000;
 221                                 tjmax = 105000;
 222                         }
 223                 }
 224         }
 225
 226         if (usemsr_ee) {
 227
 228                 err = rdmsr_safe_on_cpu(id, 0xee, &eax, &edx);
 229                 if (err) {
 230                         dev_warn(dev,
 231                                  "Unable to access MSR 0xEE, for Tjmax, left"
 232                                  " at default\n");
 233                 } else if (eax & 0x40000000) {
 234                         tjmax = tjmax_ee;
 235                 }
 236         /* if we dont use msr EE it means we are desktop CPU (with exeception
 237            of Atom) */
 238         } else if (tjmax == 100000) {
 239                 dev_warn(dev, "Using relative temperature scale!\n");
 240         }
 241
 242         return tjmax;
 243 }
 244
 245 static int __devinit get_tjmax(struct cpuinfo_x86 *c, u32 id,
 246                                struct device *dev)
 247 {
 248         /* The 100C is default for both mobile and non mobile CPUs */
 249         int err;
 250         u32 eax, edx;
 251         u32 val;
 252
 253         /* A new feature of current Intel(R) processors, the
 254            IA32_TEMPERATURE_TARGET contains the TjMax value */
 255         err = rdmsr_safe_on_cpu(id, MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
 256         if (err) {
 257                 dev_warn(dev, "Unable to read TjMax from CPU.\n");
 258         } else {
 259                 val = (eax >> 16) & 0xff;
 260                 /*
 261                  * If the TjMax is not plausible, an assumption
 262                  * will be used
 263                  */
 264                 if ((val > 80) && (val < 120)) {
 265                         dev_info(dev, "TjMax is %d C.\n", val);
 266                         return val * 1000;
 267                 }
 268         }
 269
 270         /*
 271          * An assumption is made for early CPUs and unreadable MSR.
 272          * NOTE: the given value may not be correct.
 273          */
 274
 275         switch (c->x86_model) {
 276         case 0xe:
 277         case 0xf:
 278         case 0x16:
 279         case 0x1a:
 280                 dev_warn(dev, "TjMax is assumed as 100 C!\n");
 281                 return 100000;
 282                 break;
 283         case 0x17:
 284         case 0x1c:              /* Atom CPUs */
 285                 return adjust_tjmax(c, id, dev);
 286                 break;
 287         default:
 288                 dev_warn(dev, "CPU (model=0x%x) is not supported yet,"
 289                         " using default TjMax of 100C.\n", c->x86_model);
 290                 return 100000;
 291         }
 292 }
 293
 294 static int __devinit coretemp_probe(struct platform_device *pdev)
 295 {
 296         struct coretemp_data *data;
 297         struct cpuinfo_x86 *c = &cpu_data(pdev->id);
 298         int err;
 299         u32 eax, edx;
 300
 301         if (!(data = kzalloc(sizeof(struct coretemp_data), GFP_KERNEL))) {
 302                 err = -ENOMEM;
 303                 dev_err(&pdev->dev, "Out of memory\n");
 304                 goto exit;
 305         }
 306
 307         data->id = pdev->id;
 308 #ifdef CONFIG_SMP
 309         data->core_id = c->cpu_core_id;
 310 #endif
 311         data->name = "coretemp";
 312         mutex_init(&data->update_lock);
 313
 314         /* test if we can access the THERM_STATUS MSR */
 315         err = rdmsr_safe_on_cpu(data->id, MSR_IA32_THERM_STATUS, &eax, &edx);
 316         if (err) {
 317                 dev_err(&pdev->dev,
 318                         "Unable to access THERM_STATUS MSR, giving up\n");
 319                 goto exit_free;
 320         }
 321
 322         /* Check if we have problem with errata AE18 of Core processors:
 323            Readings might stop update when processor visited too deep sleep,
 324            fixed for stepping D0 (6EC).
 325         */
 326
 327         if ((c->x86_model == 0xe) && (c->x86_mask < 0xc)) {
 328                 /* check for microcode update */
 329                 rdmsr_on_cpu(data->id, MSR_IA32_UCODE_REV, &eax, &edx);
 330                 if (edx < 0x39) {
 331                         err = -ENODEV;
 332                         dev_err(&pdev->dev,
 333                                 "Errata AE18 not fixed, update BIOS or "
 334                                 "microcode of the CPU!\n");
 335                         goto exit_free;
 336                 }
 337         }
 338
 339         data->tjmax = get_tjmax(c, data->id, &pdev->dev);
 340         platform_set_drvdata(pdev, data);
 341
 342         /*
 343          * read the still undocumented IA32_TEMPERATURE_TARGET. It exists
 344          * on older CPUs but not in this register,
 345          * Atoms don't have it either.
 346          */
 347
 348         if ((c->x86_model > 0xe) && (c->x86_model != 0x1c)) {
 349                 err = rdmsr_safe_on_cpu(data->id, MSR_IA32_TEMPERATURE_TARGET,
 350                     &eax, &edx);
 351                 if (err) {
 352                         dev_warn(&pdev->dev, "Unable to read"
 353                                         " IA32_TEMPERATURE_TARGET MSR\n");
 354                 } else {
 355                         data->ttarget = data->tjmax -
 356                                         (((eax >> 8) & 0xff) * 1000);
 357                         err = device_create_file(&pdev->dev,
 358                                         &sensor_dev_attr_temp1_max.dev_attr);
 359                         if (err)
 360                                 goto exit_free;
 361                 }
 362         }
 363
 364         if ((err = sysfs_create_group(&pdev->dev.kobj, &coretemp_group)))
 365                 goto exit_dev;
 366
 367         data->hwmon_dev = hwmon_device_register(&pdev->dev);
 368         if (IS_ERR(data->hwmon_dev)) {
 369                 err = PTR_ERR(data->hwmon_dev);
 370                 dev_err(&pdev->dev, "Class registration failed (%d)\n",
 371                         err);
 372                 goto exit_class;
 373         }
 374
 375         return 0;
 376
 377 exit_class:
 378         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 379 exit_dev:
 380         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 381 exit_free:
 382         kfree(data);
 383 exit:
 384         return err;
 385 }
 386
 387 static int __devexit coretemp_remove(struct platform_device *pdev)
 388 {
 389         struct coretemp_data *data = platform_get_drvdata(pdev);
 390
 391         hwmon_device_unregister(data->hwmon_dev);
 392         sysfs_remove_group(&pdev->dev.kobj, &coretemp_group);
 393         device_remove_file(&pdev->dev, &sensor_dev_attr_temp1_max.dev_attr);
 394         platform_set_drvdata(pdev, NULL);
 395         kfree(data);
 396         return 0;
 397 }
 398
 399 static struct platform_driver coretemp_driver = {
 400         .driver = {
 401                 .owner = THIS_MODULE,
 402                 .name = DRVNAME,
 403         },
 404         .probe = coretemp_probe,
 405         .remove = __devexit_p(coretemp_remove),
 406 };
 407
 408 struct pdev_entry {
 409         struct list_head list;
 410         struct platform_device *pdev;
 411         unsigned int cpu;
 412 #ifdef CONFIG_SMP
 413         u16 phys_proc_id;
 414         u16 cpu_core_id;
 415 #endif
 416 };
 417
 418 static LIST_HEAD(pdev_list);
 419 static DEFINE_MUTEX(pdev_list_mutex);
 420
 421 static int __cpuinit coretemp_device_add(unsigned int cpu)
 422 {
 423         int err;
 424         struct platform_device *pdev;
 425         struct pdev_entry *pdev_entry;
 426 #ifdef CONFIG_SMP
 427         struct cpuinfo_x86 *c = &cpu_data(cpu);
 428 #endif
 429
 430         mutex_lock(&pdev_list_mutex);
 431
 432 #ifdef CONFIG_SMP
 433         /* Skip second HT entry of each core */
 434         list_for_each_entry(pdev_entry, &pdev_list, list) {
 435                 if (c->phys_proc_id == pdev_entry->phys_proc_id &&
 436                     c->cpu_core_id == pdev_entry->cpu_core_id) {
 437                         err = 0;        /* Not an error */
 438                         goto exit;
 439                 }
 440         }
 441 #endif
 442
 443         pdev = platform_device_alloc(DRVNAME, cpu);
 444         if (!pdev) {
 445                 err = -ENOMEM;
 446                 printk(KERN_ERR DRVNAME ": Device allocation failed\n");
 447                 goto exit;
 448         }
 449
 450         pdev_entry = kzalloc(sizeof(struct pdev_entry), GFP_KERNEL);
 451         if (!pdev_entry) {
 452                 err = -ENOMEM;
 453                 goto exit_device_put;
 454         }
 455
 456         err = platform_device_add(pdev);
 457         if (err) {
 458                 printk(KERN_ERR DRVNAME ": Device addition failed (%d)\n",
 459                        err);
 460                 goto exit_device_free;
 461         }
 462
 463         pdev_entry->pdev = pdev;
 464         pdev_entry->cpu = cpu;
 465 #ifdef CONFIG_SMP
 466         pdev_entry->phys_proc_id = c->phys_proc_id;
 467         pdev_entry->cpu_core_id = c->cpu_core_id;
 468 #endif
 469         list_add_tail(&pdev_entry->list, &pdev_list);
 470         mutex_unlock(&pdev_list_mutex);
 471
 472         return 0;
 473
 474 exit_device_free:
 475         kfree(pdev_entry);
 476 exit_device_put:
 477         platform_device_put(pdev);
 478 exit:
 479         mutex_unlock(&pdev_list_mutex);
 480         return err;
 481 }
 482
 483 static void coretemp_device_remove(unsigned int cpu)
 484 {
 485         struct pdev_entry *p, *n;
 486         mutex_lock(&pdev_list_mutex);
 487         list_for_each_entry_safe(p, n, &pdev_list, list) {
 488                 if (p->cpu == cpu) {
 489                         platform_device_unregister(p->pdev);
 490                         list_del(&p->list);
 491                         kfree(p);
 492                 }
 493         }
 494         mutex_unlock(&pdev_list_mutex);
 495 }
 496
 497 static int __cpuinit coretemp_cpu_callback(struct notifier_block *nfb,
 498                                  unsigned long action, void *hcpu)
 499 {
 500         unsigned int cpu = (unsigned long) hcpu;
 501
 502         switch (action) {
 503         case CPU_ONLINE:
 504         case CPU_DOWN_FAILED:
 505                 coretemp_device_add(cpu);
 506                 break;
 507         case CPU_DOWN_PREPARE:
 508                 coretemp_device_remove(cpu);
 509                 break;
 510         }
 511         return NOTIFY_OK;
 512 }
 513
 514 static struct notifier_block coretemp_cpu_notifier __refdata = {
 515         .notifier_call = coretemp_cpu_callback,
 516 };
 517
 518 static int __init coretemp_init(void)
 519 {
 520         int i, err = -ENODEV;
 521         struct pdev_entry *p, *n;
 522
 523         /* quick check if we run Intel */
 524         if (cpu_data(0).x86_vendor != X86_VENDOR_INTEL)
 525                 goto exit;
 526
 527         err = platform_driver_register(&coretemp_driver);
 528         if (err)
 529                 goto exit;
 530
 531         for_each_online_cpu(i) {
 532                 struct cpuinfo_x86 *c = &cpu_data(i);
 533                 /*
 534                  * CPUID.06H.EAX[0] indicates whether the CPU has thermal
 535                  * sensors. We check this bit only, all the early CPUs
 536                  * without thermal sensors will be filtered out.
 537                  */
 538                 if (c->cpuid_level >= 6 && (cpuid_eax(0x06) & 0x01))
 539                         coretemp_device_add(i);
 540                 else {
 541                         printk(KERN_INFO DRVNAME ": CPU (model=0x%x)"
 542                                 " has no thermal sensor.\n", c->x86_model);
 543                 }
 544         }
 545         if (list_empty(&pdev_list)) {
 546                 err = -ENODEV;
 547                 goto exit_driver_unreg;
 548         }
 549
 550         register_hotcpu_notifier(&coretemp_cpu_notifier);
 551         return 0;
 552
 553 exit_driver_unreg:
 554 #ifndef CONFIG_HOTPLUG_CPU
 555         platform_driver_unregister(&coretemp_driver);
 556 #endif
 557 exit:
 558         return err;
 559 }
 560
 561 static void __exit coretemp_exit(void)
 562 {
 563         struct pdev_entry *p, *n;
 564 #ifdef CONFIG_HOTPLUG_CPU
 565         unregister_hotcpu_notifier(&coretemp_cpu_notifier);
 566 #endif
 567         mutex_lock(&pdev_list_mutex);
 568         list_for_each_entry_safe(p, n, &pdev_list, list) {
 569                 platform_device_unregister(p->pdev);
 570                 list_del(&p->list);
 571                 kfree(p);
 572         }
 573         mutex_unlock(&pdev_list_mutex);
 574         platform_driver_unregister(&coretemp_driver);
 575 }
 576
 577 MODULE_AUTHOR("Rudolf Marek <r.marek@assembler.cz>");
 578 MODULE_DESCRIPTION("Intel Core temperature monitor");
 579 MODULE_LICENSE("GPL");
 580
 581 module_init(coretemp_init)
 582 module_exit(coretemp_exit)