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ACPI: thinkpad-acpi: add development version tag
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / ahci.c
blobb2526e423dfcf1ef4fb97809a7a30aa4d969f602
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "3.0"
51
52 /* Enclosure Management Control */
53 #define EM_CTRL_MSG_TYPE 0x000f0000
54
55 /* Enclosure Management LED Message Type */
56 #define EM_MSG_LED_HBA_PORT 0x0000000f
57 #define EM_MSG_LED_PMP_SLOT 0x0000ff00
58 #define EM_MSG_LED_VALUE 0xffff0000
59 #define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60 #define EM_MSG_LED_VALUE_OFF 0xfff80000
61 #define EM_MSG_LED_VALUE_ON 0x00010000
62
63 static int ahci_skip_host_reset;
64 static int ahci_ignore_sss;
65
66 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
69 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
72 static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74 static void ahci_disable_alpm(struct ata_port *ap);
75 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
80
81 enum {
82 AHCI_PCI_BAR = 5,
83 AHCI_MAX_PORTS = 32,
84 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
86 AHCI_MAX_CMDS = 32,
87 AHCI_CMD_SZ = 32,
88 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
89 AHCI_RX_FIS_SZ = 256,
90 AHCI_CMD_TBL_CDB = 0x40,
91 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
95 AHCI_RX_FIS_SZ,
96 AHCI_IRQ_ON_SG = (1 << 31),
97 AHCI_CMD_ATAPI = (1 << 5),
98 AHCI_CMD_WRITE = (1 << 6),
99 AHCI_CMD_PREFETCH = (1 << 7),
100 AHCI_CMD_RESET = (1 << 8),
101 AHCI_CMD_CLR_BUSY = (1 << 10),
102
103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
106
107 board_ahci = 0,
108 board_ahci_vt8251 = 1,
109 board_ahci_ign_iferr = 2,
110 board_ahci_sb600 = 3,
111 board_ahci_mv = 4,
112 board_ahci_sb700 = 5, /* for SB700 and SB800 */
113 board_ahci_mcp65 = 6,
114 board_ahci_nopmp = 7,
115 board_ahci_yesncq = 8,
116
117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
125
126 /* HOST_CTL bits */
127 HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
130
131 /* HOST_CAP bits */
132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
141
142 /* registers for each SATA port */
143 PORT_LST_ADDR = 0x00, /* command list DMA addr */
144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
147 PORT_IRQ_STAT = 0x10, /* interrupt status */
148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
149 PORT_CMD = 0x18, /* port command */
150 PORT_TFDATA = 0x20, /* taskfile data */
151 PORT_SIG = 0x24, /* device TF signature */
152 PORT_CMD_ISSUE = 0x38, /* command issue */
153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
158
159 /* PORT_IRQ_{STAT,MASK} bits */
160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
168
169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
178
179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
180 PORT_IRQ_IF_ERR |
181 PORT_IRQ_CONNECT |
182 PORT_IRQ_PHYRDY |
183 PORT_IRQ_UNK_FIS |
184 PORT_IRQ_BAD_PMP,
185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
186 PORT_IRQ_TF_ERR |
187 PORT_IRQ_HBUS_DATA_ERR,
188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
191
192 /* PORT_CMD bits */
193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
196 PORT_CMD_PMP = (1 << 17), /* PMP attached */
197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
200 PORT_CMD_CLO = (1 << 3), /* Command list override */
201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
204
205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
209
210 /* hpriv->flags bits */
211 AHCI_HFLAG_NO_NCQ = (1 << 0),
212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
222 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
223 link offline */
224
225 /* ap->flags bits */
226
227 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
228 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
229 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
230 ATA_FLAG_IPM,
231
232 ICH_MAP = 0x90, /* ICH MAP register */
233
234 /* em constants */
235 EM_MAX_SLOTS = 8,
236 EM_MAX_RETRY = 5,
237
238 /* em_ctl bits */
239 EM_CTL_RST = (1 << 9), /* Reset */
240 EM_CTL_TM = (1 << 8), /* Transmit Message */
241 EM_CTL_ALHD = (1 << 26), /* Activity LED */
242 };
243
244 struct ahci_cmd_hdr {
245 __le32 opts;
246 __le32 status;
247 __le32 tbl_addr;
248 __le32 tbl_addr_hi;
249 __le32 reserved[4];
250 };
251
252 struct ahci_sg {
253 __le32 addr;
254 __le32 addr_hi;
255 __le32 reserved;
256 __le32 flags_size;
257 };
258
259 struct ahci_em_priv {
260 enum sw_activity blink_policy;
261 struct timer_list timer;
262 unsigned long saved_activity;
263 unsigned long activity;
264 unsigned long led_state;
265 };
266
267 struct ahci_host_priv {
268 unsigned int flags; /* AHCI_HFLAG_* */
269 u32 cap; /* cap to use */
270 u32 port_map; /* port map to use */
271 u32 saved_cap; /* saved initial cap */
272 u32 saved_port_map; /* saved initial port_map */
273 u32 em_loc; /* enclosure management location */
274 };
275
276 struct ahci_port_priv {
277 struct ata_link *active_link;
278 struct ahci_cmd_hdr *cmd_slot;
279 dma_addr_t cmd_slot_dma;
280 void *cmd_tbl;
281 dma_addr_t cmd_tbl_dma;
282 void *rx_fis;
283 dma_addr_t rx_fis_dma;
284 /* for NCQ spurious interrupt analysis */
285 unsigned int ncq_saw_d2h:1;
286 unsigned int ncq_saw_dmas:1;
287 unsigned int ncq_saw_sdb:1;
288 u32 intr_mask; /* interrupts to enable */
289 /* enclosure management info per PM slot */
290 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
291 };
292
293 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
294 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
295 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
296 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
297 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
298 static int ahci_port_start(struct ata_port *ap);
299 static void ahci_port_stop(struct ata_port *ap);
300 static void ahci_qc_prep(struct ata_queued_cmd *qc);
301 static void ahci_freeze(struct ata_port *ap);
302 static void ahci_thaw(struct ata_port *ap);
303 static void ahci_pmp_attach(struct ata_port *ap);
304 static void ahci_pmp_detach(struct ata_port *ap);
305 static int ahci_softreset(struct ata_link *link, unsigned int *class,
306 unsigned long deadline);
307 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
308 unsigned long deadline);
309 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline);
311 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
312 unsigned long deadline);
313 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
314 unsigned long deadline);
315 static void ahci_postreset(struct ata_link *link, unsigned int *class);
316 static void ahci_error_handler(struct ata_port *ap);
317 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
318 static int ahci_port_resume(struct ata_port *ap);
319 static void ahci_dev_config(struct ata_device *dev);
320 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
321 u32 opts);
322 #ifdef CONFIG_PM
323 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
324 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
325 static int ahci_pci_device_resume(struct pci_dev *pdev);
326 #endif
327 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
328 static ssize_t ahci_activity_store(struct ata_device *dev,
329 enum sw_activity val);
330 static void ahci_init_sw_activity(struct ata_link *link);
331
332 static struct device_attribute *ahci_shost_attrs[] = {
333 &dev_attr_link_power_management_policy,
334 &dev_attr_em_message_type,
335 &dev_attr_em_message,
336 NULL
337 };
338
339 static struct device_attribute *ahci_sdev_attrs[] = {
340 &dev_attr_sw_activity,
341 &dev_attr_unload_heads,
342 NULL
343 };
344
345 static struct scsi_host_template ahci_sht = {
346 ATA_NCQ_SHT(DRV_NAME),
347 .can_queue = AHCI_MAX_CMDS - 1,
348 .sg_tablesize = AHCI_MAX_SG,
349 .dma_boundary = AHCI_DMA_BOUNDARY,
350 .shost_attrs = ahci_shost_attrs,
351 .sdev_attrs = ahci_sdev_attrs,
352 };
353
354 static struct ata_port_operations ahci_ops = {
355 .inherits = &sata_pmp_port_ops,
356
357 .qc_defer = sata_pmp_qc_defer_cmd_switch,
358 .qc_prep = ahci_qc_prep,
359 .qc_issue = ahci_qc_issue,
360 .qc_fill_rtf = ahci_qc_fill_rtf,
361
362 .freeze = ahci_freeze,
363 .thaw = ahci_thaw,
364 .softreset = ahci_softreset,
365 .hardreset = ahci_hardreset,
366 .postreset = ahci_postreset,
367 .pmp_softreset = ahci_softreset,
368 .error_handler = ahci_error_handler,
369 .post_internal_cmd = ahci_post_internal_cmd,
370 .dev_config = ahci_dev_config,
371
372 .scr_read = ahci_scr_read,
373 .scr_write = ahci_scr_write,
374 .pmp_attach = ahci_pmp_attach,
375 .pmp_detach = ahci_pmp_detach,
376
377 .enable_pm = ahci_enable_alpm,
378 .disable_pm = ahci_disable_alpm,
379 .em_show = ahci_led_show,
380 .em_store = ahci_led_store,
381 .sw_activity_show = ahci_activity_show,
382 .sw_activity_store = ahci_activity_store,
383 #ifdef CONFIG_PM
384 .port_suspend = ahci_port_suspend,
385 .port_resume = ahci_port_resume,
386 #endif
387 .port_start = ahci_port_start,
388 .port_stop = ahci_port_stop,
389 };
390
391 static struct ata_port_operations ahci_vt8251_ops = {
392 .inherits = &ahci_ops,
393 .hardreset = ahci_vt8251_hardreset,
394 };
395
396 static struct ata_port_operations ahci_p5wdh_ops = {
397 .inherits = &ahci_ops,
398 .hardreset = ahci_p5wdh_hardreset,
399 };
400
401 static struct ata_port_operations ahci_sb600_ops = {
402 .inherits = &ahci_ops,
403 .softreset = ahci_sb600_softreset,
404 .pmp_softreset = ahci_sb600_softreset,
405 };
406
407 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
408
409 static const struct ata_port_info ahci_port_info[] = {
410 [board_ahci] =
411 {
412 .flags = AHCI_FLAG_COMMON,
413 .pio_mask = ATA_PIO4,
414 .udma_mask = ATA_UDMA6,
415 .port_ops = &ahci_ops,
416 },
417 [board_ahci_vt8251] =
418 {
419 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
420 .flags = AHCI_FLAG_COMMON,
421 .pio_mask = ATA_PIO4,
422 .udma_mask = ATA_UDMA6,
423 .port_ops = &ahci_vt8251_ops,
424 },
425 [board_ahci_ign_iferr] =
426 {
427 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
428 .flags = AHCI_FLAG_COMMON,
429 .pio_mask = ATA_PIO4,
430 .udma_mask = ATA_UDMA6,
431 .port_ops = &ahci_ops,
432 },
433 [board_ahci_sb600] =
434 {
435 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
436 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
437 AHCI_HFLAG_SECT255),
438 .flags = AHCI_FLAG_COMMON,
439 .pio_mask = ATA_PIO4,
440 .udma_mask = ATA_UDMA6,
441 .port_ops = &ahci_sb600_ops,
442 },
443 [board_ahci_mv] =
444 {
445 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
446 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
447 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
448 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
449 .pio_mask = ATA_PIO4,
450 .udma_mask = ATA_UDMA6,
451 .port_ops = &ahci_ops,
452 },
453 [board_ahci_sb700] = /* for SB700 and SB800 */
454 {
455 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
456 .flags = AHCI_FLAG_COMMON,
457 .pio_mask = ATA_PIO4,
458 .udma_mask = ATA_UDMA6,
459 .port_ops = &ahci_sb600_ops,
460 },
461 [board_ahci_mcp65] =
462 {
463 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
464 .flags = AHCI_FLAG_COMMON,
465 .pio_mask = ATA_PIO4,
466 .udma_mask = ATA_UDMA6,
467 .port_ops = &ahci_ops,
468 },
469 [board_ahci_nopmp] =
470 {
471 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
472 .flags = AHCI_FLAG_COMMON,
473 .pio_mask = ATA_PIO4,
474 .udma_mask = ATA_UDMA6,
475 .port_ops = &ahci_ops,
476 },
477 /* board_ahci_yesncq */
478 {
479 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
480 .flags = AHCI_FLAG_COMMON,
481 .pio_mask = ATA_PIO4,
482 .udma_mask = ATA_UDMA6,
483 .port_ops = &ahci_ops,
484 },
485 };
486
487 static const struct pci_device_id ahci_pci_tbl[] = {
488 /* Intel */
489 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
490 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
491 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
492 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
493 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
494 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
495 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
496 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
497 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
498 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
499 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
500 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
501 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
502 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
503 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
504 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
505 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
506 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
507 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
508 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
509 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
510 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
511 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
512 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
513 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
514 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
515 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
516 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
517 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
518 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
519 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
520 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
521 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
522 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
523 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
524 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
525 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
526 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
527 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
528 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
529
530 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
531 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
532 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
533
534 /* ATI */
535 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
536 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
537 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
538 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
539 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
540 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
541 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
542
543 /* VIA */
544 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
545 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
546
547 /* NVIDIA */
548 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
549 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
550 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
551 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
552 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
553 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
554 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
555 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
556 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
557 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
558 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
559 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
560 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
561 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
562 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
563 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
564 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
565 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
566 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
567 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
568 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
569 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
570 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
571 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
572 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
573 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
574 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
575 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
576 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
577 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
578 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
579 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
580 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
581 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
582 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
583 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
584 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
585 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
586 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
587 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
588 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
589 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
590 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
591 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
592 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
593 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
594 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
595 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
596 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
597 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
598 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
599 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
600 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
601 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
602 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
603 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
604 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
605 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
606 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
607 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
608 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
609 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
610 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
611 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
612 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
613 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
614 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
615 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
616
617 /* SiS */
618 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
619 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
620 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
621
622 /* Marvell */
623 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
624 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
625
626 /* Promise */
627 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
628
629 /* Generic, PCI class code for AHCI */
630 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
631 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
632
633 { } /* terminate list */
634 };
635
636
637 static struct pci_driver ahci_pci_driver = {
638 .name = DRV_NAME,
639 .id_table = ahci_pci_tbl,
640 .probe = ahci_init_one,
641 .remove = ata_pci_remove_one,
642 #ifdef CONFIG_PM
643 .suspend = ahci_pci_device_suspend,
644 .resume = ahci_pci_device_resume,
645 #endif
646 };
647
648 static int ahci_em_messages = 1;
649 module_param(ahci_em_messages, int, 0444);
650 /* add other LED protocol types when they become supported */
651 MODULE_PARM_DESC(ahci_em_messages,
652 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
653
654 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
655 static int marvell_enable;
656 #else
657 static int marvell_enable = 1;
658 #endif
659 module_param(marvell_enable, int, 0644);
660 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
661
662
663 static inline int ahci_nr_ports(u32 cap)
664 {
665 return (cap & 0x1f) + 1;
666 }
667
668 static inline void __iomem *__ahci_port_base(struct ata_host *host,
669 unsigned int port_no)
670 {
671 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
672
673 return mmio + 0x100 + (port_no * 0x80);
674 }
675
676 static inline void __iomem *ahci_port_base(struct ata_port *ap)
677 {
678 return __ahci_port_base(ap->host, ap->port_no);
679 }
680
681 static void ahci_enable_ahci(void __iomem *mmio)
682 {
683 int i;
684 u32 tmp;
685
686 /* turn on AHCI_EN */
687 tmp = readl(mmio + HOST_CTL);
688 if (tmp & HOST_AHCI_EN)
689 return;
690
691 /* Some controllers need AHCI_EN to be written multiple times.
692 * Try a few times before giving up.
693 */
694 for (i = 0; i < 5; i++) {
695 tmp |= HOST_AHCI_EN;
696 writel(tmp, mmio + HOST_CTL);
697 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
698 if (tmp & HOST_AHCI_EN)
699 return;
700 msleep(10);
701 }
702
703 WARN_ON(1);
704 }
705
706 /**
707 * ahci_save_initial_config - Save and fixup initial config values
708 * @pdev: target PCI device
709 * @hpriv: host private area to store config values
710 *
711 * Some registers containing configuration info might be setup by
712 * BIOS and might be cleared on reset. This function saves the
713 * initial values of those registers into @hpriv such that they
714 * can be restored after controller reset.
715 *
716 * If inconsistent, config values are fixed up by this function.
717 *
718 * LOCKING:
719 * None.
720 */
721 static void ahci_save_initial_config(struct pci_dev *pdev,
722 struct ahci_host_priv *hpriv)
723 {
724 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
725 u32 cap, port_map;
726 int i;
727 int mv;
728
729 /* make sure AHCI mode is enabled before accessing CAP */
730 ahci_enable_ahci(mmio);
731
732 /* Values prefixed with saved_ are written back to host after
733 * reset. Values without are used for driver operation.
734 */
735 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
736 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
737
738 /* some chips have errata preventing 64bit use */
739 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
740 dev_printk(KERN_INFO, &pdev->dev,
741 "controller can't do 64bit DMA, forcing 32bit\n");
742 cap &= ~HOST_CAP_64;
743 }
744
745 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
746 dev_printk(KERN_INFO, &pdev->dev,
747 "controller can't do NCQ, turning off CAP_NCQ\n");
748 cap &= ~HOST_CAP_NCQ;
749 }
750
751 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
752 dev_printk(KERN_INFO, &pdev->dev,
753 "controller can do NCQ, turning on CAP_NCQ\n");
754 cap |= HOST_CAP_NCQ;
755 }
756
757 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
758 dev_printk(KERN_INFO, &pdev->dev,
759 "controller can't do PMP, turning off CAP_PMP\n");
760 cap &= ~HOST_CAP_PMP;
761 }
762
763 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
764 port_map != 1) {
765 dev_printk(KERN_INFO, &pdev->dev,
766 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
767 port_map, 1);
768 port_map = 1;
769 }
770
771 /*
772 * Temporary Marvell 6145 hack: PATA port presence
773 * is asserted through the standard AHCI port
774 * presence register, as bit 4 (counting from 0)
775 */
776 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
777 if (pdev->device == 0x6121)
778 mv = 0x3;
779 else
780 mv = 0xf;
781 dev_printk(KERN_ERR, &pdev->dev,
782 "MV_AHCI HACK: port_map %x -> %x\n",
783 port_map,
784 port_map & mv);
785 dev_printk(KERN_ERR, &pdev->dev,
786 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
787
788 port_map &= mv;
789 }
790
791 /* cross check port_map and cap.n_ports */
792 if (port_map) {
793 int map_ports = 0;
794
795 for (i = 0; i < AHCI_MAX_PORTS; i++)
796 if (port_map & (1 << i))
797 map_ports++;
798
799 /* If PI has more ports than n_ports, whine, clear
800 * port_map and let it be generated from n_ports.
801 */
802 if (map_ports > ahci_nr_ports(cap)) {
803 dev_printk(KERN_WARNING, &pdev->dev,
804 "implemented port map (0x%x) contains more "
805 "ports than nr_ports (%u), using nr_ports\n",
806 port_map, ahci_nr_ports(cap));
807 port_map = 0;
808 }
809 }
810
811 /* fabricate port_map from cap.nr_ports */
812 if (!port_map) {
813 port_map = (1 << ahci_nr_ports(cap)) - 1;
814 dev_printk(KERN_WARNING, &pdev->dev,
815 "forcing PORTS_IMPL to 0x%x\n", port_map);
816
817 /* write the fixed up value to the PI register */
818 hpriv->saved_port_map = port_map;
819 }
820
821 /* record values to use during operation */
822 hpriv->cap = cap;
823 hpriv->port_map = port_map;
824 }
825
826 /**
827 * ahci_restore_initial_config - Restore initial config
828 * @host: target ATA host
829 *
830 * Restore initial config stored by ahci_save_initial_config().
831 *
832 * LOCKING:
833 * None.
834 */
835 static void ahci_restore_initial_config(struct ata_host *host)
836 {
837 struct ahci_host_priv *hpriv = host->private_data;
838 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
839
840 writel(hpriv->saved_cap, mmio + HOST_CAP);
841 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
842 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
843 }
844
845 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
846 {
847 static const int offset[] = {
848 [SCR_STATUS] = PORT_SCR_STAT,
849 [SCR_CONTROL] = PORT_SCR_CTL,
850 [SCR_ERROR] = PORT_SCR_ERR,
851 [SCR_ACTIVE] = PORT_SCR_ACT,
852 [SCR_NOTIFICATION] = PORT_SCR_NTF,
853 };
854 struct ahci_host_priv *hpriv = ap->host->private_data;
855
856 if (sc_reg < ARRAY_SIZE(offset) &&
857 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
858 return offset[sc_reg];
859 return 0;
860 }
861
862 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
863 {
864 void __iomem *port_mmio = ahci_port_base(link->ap);
865 int offset = ahci_scr_offset(link->ap, sc_reg);
866
867 if (offset) {
868 *val = readl(port_mmio + offset);
869 return 0;
870 }
871 return -EINVAL;
872 }
873
874 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
875 {
876 void __iomem *port_mmio = ahci_port_base(link->ap);
877 int offset = ahci_scr_offset(link->ap, sc_reg);
878
879 if (offset) {
880 writel(val, port_mmio + offset);
881 return 0;
882 }
883 return -EINVAL;
884 }
885
886 static void ahci_start_engine(struct ata_port *ap)
887 {
888 void __iomem *port_mmio = ahci_port_base(ap);
889 u32 tmp;
890
891 /* start DMA */
892 tmp = readl(port_mmio + PORT_CMD);
893 tmp |= PORT_CMD_START;
894 writel(tmp, port_mmio + PORT_CMD);
895 readl(port_mmio + PORT_CMD); /* flush */
896 }
897
898 static int ahci_stop_engine(struct ata_port *ap)
899 {
900 void __iomem *port_mmio = ahci_port_base(ap);
901 u32 tmp;
902
903 tmp = readl(port_mmio + PORT_CMD);
904
905 /* check if the HBA is idle */
906 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
907 return 0;
908
909 /* setting HBA to idle */
910 tmp &= ~PORT_CMD_START;
911 writel(tmp, port_mmio + PORT_CMD);
912
913 /* wait for engine to stop. This could be as long as 500 msec */
914 tmp = ata_wait_register(port_mmio + PORT_CMD,
915 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
916 if (tmp & PORT_CMD_LIST_ON)
917 return -EIO;
918
919 return 0;
920 }
921
922 static void ahci_start_fis_rx(struct ata_port *ap)
923 {
924 void __iomem *port_mmio = ahci_port_base(ap);
925 struct ahci_host_priv *hpriv = ap->host->private_data;
926 struct ahci_port_priv *pp = ap->private_data;
927 u32 tmp;
928
929 /* set FIS registers */
930 if (hpriv->cap & HOST_CAP_64)
931 writel((pp->cmd_slot_dma >> 16) >> 16,
932 port_mmio + PORT_LST_ADDR_HI);
933 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
934
935 if (hpriv->cap & HOST_CAP_64)
936 writel((pp->rx_fis_dma >> 16) >> 16,
937 port_mmio + PORT_FIS_ADDR_HI);
938 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
939
940 /* enable FIS reception */
941 tmp = readl(port_mmio + PORT_CMD);
942 tmp |= PORT_CMD_FIS_RX;
943 writel(tmp, port_mmio + PORT_CMD);
944
945 /* flush */
946 readl(port_mmio + PORT_CMD);
947 }
948
949 static int ahci_stop_fis_rx(struct ata_port *ap)
950 {
951 void __iomem *port_mmio = ahci_port_base(ap);
952 u32 tmp;
953
954 /* disable FIS reception */
955 tmp = readl(port_mmio + PORT_CMD);
956 tmp &= ~PORT_CMD_FIS_RX;
957 writel(tmp, port_mmio + PORT_CMD);
958
959 /* wait for completion, spec says 500ms, give it 1000 */
960 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
961 PORT_CMD_FIS_ON, 10, 1000);
962 if (tmp & PORT_CMD_FIS_ON)
963 return -EBUSY;
964
965 return 0;
966 }
967
968 static void ahci_power_up(struct ata_port *ap)
969 {
970 struct ahci_host_priv *hpriv = ap->host->private_data;
971 void __iomem *port_mmio = ahci_port_base(ap);
972 u32 cmd;
973
974 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
975
976 /* spin up device */
977 if (hpriv->cap & HOST_CAP_SSS) {
978 cmd |= PORT_CMD_SPIN_UP;
979 writel(cmd, port_mmio + PORT_CMD);
980 }
981
982 /* wake up link */
983 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
984 }
985
986 static void ahci_disable_alpm(struct ata_port *ap)
987 {
988 struct ahci_host_priv *hpriv = ap->host->private_data;
989 void __iomem *port_mmio = ahci_port_base(ap);
990 u32 cmd;
991 struct ahci_port_priv *pp = ap->private_data;
992
993 /* IPM bits should be disabled by libata-core */
994 /* get the existing command bits */
995 cmd = readl(port_mmio + PORT_CMD);
996
997 /* disable ALPM and ASP */
998 cmd &= ~PORT_CMD_ASP;
999 cmd &= ~PORT_CMD_ALPE;
1000
1001 /* force the interface back to active */
1002 cmd |= PORT_CMD_ICC_ACTIVE;
1003
1004 /* write out new cmd value */
1005 writel(cmd, port_mmio + PORT_CMD);
1006 cmd = readl(port_mmio + PORT_CMD);
1007
1008 /* wait 10ms to be sure we've come out of any low power state */
1009 msleep(10);
1010
1011 /* clear out any PhyRdy stuff from interrupt status */
1012 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1013
1014 /* go ahead and clean out PhyRdy Change from Serror too */
1015 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
1016
1017 /*
1018 * Clear flag to indicate that we should ignore all PhyRdy
1019 * state changes
1020 */
1021 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1022
1023 /*
1024 * Enable interrupts on Phy Ready.
1025 */
1026 pp->intr_mask |= PORT_IRQ_PHYRDY;
1027 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1028
1029 /*
1030 * don't change the link pm policy - we can be called
1031 * just to turn of link pm temporarily
1032 */
1033 }
1034
1035 static int ahci_enable_alpm(struct ata_port *ap,
1036 enum link_pm policy)
1037 {
1038 struct ahci_host_priv *hpriv = ap->host->private_data;
1039 void __iomem *port_mmio = ahci_port_base(ap);
1040 u32 cmd;
1041 struct ahci_port_priv *pp = ap->private_data;
1042 u32 asp;
1043
1044 /* Make sure the host is capable of link power management */
1045 if (!(hpriv->cap & HOST_CAP_ALPM))
1046 return -EINVAL;
1047
1048 switch (policy) {
1049 case MAX_PERFORMANCE:
1050 case NOT_AVAILABLE:
1051 /*
1052 * if we came here with NOT_AVAILABLE,
1053 * it just means this is the first time we
1054 * have tried to enable - default to max performance,
1055 * and let the user go to lower power modes on request.
1056 */
1057 ahci_disable_alpm(ap);
1058 return 0;
1059 case MIN_POWER:
1060 /* configure HBA to enter SLUMBER */
1061 asp = PORT_CMD_ASP;
1062 break;
1063 case MEDIUM_POWER:
1064 /* configure HBA to enter PARTIAL */
1065 asp = 0;
1066 break;
1067 default:
1068 return -EINVAL;
1069 }
1070
1071 /*
1072 * Disable interrupts on Phy Ready. This keeps us from
1073 * getting woken up due to spurious phy ready interrupts
1074 * TBD - Hot plug should be done via polling now, is
1075 * that even supported?
1076 */
1077 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1078 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1079
1080 /*
1081 * Set a flag to indicate that we should ignore all PhyRdy
1082 * state changes since these can happen now whenever we
1083 * change link state
1084 */
1085 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1086
1087 /* get the existing command bits */
1088 cmd = readl(port_mmio + PORT_CMD);
1089
1090 /*
1091 * Set ASP based on Policy
1092 */
1093 cmd |= asp;
1094
1095 /*
1096 * Setting this bit will instruct the HBA to aggressively
1097 * enter a lower power link state when it's appropriate and
1098 * based on the value set above for ASP
1099 */
1100 cmd |= PORT_CMD_ALPE;
1101
1102 /* write out new cmd value */
1103 writel(cmd, port_mmio + PORT_CMD);
1104 cmd = readl(port_mmio + PORT_CMD);
1105
1106 /* IPM bits should be set by libata-core */
1107 return 0;
1108 }
1109
1110 #ifdef CONFIG_PM
1111 static void ahci_power_down(struct ata_port *ap)
1112 {
1113 struct ahci_host_priv *hpriv = ap->host->private_data;
1114 void __iomem *port_mmio = ahci_port_base(ap);
1115 u32 cmd, scontrol;
1116
1117 if (!(hpriv->cap & HOST_CAP_SSS))
1118 return;
1119
1120 /* put device into listen mode, first set PxSCTL.DET to 0 */
1121 scontrol = readl(port_mmio + PORT_SCR_CTL);
1122 scontrol &= ~0xf;
1123 writel(scontrol, port_mmio + PORT_SCR_CTL);
1124
1125 /* then set PxCMD.SUD to 0 */
1126 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1127 cmd &= ~PORT_CMD_SPIN_UP;
1128 writel(cmd, port_mmio + PORT_CMD);
1129 }
1130 #endif
1131
1132 static void ahci_start_port(struct ata_port *ap)
1133 {
1134 struct ahci_port_priv *pp = ap->private_data;
1135 struct ata_link *link;
1136 struct ahci_em_priv *emp;
1137 ssize_t rc;
1138 int i;
1139
1140 /* enable FIS reception */
1141 ahci_start_fis_rx(ap);
1142
1143 /* enable DMA */
1144 ahci_start_engine(ap);
1145
1146 /* turn on LEDs */
1147 if (ap->flags & ATA_FLAG_EM) {
1148 ata_for_each_link(link, ap, EDGE) {
1149 emp = &pp->em_priv[link->pmp];
1150
1151 /* EM Transmit bit maybe busy during init */
1152 for (i = 0; i < EM_MAX_RETRY; i++) {
1153 rc = ahci_transmit_led_message(ap,
1154 emp->led_state,
1155 4);
1156 if (rc == -EBUSY)
1157 msleep(1);
1158 else
1159 break;
1160 }
1161 }
1162 }
1163
1164 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
1165 ata_for_each_link(link, ap, EDGE)
1166 ahci_init_sw_activity(link);
1167
1168 }
1169
1170 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
1171 {
1172 int rc;
1173
1174 /* disable DMA */
1175 rc = ahci_stop_engine(ap);
1176 if (rc) {
1177 *emsg = "failed to stop engine";
1178 return rc;
1179 }
1180
1181 /* disable FIS reception */
1182 rc = ahci_stop_fis_rx(ap);
1183 if (rc) {
1184 *emsg = "failed stop FIS RX";
1185 return rc;
1186 }
1187
1188 return 0;
1189 }
1190
1191 static int ahci_reset_controller(struct ata_host *host)
1192 {
1193 struct pci_dev *pdev = to_pci_dev(host->dev);
1194 struct ahci_host_priv *hpriv = host->private_data;
1195 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1196 u32 tmp;
1197
1198 /* we must be in AHCI mode, before using anything
1199 * AHCI-specific, such as HOST_RESET.
1200 */
1201 ahci_enable_ahci(mmio);
1202
1203 /* global controller reset */
1204 if (!ahci_skip_host_reset) {
1205 tmp = readl(mmio + HOST_CTL);
1206 if ((tmp & HOST_RESET) == 0) {
1207 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1208 readl(mmio + HOST_CTL); /* flush */
1209 }
1210
1211 /*
1212 * to perform host reset, OS should set HOST_RESET
1213 * and poll until this bit is read to be "0".
1214 * reset must complete within 1 second, or
1215 * the hardware should be considered fried.
1216 */
1217 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1218 HOST_RESET, 10, 1000);
1219
1220 if (tmp & HOST_RESET) {
1221 dev_printk(KERN_ERR, host->dev,
1222 "controller reset failed (0x%x)\n", tmp);
1223 return -EIO;
1224 }
1225
1226 /* turn on AHCI mode */
1227 ahci_enable_ahci(mmio);
1228
1229 /* Some registers might be cleared on reset. Restore
1230 * initial values.
1231 */
1232 ahci_restore_initial_config(host);
1233 } else
1234 dev_printk(KERN_INFO, host->dev,
1235 "skipping global host reset\n");
1236
1237 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1238 u16 tmp16;
1239
1240 /* configure PCS */
1241 pci_read_config_word(pdev, 0x92, &tmp16);
1242 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1243 tmp16 |= hpriv->port_map;
1244 pci_write_config_word(pdev, 0x92, tmp16);
1245 }
1246 }
1247
1248 return 0;
1249 }
1250
1251 static void ahci_sw_activity(struct ata_link *link)
1252 {
1253 struct ata_port *ap = link->ap;
1254 struct ahci_port_priv *pp = ap->private_data;
1255 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1256
1257 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1258 return;
1259
1260 emp->activity++;
1261 if (!timer_pending(&emp->timer))
1262 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1263 }
1264
1265 static void ahci_sw_activity_blink(unsigned long arg)
1266 {
1267 struct ata_link *link = (struct ata_link *)arg;
1268 struct ata_port *ap = link->ap;
1269 struct ahci_port_priv *pp = ap->private_data;
1270 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1271 unsigned long led_message = emp->led_state;
1272 u32 activity_led_state;
1273 unsigned long flags;
1274
1275 led_message &= EM_MSG_LED_VALUE;
1276 led_message |= ap->port_no | (link->pmp << 8);
1277
1278 /* check to see if we've had activity. If so,
1279 * toggle state of LED and reset timer. If not,
1280 * turn LED to desired idle state.
1281 */
1282 spin_lock_irqsave(ap->lock, flags);
1283 if (emp->saved_activity != emp->activity) {
1284 emp->saved_activity = emp->activity;
1285 /* get the current LED state */
1286 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
1287
1288 if (activity_led_state)
1289 activity_led_state = 0;
1290 else
1291 activity_led_state = 1;
1292
1293 /* clear old state */
1294 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1295
1296 /* toggle state */
1297 led_message |= (activity_led_state << 16);
1298 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1299 } else {
1300 /* switch to idle */
1301 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
1302 if (emp->blink_policy == BLINK_OFF)
1303 led_message |= (1 << 16);
1304 }
1305 spin_unlock_irqrestore(ap->lock, flags);
1306 ahci_transmit_led_message(ap, led_message, 4);
1307 }
1308
1309 static void ahci_init_sw_activity(struct ata_link *link)
1310 {
1311 struct ata_port *ap = link->ap;
1312 struct ahci_port_priv *pp = ap->private_data;
1313 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1314
1315 /* init activity stats, setup timer */
1316 emp->saved_activity = emp->activity = 0;
1317 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1318
1319 /* check our blink policy and set flag for link if it's enabled */
1320 if (emp->blink_policy)
1321 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1322 }
1323
1324 static int ahci_reset_em(struct ata_host *host)
1325 {
1326 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1327 u32 em_ctl;
1328
1329 em_ctl = readl(mmio + HOST_EM_CTL);
1330 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1331 return -EINVAL;
1332
1333 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1334 return 0;
1335 }
1336
1337 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1338 ssize_t size)
1339 {
1340 struct ahci_host_priv *hpriv = ap->host->private_data;
1341 struct ahci_port_priv *pp = ap->private_data;
1342 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1343 u32 em_ctl;
1344 u32 message[] = {0, 0};
1345 unsigned long flags;
1346 int pmp;
1347 struct ahci_em_priv *emp;
1348
1349 /* get the slot number from the message */
1350 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1351 if (pmp < EM_MAX_SLOTS)
1352 emp = &pp->em_priv[pmp];
1353 else
1354 return -EINVAL;
1355
1356 spin_lock_irqsave(ap->lock, flags);
1357
1358 /*
1359 * if we are still busy transmitting a previous message,
1360 * do not allow
1361 */
1362 em_ctl = readl(mmio + HOST_EM_CTL);
1363 if (em_ctl & EM_CTL_TM) {
1364 spin_unlock_irqrestore(ap->lock, flags);
1365 return -EBUSY;
1366 }
1367
1368 /*
1369 * create message header - this is all zero except for
1370 * the message size, which is 4 bytes.
1371 */
1372 message[0] |= (4 << 8);
1373
1374 /* ignore 0:4 of byte zero, fill in port info yourself */
1375 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
1376
1377 /* write message to EM_LOC */
1378 writel(message[0], mmio + hpriv->em_loc);
1379 writel(message[1], mmio + hpriv->em_loc+4);
1380
1381 /* save off new led state for port/slot */
1382 emp->led_state = state;
1383
1384 /*
1385 * tell hardware to transmit the message
1386 */
1387 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1388
1389 spin_unlock_irqrestore(ap->lock, flags);
1390 return size;
1391 }
1392
1393 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1394 {
1395 struct ahci_port_priv *pp = ap->private_data;
1396 struct ata_link *link;
1397 struct ahci_em_priv *emp;
1398 int rc = 0;
1399
1400 ata_for_each_link(link, ap, EDGE) {
1401 emp = &pp->em_priv[link->pmp];
1402 rc += sprintf(buf, "%lx\n", emp->led_state);
1403 }
1404 return rc;
1405 }
1406
1407 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1408 size_t size)
1409 {
1410 int state;
1411 int pmp;
1412 struct ahci_port_priv *pp = ap->private_data;
1413 struct ahci_em_priv *emp;
1414
1415 state = simple_strtoul(buf, NULL, 0);
1416
1417 /* get the slot number from the message */
1418 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1419 if (pmp < EM_MAX_SLOTS)
1420 emp = &pp->em_priv[pmp];
1421 else
1422 return -EINVAL;
1423
1424 /* mask off the activity bits if we are in sw_activity
1425 * mode, user should turn off sw_activity before setting
1426 * activity led through em_message
1427 */
1428 if (emp->blink_policy)
1429 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1430
1431 return ahci_transmit_led_message(ap, state, size);
1432 }
1433
1434 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1435 {
1436 struct ata_link *link = dev->link;
1437 struct ata_port *ap = link->ap;
1438 struct ahci_port_priv *pp = ap->private_data;
1439 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1440 u32 port_led_state = emp->led_state;
1441
1442 /* save the desired Activity LED behavior */
1443 if (val == OFF) {
1444 /* clear LFLAG */
1445 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1446
1447 /* set the LED to OFF */
1448 port_led_state &= EM_MSG_LED_VALUE_OFF;
1449 port_led_state |= (ap->port_no | (link->pmp << 8));
1450 ahci_transmit_led_message(ap, port_led_state, 4);
1451 } else {
1452 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1453 if (val == BLINK_OFF) {
1454 /* set LED to ON for idle */
1455 port_led_state &= EM_MSG_LED_VALUE_OFF;
1456 port_led_state |= (ap->port_no | (link->pmp << 8));
1457 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1458 ahci_transmit_led_message(ap, port_led_state, 4);
1459 }
1460 }
1461 emp->blink_policy = val;
1462 return 0;
1463 }
1464
1465 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1466 {
1467 struct ata_link *link = dev->link;
1468 struct ata_port *ap = link->ap;
1469 struct ahci_port_priv *pp = ap->private_data;
1470 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1471
1472 /* display the saved value of activity behavior for this
1473 * disk.
1474 */
1475 return sprintf(buf, "%d\n", emp->blink_policy);
1476 }
1477
1478 static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1479 int port_no, void __iomem *mmio,
1480 void __iomem *port_mmio)
1481 {
1482 const char *emsg = NULL;
1483 int rc;
1484 u32 tmp;
1485
1486 /* make sure port is not active */
1487 rc = ahci_deinit_port(ap, &emsg);
1488 if (rc)
1489 dev_printk(KERN_WARNING, &pdev->dev,
1490 "%s (%d)\n", emsg, rc);
1491
1492 /* clear SError */
1493 tmp = readl(port_mmio + PORT_SCR_ERR);
1494 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1495 writel(tmp, port_mmio + PORT_SCR_ERR);
1496
1497 /* clear port IRQ */
1498 tmp = readl(port_mmio + PORT_IRQ_STAT);
1499 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1500 if (tmp)
1501 writel(tmp, port_mmio + PORT_IRQ_STAT);
1502
1503 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1504 }
1505
1506 static void ahci_init_controller(struct ata_host *host)
1507 {
1508 struct ahci_host_priv *hpriv = host->private_data;
1509 struct pci_dev *pdev = to_pci_dev(host->dev);
1510 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1511 int i;
1512 void __iomem *port_mmio;
1513 u32 tmp;
1514 int mv;
1515
1516 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
1517 if (pdev->device == 0x6121)
1518 mv = 2;
1519 else
1520 mv = 4;
1521 port_mmio = __ahci_port_base(host, mv);
1522
1523 writel(0, port_mmio + PORT_IRQ_MASK);
1524
1525 /* clear port IRQ */
1526 tmp = readl(port_mmio + PORT_IRQ_STAT);
1527 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1528 if (tmp)
1529 writel(tmp, port_mmio + PORT_IRQ_STAT);
1530 }
1531
1532 for (i = 0; i < host->n_ports; i++) {
1533 struct ata_port *ap = host->ports[i];
1534
1535 port_mmio = ahci_port_base(ap);
1536 if (ata_port_is_dummy(ap))
1537 continue;
1538
1539 ahci_port_init(pdev, ap, i, mmio, port_mmio);
1540 }
1541
1542 tmp = readl(mmio + HOST_CTL);
1543 VPRINTK("HOST_CTL 0x%x\n", tmp);
1544 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1545 tmp = readl(mmio + HOST_CTL);
1546 VPRINTK("HOST_CTL 0x%x\n", tmp);
1547 }
1548
1549 static void ahci_dev_config(struct ata_device *dev)
1550 {
1551 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1552
1553 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1554 dev->max_sectors = 255;
1555 ata_dev_printk(dev, KERN_INFO,
1556 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1557 }
1558 }
1559
1560 static unsigned int ahci_dev_classify(struct ata_port *ap)
1561 {
1562 void __iomem *port_mmio = ahci_port_base(ap);
1563 struct ata_taskfile tf;
1564 u32 tmp;
1565
1566 tmp = readl(port_mmio + PORT_SIG);
1567 tf.lbah = (tmp >> 24) & 0xff;
1568 tf.lbam = (tmp >> 16) & 0xff;
1569 tf.lbal = (tmp >> 8) & 0xff;
1570 tf.nsect = (tmp) & 0xff;
1571
1572 return ata_dev_classify(&tf);
1573 }
1574
1575 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1576 u32 opts)
1577 {
1578 dma_addr_t cmd_tbl_dma;
1579
1580 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1581
1582 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1583 pp->cmd_slot[tag].status = 0;
1584 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1585 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1586 }
1587
1588 static int ahci_kick_engine(struct ata_port *ap, int force_restart)
1589 {
1590 void __iomem *port_mmio = ahci_port_base(ap);
1591 struct ahci_host_priv *hpriv = ap->host->private_data;
1592 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1593 u32 tmp;
1594 int busy, rc;
1595
1596 /* do we need to kick the port? */
1597 busy = status & (ATA_BUSY | ATA_DRQ);
1598 if (!busy && !force_restart)
1599 return 0;
1600
1601 /* stop engine */
1602 rc = ahci_stop_engine(ap);
1603 if (rc)
1604 goto out_restart;
1605
1606 /* need to do CLO? */
1607 if (!busy) {
1608 rc = 0;
1609 goto out_restart;
1610 }
1611
1612 if (!(hpriv->cap & HOST_CAP_CLO)) {
1613 rc = -EOPNOTSUPP;
1614 goto out_restart;
1615 }
1616
1617 /* perform CLO */
1618 tmp = readl(port_mmio + PORT_CMD);
1619 tmp |= PORT_CMD_CLO;
1620 writel(tmp, port_mmio + PORT_CMD);
1621
1622 rc = 0;
1623 tmp = ata_wait_register(port_mmio + PORT_CMD,
1624 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1625 if (tmp & PORT_CMD_CLO)
1626 rc = -EIO;
1627
1628 /* restart engine */
1629 out_restart:
1630 ahci_start_engine(ap);
1631 return rc;
1632 }
1633
1634 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1635 struct ata_taskfile *tf, int is_cmd, u16 flags,
1636 unsigned long timeout_msec)
1637 {
1638 const u32 cmd_fis_len = 5; /* five dwords */
1639 struct ahci_port_priv *pp = ap->private_data;
1640 void __iomem *port_mmio = ahci_port_base(ap);
1641 u8 *fis = pp->cmd_tbl;
1642 u32 tmp;
1643
1644 /* prep the command */
1645 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1646 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1647
1648 /* issue & wait */
1649 writel(1, port_mmio + PORT_CMD_ISSUE);
1650
1651 if (timeout_msec) {
1652 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1653 1, timeout_msec);
1654 if (tmp & 0x1) {
1655 ahci_kick_engine(ap, 1);
1656 return -EBUSY;
1657 }
1658 } else
1659 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1660
1661 return 0;
1662 }
1663
1664 static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1665 int pmp, unsigned long deadline,
1666 int (*check_ready)(struct ata_link *link))
1667 {
1668 struct ata_port *ap = link->ap;
1669 struct ahci_host_priv *hpriv = ap->host->private_data;
1670 const char *reason = NULL;
1671 unsigned long now, msecs;
1672 struct ata_taskfile tf;
1673 int rc;
1674
1675 DPRINTK("ENTER\n");
1676
1677 /* prepare for SRST (AHCI-1.1 10.4.1) */
1678 rc = ahci_kick_engine(ap, 1);
1679 if (rc && rc != -EOPNOTSUPP)
1680 ata_link_printk(link, KERN_WARNING,
1681 "failed to reset engine (errno=%d)\n", rc);
1682
1683 ata_tf_init(link->device, &tf);
1684
1685 /* issue the first D2H Register FIS */
1686 msecs = 0;
1687 now = jiffies;
1688 if (time_after(now, deadline))
1689 msecs = jiffies_to_msecs(deadline - now);
1690
1691 tf.ctl |= ATA_SRST;
1692 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1693 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1694 rc = -EIO;
1695 reason = "1st FIS failed";
1696 goto fail;
1697 }
1698
1699 /* spec says at least 5us, but be generous and sleep for 1ms */
1700 msleep(1);
1701
1702 /* issue the second D2H Register FIS */
1703 tf.ctl &= ~ATA_SRST;
1704 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1705
1706 /* wait for link to become ready */
1707 rc = ata_wait_after_reset(link, deadline, check_ready);
1708 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1709 /*
1710 * Workaround for cases where link online status can't
1711 * be trusted. Treat device readiness timeout as link
1712 * offline.
1713 */
1714 ata_link_printk(link, KERN_INFO,
1715 "device not ready, treating as offline\n");
1716 *class = ATA_DEV_NONE;
1717 } else if (rc) {
1718 /* link occupied, -ENODEV too is an error */
1719 reason = "device not ready";
1720 goto fail;
1721 } else
1722 *class = ahci_dev_classify(ap);
1723
1724 DPRINTK("EXIT, class=%u\n", *class);
1725 return 0;
1726
1727 fail:
1728 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
1729 return rc;
1730 }
1731
1732 static int ahci_check_ready(struct ata_link *link)
1733 {
1734 void __iomem *port_mmio = ahci_port_base(link->ap);
1735 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1736
1737 return ata_check_ready(status);
1738 }
1739
1740 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1741 unsigned long deadline)
1742 {
1743 int pmp = sata_srst_pmp(link);
1744
1745 DPRINTK("ENTER\n");
1746
1747 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1748 }
1749
1750 static int ahci_sb600_check_ready(struct ata_link *link)
1751 {
1752 void __iomem *port_mmio = ahci_port_base(link->ap);
1753 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1754 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1755
1756 /*
1757 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1758 * which can save timeout delay.
1759 */
1760 if (irq_status & PORT_IRQ_BAD_PMP)
1761 return -EIO;
1762
1763 return ata_check_ready(status);
1764 }
1765
1766 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1767 unsigned long deadline)
1768 {
1769 struct ata_port *ap = link->ap;
1770 void __iomem *port_mmio = ahci_port_base(ap);
1771 int pmp = sata_srst_pmp(link);
1772 int rc;
1773 u32 irq_sts;
1774
1775 DPRINTK("ENTER\n");
1776
1777 rc = ahci_do_softreset(link, class, pmp, deadline,
1778 ahci_sb600_check_ready);
1779
1780 /*
1781 * Soft reset fails on some ATI chips with IPMS set when PMP
1782 * is enabled but SATA HDD/ODD is connected to SATA port,
1783 * do soft reset again to port 0.
1784 */
1785 if (rc == -EIO) {
1786 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1787 if (irq_sts & PORT_IRQ_BAD_PMP) {
1788 ata_link_printk(link, KERN_WARNING,
1789 "applying SB600 PMP SRST workaround "
1790 "and retrying\n");
1791 rc = ahci_do_softreset(link, class, 0, deadline,
1792 ahci_check_ready);
1793 }
1794 }
1795
1796 return rc;
1797 }
1798
1799 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1800 unsigned long deadline)
1801 {
1802 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1803 struct ata_port *ap = link->ap;
1804 struct ahci_port_priv *pp = ap->private_data;
1805 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1806 struct ata_taskfile tf;
1807 bool online;
1808 int rc;
1809
1810 DPRINTK("ENTER\n");
1811
1812 ahci_stop_engine(ap);
1813
1814 /* clear D2H reception area to properly wait for D2H FIS */
1815 ata_tf_init(link->device, &tf);
1816 tf.command = 0x80;
1817 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1818
1819 rc = sata_link_hardreset(link, timing, deadline, &online,
1820 ahci_check_ready);
1821
1822 ahci_start_engine(ap);
1823
1824 if (online)
1825 *class = ahci_dev_classify(ap);
1826
1827 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1828 return rc;
1829 }
1830
1831 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
1832 unsigned long deadline)
1833 {
1834 struct ata_port *ap = link->ap;
1835 bool online;
1836 int rc;
1837
1838 DPRINTK("ENTER\n");
1839
1840 ahci_stop_engine(ap);
1841
1842 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1843 deadline, &online, NULL);
1844
1845 ahci_start_engine(ap);
1846
1847 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1848
1849 /* vt8251 doesn't clear BSY on signature FIS reception,
1850 * request follow-up softreset.
1851 */
1852 return online ? -EAGAIN : rc;
1853 }
1854
1855 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1856 unsigned long deadline)
1857 {
1858 struct ata_port *ap = link->ap;
1859 struct ahci_port_priv *pp = ap->private_data;
1860 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1861 struct ata_taskfile tf;
1862 bool online;
1863 int rc;
1864
1865 ahci_stop_engine(ap);
1866
1867 /* clear D2H reception area to properly wait for D2H FIS */
1868 ata_tf_init(link->device, &tf);
1869 tf.command = 0x80;
1870 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1871
1872 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1873 deadline, &online, NULL);
1874
1875 ahci_start_engine(ap);
1876
1877 /* The pseudo configuration device on SIMG4726 attached to
1878 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1879 * hardreset if no device is attached to the first downstream
1880 * port && the pseudo device locks up on SRST w/ PMP==0. To
1881 * work around this, wait for !BSY only briefly. If BSY isn't
1882 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1883 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1884 *
1885 * Wait for two seconds. Devices attached to downstream port
1886 * which can't process the following IDENTIFY after this will
1887 * have to be reset again. For most cases, this should
1888 * suffice while making probing snappish enough.
1889 */
1890 if (online) {
1891 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1892 ahci_check_ready);
1893 if (rc)
1894 ahci_kick_engine(ap, 0);
1895 }
1896 return rc;
1897 }
1898
1899 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1900 {
1901 struct ata_port *ap = link->ap;
1902 void __iomem *port_mmio = ahci_port_base(ap);
1903 u32 new_tmp, tmp;
1904
1905 ata_std_postreset(link, class);
1906
1907 /* Make sure port's ATAPI bit is set appropriately */
1908 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1909 if (*class == ATA_DEV_ATAPI)
1910 new_tmp |= PORT_CMD_ATAPI;
1911 else
1912 new_tmp &= ~PORT_CMD_ATAPI;
1913 if (new_tmp != tmp) {
1914 writel(new_tmp, port_mmio + PORT_CMD);
1915 readl(port_mmio + PORT_CMD); /* flush */
1916 }
1917 }
1918
1919 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1920 {
1921 struct scatterlist *sg;
1922 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1923 unsigned int si;
1924
1925 VPRINTK("ENTER\n");
1926
1927 /*
1928 * Next, the S/G list.
1929 */
1930 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1931 dma_addr_t addr = sg_dma_address(sg);
1932 u32 sg_len = sg_dma_len(sg);
1933
1934 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1935 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1936 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1937 }
1938
1939 return si;
1940 }
1941
1942 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1943 {
1944 struct ata_port *ap = qc->ap;
1945 struct ahci_port_priv *pp = ap->private_data;
1946 int is_atapi = ata_is_atapi(qc->tf.protocol);
1947 void *cmd_tbl;
1948 u32 opts;
1949 const u32 cmd_fis_len = 5; /* five dwords */
1950 unsigned int n_elem;
1951
1952 /*
1953 * Fill in command table information. First, the header,
1954 * a SATA Register - Host to Device command FIS.
1955 */
1956 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1957
1958 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1959 if (is_atapi) {
1960 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1961 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1962 }
1963
1964 n_elem = 0;
1965 if (qc->flags & ATA_QCFLAG_DMAMAP)
1966 n_elem = ahci_fill_sg(qc, cmd_tbl);
1967
1968 /*
1969 * Fill in command slot information.
1970 */
1971 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1972 if (qc->tf.flags & ATA_TFLAG_WRITE)
1973 opts |= AHCI_CMD_WRITE;
1974 if (is_atapi)
1975 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1976
1977 ahci_fill_cmd_slot(pp, qc->tag, opts);
1978 }
1979
1980 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1981 {
1982 struct ahci_host_priv *hpriv = ap->host->private_data;
1983 struct ahci_port_priv *pp = ap->private_data;
1984 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1985 struct ata_link *link = NULL;
1986 struct ata_queued_cmd *active_qc;
1987 struct ata_eh_info *active_ehi;
1988 u32 serror;
1989
1990 /* determine active link */
1991 ata_for_each_link(link, ap, EDGE)
1992 if (ata_link_active(link))
1993 break;
1994 if (!link)
1995 link = &ap->link;
1996
1997 active_qc = ata_qc_from_tag(ap, link->active_tag);
1998 active_ehi = &link->eh_info;
1999
2000 /* record irq stat */
2001 ata_ehi_clear_desc(host_ehi);
2002 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
2003
2004 /* AHCI needs SError cleared; otherwise, it might lock up */
2005 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2006 ahci_scr_write(&ap->link, SCR_ERROR, serror);
2007 host_ehi->serror |= serror;
2008
2009 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
2010 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
2011 irq_stat &= ~PORT_IRQ_IF_ERR;
2012
2013 if (irq_stat & PORT_IRQ_TF_ERR) {
2014 /* If qc is active, charge it; otherwise, the active
2015 * link. There's no active qc on NCQ errors. It will
2016 * be determined by EH by reading log page 10h.
2017 */
2018 if (active_qc)
2019 active_qc->err_mask |= AC_ERR_DEV;
2020 else
2021 active_ehi->err_mask |= AC_ERR_DEV;
2022
2023 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
2024 host_ehi->serror &= ~SERR_INTERNAL;
2025 }
2026
2027 if (irq_stat & PORT_IRQ_UNK_FIS) {
2028 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
2029
2030 active_ehi->err_mask |= AC_ERR_HSM;
2031 active_ehi->action |= ATA_EH_RESET;
2032 ata_ehi_push_desc(active_ehi,
2033 "unknown FIS %08x %08x %08x %08x" ,
2034 unk[0], unk[1], unk[2], unk[3]);
2035 }
2036
2037 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
2038 active_ehi->err_mask |= AC_ERR_HSM;
2039 active_ehi->action |= ATA_EH_RESET;
2040 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2041 }
2042
2043 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2044 host_ehi->err_mask |= AC_ERR_HOST_BUS;
2045 host_ehi->action |= ATA_EH_RESET;
2046 ata_ehi_push_desc(host_ehi, "host bus error");
2047 }
2048
2049 if (irq_stat & PORT_IRQ_IF_ERR) {
2050 host_ehi->err_mask |= AC_ERR_ATA_BUS;
2051 host_ehi->action |= ATA_EH_RESET;
2052 ata_ehi_push_desc(host_ehi, "interface fatal error");
2053 }
2054
2055 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2056 ata_ehi_hotplugged(host_ehi);
2057 ata_ehi_push_desc(host_ehi, "%s",
2058 irq_stat & PORT_IRQ_CONNECT ?
2059 "connection status changed" : "PHY RDY changed");
2060 }
2061
2062 /* okay, let's hand over to EH */
2063
2064 if (irq_stat & PORT_IRQ_FREEZE)
2065 ata_port_freeze(ap);
2066 else
2067 ata_port_abort(ap);
2068 }
2069
2070 static void ahci_port_intr(struct ata_port *ap)
2071 {
2072 void __iomem *port_mmio = ahci_port_base(ap);
2073 struct ata_eh_info *ehi = &ap->link.eh_info;
2074 struct ahci_port_priv *pp = ap->private_data;
2075 struct ahci_host_priv *hpriv = ap->host->private_data;
2076 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
2077 u32 status, qc_active;
2078 int rc;
2079
2080 status = readl(port_mmio + PORT_IRQ_STAT);
2081 writel(status, port_mmio + PORT_IRQ_STAT);
2082
2083 /* ignore BAD_PMP while resetting */
2084 if (unlikely(resetting))
2085 status &= ~PORT_IRQ_BAD_PMP;
2086
2087 /* If we are getting PhyRdy, this is
2088 * just a power state change, we should
2089 * clear out this, plus the PhyRdy/Comm
2090 * Wake bits from Serror
2091 */
2092 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2093 (status & PORT_IRQ_PHYRDY)) {
2094 status &= ~PORT_IRQ_PHYRDY;
2095 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
2096 }
2097
2098 if (unlikely(status & PORT_IRQ_ERROR)) {
2099 ahci_error_intr(ap, status);
2100 return;
2101 }
2102
2103 if (status & PORT_IRQ_SDB_FIS) {
2104 /* If SNotification is available, leave notification
2105 * handling to sata_async_notification(). If not,
2106 * emulate it by snooping SDB FIS RX area.
2107 *
2108 * Snooping FIS RX area is probably cheaper than
2109 * poking SNotification but some constrollers which
2110 * implement SNotification, ICH9 for example, don't
2111 * store AN SDB FIS into receive area.
2112 */
2113 if (hpriv->cap & HOST_CAP_SNTF)
2114 sata_async_notification(ap);
2115 else {
2116 /* If the 'N' bit in word 0 of the FIS is set,
2117 * we just received asynchronous notification.
2118 * Tell libata about it.
2119 */
2120 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2121 u32 f0 = le32_to_cpu(f[0]);
2122
2123 if (f0 & (1 << 15))
2124 sata_async_notification(ap);
2125 }
2126 }
2127
2128 /* pp->active_link is valid iff any command is in flight */
2129 if (ap->qc_active && pp->active_link->sactive)
2130 qc_active = readl(port_mmio + PORT_SCR_ACT);
2131 else
2132 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2133
2134 rc = ata_qc_complete_multiple(ap, qc_active);
2135
2136 /* while resetting, invalid completions are expected */
2137 if (unlikely(rc < 0 && !resetting)) {
2138 ehi->err_mask |= AC_ERR_HSM;
2139 ehi->action |= ATA_EH_RESET;
2140 ata_port_freeze(ap);
2141 }
2142 }
2143
2144 static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
2145 {
2146 struct ata_host *host = dev_instance;
2147 struct ahci_host_priv *hpriv;
2148 unsigned int i, handled = 0;
2149 void __iomem *mmio;
2150 u32 irq_stat, irq_masked;
2151
2152 VPRINTK("ENTER\n");
2153
2154 hpriv = host->private_data;
2155 mmio = host->iomap[AHCI_PCI_BAR];
2156
2157 /* sigh. 0xffffffff is a valid return from h/w */
2158 irq_stat = readl(mmio + HOST_IRQ_STAT);
2159 if (!irq_stat)
2160 return IRQ_NONE;
2161
2162 irq_masked = irq_stat & hpriv->port_map;
2163
2164 spin_lock(&host->lock);
2165
2166 for (i = 0; i < host->n_ports; i++) {
2167 struct ata_port *ap;
2168
2169 if (!(irq_masked & (1 << i)))
2170 continue;
2171
2172 ap = host->ports[i];
2173 if (ap) {
2174 ahci_port_intr(ap);
2175 VPRINTK("port %u\n", i);
2176 } else {
2177 VPRINTK("port %u (no irq)\n", i);
2178 if (ata_ratelimit())
2179 dev_printk(KERN_WARNING, host->dev,
2180 "interrupt on disabled port %u\n", i);
2181 }
2182
2183 handled = 1;
2184 }
2185
2186 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2187 * it should be cleared after all the port events are cleared;
2188 * otherwise, it will raise a spurious interrupt after each
2189 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2190 * information.
2191 *
2192 * Also, use the unmasked value to clear interrupt as spurious
2193 * pending event on a dummy port might cause screaming IRQ.
2194 */
2195 writel(irq_stat, mmio + HOST_IRQ_STAT);
2196
2197 spin_unlock(&host->lock);
2198
2199 VPRINTK("EXIT\n");
2200
2201 return IRQ_RETVAL(handled);
2202 }
2203
2204 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
2205 {
2206 struct ata_port *ap = qc->ap;
2207 void __iomem *port_mmio = ahci_port_base(ap);
2208 struct ahci_port_priv *pp = ap->private_data;
2209
2210 /* Keep track of the currently active link. It will be used
2211 * in completion path to determine whether NCQ phase is in
2212 * progress.
2213 */
2214 pp->active_link = qc->dev->link;
2215
2216 if (qc->tf.protocol == ATA_PROT_NCQ)
2217 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2218 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
2219
2220 ahci_sw_activity(qc->dev->link);
2221
2222 return 0;
2223 }
2224
2225 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2226 {
2227 struct ahci_port_priv *pp = qc->ap->private_data;
2228 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2229
2230 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2231 return true;
2232 }
2233
2234 static void ahci_freeze(struct ata_port *ap)
2235 {
2236 void __iomem *port_mmio = ahci_port_base(ap);
2237
2238 /* turn IRQ off */
2239 writel(0, port_mmio + PORT_IRQ_MASK);
2240 }
2241
2242 static void ahci_thaw(struct ata_port *ap)
2243 {
2244 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
2245 void __iomem *port_mmio = ahci_port_base(ap);
2246 u32 tmp;
2247 struct ahci_port_priv *pp = ap->private_data;
2248
2249 /* clear IRQ */
2250 tmp = readl(port_mmio + PORT_IRQ_STAT);
2251 writel(tmp, port_mmio + PORT_IRQ_STAT);
2252 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
2253
2254 /* turn IRQ back on */
2255 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2256 }
2257
2258 static void ahci_error_handler(struct ata_port *ap)
2259 {
2260 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2261 /* restart engine */
2262 ahci_stop_engine(ap);
2263 ahci_start_engine(ap);
2264 }
2265
2266 sata_pmp_error_handler(ap);
2267 }
2268
2269 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2270 {
2271 struct ata_port *ap = qc->ap;
2272
2273 /* make DMA engine forget about the failed command */
2274 if (qc->flags & ATA_QCFLAG_FAILED)
2275 ahci_kick_engine(ap, 1);
2276 }
2277
2278 static void ahci_pmp_attach(struct ata_port *ap)
2279 {
2280 void __iomem *port_mmio = ahci_port_base(ap);
2281 struct ahci_port_priv *pp = ap->private_data;
2282 u32 cmd;
2283
2284 cmd = readl(port_mmio + PORT_CMD);
2285 cmd |= PORT_CMD_PMP;
2286 writel(cmd, port_mmio + PORT_CMD);
2287
2288 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2289 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2290 }
2291
2292 static void ahci_pmp_detach(struct ata_port *ap)
2293 {
2294 void __iomem *port_mmio = ahci_port_base(ap);
2295 struct ahci_port_priv *pp = ap->private_data;
2296 u32 cmd;
2297
2298 cmd = readl(port_mmio + PORT_CMD);
2299 cmd &= ~PORT_CMD_PMP;
2300 writel(cmd, port_mmio + PORT_CMD);
2301
2302 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2303 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2304 }
2305
2306 static int ahci_port_resume(struct ata_port *ap)
2307 {
2308 ahci_power_up(ap);
2309 ahci_start_port(ap);
2310
2311 if (sata_pmp_attached(ap))
2312 ahci_pmp_attach(ap);
2313 else
2314 ahci_pmp_detach(ap);
2315
2316 return 0;
2317 }
2318
2319 #ifdef CONFIG_PM
2320 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2321 {
2322 const char *emsg = NULL;
2323 int rc;
2324
2325 rc = ahci_deinit_port(ap, &emsg);
2326 if (rc == 0)
2327 ahci_power_down(ap);
2328 else {
2329 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
2330 ahci_start_port(ap);
2331 }
2332
2333 return rc;
2334 }
2335
2336 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2337 {
2338 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2339 struct ahci_host_priv *hpriv = host->private_data;
2340 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2341 u32 ctl;
2342
2343 if (mesg.event & PM_EVENT_SUSPEND &&
2344 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2345 dev_printk(KERN_ERR, &pdev->dev,
2346 "BIOS update required for suspend/resume\n");
2347 return -EIO;
2348 }
2349
2350 if (mesg.event & PM_EVENT_SLEEP) {
2351 /* AHCI spec rev1.1 section 8.3.3:
2352 * Software must disable interrupts prior to requesting a
2353 * transition of the HBA to D3 state.
2354 */
2355 ctl = readl(mmio + HOST_CTL);
2356 ctl &= ~HOST_IRQ_EN;
2357 writel(ctl, mmio + HOST_CTL);
2358 readl(mmio + HOST_CTL); /* flush */
2359 }
2360
2361 return ata_pci_device_suspend(pdev, mesg);
2362 }
2363
2364 static int ahci_pci_device_resume(struct pci_dev *pdev)
2365 {
2366 struct ata_host *host = dev_get_drvdata(&pdev->dev);
2367 int rc;
2368
2369 rc = ata_pci_device_do_resume(pdev);
2370 if (rc)
2371 return rc;
2372
2373 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
2374 rc = ahci_reset_controller(host);
2375 if (rc)
2376 return rc;
2377
2378 ahci_init_controller(host);
2379 }
2380
2381 ata_host_resume(host);
2382
2383 return 0;
2384 }
2385 #endif
2386
2387 static int ahci_port_start(struct ata_port *ap)
2388 {
2389 struct device *dev = ap->host->dev;
2390 struct ahci_port_priv *pp;
2391 void *mem;
2392 dma_addr_t mem_dma;
2393
2394 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2395 if (!pp)
2396 return -ENOMEM;
2397
2398 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2399 GFP_KERNEL);
2400 if (!mem)
2401 return -ENOMEM;
2402 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2403
2404 /*
2405 * First item in chunk of DMA memory: 32-slot command table,
2406 * 32 bytes each in size
2407 */
2408 pp->cmd_slot = mem;
2409 pp->cmd_slot_dma = mem_dma;
2410
2411 mem += AHCI_CMD_SLOT_SZ;
2412 mem_dma += AHCI_CMD_SLOT_SZ;
2413
2414 /*
2415 * Second item: Received-FIS area
2416 */
2417 pp->rx_fis = mem;
2418 pp->rx_fis_dma = mem_dma;
2419
2420 mem += AHCI_RX_FIS_SZ;
2421 mem_dma += AHCI_RX_FIS_SZ;
2422
2423 /*
2424 * Third item: data area for storing a single command
2425 * and its scatter-gather table
2426 */
2427 pp->cmd_tbl = mem;
2428 pp->cmd_tbl_dma = mem_dma;
2429
2430 /*
2431 * Save off initial list of interrupts to be enabled.
2432 * This could be changed later
2433 */
2434 pp->intr_mask = DEF_PORT_IRQ;
2435
2436 ap->private_data = pp;
2437
2438 /* engage engines, captain */
2439 return ahci_port_resume(ap);
2440 }
2441
2442 static void ahci_port_stop(struct ata_port *ap)
2443 {
2444 const char *emsg = NULL;
2445 int rc;
2446
2447 /* de-initialize port */
2448 rc = ahci_deinit_port(ap, &emsg);
2449 if (rc)
2450 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
2451 }
2452
2453 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
2454 {
2455 int rc;
2456
2457 if (using_dac &&
2458 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2459 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2460 if (rc) {
2461 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2462 if (rc) {
2463 dev_printk(KERN_ERR, &pdev->dev,
2464 "64-bit DMA enable failed\n");
2465 return rc;
2466 }
2467 }
2468 } else {
2469 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2470 if (rc) {
2471 dev_printk(KERN_ERR, &pdev->dev,
2472 "32-bit DMA enable failed\n");
2473 return rc;
2474 }
2475 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
2476 if (rc) {
2477 dev_printk(KERN_ERR, &pdev->dev,
2478 "32-bit consistent DMA enable failed\n");
2479 return rc;
2480 }
2481 }
2482 return 0;
2483 }
2484
2485 static void ahci_print_info(struct ata_host *host)
2486 {
2487 struct ahci_host_priv *hpriv = host->private_data;
2488 struct pci_dev *pdev = to_pci_dev(host->dev);
2489 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
2490 u32 vers, cap, impl, speed;
2491 const char *speed_s;
2492 u16 cc;
2493 const char *scc_s;
2494
2495 vers = readl(mmio + HOST_VERSION);
2496 cap = hpriv->cap;
2497 impl = hpriv->port_map;
2498
2499 speed = (cap >> 20) & 0xf;
2500 if (speed == 1)
2501 speed_s = "1.5";
2502 else if (speed == 2)
2503 speed_s = "3";
2504 else if (speed == 3)
2505 speed_s = "6";
2506 else
2507 speed_s = "?";
2508
2509 pci_read_config_word(pdev, 0x0a, &cc);
2510 if (cc == PCI_CLASS_STORAGE_IDE)
2511 scc_s = "IDE";
2512 else if (cc == PCI_CLASS_STORAGE_SATA)
2513 scc_s = "SATA";
2514 else if (cc == PCI_CLASS_STORAGE_RAID)
2515 scc_s = "RAID";
2516 else
2517 scc_s = "unknown";
2518
2519 dev_printk(KERN_INFO, &pdev->dev,
2520 "AHCI %02x%02x.%02x%02x "
2521 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2522 ,
2523
2524 (vers >> 24) & 0xff,
2525 (vers >> 16) & 0xff,
2526 (vers >> 8) & 0xff,
2527 vers & 0xff,
2528
2529 ((cap >> 8) & 0x1f) + 1,
2530 (cap & 0x1f) + 1,
2531 speed_s,
2532 impl,
2533 scc_s);
2534
2535 dev_printk(KERN_INFO, &pdev->dev,
2536 "flags: "
2537 "%s%s%s%s%s%s%s"
2538 "%s%s%s%s%s%s%s"
2539 "%s\n"
2540 ,
2541
2542 cap & (1 << 31) ? "64bit " : "",
2543 cap & (1 << 30) ? "ncq " : "",
2544 cap & (1 << 29) ? "sntf " : "",
2545 cap & (1 << 28) ? "ilck " : "",
2546 cap & (1 << 27) ? "stag " : "",
2547 cap & (1 << 26) ? "pm " : "",
2548 cap & (1 << 25) ? "led " : "",
2549
2550 cap & (1 << 24) ? "clo " : "",
2551 cap & (1 << 19) ? "nz " : "",
2552 cap & (1 << 18) ? "only " : "",
2553 cap & (1 << 17) ? "pmp " : "",
2554 cap & (1 << 15) ? "pio " : "",
2555 cap & (1 << 14) ? "slum " : "",
2556 cap & (1 << 13) ? "part " : "",
2557 cap & (1 << 6) ? "ems ": ""
2558 );
2559 }
2560
2561 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2562 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2563 * support PMP and the 4726 either directly exports the device
2564 * attached to the first downstream port or acts as a hardware storage
2565 * controller and emulate a single ATA device (can be RAID 0/1 or some
2566 * other configuration).
2567 *
2568 * When there's no device attached to the first downstream port of the
2569 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2570 * configure the 4726. However, ATA emulation of the device is very
2571 * lame. It doesn't send signature D2H Reg FIS after the initial
2572 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2573 *
2574 * The following function works around the problem by always using
2575 * hardreset on the port and not depending on receiving signature FIS
2576 * afterward. If signature FIS isn't received soon, ATA class is
2577 * assumed without follow-up softreset.
2578 */
2579 static void ahci_p5wdh_workaround(struct ata_host *host)
2580 {
2581 static struct dmi_system_id sysids[] = {
2582 {
2583 .ident = "P5W DH Deluxe",
2584 .matches = {
2585 DMI_MATCH(DMI_SYS_VENDOR,
2586 "ASUSTEK COMPUTER INC"),
2587 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2588 },
2589 },
2590 { }
2591 };
2592 struct pci_dev *pdev = to_pci_dev(host->dev);
2593
2594 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2595 dmi_check_system(sysids)) {
2596 struct ata_port *ap = host->ports[1];
2597
2598 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2599 "Deluxe on-board SIMG4726 workaround\n");
2600
2601 ap->ops = &ahci_p5wdh_ops;
2602 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2603 }
2604 }
2605
2606 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2607 {
2608 static const struct dmi_system_id broken_systems[] = {
2609 {
2610 .ident = "HP Compaq nx6310",
2611 .matches = {
2612 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2613 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2614 },
2615 /* PCI slot number of the controller */
2616 .driver_data = (void *)0x1FUL,
2617 },
2618 {
2619 .ident = "HP Compaq 6720s",
2620 .matches = {
2621 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2622 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2623 },
2624 /* PCI slot number of the controller */
2625 .driver_data = (void *)0x1FUL,
2626 },
2627
2628 { } /* terminate list */
2629 };
2630 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2631
2632 if (dmi) {
2633 unsigned long slot = (unsigned long)dmi->driver_data;
2634 /* apply the quirk only to on-board controllers */
2635 return slot == PCI_SLOT(pdev->devfn);
2636 }
2637
2638 return false;
2639 }
2640
2641 static bool ahci_broken_suspend(struct pci_dev *pdev)
2642 {
2643 static const struct dmi_system_id sysids[] = {
2644 /*
2645 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2646 * to the harddisk doesn't become online after
2647 * resuming from STR. Warn and fail suspend.
2648 */
2649 {
2650 .ident = "dv4",
2651 .matches = {
2652 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2653 DMI_MATCH(DMI_PRODUCT_NAME,
2654 "HP Pavilion dv4 Notebook PC"),
2655 },
2656 .driver_data = "F.30", /* cutoff BIOS version */
2657 },
2658 {
2659 .ident = "dv5",
2660 .matches = {
2661 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2662 DMI_MATCH(DMI_PRODUCT_NAME,
2663 "HP Pavilion dv5 Notebook PC"),
2664 },
2665 .driver_data = "F.16", /* cutoff BIOS version */
2666 },
2667 {
2668 .ident = "dv6",
2669 .matches = {
2670 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2671 DMI_MATCH(DMI_PRODUCT_NAME,
2672 "HP Pavilion dv6 Notebook PC"),
2673 },
2674 .driver_data = "F.21", /* cutoff BIOS version */
2675 },
2676 {
2677 .ident = "HDX18",
2678 .matches = {
2679 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2680 DMI_MATCH(DMI_PRODUCT_NAME,
2681 "HP HDX18 Notebook PC"),
2682 },
2683 .driver_data = "F.23", /* cutoff BIOS version */
2684 },
2685 { } /* terminate list */
2686 };
2687 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2688 const char *ver;
2689
2690 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2691 return false;
2692
2693 ver = dmi_get_system_info(DMI_BIOS_VERSION);
2694
2695 return !ver || strcmp(ver, dmi->driver_data) < 0;
2696 }
2697
2698 static bool ahci_broken_online(struct pci_dev *pdev)
2699 {
2700 #define ENCODE_BUSDEVFN(bus, slot, func) \
2701 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2702 static const struct dmi_system_id sysids[] = {
2703 /*
2704 * There are several gigabyte boards which use
2705 * SIMG5723s configured as hardware RAID. Certain
2706 * 5723 firmware revisions shipped there keep the link
2707 * online but fail to answer properly to SRST or
2708 * IDENTIFY when no device is attached downstream
2709 * causing libata to retry quite a few times leading
2710 * to excessive detection delay.
2711 *
2712 * As these firmwares respond to the second reset try
2713 * with invalid device signature, considering unknown
2714 * sig as offline works around the problem acceptably.
2715 */
2716 {
2717 .ident = "EP45-DQ6",
2718 .matches = {
2719 DMI_MATCH(DMI_BOARD_VENDOR,
2720 "Gigabyte Technology Co., Ltd."),
2721 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2722 },
2723 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2724 },
2725 {
2726 .ident = "EP45-DS5",
2727 .matches = {
2728 DMI_MATCH(DMI_BOARD_VENDOR,
2729 "Gigabyte Technology Co., Ltd."),
2730 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2731 },
2732 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2733 },
2734 { } /* terminate list */
2735 };
2736 #undef ENCODE_BUSDEVFN
2737 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2738 unsigned int val;
2739
2740 if (!dmi)
2741 return false;
2742
2743 val = (unsigned long)dmi->driver_data;
2744
2745 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2746 }
2747
2748 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2749 {
2750 static int printed_version;
2751 unsigned int board_id = ent->driver_data;
2752 struct ata_port_info pi = ahci_port_info[board_id];
2753 const struct ata_port_info *ppi[] = { &pi, NULL };
2754 struct device *dev = &pdev->dev;
2755 struct ahci_host_priv *hpriv;
2756 struct ata_host *host;
2757 int n_ports, i, rc;
2758
2759 VPRINTK("ENTER\n");
2760
2761 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2762
2763 if (!printed_version++)
2764 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
2765
2766 /* The AHCI driver can only drive the SATA ports, the PATA driver
2767 can drive them all so if both drivers are selected make sure
2768 AHCI stays out of the way */
2769 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2770 return -ENODEV;
2771
2772 /* acquire resources */
2773 rc = pcim_enable_device(pdev);
2774 if (rc)
2775 return rc;
2776
2777 /* AHCI controllers often implement SFF compatible interface.
2778 * Grab all PCI BARs just in case.
2779 */
2780 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2781 if (rc == -EBUSY)
2782 pcim_pin_device(pdev);
2783 if (rc)
2784 return rc;
2785
2786 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2787 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2788 u8 map;
2789
2790 /* ICH6s share the same PCI ID for both piix and ahci
2791 * modes. Enabling ahci mode while MAP indicates
2792 * combined mode is a bad idea. Yield to ata_piix.
2793 */
2794 pci_read_config_byte(pdev, ICH_MAP, &map);
2795 if (map & 0x3) {
2796 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2797 "combined mode, can't enable AHCI mode\n");
2798 return -ENODEV;
2799 }
2800 }
2801
2802 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2803 if (!hpriv)
2804 return -ENOMEM;
2805 hpriv->flags |= (unsigned long)pi.private_data;
2806
2807 /* MCP65 revision A1 and A2 can't do MSI */
2808 if (board_id == board_ahci_mcp65 &&
2809 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2810 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2811
2812 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2813 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2814 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2815
2816 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2817 pci_intx(pdev, 1);
2818
2819 /* save initial config */
2820 ahci_save_initial_config(pdev, hpriv);
2821
2822 /* prepare host */
2823 if (hpriv->cap & HOST_CAP_NCQ)
2824 pi.flags |= ATA_FLAG_NCQ;
2825
2826 if (hpriv->cap & HOST_CAP_PMP)
2827 pi.flags |= ATA_FLAG_PMP;
2828
2829 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2830 u8 messages;
2831 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2832 u32 em_loc = readl(mmio + HOST_EM_LOC);
2833 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2834
2835 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2836
2837 /* we only support LED message type right now */
2838 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2839 /* store em_loc */
2840 hpriv->em_loc = ((em_loc >> 16) * 4);
2841 pi.flags |= ATA_FLAG_EM;
2842 if (!(em_ctl & EM_CTL_ALHD))
2843 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2844 }
2845 }
2846
2847 if (ahci_broken_system_poweroff(pdev)) {
2848 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2849 dev_info(&pdev->dev,
2850 "quirky BIOS, skipping spindown on poweroff\n");
2851 }
2852
2853 if (ahci_broken_suspend(pdev)) {
2854 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
2855 dev_printk(KERN_WARNING, &pdev->dev,
2856 "BIOS update required for suspend/resume\n");
2857 }
2858
2859 if (ahci_broken_online(pdev)) {
2860 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
2861 dev_info(&pdev->dev,
2862 "online status unreliable, applying workaround\n");
2863 }
2864
2865 /* CAP.NP sometimes indicate the index of the last enabled
2866 * port, at other times, that of the last possible port, so
2867 * determining the maximum port number requires looking at
2868 * both CAP.NP and port_map.
2869 */
2870 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2871
2872 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
2873 if (!host)
2874 return -ENOMEM;
2875 host->iomap = pcim_iomap_table(pdev);
2876 host->private_data = hpriv;
2877
2878 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
2879 host->flags |= ATA_HOST_PARALLEL_SCAN;
2880 else
2881 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
2882
2883 if (pi.flags & ATA_FLAG_EM)
2884 ahci_reset_em(host);
2885
2886 for (i = 0; i < host->n_ports; i++) {
2887 struct ata_port *ap = host->ports[i];
2888
2889 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2890 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2891 0x100 + ap->port_no * 0x80, "port");
2892
2893 /* set initial link pm policy */
2894 ap->pm_policy = NOT_AVAILABLE;
2895
2896 /* set enclosure management message type */
2897 if (ap->flags & ATA_FLAG_EM)
2898 ap->em_message_type = ahci_em_messages;
2899
2900
2901 /* disabled/not-implemented port */
2902 if (!(hpriv->port_map & (1 << i)))
2903 ap->ops = &ata_dummy_port_ops;
2904 }
2905
2906 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2907 ahci_p5wdh_workaround(host);
2908
2909 /* initialize adapter */
2910 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
2911 if (rc)
2912 return rc;
2913
2914 rc = ahci_reset_controller(host);
2915 if (rc)
2916 return rc;
2917
2918 ahci_init_controller(host);
2919 ahci_print_info(host);
2920
2921 pci_set_master(pdev);
2922 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2923 &ahci_sht);
2924 }
2925
2926 static int __init ahci_init(void)
2927 {
2928 return pci_register_driver(&ahci_pci_driver);
2929 }
2930
2931 static void __exit ahci_exit(void)
2932 {
2933 pci_unregister_driver(&ahci_pci_driver);
2934 }
2935
2936
2937 MODULE_AUTHOR("Jeff Garzik");
2938 MODULE_DESCRIPTION("AHCI SATA low-level driver");
2939 MODULE_LICENSE("GPL");
2940 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
2941 MODULE_VERSION(DRV_VERSION);
2942
2943 module_init(ahci_init);
2944 module_exit(ahci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree