| blob | 5bdcc06d294c846d416c76dbb4eca8e7aa37fecd |
1 /*
2 * Kernel execution entry point code.
3 *
4 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
5 * Initial PowerPC version.
6 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Rewritten for PReP
8 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
9 * Low-level exception handers, MMU support, and rewrite.
10 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
11 * PowerPC 8xx modifications.
12 * Copyright (c) 1998-1999 TiVo, Inc.
13 * PowerPC 403GCX modifications.
14 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
15 * PowerPC 403GCX/405GP modifications.
16 * Copyright 2000 MontaVista Software Inc.
17 * PPC405 modifications
18 * PowerPC 403GCX/405GP modifications.
19 * Author: MontaVista Software, Inc.
20 * frank_rowand@mvista.com or source@mvista.com
21 * debbie_chu@mvista.com
22 * Copyright 2002-2004 MontaVista Software, Inc.
23 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
24 * Copyright 2004 Freescale Semiconductor, Inc
25 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 */
33 #include <linux/init.h>
34 #include <linux/threads.h>
35 #include <asm/processor.h>
36 #include <asm/page.h>
37 #include <asm/mmu.h>
38 #include <asm/pgtable.h>
39 #include <asm/cputable.h>
40 #include <asm/thread_info.h>
41 #include <asm/ppc_asm.h>
42 #include <asm/asm-offsets.h>
43 #include <asm/cache.h>
44 #include "head_booke.h"
46 /* As with the other PowerPC ports, it is expected that when code
47 * execution begins here, the following registers contain valid, yet
48 * optional, information:
49 *
50 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
51 * r4 - Starting address of the init RAM disk
52 * r5 - Ending address of the init RAM disk
53 * r6 - Start of kernel command line string (e.g. "mem=128")
54 * r7 - End of kernel command line string
55 *
56 */
57 __HEAD
58 _ENTRY(_stext);
59 _ENTRY(_start);
60 /*
61 * Reserve a word at a fixed location to store the address
62 * of abatron_pteptrs
63 */
64 nop
65 /*
66 * Save parameters we are passed
67 */
68 mr r31,r3
69 mr r30,r4
70 mr r29,r5
71 mr r28,r6
72 mr r27,r7
73 li r25,0 /* phys kernel start (low) */
74 li r24,0 /* CPU number */
75 li r23,0 /* phys kernel start (high) */
77 /* We try to not make any assumptions about how the boot loader
78 * setup or used the TLBs. We invalidate all mappings from the
79 * boot loader and load a single entry in TLB1[0] to map the
80 * first 64M of kernel memory. Any boot info passed from the
81 * bootloader needs to live in this first 64M.
82 *
83 * Requirement on bootloader:
84 * - The page we're executing in needs to reside in TLB1 and
85 * have IPROT=1. If not an invalidate broadcast could
86 * evict the entry we're currently executing in.
87 *
88 * r3 = Index of TLB1 were executing in
89 * r4 = Current MSR[IS]
90 * r5 = Index of TLB1 temp mapping
91 *
92 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
93 * if needed
94 */
96 _ENTRY(__early_start)
97 /* 1. Find the index of the entry we're executing in */
98 bl invstr /* Find our address */
99 invstr: mflr r6 /* Make it accessible */
100 mfmsr r7
101 rlwinm r4,r7,27,31,31 /* extract MSR[IS] */
102 mfspr r7, SPRN_PID0
103 slwi r7,r7,16
104 or r7,r7,r4
105 mtspr SPRN_MAS6,r7
106 tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */
107 mfspr r7,SPRN_MAS1
108 andis. r7,r7,MAS1_VALID@h
109 bne match_TLB
111 mfspr r7,SPRN_MMUCFG
112 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
113 cmpwi r7,3
114 bne match_TLB /* skip if NPIDS != 3 */
116 mfspr r7,SPRN_PID1
117 slwi r7,r7,16
118 or r7,r7,r4
119 mtspr SPRN_MAS6,r7
120 tlbsx 0,r6 /* search MSR[IS], SPID=PID1 */
121 mfspr r7,SPRN_MAS1
122 andis. r7,r7,MAS1_VALID@h
123 bne match_TLB
124 mfspr r7, SPRN_PID2
125 slwi r7,r7,16
126 or r7,r7,r4
127 mtspr SPRN_MAS6,r7
128 tlbsx 0,r6 /* Fall through, we had to match */
130 match_TLB:
131 mfspr r7,SPRN_MAS0
132 rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */
134 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
135 oris r7,r7,MAS1_IPROT@h
136 mtspr SPRN_MAS1,r7
137 tlbwe
139 /* 2. Invalidate all entries except the entry we're executing in */
140 mfspr r9,SPRN_TLB1CFG
141 andi. r9,r9,0xfff
142 li r6,0 /* Set Entry counter to 0 */
143 1: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
144 rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */
145 mtspr SPRN_MAS0,r7
146 tlbre
147 mfspr r7,SPRN_MAS1
148 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */
149 cmpw r3,r6
150 beq skpinv /* Dont update the current execution TLB */
151 mtspr SPRN_MAS1,r7
152 tlbwe
153 isync
154 skpinv: addi r6,r6,1 /* Increment */
155 cmpw r6,r9 /* Are we done? */
156 bne 1b /* If not, repeat */
158 /* Invalidate TLB0 */
159 li r6,0x04
160 tlbivax 0,r6
161 TLBSYNC
162 /* Invalidate TLB1 */
163 li r6,0x0c
164 tlbivax 0,r6
165 TLBSYNC
167 /* 3. Setup a temp mapping and jump to it */
168 andi. r5, r3, 0x1 /* Find an entry not used and is non-zero */
169 addi r5, r5, 0x1
170 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
171 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
172 mtspr SPRN_MAS0,r7
173 tlbre
175 /* grab and fixup the RPN */
176 mfspr r6,SPRN_MAS1 /* extract MAS1[SIZE] */
177 rlwinm r6,r6,25,27,31
178 li r8,-1
179 addi r6,r6,10
180 slw r6,r8,r6 /* convert to mask */
182 bl 1f /* Find our address */
183 1: mflr r7
185 mfspr r8,SPRN_MAS3
186 #ifdef CONFIG_PHYS_64BIT
187 mfspr r23,SPRN_MAS7
188 #endif
189 and r8,r6,r8
190 subfic r9,r6,-4096
191 and r9,r9,r7
193 or r25,r8,r9
194 ori r8,r25,(MAS3_SX|MAS3_SW|MAS3_SR)
196 /* Just modify the entry ID and EPN for the temp mapping */
197 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
198 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
199 mtspr SPRN_MAS0,r7
200 xori r6,r4,1 /* Setup TMP mapping in the other Address space */
201 slwi r6,r6,12
202 oris r6,r6,(MAS1_VALID|MAS1_IPROT)@h
203 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_4K))@l
204 mtspr SPRN_MAS1,r6
205 mfspr r6,SPRN_MAS2
206 li r7,0 /* temp EPN = 0 */
207 rlwimi r7,r6,0,20,31
208 mtspr SPRN_MAS2,r7
209 mtspr SPRN_MAS3,r8
210 tlbwe
212 xori r6,r4,1
213 slwi r6,r6,5 /* setup new context with other address space */
214 bl 1f /* Find our address */
215 1: mflr r9
216 rlwimi r7,r9,0,20,31
217 addi r7,r7,24
218 mtspr SPRN_SRR0,r7
219 mtspr SPRN_SRR1,r6
220 rfi
222 /* 4. Clear out PIDs & Search info */
223 li r6,0
224 mtspr SPRN_MAS6,r6
225 mtspr SPRN_PID0,r6
227 mfspr r7,SPRN_MMUCFG
228 rlwinm r7,r7,21,28,31 /* extract MMUCFG[NPIDS] */
229 cmpwi r7,3
230 bne 2f /* skip if NPIDS != 3 */
232 mtspr SPRN_PID1,r6
233 mtspr SPRN_PID2,r6
235 /* 5. Invalidate mapping we started in */
236 2:
237 lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
238 rlwimi r7,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
239 mtspr SPRN_MAS0,r7
240 tlbre
241 mfspr r6,SPRN_MAS1
242 rlwinm r6,r6,0,2,0 /* clear IPROT */
243 mtspr SPRN_MAS1,r6
244 tlbwe
245 /* Invalidate TLB1 */
246 li r9,0x0c
247 tlbivax 0,r9
248 TLBSYNC
250 /* The mapping only needs to be cache-coherent on SMP */
251 #ifdef CONFIG_SMP
252 #define M_IF_SMP MAS2_M
253 #else
254 #define M_IF_SMP 0
255 #endif
257 /* 6. Setup KERNELBASE mapping in TLB1[0] */
258 lis r6,0x1000 /* Set MAS0(TLBSEL) = TLB1(1), ESEL = 0 */
259 mtspr SPRN_MAS0,r6
260 lis r6,(MAS1_VALID|MAS1_IPROT)@h
261 ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_64M))@l
262 mtspr SPRN_MAS1,r6
263 lis r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@h
264 ori r6,r6,MAS2_VAL(PAGE_OFFSET, BOOK3E_PAGESZ_64M, M_IF_SMP)@l
265 mtspr SPRN_MAS2,r6
266 mtspr SPRN_MAS3,r8
267 tlbwe
269 /* 7. Jump to KERNELBASE mapping */
270 lis r6,(KERNELBASE & ~0xfff)@h
271 ori r6,r6,(KERNELBASE & ~0xfff)@l
272 lis r7,MSR_KERNEL@h
273 ori r7,r7,MSR_KERNEL@l
274 bl 1f /* Find our address */
275 1: mflr r9
276 rlwimi r6,r9,0,20,31
277 addi r6,r6,(2f - 1b)
278 mtspr SPRN_SRR0,r6
279 mtspr SPRN_SRR1,r7
280 rfi /* start execution out of TLB1[0] entry */
282 /* 8. Clear out the temp mapping */
283 2: lis r7,0x1000 /* Set MAS0(TLBSEL) = 1 */
284 rlwimi r7,r5,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r5) */
285 mtspr SPRN_MAS0,r7
286 tlbre
287 mfspr r8,SPRN_MAS1
288 rlwinm r8,r8,0,2,0 /* clear IPROT */
289 mtspr SPRN_MAS1,r8
290 tlbwe
291 /* Invalidate TLB1 */
292 li r9,0x0c
293 tlbivax 0,r9
294 TLBSYNC
296 /* Establish the interrupt vector offsets */
297 SET_IVOR(0, CriticalInput);
298 SET_IVOR(1, MachineCheck);
299 SET_IVOR(2, DataStorage);
300 SET_IVOR(3, InstructionStorage);
301 SET_IVOR(4, ExternalInput);
302 SET_IVOR(5, Alignment);
303 SET_IVOR(6, Program);
304 SET_IVOR(7, FloatingPointUnavailable);
305 SET_IVOR(8, SystemCall);
306 SET_IVOR(9, AuxillaryProcessorUnavailable);
307 SET_IVOR(10, Decrementer);
308 SET_IVOR(11, FixedIntervalTimer);
309 SET_IVOR(12, WatchdogTimer);
310 SET_IVOR(13, DataTLBError);
311 SET_IVOR(14, InstructionTLBError);
312 SET_IVOR(15, DebugCrit);
314 /* Establish the interrupt vector base */
315 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
316 mtspr SPRN_IVPR,r4
318 /* Setup the defaults for TLB entries */
319 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
320 #ifdef CONFIG_E200
321 oris r2,r2,MAS4_TLBSELD(1)@h
322 #endif
323 mtspr SPRN_MAS4, r2
325 #if 0
326 /* Enable DOZE */
327 mfspr r2,SPRN_HID0
328 oris r2,r2,HID0_DOZE@h
329 mtspr SPRN_HID0, r2
330 #endif
332 #if !defined(CONFIG_BDI_SWITCH)
333 /*
334 * The Abatron BDI JTAG debugger does not tolerate others
335 * mucking with the debug registers.
336 */
337 lis r2,DBCR0_IDM@h
338 mtspr SPRN_DBCR0,r2
339 isync
340 /* clear any residual debug events */
341 li r2,-1
342 mtspr SPRN_DBSR,r2
343 #endif
345 #ifdef CONFIG_SMP
346 /* Check to see if we're the second processor, and jump
347 * to the secondary_start code if so
348 */
349 mfspr r24,SPRN_PIR
350 cmpwi r24,0
351 bne __secondary_start
352 #endif
354 /*
355 * This is where the main kernel code starts.
356 */
358 /* ptr to current */
359 lis r2,init_task@h
360 ori r2,r2,init_task@l
362 /* ptr to current thread */
363 addi r4,r2,THREAD /* init task's THREAD */
364 mtspr SPRN_SPRG3,r4
366 /* stack */
367 lis r1,init_thread_union@h
368 ori r1,r1,init_thread_union@l
369 li r0,0
370 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
372 bl early_init
374 #ifdef CONFIG_RELOCATABLE
375 lis r3,kernstart_addr@ha
376 la r3,kernstart_addr@l(r3)
377 #ifdef CONFIG_PHYS_64BIT
378 stw r23,0(r3)
379 stw r25,4(r3)
380 #else
381 stw r25,0(r3)
382 #endif
383 #endif
385 /*
386 * Decide what sort of machine this is and initialize the MMU.
387 */
388 mr r3,r31
389 mr r4,r30
390 mr r5,r29
391 mr r6,r28
392 mr r7,r27
393 bl machine_init
394 bl MMU_init
396 /* Setup PTE pointers for the Abatron bdiGDB */
397 lis r6, swapper_pg_dir@h
398 ori r6, r6, swapper_pg_dir@l
399 lis r5, abatron_pteptrs@h
400 ori r5, r5, abatron_pteptrs@l
401 lis r4, KERNELBASE@h
402 ori r4, r4, KERNELBASE@l
403 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
404 stw r6, 0(r5)
406 /* Let's move on */
407 lis r4,start_kernel@h
408 ori r4,r4,start_kernel@l
409 lis r3,MSR_KERNEL@h
410 ori r3,r3,MSR_KERNEL@l
411 mtspr SPRN_SRR0,r4
412 mtspr SPRN_SRR1,r3
413 rfi /* change context and jump to start_kernel */
415 /* Macros to hide the PTE size differences
416 *
417 * FIND_PTE -- walks the page tables given EA & pgdir pointer
418 * r10 -- EA of fault
419 * r11 -- PGDIR pointer
420 * r12 -- free
421 * label 2: is the bailout case
422 *
423 * if we find the pte (fall through):
424 * r11 is low pte word
425 * r12 is pointer to the pte
426 */
427 #ifdef CONFIG_PTE_64BIT
428 #define FIND_PTE \
429 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
430 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
431 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
432 beq 2f; /* Bail if no table */ \
433 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
434 lwz r11, 4(r12); /* Get pte entry */
435 #else
436 #define FIND_PTE \
437 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
438 lwz r11, 0(r11); /* Get L1 entry */ \
439 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
440 beq 2f; /* Bail if no table */ \
441 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
442 lwz r11, 0(r12); /* Get Linux PTE */
443 #endif
445 /*
446 * Interrupt vector entry code
447 *
448 * The Book E MMUs are always on so we don't need to handle
449 * interrupts in real mode as with previous PPC processors. In
450 * this case we handle interrupts in the kernel virtual address
451 * space.
452 *
453 * Interrupt vectors are dynamically placed relative to the
454 * interrupt prefix as determined by the address of interrupt_base.
455 * The interrupt vectors offsets are programmed using the labels
456 * for each interrupt vector entry.
457 *
458 * Interrupt vectors must be aligned on a 16 byte boundary.
459 * We align on a 32 byte cache line boundary for good measure.
460 */
462 interrupt_base:
463 /* Critical Input Interrupt */
464 CRITICAL_EXCEPTION(0x0100, CriticalInput, unknown_exception)
466 /* Machine Check Interrupt */
467 #ifdef CONFIG_E200
468 /* no RFMCI, MCSRRs on E200 */
469 CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
470 #else
471 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
472 #endif
474 /* Data Storage Interrupt */
475 START_EXCEPTION(DataStorage)
476 NORMAL_EXCEPTION_PROLOG
477 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
478 stw r5,_ESR(r11)
479 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
480 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
481 bne 1f
482 EXC_XFER_EE_LITE(0x0300, handle_page_fault)
483 1:
484 addi r3,r1,STACK_FRAME_OVERHEAD
485 EXC_XFER_EE_LITE(0x0300, CacheLockingException)
487 /* Instruction Storage Interrupt */
488 INSTRUCTION_STORAGE_EXCEPTION
490 /* External Input Interrupt */
491 EXCEPTION(0x0500, ExternalInput, do_IRQ, EXC_XFER_LITE)
493 /* Alignment Interrupt */
494 ALIGNMENT_EXCEPTION
496 /* Program Interrupt */
497 PROGRAM_EXCEPTION
499 /* Floating Point Unavailable Interrupt */
500 #ifdef CONFIG_PPC_FPU
501 FP_UNAVAILABLE_EXCEPTION
502 #else
503 #ifdef CONFIG_E200
504 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
505 EXCEPTION(0x0800, FloatingPointUnavailable, program_check_exception, EXC_XFER_EE)
506 #else
507 EXCEPTION(0x0800, FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
508 #endif
509 #endif
511 /* System Call Interrupt */
512 START_EXCEPTION(SystemCall)
513 NORMAL_EXCEPTION_PROLOG
514 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
516 /* Auxillary Processor Unavailable Interrupt */
517 EXCEPTION(0x2900, AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
519 /* Decrementer Interrupt */
520 DECREMENTER_EXCEPTION
522 /* Fixed Internal Timer Interrupt */
523 /* TODO: Add FIT support */
524 EXCEPTION(0x3100, FixedIntervalTimer, unknown_exception, EXC_XFER_EE)
526 /* Watchdog Timer Interrupt */
527 #ifdef CONFIG_BOOKE_WDT
528 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, WatchdogException)
529 #else
530 CRITICAL_EXCEPTION(0x3200, WatchdogTimer, unknown_exception)
531 #endif
533 /* Data TLB Error Interrupt */
534 START_EXCEPTION(DataTLBError)
535 mtspr SPRN_SPRG0, r10 /* Save some working registers */
536 mtspr SPRN_SPRG1, r11
537 mtspr SPRN_SPRG4W, r12
538 mtspr SPRN_SPRG5W, r13
539 mfcr r11
540 mtspr SPRN_SPRG7W, r11
541 mfspr r10, SPRN_DEAR /* Get faulting address */
543 /* If we are faulting a kernel address, we have to use the
544 * kernel page tables.
545 */
546 lis r11, PAGE_OFFSET@h
547 cmplw 5, r10, r11
548 blt 5, 3f
549 lis r11, swapper_pg_dir@h
550 ori r11, r11, swapper_pg_dir@l
552 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
553 rlwinm r12,r12,0,16,1
554 mtspr SPRN_MAS1,r12
556 b 4f
558 /* Get the PGD for the current thread */
559 3:
560 mfspr r11,SPRN_SPRG3
561 lwz r11,PGDIR(r11)
563 4:
564 /* Mask of required permission bits. Note that while we
565 * do copy ESR:ST to _PAGE_RW position as trying to write
566 * to an RO page is pretty common, we don't do it with
567 * _PAGE_DIRTY. We could do it, but it's a fairly rare
568 * event so I'd rather take the overhead when it happens
569 * rather than adding an instruction here. We should measure
570 * whether the whole thing is worth it in the first place
571 * as we could avoid loading SPRN_ESR completely in the first
572 * place...
573 *
574 * TODO: Is it worth doing that mfspr & rlwimi in the first
575 * place or can we save a couple of instructions here ?
576 */
577 mfspr r12,SPRN_ESR
578 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
579 rlwimi r13,r12,11,29,29
581 FIND_PTE
582 andc. r13,r13,r11 /* Check permission */
584 #ifdef CONFIG_PTE_64BIT
585 #ifdef CONFIG_SMP
586 subf r10,r11,r12 /* create false data dep */
587 lwzx r13,r11,r10 /* Get upper pte bits */
588 #else
589 lwz r13,0(r12) /* Get upper pte bits */
590 #endif
591 #endif
593 bne 2f /* Bail if permission/valid mismach */
595 /* Jump to common tlb load */
596 b finish_tlb_load
597 2:
598 /* The bailout. Restore registers to pre-exception conditions
599 * and call the heavyweights to help us out.
600 */
601 mfspr r11, SPRN_SPRG7R
602 mtcr r11
603 mfspr r13, SPRN_SPRG5R
604 mfspr r12, SPRN_SPRG4R
605 mfspr r11, SPRN_SPRG1
606 mfspr r10, SPRN_SPRG0
607 b DataStorage
609 /* Instruction TLB Error Interrupt */
610 /*
611 * Nearly the same as above, except we get our
612 * information from different registers and bailout
613 * to a different point.
614 */
615 START_EXCEPTION(InstructionTLBError)
616 mtspr SPRN_SPRG0, r10 /* Save some working registers */
617 mtspr SPRN_SPRG1, r11
618 mtspr SPRN_SPRG4W, r12
619 mtspr SPRN_SPRG5W, r13
620 mfcr r11
621 mtspr SPRN_SPRG7W, r11
622 mfspr r10, SPRN_SRR0 /* Get faulting address */
624 /* If we are faulting a kernel address, we have to use the
625 * kernel page tables.
626 */
627 lis r11, PAGE_OFFSET@h
628 cmplw 5, r10, r11
629 blt 5, 3f
630 lis r11, swapper_pg_dir@h
631 ori r11, r11, swapper_pg_dir@l
633 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
634 rlwinm r12,r12,0,16,1
635 mtspr SPRN_MAS1,r12
637 b 4f
639 /* Get the PGD for the current thread */
640 3:
641 mfspr r11,SPRN_SPRG3
642 lwz r11,PGDIR(r11)
644 4:
645 /* Make up the required permissions */
646 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
648 FIND_PTE
649 andc. r13,r13,r11 /* Check permission */
651 #ifdef CONFIG_PTE_64BIT
652 #ifdef CONFIG_SMP
653 subf r10,r11,r12 /* create false data dep */
654 lwzx r13,r11,r10 /* Get upper pte bits */
655 #else
656 lwz r13,0(r12) /* Get upper pte bits */
657 #endif
658 #endif
660 bne 2f /* Bail if permission mismach */
662 /* Jump to common TLB load point */
663 b finish_tlb_load
665 2:
666 /* The bailout. Restore registers to pre-exception conditions
667 * and call the heavyweights to help us out.
668 */
669 mfspr r11, SPRN_SPRG7R
670 mtcr r11
671 mfspr r13, SPRN_SPRG5R
672 mfspr r12, SPRN_SPRG4R
673 mfspr r11, SPRN_SPRG1
674 mfspr r10, SPRN_SPRG0
675 b InstructionStorage
677 #ifdef CONFIG_SPE
678 /* SPE Unavailable */
679 START_EXCEPTION(SPEUnavailable)
680 NORMAL_EXCEPTION_PROLOG
681 bne load_up_spe
682 addi r3,r1,STACK_FRAME_OVERHEAD
683 EXC_XFER_EE_LITE(0x2010, KernelSPE)
684 #else
685 EXCEPTION(0x2020, SPEUnavailable, unknown_exception, EXC_XFER_EE)
686 #endif /* CONFIG_SPE */
688 /* SPE Floating Point Data */
689 #ifdef CONFIG_SPE
690 EXCEPTION(0x2030, SPEFloatingPointData, SPEFloatingPointException, EXC_XFER_EE);
692 /* SPE Floating Point Round */
693 EXCEPTION(0x2050, SPEFloatingPointRound, SPEFloatingPointRoundException, EXC_XFER_EE)
694 #else
695 EXCEPTION(0x2040, SPEFloatingPointData, unknown_exception, EXC_XFER_EE)
696 EXCEPTION(0x2050, SPEFloatingPointRound, unknown_exception, EXC_XFER_EE)
697 #endif /* CONFIG_SPE */
699 /* Performance Monitor */
700 EXCEPTION(0x2060, PerformanceMonitor, performance_monitor_exception, EXC_XFER_STD)
702 EXCEPTION(0x2070, Doorbell, doorbell_exception, EXC_XFER_STD)
704 CRITICAL_EXCEPTION(0x2080, CriticalDoorbell, unknown_exception)
706 /* Debug Interrupt */
707 DEBUG_DEBUG_EXCEPTION
708 DEBUG_CRIT_EXCEPTION
710 /*
711 * Local functions
712 */
714 /*
715 * Both the instruction and data TLB miss get to this
716 * point to load the TLB.
717 * r10 - available to use
718 * r11 - TLB (info from Linux PTE)
719 * r12 - available to use
720 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
721 * CR5 - results of addr >= PAGE_OFFSET
722 * MAS0, MAS1 - loaded with proper value when we get here
723 * MAS2, MAS3 - will need additional info from Linux PTE
724 * Upon exit, we reload everything and RFI.
725 */
726 finish_tlb_load:
727 /*
728 * We set execute, because we don't have the granularity to
729 * properly set this at the page level (Linux problem).
730 * Many of these bits are software only. Bits we don't set
731 * here we (properly should) assume have the appropriate value.
732 */
734 mfspr r12, SPRN_MAS2
735 #ifdef CONFIG_PTE_64BIT
736 rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
737 #else
738 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
739 #endif
740 #ifdef CONFIG_SMP
741 ori r12, r12, MAS2_M
742 #endif
743 mtspr SPRN_MAS2, r12
745 li r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
746 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
747 and r12, r11, r10
748 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
749 slwi r10, r12, 1
750 or r10, r10, r12
751 iseleq r12, r12, r10
753 #ifdef CONFIG_PTE_64BIT
754 rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
755 rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
756 mtspr SPRN_MAS3, r12
757 BEGIN_MMU_FTR_SECTION
758 srwi r10, r13, 8 /* grab RPN[8:31] */
759 mtspr SPRN_MAS7, r10
760 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
761 #else
762 rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
763 mtspr SPRN_MAS3, r11
764 #endif
765 #ifdef CONFIG_E200
766 /* Round robin TLB1 entries assignment */
767 mfspr r12, SPRN_MAS0
769 /* Extract TLB1CFG(NENTRY) */
770 mfspr r11, SPRN_TLB1CFG
771 andi. r11, r11, 0xfff
773 /* Extract MAS0(NV) */
774 andi. r13, r12, 0xfff
775 addi r13, r13, 1
776 cmpw 0, r13, r11
777 addi r12, r12, 1
779 /* check if we need to wrap */
780 blt 7f
782 /* wrap back to first free tlbcam entry */
783 lis r13, tlbcam_index@ha
784 lwz r13, tlbcam_index@l(r13)
785 rlwimi r12, r13, 0, 20, 31
786 7:
787 mtspr SPRN_MAS0,r12
788 #endif /* CONFIG_E200 */
790 tlbwe
792 /* Done...restore registers and get out of here. */
793 mfspr r11, SPRN_SPRG7R
794 mtcr r11
795 mfspr r13, SPRN_SPRG5R
796 mfspr r12, SPRN_SPRG4R
797 mfspr r11, SPRN_SPRG1
798 mfspr r10, SPRN_SPRG0
799 rfi /* Force context change */
801 #ifdef CONFIG_SPE
802 /* Note that the SPE support is closely modeled after the AltiVec
803 * support. Changes to one are likely to be applicable to the
804 * other! */
805 load_up_spe:
806 /*
807 * Disable SPE for the task which had SPE previously,
808 * and save its SPE registers in its thread_struct.
809 * Enables SPE for use in the kernel on return.
810 * On SMP we know the SPE units are free, since we give it up every
811 * switch. -- Kumar
812 */
813 mfmsr r5
814 oris r5,r5,MSR_SPE@h
815 mtmsr r5 /* enable use of SPE now */
816 isync
817 /*
818 * For SMP, we don't do lazy SPE switching because it just gets too
819 * horrendously complex, especially when a task switches from one CPU
820 * to another. Instead we call giveup_spe in switch_to.
821 */
822 #ifndef CONFIG_SMP
823 lis r3,last_task_used_spe@ha
824 lwz r4,last_task_used_spe@l(r3)
825 cmpi 0,r4,0
826 beq 1f
827 addi r4,r4,THREAD /* want THREAD of last_task_used_spe */
828 SAVE_32EVRS(0,r10,r4)
829 evxor evr10, evr10, evr10 /* clear out evr10 */
830 evmwumiaa evr10, evr10, evr10 /* evr10 <- ACC = 0 * 0 + ACC */
831 li r5,THREAD_ACC
832 evstddx evr10, r4, r5 /* save off accumulator */
833 lwz r5,PT_REGS(r4)
834 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
835 lis r10,MSR_SPE@h
836 andc r4,r4,r10 /* disable SPE for previous task */
837 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
838 1:
839 #endif /* !CONFIG_SMP */
840 /* enable use of SPE after return */
841 oris r9,r9,MSR_SPE@h
842 mfspr r5,SPRN_SPRG3 /* current task's THREAD (phys) */
843 li r4,1
844 li r10,THREAD_ACC
845 stw r4,THREAD_USED_SPE(r5)
846 evlddx evr4,r10,r5
847 evmra evr4,evr4
848 REST_32EVRS(0,r10,r5)
849 #ifndef CONFIG_SMP
850 subi r4,r5,THREAD
851 stw r4,last_task_used_spe@l(r3)
852 #endif /* !CONFIG_SMP */
853 /* restore registers and return */
854 2: REST_4GPRS(3, r11)
855 lwz r10,_CCR(r11)
856 REST_GPR(1, r11)
857 mtcr r10
858 lwz r10,_LINK(r11)
859 mtlr r10
860 REST_GPR(10, r11)
861 mtspr SPRN_SRR1,r9
862 mtspr SPRN_SRR0,r12
863 REST_GPR(9, r11)
864 REST_GPR(12, r11)
865 lwz r11,GPR11(r11)
866 rfi
868 /*
869 * SPE unavailable trap from kernel - print a message, but let
870 * the task use SPE in the kernel until it returns to user mode.
871 */
872 KernelSPE:
873 lwz r3,_MSR(r1)
874 oris r3,r3,MSR_SPE@h
875 stw r3,_MSR(r1) /* enable use of SPE after return */
876 lis r3,87f@h
877 ori r3,r3,87f@l
878 mr r4,r2 /* current */
879 lwz r5,_NIP(r1)
880 bl printk
881 b ret_from_except
882 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
883 .align 4,0
885 #endif /* CONFIG_SPE */
887 /*
888 * Global functions
889 */
891 /* Adjust or setup IVORs for e200 */
892 _GLOBAL(__setup_e200_ivors)
893 li r3,DebugDebug@l
894 mtspr SPRN_IVOR15,r3
895 li r3,SPEUnavailable@l
896 mtspr SPRN_IVOR32,r3
897 li r3,SPEFloatingPointData@l
898 mtspr SPRN_IVOR33,r3
899 li r3,SPEFloatingPointRound@l
900 mtspr SPRN_IVOR34,r3
901 sync
902 blr
904 /* Adjust or setup IVORs for e500v1/v2 */
905 _GLOBAL(__setup_e500_ivors)
906 li r3,DebugCrit@l
907 mtspr SPRN_IVOR15,r3
908 li r3,SPEUnavailable@l
909 mtspr SPRN_IVOR32,r3
910 li r3,SPEFloatingPointData@l
911 mtspr SPRN_IVOR33,r3
912 li r3,SPEFloatingPointRound@l
913 mtspr SPRN_IVOR34,r3
914 li r3,PerformanceMonitor@l
915 mtspr SPRN_IVOR35,r3
916 sync
917 blr
919 /* Adjust or setup IVORs for e500mc */
920 _GLOBAL(__setup_e500mc_ivors)
921 li r3,DebugDebug@l
922 mtspr SPRN_IVOR15,r3
923 li r3,PerformanceMonitor@l
924 mtspr SPRN_IVOR35,r3
925 li r3,Doorbell@l
926 mtspr SPRN_IVOR36,r3
927 li r3,CriticalDoorbell@l
928 mtspr SPRN_IVOR37,r3
929 sync
930 blr
932 /*
933 * extern void loadcam_entry(unsigned int index)
934 *
935 * Load TLBCAM[index] entry in to the L2 CAM MMU
936 */
937 _GLOBAL(loadcam_entry)
938 lis r4,TLBCAM@ha
939 addi r4,r4,TLBCAM@l
940 mulli r5,r3,TLBCAM_SIZE
941 add r3,r5,r4
942 lwz r4,0(r3)
943 mtspr SPRN_MAS0,r4
944 lwz r4,4(r3)
945 mtspr SPRN_MAS1,r4
946 lwz r4,8(r3)
947 mtspr SPRN_MAS2,r4
948 lwz r4,12(r3)
949 mtspr SPRN_MAS3,r4
950 tlbwe
951 isync
952 blr
954 /*
955 * extern void giveup_altivec(struct task_struct *prev)
956 *
957 * The e500 core does not have an AltiVec unit.
958 */
959 _GLOBAL(giveup_altivec)
960 blr
962 #ifdef CONFIG_SPE
963 /*
964 * extern void giveup_spe(struct task_struct *prev)
965 *
966 */
967 _GLOBAL(giveup_spe)
968 mfmsr r5
969 oris r5,r5,MSR_SPE@h
970 mtmsr r5 /* enable use of SPE now */
971 isync
972 cmpi 0,r3,0
973 beqlr- /* if no previous owner, done */
974 addi r3,r3,THREAD /* want THREAD of task */
975 lwz r5,PT_REGS(r3)
976 cmpi 0,r5,0
977 SAVE_32EVRS(0, r4, r3)
978 evxor evr6, evr6, evr6 /* clear out evr6 */
979 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
980 li r4,THREAD_ACC
981 evstddx evr6, r4, r3 /* save off accumulator */
982 mfspr r6,SPRN_SPEFSCR
983 stw r6,THREAD_SPEFSCR(r3) /* save spefscr register value */
984 beq 1f
985 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
986 lis r3,MSR_SPE@h
987 andc r4,r4,r3 /* disable SPE for previous task */
988 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
989 1:
990 #ifndef CONFIG_SMP
991 li r5,0
992 lis r4,last_task_used_spe@ha
993 stw r5,last_task_used_spe@l(r4)
994 #endif /* !CONFIG_SMP */
995 blr
996 #endif /* CONFIG_SPE */
998 /*
999 * extern void giveup_fpu(struct task_struct *prev)
1000 *
1001 * Not all FSL Book-E cores have an FPU
1002 */
1003 #ifndef CONFIG_PPC_FPU
1004 _GLOBAL(giveup_fpu)
1005 blr
1006 #endif
1008 /*
1009 * extern void abort(void)
1010 *
1011 * At present, this routine just applies a system reset.
1012 */
1013 _GLOBAL(abort)
1014 li r13,0
1015 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1016 isync
1017 mfmsr r13
1018 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1019 mtmsr r13
1020 isync
1021 mfspr r13,SPRN_DBCR0
1022 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1023 mtspr SPRN_DBCR0,r13
1024 isync
1026 _GLOBAL(set_context)
1028 #ifdef CONFIG_BDI_SWITCH
1029 /* Context switch the PTE pointer for the Abatron BDI2000.
1030 * The PGDIR is the second parameter.
1031 */
1032 lis r5, abatron_pteptrs@h
1033 ori r5, r5, abatron_pteptrs@l
1034 stw r4, 0x4(r5)
1035 #endif
1036 mtspr SPRN_PID,r3
1037 isync /* Force context change */
1038 blr
1040 _GLOBAL(flush_dcache_L1)
1041 mfspr r3,SPRN_L1CFG0
1043 rlwinm r5,r3,9,3 /* Extract cache block size */
1044 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1045 * are currently defined.
1046 */
1047 li r4,32
1048 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1049 * log2(number of ways)
1050 */
1051 slw r5,r4,r5 /* r5 = cache block size */
1053 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1054 mulli r7,r7,13 /* An 8-way cache will require 13
1055 * loads per set.
1056 */
1057 slw r7,r7,r6
1059 /* save off HID0 and set DCFA */
1060 mfspr r8,SPRN_HID0
1061 ori r9,r8,HID0_DCFA@l
1062 mtspr SPRN_HID0,r9
1063 isync
1065 lis r4,KERNELBASE@h
1066 mtctr r7
1068 1: lwz r3,0(r4) /* Load... */
1069 add r4,r4,r5
1070 bdnz 1b
1072 msync
1073 lis r4,KERNELBASE@h
1074 mtctr r7
1076 1: dcbf 0,r4 /* ...and flush. */
1077 add r4,r4,r5
1078 bdnz 1b
1080 /* restore HID0 */
1081 mtspr SPRN_HID0,r8
1082 isync
1084 blr
1086 #ifdef CONFIG_SMP
1087 /* When we get here, r24 needs to hold the CPU # */
1088 .globl __secondary_start
1089 __secondary_start:
1090 lis r3,__secondary_hold_acknowledge@h
1091 ori r3,r3,__secondary_hold_acknowledge@l
1092 stw r24,0(r3)
1094 li r3,0
1095 mr r4,r24 /* Why? */
1096 bl call_setup_cpu
1098 lis r3,tlbcam_index@ha
1099 lwz r3,tlbcam_index@l(r3)
1100 mtctr r3
1101 li r26,0 /* r26 safe? */
1103 /* Load each CAM entry */
1104 1: mr r3,r26
1105 bl loadcam_entry
1106 addi r26,r26,1
1107 bdnz 1b
1109 /* get current_thread_info and current */
1110 lis r1,secondary_ti@ha
1111 lwz r1,secondary_ti@l(r1)
1112 lwz r2,TI_TASK(r1)
1114 /* stack */
1115 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1116 li r0,0
1117 stw r0,0(r1)
1119 /* ptr to current thread */
1120 addi r4,r2,THREAD /* address of our thread_struct */
1121 mtspr SPRN_SPRG3,r4
1123 /* Setup the defaults for TLB entries */
1124 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1125 mtspr SPRN_MAS4,r4
1127 /* Jump to start_secondary */
1128 lis r4,MSR_KERNEL@h
1129 ori r4,r4,MSR_KERNEL@l
1130 lis r3,start_secondary@h
1131 ori r3,r3,start_secondary@l
1132 mtspr SPRN_SRR0,r3
1133 mtspr SPRN_SRR1,r4
1134 sync
1135 rfi
1136 sync
1138 .globl __secondary_hold_acknowledge
1139 __secondary_hold_acknowledge:
1140 .long -1
1141 #endif
1143 /*
1144 * We put a few things here that have to be page-aligned. This stuff
1145 * goes at the beginning of the data segment, which is page-aligned.
1146 */
1147 .data
1148 .align 12
1149 .globl sdata
1150 sdata:
1151 .globl empty_zero_page
1152 empty_zero_page:
1153 .space 4096
1154 .globl swapper_pg_dir
1155 swapper_pg_dir:
1156 .space PGD_TABLE_SIZE
1158 /*
1159 * Room for two PTE pointers, usually the kernel and current user pointers
1160 * to their respective root page table.
1161 */
1162 abatron_pteptrs:
1163 .space 8