2 * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
5 * Author: Nicolas Pitre
6 * Created: Dec 02, 2004
7 * Copyright: MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
20 #include <sound/ac97_codec.h>
21 #include <sound/pxa2xx-lib.h>
24 #include <mach/regs-ac97.h>
25 #include <mach/audio.h>
27 static DEFINE_MUTEX(car_mutex
);
28 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq
);
29 static volatile long gsr_bits
;
30 static struct clk
*ac97_clk
;
31 static struct clk
*ac97conf_clk
;
32 static int reset_gpio
;
34 extern void pxa27x_assert_ac97reset(int reset_gpio
, int on
);
39 * o Slot 12 read from modem space will hang controller.
40 * o CDONE, SDONE interrupt fails after any slot 12 IO.
42 * We therefore have an hybrid approach for waiting on SDONE (interrupt or
43 * 1 jiffy timeout if interrupt never comes).
46 unsigned short pxa2xx_ac97_read(struct snd_ac97
*ac97
, unsigned short reg
)
48 unsigned short val
= -1;
49 volatile u32
*reg_addr
;
51 mutex_lock(&car_mutex
);
53 /* set up primary or secondary codec space */
54 if (cpu_is_pxa25x() && reg
== AC97_GPIO_STATUS
)
55 reg_addr
= ac97
->num
? &SMC_REG_BASE
: &PMC_REG_BASE
;
57 reg_addr
= ac97
->num
? &SAC_REG_BASE
: &PAC_REG_BASE
;
58 reg_addr
+= (reg
>> 1);
60 /* start read access across the ac97 link */
61 GSR
= GSR_CDONE
| GSR_SDONE
;
64 if (reg
== AC97_GPIO_STATUS
)
66 if (wait_event_timeout(gsr_wq
, (GSR
| gsr_bits
) & GSR_SDONE
, 1) <= 0 &&
67 !((GSR
| gsr_bits
) & GSR_SDONE
)) {
68 printk(KERN_ERR
"%s: read error (ac97_reg=%d GSR=%#lx)\n",
69 __func__
, reg
, GSR
| gsr_bits
);
75 GSR
= GSR_CDONE
| GSR_SDONE
;
78 /* but we've just started another cycle... */
79 wait_event_timeout(gsr_wq
, (GSR
| gsr_bits
) & GSR_SDONE
, 1);
81 out
: mutex_unlock(&car_mutex
);
84 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read
);
86 void pxa2xx_ac97_write(struct snd_ac97
*ac97
, unsigned short reg
,
89 volatile u32
*reg_addr
;
91 mutex_lock(&car_mutex
);
93 /* set up primary or secondary codec space */
94 if (cpu_is_pxa25x() && reg
== AC97_GPIO_STATUS
)
95 reg_addr
= ac97
->num
? &SMC_REG_BASE
: &PMC_REG_BASE
;
97 reg_addr
= ac97
->num
? &SAC_REG_BASE
: &PAC_REG_BASE
;
98 reg_addr
+= (reg
>> 1);
100 GSR
= GSR_CDONE
| GSR_SDONE
;
103 if (wait_event_timeout(gsr_wq
, (GSR
| gsr_bits
) & GSR_CDONE
, 1) <= 0 &&
104 !((GSR
| gsr_bits
) & GSR_CDONE
))
105 printk(KERN_ERR
"%s: write error (ac97_reg=%d GSR=%#lx)\n",
106 __func__
, reg
, GSR
| gsr_bits
);
108 mutex_unlock(&car_mutex
);
110 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write
);
113 static inline void pxa_ac97_warm_pxa25x(void)
117 GCR
|= GCR_WARM_RST
| GCR_PRIRDY_IEN
| GCR_SECRDY_IEN
;
118 wait_event_timeout(gsr_wq
, gsr_bits
& (GSR_PCR
| GSR_SCR
), 1);
121 static inline void pxa_ac97_cold_pxa25x(void)
123 GCR
&= GCR_COLD_RST
; /* clear everything but nCRST */
124 GCR
&= ~GCR_COLD_RST
; /* then assert nCRST */
129 GCR
|= GCR_CDONE_IE
|GCR_SDONE_IE
;
130 wait_event_timeout(gsr_wq
, gsr_bits
& (GSR_PCR
| GSR_SCR
), 1);
135 static inline void pxa_ac97_warm_pxa27x(void)
139 /* warm reset broken on Bulverde, so manually keep AC97 reset high */
140 pxa27x_assert_ac97reset(reset_gpio
, 1);
143 pxa27x_assert_ac97reset(reset_gpio
, 0);
147 static inline void pxa_ac97_cold_pxa27x(void)
149 GCR
&= GCR_COLD_RST
; /* clear everything but nCRST */
150 GCR
&= ~GCR_COLD_RST
; /* then assert nCRST */
154 /* PXA27x Developers Manual section 13.5.2.2.1 */
155 clk_enable(ac97conf_clk
);
157 clk_disable(ac97conf_clk
);
164 static inline void pxa_ac97_warm_pxa3xx(void)
170 /* Can't use interrupts */
172 while (!((GSR
| gsr_bits
) & (GSR_PCR
| GSR_SCR
)) && timeout
--)
176 static inline void pxa_ac97_cold_pxa3xx(void)
180 /* Hold CLKBPB for 100us */
186 GCR
&= GCR_COLD_RST
; /* clear everything but nCRST */
187 GCR
&= ~GCR_COLD_RST
; /* then assert nCRST */
191 /* Can't use interrupts on PXA3xx */
192 GCR
&= ~(GCR_PRIRDY_IEN
|GCR_SECRDY_IEN
);
194 GCR
= GCR_WARM_RST
| GCR_COLD_RST
;
195 while (!(GSR
& (GSR_PCR
| GSR_SCR
)) && timeout
--)
200 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97
*ac97
)
206 pxa_ac97_warm_pxa25x();
211 pxa_ac97_warm_pxa27x();
216 pxa_ac97_warm_pxa3xx();
220 gsr
= GSR
| gsr_bits
;
221 if (!(gsr
& (GSR_PCR
| GSR_SCR
))) {
222 printk(KERN_INFO
"%s: warm reset timeout (GSR=%#lx)\n",
230 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset
);
232 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97
*ac97
)
238 pxa_ac97_cold_pxa25x();
243 pxa_ac97_cold_pxa27x();
248 pxa_ac97_cold_pxa3xx();
253 gsr
= GSR
| gsr_bits
;
254 if (!(gsr
& (GSR_PCR
| GSR_SCR
))) {
255 printk(KERN_INFO
"%s: cold reset timeout (GSR=%#lx)\n",
263 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset
);
266 void pxa2xx_ac97_finish_reset(struct snd_ac97
*ac97
)
268 GCR
&= ~(GCR_PRIRDY_IEN
|GCR_SECRDY_IEN
);
269 GCR
|= GCR_SDONE_IE
|GCR_CDONE_IE
;
271 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset
);
273 static irqreturn_t
pxa2xx_ac97_irq(int irq
, void *dev_id
)
283 /* Although we don't use those we still need to clear them
284 since they tend to spuriously trigger when MMC is used
285 (hardware bug? go figure)... */
286 if (cpu_is_pxa27x()) {
299 int pxa2xx_ac97_hw_suspend(void)
301 GCR
|= GCR_ACLINK_OFF
;
302 clk_disable(ac97_clk
);
305 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend
);
307 int pxa2xx_ac97_hw_resume(void)
309 clk_enable(ac97_clk
);
312 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume
);
315 int __devinit
pxa2xx_ac97_hw_probe(struct platform_device
*dev
)
318 pxa2xx_audio_ops_t
*pdata
= dev
->dev
.platform_data
;
321 switch (pdata
->reset_gpio
) {
324 reset_gpio
= pdata
->reset_gpio
;
332 dev_err(&dev
->dev
, "Invalid reset GPIO %d\n",
340 if (cpu_is_pxa27x()) {
341 /* Use GPIO 113 as AC97 Reset on Bulverde */
342 pxa27x_assert_ac97reset(reset_gpio
, 0);
343 ac97conf_clk
= clk_get(&dev
->dev
, "AC97CONFCLK");
344 if (IS_ERR(ac97conf_clk
)) {
345 ret
= PTR_ERR(ac97conf_clk
);
351 ac97_clk
= clk_get(&dev
->dev
, "AC97CLK");
352 if (IS_ERR(ac97_clk
)) {
353 ret
= PTR_ERR(ac97_clk
);
358 ret
= clk_enable(ac97_clk
);
362 ret
= request_irq(IRQ_AC97
, pxa2xx_ac97_irq
, IRQF_DISABLED
, "AC97", NULL
);
369 GCR
|= GCR_ACLINK_OFF
;
375 clk_put(ac97conf_clk
);
381 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe
);
383 void pxa2xx_ac97_hw_remove(struct platform_device
*dev
)
385 GCR
|= GCR_ACLINK_OFF
;
386 free_irq(IRQ_AC97
, NULL
);
388 clk_put(ac97conf_clk
);
391 clk_disable(ac97_clk
);
395 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove
);
397 MODULE_AUTHOR("Nicolas Pitre");
398 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
399 MODULE_LICENSE("GPL");