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proc: switch /proc/excite/unit_id to seq_file interface
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / sparc64 / mm / init.c
blob8c2b50e8abc63d7696386f96d0ce06c62003c1fc
1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/sstate.h>
50 #include <asm/mdesc.h>
51 #include <asm/cpudata.h>
52
53 #define MAX_PHYS_ADDRESS (1UL << 42UL)
54 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
55 #define KPTE_BITMAP_BYTES \
56 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
57
58 unsigned long kern_linear_pte_xor[2] __read_mostly;
59
60 /* A bitmap, one bit for every 256MB of physical memory. If the bit
61 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
62 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
63 */
64 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
65
66 #ifndef CONFIG_DEBUG_PAGEALLOC
67 /* A special kernel TSB for 4MB and 256MB linear mappings.
68 * Space is allocated for this right after the trap table
69 * in arch/sparc64/kernel/head.S
70 */
71 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
72 #endif
73
74 #define MAX_BANKS 32
75
76 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
77 static int pavail_ents __initdata;
78
79 static int cmp_p64(const void *a, const void *b)
80 {
81 const struct linux_prom64_registers *x = a, *y = b;
82
83 if (x->phys_addr > y->phys_addr)
84 return 1;
85 if (x->phys_addr < y->phys_addr)
86 return -1;
87 return 0;
88 }
89
90 static void __init read_obp_memory(const char *property,
91 struct linux_prom64_registers *regs,
92 int *num_ents)
93 {
94 int node = prom_finddevice("/memory");
95 int prop_size = prom_getproplen(node, property);
96 int ents, ret, i;
97
98 ents = prop_size / sizeof(struct linux_prom64_registers);
99 if (ents > MAX_BANKS) {
100 prom_printf("The machine has more %s property entries than "
101 "this kernel can support (%d).\n",
102 property, MAX_BANKS);
103 prom_halt();
104 }
105
106 ret = prom_getproperty(node, property, (char *) regs, prop_size);
107 if (ret == -1) {
108 prom_printf("Couldn't get %s property from /memory.\n");
109 prom_halt();
110 }
111
112 /* Sanitize what we got from the firmware, by page aligning
113 * everything.
114 */
115 for (i = 0; i < ents; i++) {
116 unsigned long base, size;
117
118 base = regs[i].phys_addr;
119 size = regs[i].reg_size;
120
121 size &= PAGE_MASK;
122 if (base & ~PAGE_MASK) {
123 unsigned long new_base = PAGE_ALIGN(base);
124
125 size -= new_base - base;
126 if ((long) size < 0L)
127 size = 0UL;
128 base = new_base;
129 }
130 if (size == 0UL) {
131 /* If it is empty, simply get rid of it.
132 * This simplifies the logic of the other
133 * functions that process these arrays.
134 */
135 memmove(&regs[i], &regs[i + 1],
136 (ents - i - 1) * sizeof(regs[0]));
137 i--;
138 ents--;
139 continue;
140 }
141 regs[i].phys_addr = base;
142 regs[i].reg_size = size;
143 }
144
145 *num_ents = ents;
146
147 sort(regs, ents, sizeof(struct linux_prom64_registers),
148 cmp_p64, NULL);
149 }
150
151 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
152
153 /* Kernel physical address base and size in bytes. */
154 unsigned long kern_base __read_mostly;
155 unsigned long kern_size __read_mostly;
156
157 /* Initial ramdisk setup */
158 extern unsigned long sparc_ramdisk_image64;
159 extern unsigned int sparc_ramdisk_image;
160 extern unsigned int sparc_ramdisk_size;
161
162 struct page *mem_map_zero __read_mostly;
163
164 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
165
166 unsigned long sparc64_kern_pri_context __read_mostly;
167 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
168 unsigned long sparc64_kern_sec_context __read_mostly;
169
170 int num_kernel_image_mappings;
171
172 #ifdef CONFIG_DEBUG_DCFLUSH
173 atomic_t dcpage_flushes = ATOMIC_INIT(0);
174 #ifdef CONFIG_SMP
175 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
176 #endif
177 #endif
178
179 inline void flush_dcache_page_impl(struct page *page)
180 {
181 BUG_ON(tlb_type == hypervisor);
182 #ifdef CONFIG_DEBUG_DCFLUSH
183 atomic_inc(&dcpage_flushes);
184 #endif
185
186 #ifdef DCACHE_ALIASING_POSSIBLE
187 __flush_dcache_page(page_address(page),
188 ((tlb_type == spitfire) &&
189 page_mapping(page) != NULL));
190 #else
191 if (page_mapping(page) != NULL &&
192 tlb_type == spitfire)
193 __flush_icache_page(__pa(page_address(page)));
194 #endif
195 }
196
197 #define PG_dcache_dirty PG_arch_1
198 #define PG_dcache_cpu_shift 32UL
199 #define PG_dcache_cpu_mask \
200 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
201
202 #define dcache_dirty_cpu(page) \
203 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
204
205 static inline void set_dcache_dirty(struct page *page, int this_cpu)
206 {
207 unsigned long mask = this_cpu;
208 unsigned long non_cpu_bits;
209
210 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
211 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
212
213 __asm__ __volatile__("1:\n\t"
214 "ldx [%2], %%g7\n\t"
215 "and %%g7, %1, %%g1\n\t"
216 "or %%g1, %0, %%g1\n\t"
217 "casx [%2], %%g7, %%g1\n\t"
218 "cmp %%g7, %%g1\n\t"
219 "membar #StoreLoad | #StoreStore\n\t"
220 "bne,pn %%xcc, 1b\n\t"
221 " nop"
222 : /* no outputs */
223 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
224 : "g1", "g7");
225 }
226
227 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
228 {
229 unsigned long mask = (1UL << PG_dcache_dirty);
230
231 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
232 "1:\n\t"
233 "ldx [%2], %%g7\n\t"
234 "srlx %%g7, %4, %%g1\n\t"
235 "and %%g1, %3, %%g1\n\t"
236 "cmp %%g1, %0\n\t"
237 "bne,pn %%icc, 2f\n\t"
238 " andn %%g7, %1, %%g1\n\t"
239 "casx [%2], %%g7, %%g1\n\t"
240 "cmp %%g7, %%g1\n\t"
241 "membar #StoreLoad | #StoreStore\n\t"
242 "bne,pn %%xcc, 1b\n\t"
243 " nop\n"
244 "2:"
245 : /* no outputs */
246 : "r" (cpu), "r" (mask), "r" (&page->flags),
247 "i" (PG_dcache_cpu_mask),
248 "i" (PG_dcache_cpu_shift)
249 : "g1", "g7");
250 }
251
252 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
253 {
254 unsigned long tsb_addr = (unsigned long) ent;
255
256 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
257 tsb_addr = __pa(tsb_addr);
258
259 __tsb_insert(tsb_addr, tag, pte);
260 }
261
262 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
263 unsigned long _PAGE_SZBITS __read_mostly;
264
265 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
266 {
267 struct mm_struct *mm;
268 struct tsb *tsb;
269 unsigned long tag, flags;
270 unsigned long tsb_index, tsb_hash_shift;
271
272 if (tlb_type != hypervisor) {
273 unsigned long pfn = pte_pfn(pte);
274 unsigned long pg_flags;
275 struct page *page;
276
277 if (pfn_valid(pfn) &&
278 (page = pfn_to_page(pfn), page_mapping(page)) &&
279 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
280 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
281 PG_dcache_cpu_mask);
282 int this_cpu = get_cpu();
283
284 /* This is just to optimize away some function calls
285 * in the SMP case.
286 */
287 if (cpu == this_cpu)
288 flush_dcache_page_impl(page);
289 else
290 smp_flush_dcache_page_impl(page, cpu);
291
292 clear_dcache_dirty_cpu(page, cpu);
293
294 put_cpu();
295 }
296 }
297
298 mm = vma->vm_mm;
299
300 tsb_index = MM_TSB_BASE;
301 tsb_hash_shift = PAGE_SHIFT;
302
303 spin_lock_irqsave(&mm->context.lock, flags);
304
305 #ifdef CONFIG_HUGETLB_PAGE
306 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
307 if ((tlb_type == hypervisor &&
308 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
309 (tlb_type != hypervisor &&
310 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
311 tsb_index = MM_TSB_HUGE;
312 tsb_hash_shift = HPAGE_SHIFT;
313 }
314 }
315 #endif
316
317 tsb = mm->context.tsb_block[tsb_index].tsb;
318 tsb += ((address >> tsb_hash_shift) &
319 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
320 tag = (address >> 22UL);
321 tsb_insert(tsb, tag, pte_val(pte));
322
323 spin_unlock_irqrestore(&mm->context.lock, flags);
324 }
325
326 void flush_dcache_page(struct page *page)
327 {
328 struct address_space *mapping;
329 int this_cpu;
330
331 if (tlb_type == hypervisor)
332 return;
333
334 /* Do not bother with the expensive D-cache flush if it
335 * is merely the zero page. The 'bigcore' testcase in GDB
336 * causes this case to run millions of times.
337 */
338 if (page == ZERO_PAGE(0))
339 return;
340
341 this_cpu = get_cpu();
342
343 mapping = page_mapping(page);
344 if (mapping && !mapping_mapped(mapping)) {
345 int dirty = test_bit(PG_dcache_dirty, &page->flags);
346 if (dirty) {
347 int dirty_cpu = dcache_dirty_cpu(page);
348
349 if (dirty_cpu == this_cpu)
350 goto out;
351 smp_flush_dcache_page_impl(page, dirty_cpu);
352 }
353 set_dcache_dirty(page, this_cpu);
354 } else {
355 /* We could delay the flush for the !page_mapping
356 * case too. But that case is for exec env/arg
357 * pages and those are %99 certainly going to get
358 * faulted into the tlb (and thus flushed) anyways.
359 */
360 flush_dcache_page_impl(page);
361 }
362
363 out:
364 put_cpu();
365 }
366
367 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
368 {
369 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
370 if (tlb_type == spitfire) {
371 unsigned long kaddr;
372
373 /* This code only runs on Spitfire cpus so this is
374 * why we can assume _PAGE_PADDR_4U.
375 */
376 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
377 unsigned long paddr, mask = _PAGE_PADDR_4U;
378
379 if (kaddr >= PAGE_OFFSET)
380 paddr = kaddr & mask;
381 else {
382 pgd_t *pgdp = pgd_offset_k(kaddr);
383 pud_t *pudp = pud_offset(pgdp, kaddr);
384 pmd_t *pmdp = pmd_offset(pudp, kaddr);
385 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
386
387 paddr = pte_val(*ptep) & mask;
388 }
389 __flush_icache_page(paddr);
390 }
391 }
392 }
393
394 void show_mem(void)
395 {
396 unsigned long total = 0, reserved = 0;
397 unsigned long shared = 0, cached = 0;
398 pg_data_t *pgdat;
399
400 printk(KERN_INFO "Mem-info:\n");
401 show_free_areas();
402 printk(KERN_INFO "Free swap: %6ldkB\n",
403 nr_swap_pages << (PAGE_SHIFT-10));
404 for_each_online_pgdat(pgdat) {
405 unsigned long i, flags;
406
407 pgdat_resize_lock(pgdat, &flags);
408 for (i = 0; i < pgdat->node_spanned_pages; i++) {
409 struct page *page = pgdat_page_nr(pgdat, i);
410 total++;
411 if (PageReserved(page))
412 reserved++;
413 else if (PageSwapCache(page))
414 cached++;
415 else if (page_count(page))
416 shared += page_count(page) - 1;
417 }
418 pgdat_resize_unlock(pgdat, &flags);
419 }
420
421 printk(KERN_INFO "%lu pages of RAM\n", total);
422 printk(KERN_INFO "%lu reserved pages\n", reserved);
423 printk(KERN_INFO "%lu pages shared\n", shared);
424 printk(KERN_INFO "%lu pages swap cached\n", cached);
425
426 printk(KERN_INFO "%lu pages dirty\n",
427 global_page_state(NR_FILE_DIRTY));
428 printk(KERN_INFO "%lu pages writeback\n",
429 global_page_state(NR_WRITEBACK));
430 printk(KERN_INFO "%lu pages mapped\n",
431 global_page_state(NR_FILE_MAPPED));
432 printk(KERN_INFO "%lu pages slab\n",
433 global_page_state(NR_SLAB_RECLAIMABLE) +
434 global_page_state(NR_SLAB_UNRECLAIMABLE));
435 printk(KERN_INFO "%lu pages pagetables\n",
436 global_page_state(NR_PAGETABLE));
437 }
438
439 void mmu_info(struct seq_file *m)
440 {
441 if (tlb_type == cheetah)
442 seq_printf(m, "MMU Type\t: Cheetah\n");
443 else if (tlb_type == cheetah_plus)
444 seq_printf(m, "MMU Type\t: Cheetah+\n");
445 else if (tlb_type == spitfire)
446 seq_printf(m, "MMU Type\t: Spitfire\n");
447 else if (tlb_type == hypervisor)
448 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
449 else
450 seq_printf(m, "MMU Type\t: ???\n");
451
452 #ifdef CONFIG_DEBUG_DCFLUSH
453 seq_printf(m, "DCPageFlushes\t: %d\n",
454 atomic_read(&dcpage_flushes));
455 #ifdef CONFIG_SMP
456 seq_printf(m, "DCPageFlushesXC\t: %d\n",
457 atomic_read(&dcpage_flushes_xcall));
458 #endif /* CONFIG_SMP */
459 #endif /* CONFIG_DEBUG_DCFLUSH */
460 }
461
462 struct linux_prom_translation {
463 unsigned long virt;
464 unsigned long size;
465 unsigned long data;
466 };
467
468 /* Exported for kernel TLB miss handling in ktlb.S */
469 struct linux_prom_translation prom_trans[512] __read_mostly;
470 unsigned int prom_trans_ents __read_mostly;
471
472 /* Exported for SMP bootup purposes. */
473 unsigned long kern_locked_tte_data;
474
475 /* The obp translations are saved based on 8k pagesize, since obp can
476 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
477 * HI_OBP_ADDRESS range are handled in ktlb.S.
478 */
479 static inline int in_obp_range(unsigned long vaddr)
480 {
481 return (vaddr >= LOW_OBP_ADDRESS &&
482 vaddr < HI_OBP_ADDRESS);
483 }
484
485 static int cmp_ptrans(const void *a, const void *b)
486 {
487 const struct linux_prom_translation *x = a, *y = b;
488
489 if (x->virt > y->virt)
490 return 1;
491 if (x->virt < y->virt)
492 return -1;
493 return 0;
494 }
495
496 /* Read OBP translations property into 'prom_trans[]'. */
497 static void __init read_obp_translations(void)
498 {
499 int n, node, ents, first, last, i;
500
501 node = prom_finddevice("/virtual-memory");
502 n = prom_getproplen(node, "translations");
503 if (unlikely(n == 0 || n == -1)) {
504 prom_printf("prom_mappings: Couldn't get size.\n");
505 prom_halt();
506 }
507 if (unlikely(n > sizeof(prom_trans))) {
508 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
509 prom_halt();
510 }
511
512 if ((n = prom_getproperty(node, "translations",
513 (char *)&prom_trans[0],
514 sizeof(prom_trans))) == -1) {
515 prom_printf("prom_mappings: Couldn't get property.\n");
516 prom_halt();
517 }
518
519 n = n / sizeof(struct linux_prom_translation);
520
521 ents = n;
522
523 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
524 cmp_ptrans, NULL);
525
526 /* Now kick out all the non-OBP entries. */
527 for (i = 0; i < ents; i++) {
528 if (in_obp_range(prom_trans[i].virt))
529 break;
530 }
531 first = i;
532 for (; i < ents; i++) {
533 if (!in_obp_range(prom_trans[i].virt))
534 break;
535 }
536 last = i;
537
538 for (i = 0; i < (last - first); i++) {
539 struct linux_prom_translation *src = &prom_trans[i + first];
540 struct linux_prom_translation *dest = &prom_trans[i];
541
542 *dest = *src;
543 }
544 for (; i < ents; i++) {
545 struct linux_prom_translation *dest = &prom_trans[i];
546 dest->virt = dest->size = dest->data = 0x0UL;
547 }
548
549 prom_trans_ents = last - first;
550
551 if (tlb_type == spitfire) {
552 /* Clear diag TTE bits. */
553 for (i = 0; i < prom_trans_ents; i++)
554 prom_trans[i].data &= ~0x0003fe0000000000UL;
555 }
556 }
557
558 static void __init hypervisor_tlb_lock(unsigned long vaddr,
559 unsigned long pte,
560 unsigned long mmu)
561 {
562 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
563
564 if (ret != 0) {
565 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
566 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
567 prom_halt();
568 }
569 }
570
571 static unsigned long kern_large_tte(unsigned long paddr);
572
573 static void __init remap_kernel(void)
574 {
575 unsigned long phys_page, tte_vaddr, tte_data;
576 int i, tlb_ent = sparc64_highest_locked_tlbent();
577
578 tte_vaddr = (unsigned long) KERNBASE;
579 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
580 tte_data = kern_large_tte(phys_page);
581
582 kern_locked_tte_data = tte_data;
583
584 /* Now lock us into the TLBs via Hypervisor or OBP. */
585 if (tlb_type == hypervisor) {
586 for (i = 0; i < num_kernel_image_mappings; i++) {
587 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
588 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
589 tte_vaddr += 0x400000;
590 tte_data += 0x400000;
591 }
592 } else {
593 for (i = 0; i < num_kernel_image_mappings; i++) {
594 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
595 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
596 tte_vaddr += 0x400000;
597 tte_data += 0x400000;
598 }
599 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
600 }
601 if (tlb_type == cheetah_plus) {
602 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
603 CTX_CHEETAH_PLUS_NUC);
604 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
605 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
606 }
607 }
608
609
610 static void __init inherit_prom_mappings(void)
611 {
612 read_obp_translations();
613
614 /* Now fixup OBP's idea about where we really are mapped. */
615 printk("Remapping the kernel... ");
616 remap_kernel();
617 printk("done.\n");
618 }
619
620 void prom_world(int enter)
621 {
622 if (!enter)
623 set_fs((mm_segment_t) { get_thread_current_ds() });
624
625 __asm__ __volatile__("flushw");
626 }
627
628 void __flush_dcache_range(unsigned long start, unsigned long end)
629 {
630 unsigned long va;
631
632 if (tlb_type == spitfire) {
633 int n = 0;
634
635 for (va = start; va < end; va += 32) {
636 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
637 if (++n >= 512)
638 break;
639 }
640 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
641 start = __pa(start);
642 end = __pa(end);
643 for (va = start; va < end; va += 32)
644 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
645 "membar #Sync"
646 : /* no outputs */
647 : "r" (va),
648 "i" (ASI_DCACHE_INVALIDATE));
649 }
650 }
651
652 /* get_new_mmu_context() uses "cache + 1". */
653 DEFINE_SPINLOCK(ctx_alloc_lock);
654 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
655 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
656 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
657 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
658
659 /* Caller does TLB context flushing on local CPU if necessary.
660 * The caller also ensures that CTX_VALID(mm->context) is false.
661 *
662 * We must be careful about boundary cases so that we never
663 * let the user have CTX 0 (nucleus) or we ever use a CTX
664 * version of zero (and thus NO_CONTEXT would not be caught
665 * by version mis-match tests in mmu_context.h).
666 *
667 * Always invoked with interrupts disabled.
668 */
669 void get_new_mmu_context(struct mm_struct *mm)
670 {
671 unsigned long ctx, new_ctx;
672 unsigned long orig_pgsz_bits;
673 unsigned long flags;
674 int new_version;
675
676 spin_lock_irqsave(&ctx_alloc_lock, flags);
677 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
678 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
679 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
680 new_version = 0;
681 if (new_ctx >= (1 << CTX_NR_BITS)) {
682 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
683 if (new_ctx >= ctx) {
684 int i;
685 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
686 CTX_FIRST_VERSION;
687 if (new_ctx == 1)
688 new_ctx = CTX_FIRST_VERSION;
689
690 /* Don't call memset, for 16 entries that's just
691 * plain silly...
692 */
693 mmu_context_bmap[0] = 3;
694 mmu_context_bmap[1] = 0;
695 mmu_context_bmap[2] = 0;
696 mmu_context_bmap[3] = 0;
697 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
698 mmu_context_bmap[i + 0] = 0;
699 mmu_context_bmap[i + 1] = 0;
700 mmu_context_bmap[i + 2] = 0;
701 mmu_context_bmap[i + 3] = 0;
702 }
703 new_version = 1;
704 goto out;
705 }
706 }
707 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
708 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
709 out:
710 tlb_context_cache = new_ctx;
711 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
712 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
713
714 if (unlikely(new_version))
715 smp_new_mmu_context_version();
716 }
717
718 static int numa_enabled = 1;
719 static int numa_debug;
720
721 static int __init early_numa(char *p)
722 {
723 if (!p)
724 return 0;
725
726 if (strstr(p, "off"))
727 numa_enabled = 0;
728
729 if (strstr(p, "debug"))
730 numa_debug = 1;
731
732 return 0;
733 }
734 early_param("numa", early_numa);
735
736 #define numadbg(f, a...) \
737 do { if (numa_debug) \
738 printk(KERN_INFO f, ## a); \
739 } while (0)
740
741 static void __init find_ramdisk(unsigned long phys_base)
742 {
743 #ifdef CONFIG_BLK_DEV_INITRD
744 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
745 unsigned long ramdisk_image;
746
747 /* Older versions of the bootloader only supported a
748 * 32-bit physical address for the ramdisk image
749 * location, stored at sparc_ramdisk_image. Newer
750 * SILO versions set sparc_ramdisk_image to zero and
751 * provide a full 64-bit physical address at
752 * sparc_ramdisk_image64.
753 */
754 ramdisk_image = sparc_ramdisk_image;
755 if (!ramdisk_image)
756 ramdisk_image = sparc_ramdisk_image64;
757
758 /* Another bootloader quirk. The bootloader normalizes
759 * the physical address to KERNBASE, so we have to
760 * factor that back out and add in the lowest valid
761 * physical page address to get the true physical address.
762 */
763 ramdisk_image -= KERNBASE;
764 ramdisk_image += phys_base;
765
766 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
767 ramdisk_image, sparc_ramdisk_size);
768
769 initrd_start = ramdisk_image;
770 initrd_end = ramdisk_image + sparc_ramdisk_size;
771
772 lmb_reserve(initrd_start, initrd_end);
773 }
774 #endif
775 }
776
777 struct node_mem_mask {
778 unsigned long mask;
779 unsigned long val;
780 unsigned long bootmem_paddr;
781 };
782 static struct node_mem_mask node_masks[MAX_NUMNODES];
783 static int num_node_masks;
784
785 int numa_cpu_lookup_table[NR_CPUS];
786 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
787
788 #ifdef CONFIG_NEED_MULTIPLE_NODES
789 static bootmem_data_t plat_node_bdata[MAX_NUMNODES];
790
791 struct mdesc_mblock {
792 u64 base;
793 u64 size;
794 u64 offset; /* RA-to-PA */
795 };
796 static struct mdesc_mblock *mblocks;
797 static int num_mblocks;
798
799 static unsigned long ra_to_pa(unsigned long addr)
800 {
801 int i;
802
803 for (i = 0; i < num_mblocks; i++) {
804 struct mdesc_mblock *m = &mblocks[i];
805
806 if (addr >= m->base &&
807 addr < (m->base + m->size)) {
808 addr += m->offset;
809 break;
810 }
811 }
812 return addr;
813 }
814
815 static int find_node(unsigned long addr)
816 {
817 int i;
818
819 addr = ra_to_pa(addr);
820 for (i = 0; i < num_node_masks; i++) {
821 struct node_mem_mask *p = &node_masks[i];
822
823 if ((addr & p->mask) == p->val)
824 return i;
825 }
826 return -1;
827 }
828
829 static unsigned long nid_range(unsigned long start, unsigned long end,
830 int *nid)
831 {
832 *nid = find_node(start);
833 start += PAGE_SIZE;
834 while (start < end) {
835 int n = find_node(start);
836
837 if (n != *nid)
838 break;
839 start += PAGE_SIZE;
840 }
841
842 return start;
843 }
844 #else
845 static unsigned long nid_range(unsigned long start, unsigned long end,
846 int *nid)
847 {
848 *nid = 0;
849 return end;
850 }
851 #endif
852
853 /* This must be invoked after performing all of the necessary
854 * add_active_range() calls for 'nid'. We need to be able to get
855 * correct data from get_pfn_range_for_nid().
856 */
857 static void __init allocate_node_data(int nid)
858 {
859 unsigned long paddr, num_pages, start_pfn, end_pfn;
860 struct pglist_data *p;
861
862 #ifdef CONFIG_NEED_MULTIPLE_NODES
863 paddr = lmb_alloc_nid(sizeof(struct pglist_data),
864 SMP_CACHE_BYTES, nid, nid_range);
865 if (!paddr) {
866 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
867 prom_halt();
868 }
869 NODE_DATA(nid) = __va(paddr);
870 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
871
872 NODE_DATA(nid)->bdata = &plat_node_bdata[nid];
873 #endif
874
875 p = NODE_DATA(nid);
876
877 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
878 p->node_start_pfn = start_pfn;
879 p->node_spanned_pages = end_pfn - start_pfn;
880
881 if (p->node_spanned_pages) {
882 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
883
884 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
885 nid_range);
886 if (!paddr) {
887 prom_printf("Cannot allocate bootmap for nid[%d]\n",
888 nid);
889 prom_halt();
890 }
891 node_masks[nid].bootmem_paddr = paddr;
892 }
893 }
894
895 static void init_node_masks_nonnuma(void)
896 {
897 int i;
898
899 numadbg("Initializing tables for non-numa.\n");
900
901 node_masks[0].mask = node_masks[0].val = 0;
902 num_node_masks = 1;
903
904 for (i = 0; i < NR_CPUS; i++)
905 numa_cpu_lookup_table[i] = 0;
906
907 numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
908 }
909
910 #ifdef CONFIG_NEED_MULTIPLE_NODES
911 struct pglist_data *node_data[MAX_NUMNODES];
912
913 EXPORT_SYMBOL(numa_cpu_lookup_table);
914 EXPORT_SYMBOL(numa_cpumask_lookup_table);
915 EXPORT_SYMBOL(node_data);
916
917 struct mdesc_mlgroup {
918 u64 node;
919 u64 latency;
920 u64 match;
921 u64 mask;
922 };
923 static struct mdesc_mlgroup *mlgroups;
924 static int num_mlgroups;
925
926 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
927 u32 cfg_handle)
928 {
929 u64 arc;
930
931 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
932 u64 target = mdesc_arc_target(md, arc);
933 const u64 *val;
934
935 val = mdesc_get_property(md, target,
936 "cfg-handle", NULL);
937 if (val && *val == cfg_handle)
938 return 0;
939 }
940 return -ENODEV;
941 }
942
943 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
944 u32 cfg_handle)
945 {
946 u64 arc, candidate, best_latency = ~(u64)0;
947
948 candidate = MDESC_NODE_NULL;
949 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
950 u64 target = mdesc_arc_target(md, arc);
951 const char *name = mdesc_node_name(md, target);
952 const u64 *val;
953
954 if (strcmp(name, "pio-latency-group"))
955 continue;
956
957 val = mdesc_get_property(md, target, "latency", NULL);
958 if (!val)
959 continue;
960
961 if (*val < best_latency) {
962 candidate = target;
963 best_latency = *val;
964 }
965 }
966
967 if (candidate == MDESC_NODE_NULL)
968 return -ENODEV;
969
970 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
971 }
972
973 int of_node_to_nid(struct device_node *dp)
974 {
975 const struct linux_prom64_registers *regs;
976 struct mdesc_handle *md;
977 u32 cfg_handle;
978 int count, nid;
979 u64 grp;
980
981 if (!mlgroups)
982 return -1;
983
984 regs = of_get_property(dp, "reg", NULL);
985 if (!regs)
986 return -1;
987
988 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
989
990 md = mdesc_grab();
991
992 count = 0;
993 nid = -1;
994 mdesc_for_each_node_by_name(md, grp, "group") {
995 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
996 nid = count;
997 break;
998 }
999 count++;
1000 }
1001
1002 mdesc_release(md);
1003
1004 return nid;
1005 }
1006
1007 static void add_node_ranges(void)
1008 {
1009 int i;
1010
1011 for (i = 0; i < lmb.memory.cnt; i++) {
1012 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1013 unsigned long start, end;
1014
1015 start = lmb.memory.region[i].base;
1016 end = start + size;
1017 while (start < end) {
1018 unsigned long this_end;
1019 int nid;
1020
1021 this_end = nid_range(start, end, &nid);
1022
1023 numadbg("Adding active range nid[%d] "
1024 "start[%lx] end[%lx]\n",
1025 nid, start, this_end);
1026
1027 add_active_range(nid,
1028 start >> PAGE_SHIFT,
1029 this_end >> PAGE_SHIFT);
1030
1031 start = this_end;
1032 }
1033 }
1034 }
1035
1036 static int __init grab_mlgroups(struct mdesc_handle *md)
1037 {
1038 unsigned long paddr;
1039 int count = 0;
1040 u64 node;
1041
1042 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1043 count++;
1044 if (!count)
1045 return -ENOENT;
1046
1047 paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1048 SMP_CACHE_BYTES);
1049 if (!paddr)
1050 return -ENOMEM;
1051
1052 mlgroups = __va(paddr);
1053 num_mlgroups = count;
1054
1055 count = 0;
1056 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1057 struct mdesc_mlgroup *m = &mlgroups[count++];
1058 const u64 *val;
1059
1060 m->node = node;
1061
1062 val = mdesc_get_property(md, node, "latency", NULL);
1063 m->latency = *val;
1064 val = mdesc_get_property(md, node, "address-match", NULL);
1065 m->match = *val;
1066 val = mdesc_get_property(md, node, "address-mask", NULL);
1067 m->mask = *val;
1068
1069 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1070 "match[%lx] mask[%lx]\n",
1071 count - 1, m->node, m->latency, m->match, m->mask);
1072 }
1073
1074 return 0;
1075 }
1076
1077 static int __init grab_mblocks(struct mdesc_handle *md)
1078 {
1079 unsigned long paddr;
1080 int count = 0;
1081 u64 node;
1082
1083 mdesc_for_each_node_by_name(md, node, "mblock")
1084 count++;
1085 if (!count)
1086 return -ENOENT;
1087
1088 paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1089 SMP_CACHE_BYTES);
1090 if (!paddr)
1091 return -ENOMEM;
1092
1093 mblocks = __va(paddr);
1094 num_mblocks = count;
1095
1096 count = 0;
1097 mdesc_for_each_node_by_name(md, node, "mblock") {
1098 struct mdesc_mblock *m = &mblocks[count++];
1099 const u64 *val;
1100
1101 val = mdesc_get_property(md, node, "base", NULL);
1102 m->base = *val;
1103 val = mdesc_get_property(md, node, "size", NULL);
1104 m->size = *val;
1105 val = mdesc_get_property(md, node,
1106 "address-congruence-offset", NULL);
1107 m->offset = *val;
1108
1109 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1110 count - 1, m->base, m->size, m->offset);
1111 }
1112
1113 return 0;
1114 }
1115
1116 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1117 u64 grp, cpumask_t *mask)
1118 {
1119 u64 arc;
1120
1121 cpus_clear(*mask);
1122
1123 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1124 u64 target = mdesc_arc_target(md, arc);
1125 const char *name = mdesc_node_name(md, target);
1126 const u64 *id;
1127
1128 if (strcmp(name, "cpu"))
1129 continue;
1130 id = mdesc_get_property(md, target, "id", NULL);
1131 if (*id < NR_CPUS)
1132 cpu_set(*id, *mask);
1133 }
1134 }
1135
1136 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1137 {
1138 int i;
1139
1140 for (i = 0; i < num_mlgroups; i++) {
1141 struct mdesc_mlgroup *m = &mlgroups[i];
1142 if (m->node == node)
1143 return m;
1144 }
1145 return NULL;
1146 }
1147
1148 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1149 int index)
1150 {
1151 struct mdesc_mlgroup *candidate = NULL;
1152 u64 arc, best_latency = ~(u64)0;
1153 struct node_mem_mask *n;
1154
1155 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1156 u64 target = mdesc_arc_target(md, arc);
1157 struct mdesc_mlgroup *m = find_mlgroup(target);
1158 if (!m)
1159 continue;
1160 if (m->latency < best_latency) {
1161 candidate = m;
1162 best_latency = m->latency;
1163 }
1164 }
1165 if (!candidate)
1166 return -ENOENT;
1167
1168 if (num_node_masks != index) {
1169 printk(KERN_ERR "Inconsistent NUMA state, "
1170 "index[%d] != num_node_masks[%d]\n",
1171 index, num_node_masks);
1172 return -EINVAL;
1173 }
1174
1175 n = &node_masks[num_node_masks++];
1176
1177 n->mask = candidate->mask;
1178 n->val = candidate->match;
1179
1180 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1181 index, n->mask, n->val, candidate->latency);
1182
1183 return 0;
1184 }
1185
1186 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1187 int index)
1188 {
1189 cpumask_t mask;
1190 int cpu;
1191
1192 numa_parse_mdesc_group_cpus(md, grp, &mask);
1193
1194 for_each_cpu_mask(cpu, mask)
1195 numa_cpu_lookup_table[cpu] = index;
1196 numa_cpumask_lookup_table[index] = mask;
1197
1198 if (numa_debug) {
1199 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1200 for_each_cpu_mask(cpu, mask)
1201 printk("%d ", cpu);
1202 printk("]\n");
1203 }
1204
1205 return numa_attach_mlgroup(md, grp, index);
1206 }
1207
1208 static int __init numa_parse_mdesc(void)
1209 {
1210 struct mdesc_handle *md = mdesc_grab();
1211 int i, err, count;
1212 u64 node;
1213
1214 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1215 if (node == MDESC_NODE_NULL) {
1216 mdesc_release(md);
1217 return -ENOENT;
1218 }
1219
1220 err = grab_mblocks(md);
1221 if (err < 0)
1222 goto out;
1223
1224 err = grab_mlgroups(md);
1225 if (err < 0)
1226 goto out;
1227
1228 count = 0;
1229 mdesc_for_each_node_by_name(md, node, "group") {
1230 err = numa_parse_mdesc_group(md, node, count);
1231 if (err < 0)
1232 break;
1233 count++;
1234 }
1235
1236 add_node_ranges();
1237
1238 for (i = 0; i < num_node_masks; i++) {
1239 allocate_node_data(i);
1240 node_set_online(i);
1241 }
1242
1243 err = 0;
1244 out:
1245 mdesc_release(md);
1246 return err;
1247 }
1248
1249 static int __init numa_parse_sun4u(void)
1250 {
1251 return -1;
1252 }
1253
1254 static int __init bootmem_init_numa(void)
1255 {
1256 int err = -1;
1257
1258 numadbg("bootmem_init_numa()\n");
1259
1260 if (numa_enabled) {
1261 if (tlb_type == hypervisor)
1262 err = numa_parse_mdesc();
1263 else
1264 err = numa_parse_sun4u();
1265 }
1266 return err;
1267 }
1268
1269 #else
1270
1271 static int bootmem_init_numa(void)
1272 {
1273 return -1;
1274 }
1275
1276 #endif
1277
1278 static void __init bootmem_init_nonnuma(void)
1279 {
1280 unsigned long top_of_ram = lmb_end_of_DRAM();
1281 unsigned long total_ram = lmb_phys_mem_size();
1282 unsigned int i;
1283
1284 numadbg("bootmem_init_nonnuma()\n");
1285
1286 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1287 top_of_ram, total_ram);
1288 printk(KERN_INFO "Memory hole size: %ldMB\n",
1289 (top_of_ram - total_ram) >> 20);
1290
1291 init_node_masks_nonnuma();
1292
1293 for (i = 0; i < lmb.memory.cnt; i++) {
1294 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1295 unsigned long start_pfn, end_pfn;
1296
1297 if (!size)
1298 continue;
1299
1300 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1301 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1302 add_active_range(0, start_pfn, end_pfn);
1303 }
1304
1305 allocate_node_data(0);
1306
1307 node_set_online(0);
1308 }
1309
1310 static void __init reserve_range_in_node(int nid, unsigned long start,
1311 unsigned long end)
1312 {
1313 numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1314 nid, start, end);
1315 while (start < end) {
1316 unsigned long this_end;
1317 int n;
1318
1319 this_end = nid_range(start, end, &n);
1320 if (n == nid) {
1321 numadbg(" MATCH reserving range [%lx:%lx]\n",
1322 start, this_end);
1323 reserve_bootmem_node(NODE_DATA(nid), start,
1324 (this_end - start), BOOTMEM_DEFAULT);
1325 } else
1326 numadbg(" NO MATCH, advancing start to %lx\n",
1327 this_end);
1328
1329 start = this_end;
1330 }
1331 }
1332
1333 static void __init trim_reserved_in_node(int nid)
1334 {
1335 int i;
1336
1337 numadbg(" trim_reserved_in_node(%d)\n", nid);
1338
1339 for (i = 0; i < lmb.reserved.cnt; i++) {
1340 unsigned long start = lmb.reserved.region[i].base;
1341 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1342 unsigned long end = start + size;
1343
1344 reserve_range_in_node(nid, start, end);
1345 }
1346 }
1347
1348 static void __init bootmem_init_one_node(int nid)
1349 {
1350 struct pglist_data *p;
1351
1352 numadbg("bootmem_init_one_node(%d)\n", nid);
1353
1354 p = NODE_DATA(nid);
1355
1356 if (p->node_spanned_pages) {
1357 unsigned long paddr = node_masks[nid].bootmem_paddr;
1358 unsigned long end_pfn;
1359
1360 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1361
1362 numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n",
1363 nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1364
1365 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1366 p->node_start_pfn, end_pfn);
1367
1368 numadbg(" free_bootmem_with_active_regions(%d, %lx)\n",
1369 nid, end_pfn);
1370 free_bootmem_with_active_regions(nid, end_pfn);
1371
1372 trim_reserved_in_node(nid);
1373
1374 numadbg(" sparse_memory_present_with_active_regions(%d)\n",
1375 nid);
1376 sparse_memory_present_with_active_regions(nid);
1377 }
1378 }
1379
1380 static unsigned long __init bootmem_init(unsigned long phys_base)
1381 {
1382 unsigned long end_pfn;
1383 int nid;
1384
1385 end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1386 max_pfn = max_low_pfn = end_pfn;
1387 min_low_pfn = (phys_base >> PAGE_SHIFT);
1388
1389 if (bootmem_init_numa() < 0)
1390 bootmem_init_nonnuma();
1391
1392 /* XXX cpu notifier XXX */
1393
1394 for_each_online_node(nid)
1395 bootmem_init_one_node(nid);
1396
1397 sparse_init();
1398
1399 return end_pfn;
1400 }
1401
1402 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1403 static int pall_ents __initdata;
1404
1405 #ifdef CONFIG_DEBUG_PAGEALLOC
1406 static unsigned long __ref kernel_map_range(unsigned long pstart,
1407 unsigned long pend, pgprot_t prot)
1408 {
1409 unsigned long vstart = PAGE_OFFSET + pstart;
1410 unsigned long vend = PAGE_OFFSET + pend;
1411 unsigned long alloc_bytes = 0UL;
1412
1413 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1414 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1415 vstart, vend);
1416 prom_halt();
1417 }
1418
1419 while (vstart < vend) {
1420 unsigned long this_end, paddr = __pa(vstart);
1421 pgd_t *pgd = pgd_offset_k(vstart);
1422 pud_t *pud;
1423 pmd_t *pmd;
1424 pte_t *pte;
1425
1426 pud = pud_offset(pgd, vstart);
1427 if (pud_none(*pud)) {
1428 pmd_t *new;
1429
1430 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1431 alloc_bytes += PAGE_SIZE;
1432 pud_populate(&init_mm, pud, new);
1433 }
1434
1435 pmd = pmd_offset(pud, vstart);
1436 if (!pmd_present(*pmd)) {
1437 pte_t *new;
1438
1439 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1440 alloc_bytes += PAGE_SIZE;
1441 pmd_populate_kernel(&init_mm, pmd, new);
1442 }
1443
1444 pte = pte_offset_kernel(pmd, vstart);
1445 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1446 if (this_end > vend)
1447 this_end = vend;
1448
1449 while (vstart < this_end) {
1450 pte_val(*pte) = (paddr | pgprot_val(prot));
1451
1452 vstart += PAGE_SIZE;
1453 paddr += PAGE_SIZE;
1454 pte++;
1455 }
1456 }
1457
1458 return alloc_bytes;
1459 }
1460
1461 extern unsigned int kvmap_linear_patch[1];
1462 #endif /* CONFIG_DEBUG_PAGEALLOC */
1463
1464 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1465 {
1466 const unsigned long shift_256MB = 28;
1467 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1468 const unsigned long size_256MB = (1UL << shift_256MB);
1469
1470 while (start < end) {
1471 long remains;
1472
1473 remains = end - start;
1474 if (remains < size_256MB)
1475 break;
1476
1477 if (start & mask_256MB) {
1478 start = (start + size_256MB) & ~mask_256MB;
1479 continue;
1480 }
1481
1482 while (remains >= size_256MB) {
1483 unsigned long index = start >> shift_256MB;
1484
1485 __set_bit(index, kpte_linear_bitmap);
1486
1487 start += size_256MB;
1488 remains -= size_256MB;
1489 }
1490 }
1491 }
1492
1493 static void __init init_kpte_bitmap(void)
1494 {
1495 unsigned long i;
1496
1497 for (i = 0; i < pall_ents; i++) {
1498 unsigned long phys_start, phys_end;
1499
1500 phys_start = pall[i].phys_addr;
1501 phys_end = phys_start + pall[i].reg_size;
1502
1503 mark_kpte_bitmap(phys_start, phys_end);
1504 }
1505 }
1506
1507 static void __init kernel_physical_mapping_init(void)
1508 {
1509 #ifdef CONFIG_DEBUG_PAGEALLOC
1510 unsigned long i, mem_alloced = 0UL;
1511
1512 for (i = 0; i < pall_ents; i++) {
1513 unsigned long phys_start, phys_end;
1514
1515 phys_start = pall[i].phys_addr;
1516 phys_end = phys_start + pall[i].reg_size;
1517
1518 mem_alloced += kernel_map_range(phys_start, phys_end,
1519 PAGE_KERNEL);
1520 }
1521
1522 printk("Allocated %ld bytes for kernel page tables.\n",
1523 mem_alloced);
1524
1525 kvmap_linear_patch[0] = 0x01000000; /* nop */
1526 flushi(&kvmap_linear_patch[0]);
1527
1528 __flush_tlb_all();
1529 #endif
1530 }
1531
1532 #ifdef CONFIG_DEBUG_PAGEALLOC
1533 void kernel_map_pages(struct page *page, int numpages, int enable)
1534 {
1535 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1536 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1537
1538 kernel_map_range(phys_start, phys_end,
1539 (enable ? PAGE_KERNEL : __pgprot(0)));
1540
1541 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1542 PAGE_OFFSET + phys_end);
1543
1544 /* we should perform an IPI and flush all tlbs,
1545 * but that can deadlock->flush only current cpu.
1546 */
1547 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1548 PAGE_OFFSET + phys_end);
1549 }
1550 #endif
1551
1552 unsigned long __init find_ecache_flush_span(unsigned long size)
1553 {
1554 int i;
1555
1556 for (i = 0; i < pavail_ents; i++) {
1557 if (pavail[i].reg_size >= size)
1558 return pavail[i].phys_addr;
1559 }
1560
1561 return ~0UL;
1562 }
1563
1564 static void __init tsb_phys_patch(void)
1565 {
1566 struct tsb_ldquad_phys_patch_entry *pquad;
1567 struct tsb_phys_patch_entry *p;
1568
1569 pquad = &__tsb_ldquad_phys_patch;
1570 while (pquad < &__tsb_ldquad_phys_patch_end) {
1571 unsigned long addr = pquad->addr;
1572
1573 if (tlb_type == hypervisor)
1574 *(unsigned int *) addr = pquad->sun4v_insn;
1575 else
1576 *(unsigned int *) addr = pquad->sun4u_insn;
1577 wmb();
1578 __asm__ __volatile__("flush %0"
1579 : /* no outputs */
1580 : "r" (addr));
1581
1582 pquad++;
1583 }
1584
1585 p = &__tsb_phys_patch;
1586 while (p < &__tsb_phys_patch_end) {
1587 unsigned long addr = p->addr;
1588
1589 *(unsigned int *) addr = p->insn;
1590 wmb();
1591 __asm__ __volatile__("flush %0"
1592 : /* no outputs */
1593 : "r" (addr));
1594
1595 p++;
1596 }
1597 }
1598
1599 /* Don't mark as init, we give this to the Hypervisor. */
1600 #ifndef CONFIG_DEBUG_PAGEALLOC
1601 #define NUM_KTSB_DESCR 2
1602 #else
1603 #define NUM_KTSB_DESCR 1
1604 #endif
1605 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1606 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1607
1608 static void __init sun4v_ktsb_init(void)
1609 {
1610 unsigned long ktsb_pa;
1611
1612 /* First KTSB for PAGE_SIZE mappings. */
1613 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1614
1615 switch (PAGE_SIZE) {
1616 case 8 * 1024:
1617 default:
1618 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1619 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1620 break;
1621
1622 case 64 * 1024:
1623 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1624 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1625 break;
1626
1627 case 512 * 1024:
1628 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1629 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1630 break;
1631
1632 case 4 * 1024 * 1024:
1633 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1634 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1635 break;
1636 };
1637
1638 ktsb_descr[0].assoc = 1;
1639 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1640 ktsb_descr[0].ctx_idx = 0;
1641 ktsb_descr[0].tsb_base = ktsb_pa;
1642 ktsb_descr[0].resv = 0;
1643
1644 #ifndef CONFIG_DEBUG_PAGEALLOC
1645 /* Second KTSB for 4MB/256MB mappings. */
1646 ktsb_pa = (kern_base +
1647 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1648
1649 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1650 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1651 HV_PGSZ_MASK_256MB);
1652 ktsb_descr[1].assoc = 1;
1653 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1654 ktsb_descr[1].ctx_idx = 0;
1655 ktsb_descr[1].tsb_base = ktsb_pa;
1656 ktsb_descr[1].resv = 0;
1657 #endif
1658 }
1659
1660 void __cpuinit sun4v_ktsb_register(void)
1661 {
1662 unsigned long pa, ret;
1663
1664 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1665
1666 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1667 if (ret != 0) {
1668 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1669 "errors with %lx\n", pa, ret);
1670 prom_halt();
1671 }
1672 }
1673
1674 /* paging_init() sets up the page tables */
1675
1676 extern void central_probe(void);
1677
1678 static unsigned long last_valid_pfn;
1679 pgd_t swapper_pg_dir[2048];
1680
1681 static void sun4u_pgprot_init(void);
1682 static void sun4v_pgprot_init(void);
1683
1684 /* Dummy function */
1685 void __init setup_per_cpu_areas(void)
1686 {
1687 }
1688
1689 void __init paging_init(void)
1690 {
1691 unsigned long end_pfn, shift, phys_base;
1692 unsigned long real_end, i;
1693
1694 /* These build time checkes make sure that the dcache_dirty_cpu()
1695 * page->flags usage will work.
1696 *
1697 * When a page gets marked as dcache-dirty, we store the
1698 * cpu number starting at bit 32 in the page->flags. Also,
1699 * functions like clear_dcache_dirty_cpu use the cpu mask
1700 * in 13-bit signed-immediate instruction fields.
1701 */
1702
1703 /*
1704 * Page flags must not reach into upper 32 bits that are used
1705 * for the cpu number
1706 */
1707 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1708
1709 /*
1710 * The bit fields placed in the high range must not reach below
1711 * the 32 bit boundary. Otherwise we cannot place the cpu field
1712 * at the 32 bit boundary.
1713 */
1714 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1715 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1716
1717 BUILD_BUG_ON(NR_CPUS > 4096);
1718
1719 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1720 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1721
1722 sstate_booting();
1723
1724 /* Invalidate both kernel TSBs. */
1725 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1726 #ifndef CONFIG_DEBUG_PAGEALLOC
1727 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1728 #endif
1729
1730 if (tlb_type == hypervisor)
1731 sun4v_pgprot_init();
1732 else
1733 sun4u_pgprot_init();
1734
1735 if (tlb_type == cheetah_plus ||
1736 tlb_type == hypervisor)
1737 tsb_phys_patch();
1738
1739 if (tlb_type == hypervisor) {
1740 sun4v_patch_tlb_handlers();
1741 sun4v_ktsb_init();
1742 }
1743
1744 lmb_init();
1745
1746 /* Find available physical memory... */
1747 read_obp_memory("available", &pavail[0], &pavail_ents);
1748
1749 phys_base = 0xffffffffffffffffUL;
1750 for (i = 0; i < pavail_ents; i++) {
1751 phys_base = min(phys_base, pavail[i].phys_addr);
1752 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1753 }
1754
1755 lmb_reserve(kern_base, kern_size);
1756
1757 find_ramdisk(phys_base);
1758
1759 if (cmdline_memory_size)
1760 lmb_enforce_memory_limit(phys_base + cmdline_memory_size);
1761
1762 lmb_analyze();
1763 lmb_dump_all();
1764
1765 set_bit(0, mmu_context_bmap);
1766
1767 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1768
1769 real_end = (unsigned long)_end;
1770 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1771 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1772 num_kernel_image_mappings);
1773
1774 /* Set kernel pgd to upper alias so physical page computations
1775 * work.
1776 */
1777 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1778
1779 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1780
1781 /* Now can init the kernel/bad page tables. */
1782 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1783 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1784
1785 inherit_prom_mappings();
1786
1787 read_obp_memory("reg", &pall[0], &pall_ents);
1788
1789 init_kpte_bitmap();
1790
1791 /* Ok, we can use our TLB miss and window trap handlers safely. */
1792 setup_tba();
1793
1794 __flush_tlb_all();
1795
1796 if (tlb_type == hypervisor)
1797 sun4v_ktsb_register();
1798
1799 /* We must setup the per-cpu areas before we pull in the
1800 * PROM and the MDESC. The code there fills in cpu and
1801 * other information into per-cpu data structures.
1802 */
1803 real_setup_per_cpu_areas();
1804
1805 prom_build_devicetree();
1806
1807 if (tlb_type == hypervisor)
1808 sun4v_mdesc_init();
1809
1810 /* Setup bootmem... */
1811 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1812
1813 #ifndef CONFIG_NEED_MULTIPLE_NODES
1814 max_mapnr = last_valid_pfn;
1815 #endif
1816 kernel_physical_mapping_init();
1817
1818 {
1819 unsigned long max_zone_pfns[MAX_NR_ZONES];
1820
1821 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1822
1823 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1824
1825 free_area_init_nodes(max_zone_pfns);
1826 }
1827
1828 printk("Booting Linux...\n");
1829
1830 central_probe();
1831 cpu_probe();
1832 }
1833
1834 int __init page_in_phys_avail(unsigned long paddr)
1835 {
1836 int i;
1837
1838 paddr &= PAGE_MASK;
1839
1840 for (i = 0; i < pavail_ents; i++) {
1841 unsigned long start, end;
1842
1843 start = pavail[i].phys_addr;
1844 end = start + pavail[i].reg_size;
1845
1846 if (paddr >= start && paddr < end)
1847 return 1;
1848 }
1849 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1850 return 1;
1851 #ifdef CONFIG_BLK_DEV_INITRD
1852 if (paddr >= __pa(initrd_start) &&
1853 paddr < __pa(PAGE_ALIGN(initrd_end)))
1854 return 1;
1855 #endif
1856
1857 return 0;
1858 }
1859
1860 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1861 static int pavail_rescan_ents __initdata;
1862
1863 /* Certain OBP calls, such as fetching "available" properties, can
1864 * claim physical memory. So, along with initializing the valid
1865 * address bitmap, what we do here is refetch the physical available
1866 * memory list again, and make sure it provides at least as much
1867 * memory as 'pavail' does.
1868 */
1869 static void setup_valid_addr_bitmap_from_pavail(void)
1870 {
1871 int i;
1872
1873 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1874
1875 for (i = 0; i < pavail_ents; i++) {
1876 unsigned long old_start, old_end;
1877
1878 old_start = pavail[i].phys_addr;
1879 old_end = old_start + pavail[i].reg_size;
1880 while (old_start < old_end) {
1881 int n;
1882
1883 for (n = 0; n < pavail_rescan_ents; n++) {
1884 unsigned long new_start, new_end;
1885
1886 new_start = pavail_rescan[n].phys_addr;
1887 new_end = new_start +
1888 pavail_rescan[n].reg_size;
1889
1890 if (new_start <= old_start &&
1891 new_end >= (old_start + PAGE_SIZE)) {
1892 set_bit(old_start >> 22,
1893 sparc64_valid_addr_bitmap);
1894 goto do_next_page;
1895 }
1896 }
1897
1898 prom_printf("mem_init: Lost memory in pavail\n");
1899 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1900 pavail[i].phys_addr,
1901 pavail[i].reg_size);
1902 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1903 pavail_rescan[i].phys_addr,
1904 pavail_rescan[i].reg_size);
1905 prom_printf("mem_init: Cannot continue, aborting.\n");
1906 prom_halt();
1907
1908 do_next_page:
1909 old_start += PAGE_SIZE;
1910 }
1911 }
1912 }
1913
1914 void __init mem_init(void)
1915 {
1916 unsigned long codepages, datapages, initpages;
1917 unsigned long addr, last;
1918 int i;
1919
1920 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1921 i += 1;
1922 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1923 if (sparc64_valid_addr_bitmap == NULL) {
1924 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1925 prom_halt();
1926 }
1927 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1928
1929 addr = PAGE_OFFSET + kern_base;
1930 last = PAGE_ALIGN(kern_size) + addr;
1931 while (addr < last) {
1932 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1933 addr += PAGE_SIZE;
1934 }
1935
1936 setup_valid_addr_bitmap_from_pavail();
1937
1938 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1939
1940 #ifdef CONFIG_NEED_MULTIPLE_NODES
1941 for_each_online_node(i) {
1942 if (NODE_DATA(i)->node_spanned_pages != 0) {
1943 totalram_pages +=
1944 free_all_bootmem_node(NODE_DATA(i));
1945 }
1946 }
1947 #else
1948 totalram_pages = free_all_bootmem();
1949 #endif
1950
1951 /* We subtract one to account for the mem_map_zero page
1952 * allocated below.
1953 */
1954 totalram_pages -= 1;
1955 num_physpages = totalram_pages;
1956
1957 /*
1958 * Set up the zero page, mark it reserved, so that page count
1959 * is not manipulated when freeing the page from user ptes.
1960 */
1961 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1962 if (mem_map_zero == NULL) {
1963 prom_printf("paging_init: Cannot alloc zero page.\n");
1964 prom_halt();
1965 }
1966 SetPageReserved(mem_map_zero);
1967
1968 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1969 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1970 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1971 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1972 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1973 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1974
1975 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1976 nr_free_pages() << (PAGE_SHIFT-10),
1977 codepages << (PAGE_SHIFT-10),
1978 datapages << (PAGE_SHIFT-10),
1979 initpages << (PAGE_SHIFT-10),
1980 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1981
1982 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1983 cheetah_ecache_flush_init();
1984 }
1985
1986 void free_initmem(void)
1987 {
1988 unsigned long addr, initend;
1989
1990 /*
1991 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1992 */
1993 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1994 initend = (unsigned long)(__init_end) & PAGE_MASK;
1995 for (; addr < initend; addr += PAGE_SIZE) {
1996 unsigned long page;
1997 struct page *p;
1998
1999 page = (addr +
2000 ((unsigned long) __va(kern_base)) -
2001 ((unsigned long) KERNBASE));
2002 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2003 p = virt_to_page(page);
2004
2005 ClearPageReserved(p);
2006 init_page_count(p);
2007 __free_page(p);
2008 num_physpages++;
2009 totalram_pages++;
2010 }
2011 }
2012
2013 #ifdef CONFIG_BLK_DEV_INITRD
2014 void free_initrd_mem(unsigned long start, unsigned long end)
2015 {
2016 if (start < end)
2017 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2018 for (; start < end; start += PAGE_SIZE) {
2019 struct page *p = virt_to_page(start);
2020
2021 ClearPageReserved(p);
2022 init_page_count(p);
2023 __free_page(p);
2024 num_physpages++;
2025 totalram_pages++;
2026 }
2027 }
2028 #endif
2029
2030 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2031 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2032 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2033 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2034 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2035 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2036
2037 pgprot_t PAGE_KERNEL __read_mostly;
2038 EXPORT_SYMBOL(PAGE_KERNEL);
2039
2040 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2041 pgprot_t PAGE_COPY __read_mostly;
2042
2043 pgprot_t PAGE_SHARED __read_mostly;
2044 EXPORT_SYMBOL(PAGE_SHARED);
2045
2046 pgprot_t PAGE_EXEC __read_mostly;
2047 unsigned long pg_iobits __read_mostly;
2048
2049 unsigned long _PAGE_IE __read_mostly;
2050 EXPORT_SYMBOL(_PAGE_IE);
2051
2052 unsigned long _PAGE_E __read_mostly;
2053 EXPORT_SYMBOL(_PAGE_E);
2054
2055 unsigned long _PAGE_CACHE __read_mostly;
2056 EXPORT_SYMBOL(_PAGE_CACHE);
2057
2058 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2059
2060 #define VMEMMAP_CHUNK_SHIFT 22
2061 #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
2062 #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
2063 #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2064
2065 #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2066 sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2067 unsigned long vmemmap_table[VMEMMAP_SIZE];
2068
2069 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2070 {
2071 unsigned long vstart = (unsigned long) start;
2072 unsigned long vend = (unsigned long) (start + nr);
2073 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2074 unsigned long phys_end = (vend - VMEMMAP_BASE);
2075 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2076 unsigned long end = VMEMMAP_ALIGN(phys_end);
2077 unsigned long pte_base;
2078
2079 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2080 _PAGE_CP_4U | _PAGE_CV_4U |
2081 _PAGE_P_4U | _PAGE_W_4U);
2082 if (tlb_type == hypervisor)
2083 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2084 _PAGE_CP_4V | _PAGE_CV_4V |
2085 _PAGE_P_4V | _PAGE_W_4V);
2086
2087 for (; addr < end; addr += VMEMMAP_CHUNK) {
2088 unsigned long *vmem_pp =
2089 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2090 void *block;
2091
2092 if (!(*vmem_pp & _PAGE_VALID)) {
2093 block = vmemmap_alloc_block(1UL << 22, node);
2094 if (!block)
2095 return -ENOMEM;
2096
2097 *vmem_pp = pte_base | __pa(block);
2098
2099 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2100 "node=%d entry=%lu/%lu\n", start, block, nr,
2101 node,
2102 addr >> VMEMMAP_CHUNK_SHIFT,
2103 VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2104 }
2105 }
2106 return 0;
2107 }
2108 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2109
2110 static void prot_init_common(unsigned long page_none,
2111 unsigned long page_shared,
2112 unsigned long page_copy,
2113 unsigned long page_readonly,
2114 unsigned long page_exec_bit)
2115 {
2116 PAGE_COPY = __pgprot(page_copy);
2117 PAGE_SHARED = __pgprot(page_shared);
2118
2119 protection_map[0x0] = __pgprot(page_none);
2120 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2121 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2122 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2123 protection_map[0x4] = __pgprot(page_readonly);
2124 protection_map[0x5] = __pgprot(page_readonly);
2125 protection_map[0x6] = __pgprot(page_copy);
2126 protection_map[0x7] = __pgprot(page_copy);
2127 protection_map[0x8] = __pgprot(page_none);
2128 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2129 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2130 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2131 protection_map[0xc] = __pgprot(page_readonly);
2132 protection_map[0xd] = __pgprot(page_readonly);
2133 protection_map[0xe] = __pgprot(page_shared);
2134 protection_map[0xf] = __pgprot(page_shared);
2135 }
2136
2137 static void __init sun4u_pgprot_init(void)
2138 {
2139 unsigned long page_none, page_shared, page_copy, page_readonly;
2140 unsigned long page_exec_bit;
2141
2142 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2143 _PAGE_CACHE_4U | _PAGE_P_4U |
2144 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2145 _PAGE_EXEC_4U);
2146 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2147 _PAGE_CACHE_4U | _PAGE_P_4U |
2148 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2149 _PAGE_EXEC_4U | _PAGE_L_4U);
2150 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
2151
2152 _PAGE_IE = _PAGE_IE_4U;
2153 _PAGE_E = _PAGE_E_4U;
2154 _PAGE_CACHE = _PAGE_CACHE_4U;
2155
2156 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2157 __ACCESS_BITS_4U | _PAGE_E_4U);
2158
2159 #ifdef CONFIG_DEBUG_PAGEALLOC
2160 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2161 0xfffff80000000000;
2162 #else
2163 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2164 0xfffff80000000000;
2165 #endif
2166 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2167 _PAGE_P_4U | _PAGE_W_4U);
2168
2169 /* XXX Should use 256MB on Panther. XXX */
2170 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2171
2172 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2173 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2174 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2175 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2176
2177
2178 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2179 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2180 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2181 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2182 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2183 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2184 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2185
2186 page_exec_bit = _PAGE_EXEC_4U;
2187
2188 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2189 page_exec_bit);
2190 }
2191
2192 static void __init sun4v_pgprot_init(void)
2193 {
2194 unsigned long page_none, page_shared, page_copy, page_readonly;
2195 unsigned long page_exec_bit;
2196
2197 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2198 _PAGE_CACHE_4V | _PAGE_P_4V |
2199 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2200 _PAGE_EXEC_4V);
2201 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2202 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
2203
2204 _PAGE_IE = _PAGE_IE_4V;
2205 _PAGE_E = _PAGE_E_4V;
2206 _PAGE_CACHE = _PAGE_CACHE_4V;
2207
2208 #ifdef CONFIG_DEBUG_PAGEALLOC
2209 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2210 0xfffff80000000000;
2211 #else
2212 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2213 0xfffff80000000000;
2214 #endif
2215 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2216 _PAGE_P_4V | _PAGE_W_4V);
2217
2218 #ifdef CONFIG_DEBUG_PAGEALLOC
2219 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2220 0xfffff80000000000;
2221 #else
2222 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2223 0xfffff80000000000;
2224 #endif
2225 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2226 _PAGE_P_4V | _PAGE_W_4V);
2227
2228 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2229 __ACCESS_BITS_4V | _PAGE_E_4V);
2230
2231 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2232 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2233 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2234 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2235 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2236
2237 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2238 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2239 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2240 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2241 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2242 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2243 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2244
2245 page_exec_bit = _PAGE_EXEC_4V;
2246
2247 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2248 page_exec_bit);
2249 }
2250
2251 unsigned long pte_sz_bits(unsigned long sz)
2252 {
2253 if (tlb_type == hypervisor) {
2254 switch (sz) {
2255 case 8 * 1024:
2256 default:
2257 return _PAGE_SZ8K_4V;
2258 case 64 * 1024:
2259 return _PAGE_SZ64K_4V;
2260 case 512 * 1024:
2261 return _PAGE_SZ512K_4V;
2262 case 4 * 1024 * 1024:
2263 return _PAGE_SZ4MB_4V;
2264 };
2265 } else {
2266 switch (sz) {
2267 case 8 * 1024:
2268 default:
2269 return _PAGE_SZ8K_4U;
2270 case 64 * 1024:
2271 return _PAGE_SZ64K_4U;
2272 case 512 * 1024:
2273 return _PAGE_SZ512K_4U;
2274 case 4 * 1024 * 1024:
2275 return _PAGE_SZ4MB_4U;
2276 };
2277 }
2278 }
2279
2280 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2281 {
2282 pte_t pte;
2283
2284 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2285 pte_val(pte) |= (((unsigned long)space) << 32);
2286 pte_val(pte) |= pte_sz_bits(page_size);
2287
2288 return pte;
2289 }
2290
2291 static unsigned long kern_large_tte(unsigned long paddr)
2292 {
2293 unsigned long val;
2294
2295 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2296 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2297 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2298 if (tlb_type == hypervisor)
2299 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2300 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2301 _PAGE_EXEC_4V | _PAGE_W_4V);
2302
2303 return val | paddr;
2304 }
2305
2306 /* If not locked, zap it. */
2307 void __flush_tlb_all(void)
2308 {
2309 unsigned long pstate;
2310 int i;
2311
2312 __asm__ __volatile__("flushw\n\t"
2313 "rdpr %%pstate, %0\n\t"
2314 "wrpr %0, %1, %%pstate"
2315 : "=r" (pstate)
2316 : "i" (PSTATE_IE));
2317 if (tlb_type == hypervisor) {
2318 sun4v_mmu_demap_all();
2319 } else if (tlb_type == spitfire) {
2320 for (i = 0; i < 64; i++) {
2321 /* Spitfire Errata #32 workaround */
2322 /* NOTE: Always runs on spitfire, so no
2323 * cheetah+ page size encodings.
2324 */
2325 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2326 "flush %%g6"
2327 : /* No outputs */
2328 : "r" (0),
2329 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2330
2331 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2332 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2333 "membar #Sync"
2334 : /* no outputs */
2335 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2336 spitfire_put_dtlb_data(i, 0x0UL);
2337 }
2338
2339 /* Spitfire Errata #32 workaround */
2340 /* NOTE: Always runs on spitfire, so no
2341 * cheetah+ page size encodings.
2342 */
2343 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2344 "flush %%g6"
2345 : /* No outputs */
2346 : "r" (0),
2347 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2348
2349 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2350 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2351 "membar #Sync"
2352 : /* no outputs */
2353 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2354 spitfire_put_itlb_data(i, 0x0UL);
2355 }
2356 }
2357 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2358 cheetah_flush_dtlb_all();
2359 cheetah_flush_itlb_all();
2360 }
2361 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2362 : : "r" (pstate));
2363 }
2364
2365 #ifdef CONFIG_MEMORY_HOTPLUG
2366
2367 void online_page(struct page *page)
2368 {
2369 ClearPageReserved(page);
2370 init_page_count(page);
2371 __free_page(page);
2372 totalram_pages++;
2373 num_physpages++;
2374 }
2375
2376 #endif /* CONFIG_MEMORY_HOTPLUG */
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