2 * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
4 * Author: Mark A. Greerinclude/asm-ppc/hawk.h
7 * Modified by Randy Vinson (rvinson@mvista.com)
9 * 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
21 * Due to limitations imposed by legacy hardware (primarily IDE controllers),
22 * the PPLUS boards operate using a PReP address map.
24 * From Processor (physical) -> PCI:
25 * PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
26 * PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
27 * Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
29 * From PCI -> Processor (physical):
30 * System Memory: 0x80000000 -> 0x00000000
33 #define PPLUS_ISA_MEM_BASE PREP_ISA_MEM_BASE
34 #define PPLUS_ISA_IO_BASE PREP_ISA_IO_BASE
36 /* PCI Memory space mapping info */
37 #define PPLUS_PCI_MEM_SIZE 0x30000000U
38 #define PPLUS_PROC_PCI_MEM_START PPLUS_ISA_MEM_BASE
39 #define PPLUS_PROC_PCI_MEM_END (PPLUS_PROC_PCI_MEM_START + \
40 PPLUS_PCI_MEM_SIZE - 1)
41 #define PPLUS_PCI_MEM_START 0x00000000U
42 #define PPLUS_PCI_MEM_END (PPLUS_PCI_MEM_START + \
43 PPLUS_PCI_MEM_SIZE - 1)
45 /* PCI I/O space mapping info */
46 #define PPLUS_PCI_IO_SIZE 0x10000000U
47 #define PPLUS_PROC_PCI_IO_START PPLUS_ISA_IO_BASE
48 #define PPLUS_PROC_PCI_IO_END (PPLUS_PROC_PCI_IO_START + \
49 PPLUS_PCI_IO_SIZE - 1)
50 #define PPLUS_PCI_IO_START 0x00000000U
51 #define PPLUS_PCI_IO_END (PPLUS_PCI_IO_START + \
52 PPLUS_PCI_IO_SIZE - 1)
53 /* System memory mapping info */
54 #define PPLUS_PCI_DRAM_OFFSET PREP_PCI_DRAM_OFFSET
55 #define PPLUS_PCI_PHY_MEM_OFFSET (PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
57 /* Define base addresses for important sets of registers */
58 #define PPLUS_HAWK_SMC_BASE 0xfef80000U
59 #define PPLUS_HAWK_PPC_REG_BASE 0xfeff0000U
60 #define PPLUS_SYS_CONFIG_REG 0xfef80400U
61 #define PPLUS_L2_CONTROL_REG 0x8000081cU
63 #define PPLUS_VGA_MEM_BASE 0xf0000000U
65 #endif /* __PPC_PPLUS_H */