drivers/staging/gma500/mdfld_dsi_dbi.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  * jim liu <jim.liu@intel.com>
  25  * Jackie Li<yaodong.li@intel.com>
  26  */
  27
  28 #ifndef __MDFLD_DSI_DBI_H__
  29 #define __MDFLD_DSI_DBI_H__
  30
  31 #include <linux/backlight.h>
  32 #include <linux/version.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37
  38 #include "psb_drv.h"
  39 #include "psb_intel_drv.h"
  40 #include "psb_intel_reg.h"
  41 #include "power.h"
  42
  43 #include "mdfld_dsi_output.h"
  44 #include "mdfld_output.h"
  45
  46 #define DRM_MODE_ENCODER_MIPI  5
  47
  48
  49 /*
  50  * DBI encoder which inherits from mdfld_dsi_encoder
  51  */
  52 struct mdfld_dsi_dbi_output {
  53         struct mdfld_dsi_encoder base;
  54         struct drm_display_mode *panel_fixed_mode;
  55         u8 last_cmd;
  56         u8 lane_count;
  57         u8 channel_num;
  58         struct drm_device *dev;
  59
  60         /* Backlight operations */
  61
  62         /* DSR timer */
  63         spinlock_t dsr_timer_lock;
  64         struct timer_list dsr_timer;
  65         void(*dsi_timer_func)(unsigned long data);
  66         u32 dsr_idle_count;
  67         bool dsr_fb_update_done;
  68
  69         /* Mode setting flags */
  70         u32 mode_flags;
  71
  72         /* Panel status */
  73         bool dbi_panel_on;
  74         bool first_boot;
  75         struct panel_funcs *p_funcs;
  76 };
  77
  78 #define MDFLD_DSI_DBI_OUTPUT(dsi_encoder) \
  79         container_of(dsi_encoder, struct mdfld_dsi_dbi_output, base)
  80
  81 struct mdfld_dbi_dsr_info {
  82         int dbi_output_num;
  83         struct mdfld_dsi_dbi_output *dbi_outputs[2];
  84
  85         spinlock_t dsr_timer_lock;
  86         struct timer_list dsr_timer;
  87         u32 dsr_idle_count;
  88 };
  89
  90 #define DBI_CB_TIMEOUT_COUNT    0xffff
  91
  92 /* DCS commands */
  93 #define enter_sleep_mode        0x10
  94 #define exit_sleep_mode         0x11
  95 #define set_display_off         0x28
  96 #define set_dispaly_on          0x29
  97 #define set_column_address      0x2a
  98 #define set_page_addr           0x2b
  99 #define write_mem_start         0x2c
 100
 101 /* Offsets */
 102 #define CMD_MEM_ADDR_OFFSET     0
 103
 104 #define CMD_DATA_SRC_SYSTEM_MEM 0
 105 #define CMD_DATA_SRC_PIPE       1
 106
 107 static inline int mdfld_dsi_dbi_fifo_ready(struct mdfld_dsi_dbi_output *dbi_output)
 108 {
 109         struct drm_device *dev = dbi_output->dev;
 110         u32 retry = DBI_CB_TIMEOUT_COUNT;
 111         int reg_offset = (dbi_output->channel_num == 1) ? MIPIC_REG_OFFSET : 0;
 112         int ret = 0;
 113
 114         /* Query the dbi fifo status*/
 115         while (retry--) {
 116                 if (REG_READ(MIPIA_GEN_FIFO_STAT_REG + reg_offset) & (1 << 27))
 117                         break;
 118         }
 119
 120         if (!retry) {
 121                 DRM_ERROR("Timeout waiting for DBI FIFO empty\n");
 122                 ret = -EAGAIN;
 123         }
 124         return ret;
 125 }
 126
 127 static inline int mdfld_dsi_dbi_cmd_sent(struct mdfld_dsi_dbi_output *dbi_output)
 128 {
 129         struct drm_device *dev = dbi_output->dev;
 130         u32 retry = DBI_CB_TIMEOUT_COUNT;
 131         int reg_offset = (dbi_output->channel_num == 1) ? MIPIC_REG_OFFSET : 0;
 132         int ret = 0;
 133
 134         /* Query the command execution status */
 135         while (retry--)
 136                 if (!(REG_READ(MIPIA_CMD_ADD_REG + reg_offset) & (1 << 10)))
 137                         break;
 138
 139         if (!retry) {
 140                 DRM_ERROR("Timeout waiting for DBI command status\n");
 141                 ret = -EAGAIN;
 142         }
 143
 144         return ret;
 145 }
 146
 147 static inline int mdfld_dsi_dbi_cb_ready(struct mdfld_dsi_dbi_output *dbi_output)
 148 {
 149         int ret = 0;
 150
 151         /* Query the command execution status*/
 152         ret = mdfld_dsi_dbi_cmd_sent(dbi_output);
 153         if (ret) {
 154                 DRM_ERROR("Peripheral is busy\n");
 155                 ret = -EAGAIN;
 156         }
 157         /* Query the dbi fifo status*/
 158         ret = mdfld_dsi_dbi_fifo_ready(dbi_output);
 159         if (ret) {
 160                 DRM_ERROR("DBI FIFO is not empty\n");
 161                 ret = -EAGAIN;
 162         }
 163         return ret;
 164 }
 165
 166 extern void mdfld_dsi_dbi_output_init(struct drm_device *dev,
 167                         struct psb_intel_mode_device *mode_dev, int pipe);
 168 extern void mdfld_dsi_dbi_exit_dsr(struct drm_device *dev, u32 update_src,
 169                         void *p_surfaceAddr, bool check_hw_on_only);
 170 extern void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output *dbi_output,
 171                         int pipe);
 172 extern int mdfld_dbi_dsr_init(struct drm_device *dev);
 173 extern void mdfld_dbi_dsr_exit(struct drm_device *dev);
 174 extern void mdfld_dbi_dsr_timer_start(struct mdfld_dbi_dsr_info *dsr_info);
 175 extern struct mdfld_dsi_encoder *mdfld_dsi_dbi_init(struct drm_device *dev,
 176                         struct mdfld_dsi_connector *dsi_connector,
 177                         struct panel_funcs *p_funcs);
 178 extern int mdfld_dsi_dbi_send_dcs(struct mdfld_dsi_dbi_output *dbi_output,
 179                         u8 dcs, u8 *param, u32 num, u8 data_src);
 180 extern int mdfld_dsi_dbi_update_area(struct mdfld_dsi_dbi_output *dbi_output,
 181                         u16 x1, u16 y1, u16 x2, u16 y2);
 182 extern void mdfld_dbi_dsr_timer_start(struct mdfld_dbi_dsr_info *dsr_info);
 183 extern int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output *dbi_output,
 184                         int mode);
 185 extern void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config *dsi_config,
 186                         int pipe);
 187
 188 #endif /*__MDFLD_DSI_DBI_H__*/