2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * jim liu <jim.liu@intel.com>
25 * Jackie Li<yaodong.li@intel.com>
28 #include "mdfld_dsi_dbi.h"
29 #include "mdfld_dsi_dbi_dpu.h"
30 #include "mdfld_dsi_pkg_sender.h"
33 #include <linux/pm_runtime.h>
37 extern struct drm_device
*gpDrmDevice
;
38 extern int gfxrtdelay
;
40 struct mdfld_dsi_dbi_output
*gdbi_output
;
41 extern bool gbgfxsuspended
;
42 extern int gfxrtdelay
;
44 #ifdef CONFIG_GFX_RTPM
45 static void psb_runtimepm_wq_handler(struct work_struct
*work
);
46 DECLARE_DELAYED_WORK(rtpm_work
, psb_runtimepm_wq_handler
);
48 void psb_runtimepm_wq_handler(struct work_struct
*work
)
50 struct drm_psb_private
*dev_priv
= gpDrmDevice
->dev_private
;
52 if (drm_psb_ospm
&& !enable_gfx_rtpm
) {
53 pr_info("Enable GFX runtime_pm\n");
54 dev_priv
->rpm_enabled
= 1;
57 pm_runtime_enable(&gpDrmDevice
->pdev
->dev
);
58 pm_runtime_set_active(&gpDrmDevice
->pdev
->dev
);
60 pm_runtime_allow(&gpDrmDevice
->pdev
->dev
);
69 int mdfld_dsi_dbi_update_area(struct mdfld_dsi_dbi_output
*dbi_output
,
70 u16 x1
, u16 y1
, u16 x2
, u16 y2
)
72 struct mdfld_dsi_pkg_sender
*sender
=
73 mdfld_dsi_encoder_get_pkg_sender(&dbi_output
->base
);
84 cmd
= set_column_address
;
90 err
= mdfld_dsi_send_dcs(sender
,
94 CMD_DATA_SRC_SYSTEM_MEM
,
95 MDFLD_DSI_QUEUE_PACKAGE
);
97 dev_err(sender
->dev
->dev
, "DCS 0x%x sent failed\n", cmd
);
108 err
= mdfld_dsi_send_dcs(sender
,
112 CMD_DATA_SRC_SYSTEM_MEM
,
113 MDFLD_DSI_QUEUE_PACKAGE
);
115 dev_err(sender
->dev
->dev
, "DCS 0x%x sent failed\n", cmd
);
120 err
= mdfld_dsi_send_dcs(sender
,
125 MDFLD_DSI_QUEUE_PACKAGE
);
127 dev_err(sender
->dev
->dev
, "DCS 0x%x sent failed\n", cmd
);
130 mdfld_dsi_cmds_kick_out(sender
);
136 * set panel's power state
138 int mdfld_dsi_dbi_update_power(struct mdfld_dsi_dbi_output
*dbi_output
,
141 struct drm_device
*dev
= dbi_output
->dev
;
142 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
143 struct mdfld_dsi_pkg_sender
*sender
=
144 mdfld_dsi_encoder_get_pkg_sender(&dbi_output
->base
);
148 if (!dev_priv
->dispstatus
&& mode
!= DRM_MODE_DPMS_ON
) {
149 dev_err(dev
->dev
, "%s: already OFF ignoring\n", __func__
);
152 if (dev_priv
->dispstatus
&& mode
== DRM_MODE_DPMS_ON
) {
153 dev_err(dev
->dev
, "%s: already ON ignoring\n", __func__
);
162 if (mode
== DRM_MODE_DPMS_ON
) {
164 err
= mdfld_dsi_send_dcs(sender
,
168 CMD_DATA_SRC_SYSTEM_MEM
,
169 MDFLD_DSI_QUEUE_PACKAGE
);
171 dev_err(dev
->dev
, "DCS 0x%x sent failed\n",
177 err
= mdfld_dsi_send_dcs(sender
,
181 CMD_DATA_SRC_SYSTEM_MEM
,
182 MDFLD_DSI_QUEUE_PACKAGE
);
184 dev_err(dev
->dev
, "DCS 0x%x sent failed\n",
189 /* set tear effect on */
190 err
= mdfld_dsi_send_dcs(sender
,
194 CMD_DATA_SRC_SYSTEM_MEM
,
195 MDFLD_DSI_QUEUE_PACKAGE
);
197 dev_err(dev
->dev
, "DCS 0x%x sent failed\n",
203 * FIXME: remove this later
205 err
= mdfld_dsi_send_dcs(sender
,
210 MDFLD_DSI_QUEUE_PACKAGE
);
212 dev_err(dev
->dev
, "DCS 0x%x sent failed\n",
217 /*set tear effect off */
218 err
= mdfld_dsi_send_dcs(sender
,
222 CMD_DATA_SRC_SYSTEM_MEM
,
223 MDFLD_DSI_QUEUE_PACKAGE
);
225 dev_err(dev
->dev
, "DCS 0x%x sent failed\n",
231 err
= mdfld_dsi_send_dcs(sender
,
235 CMD_DATA_SRC_SYSTEM_MEM
,
236 MDFLD_DSI_QUEUE_PACKAGE
);
238 dev_err(dev
->dev
, "DCS 0x%x sent failed\n",
244 err
= mdfld_dsi_send_dcs(sender
,
248 CMD_DATA_SRC_SYSTEM_MEM
,
249 MDFLD_DSI_QUEUE_PACKAGE
);
251 dev_err(dev
->dev
, "DCS 0x%x sent failed\n",
256 mdfld_dsi_cmds_kick_out(sender
);
262 * send a generic DCS command with a parameter list
264 int mdfld_dsi_dbi_send_dcs(struct mdfld_dsi_dbi_output
*dbi_output
,
265 u8 dcs
, u8
*param
, u32 num
, u8 data_src
)
267 struct mdfld_dsi_pkg_sender
*sender
=
268 mdfld_dsi_encoder_get_pkg_sender(&dbi_output
->base
);
276 ret
= mdfld_dsi_send_dcs(sender
,
281 MDFLD_DSI_SEND_PACKAGE
);
290 void mdfld_dsi_dbi_enter_dsr(struct mdfld_dsi_dbi_output
*dbi_output
, int pipe
)
293 struct drm_device
*dev
= dbi_output
->dev
;
294 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
295 struct drm_crtc
*crtc
= dbi_output
->base
.base
.crtc
;
296 struct psb_intel_crtc
*psb_crtc
= (crtc
) ?
297 to_psb_intel_crtc(crtc
) : NULL
;
298 u32 dpll_reg
= MRST_DPLL_A
;
299 u32 pipeconf_reg
= PIPEACONF
;
300 u32 dspcntr_reg
= DSPACNTR
;
302 dev_priv
->is_in_idle
= true;
307 gdbi_output
= dbi_output
;
308 if ((dbi_output
->mode_flags
& MODE_SETTING_ON_GOING
) ||
309 (psb_crtc
&& psb_crtc
->mode_flags
& MODE_SETTING_ON_GOING
))
313 dpll_reg
= MRST_DPLL_A
;
314 pipeconf_reg
= PIPECCONF
;
315 dspcntr_reg
= DSPCCNTR
;
318 if (!gma_power_begin(dev
, true)) {
319 dev_err(dev
->dev
, "hw begin failed\n");
322 /*disable te interrupts. */
323 mdfld_disable_te(dev
, pipe
);
326 reg_val
= REG_READ(dspcntr_reg
);
327 if (!(reg_val
& DISPLAY_PLANE_ENABLE
)) {
328 REG_WRITE(dspcntr_reg
, reg_val
& ~DISPLAY_PLANE_ENABLE
);
329 REG_READ(dspcntr_reg
);
332 reg_val
= REG_READ(pipeconf_reg
);
333 if (!(reg_val
& DISPLAY_PLANE_ENABLE
)) {
334 reg_val
&= ~DISPLAY_PLANE_ENABLE
;
335 reg_val
|= (PIPECONF_PLANE_OFF
| PIPECONF_CURSOR_OFF
);
336 REG_WRITE(pipeconf_reg
, reg_val
);
337 REG_READ(pipeconf_reg
);
338 mdfldWaitForPipeDisable(dev
, pipe
);
342 reg_val
= REG_READ(dpll_reg
);
343 if (!(reg_val
& DPLL_VCO_ENABLE
)) {
344 reg_val
&= ~DPLL_VCO_ENABLE
;
345 REG_WRITE(dpll_reg
, reg_val
);
351 dbi_output
->mode_flags
|= MODE_SETTING_IN_DSR
;
354 /* pm_schedule_suspend(&dev->pdev->dev, gfxrtdelay); */
358 #ifndef CONFIG_MDFLD_DSI_DPU
359 static void mdfld_dbi_output_exit_dsr(struct mdfld_dsi_dbi_output
*dbi_output
,
360 int pipe
, void *p_surfaceAddr
, bool check_hw_on_only
)
362 struct drm_device
*dev
= dbi_output
->dev
;
363 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
364 struct drm_crtc
*crtc
= dbi_output
->base
.base
.crtc
;
365 struct psb_intel_crtc
*psb_crtc
= (crtc
) ?
366 to_psb_intel_crtc(crtc
) : NULL
;
368 u32 dpll_reg
= MRST_DPLL_A
;
369 u32 pipeconf_reg
= PIPEACONF
;
370 u32 dspcntr_reg
= DSPACNTR
;
371 u32 dspsurf_reg
= DSPASURF
;
374 /*if mode setting on-going, back off*/
375 if ((dbi_output
->mode_flags
& MODE_SETTING_ON_GOING
) ||
376 (psb_crtc
&& psb_crtc
->mode_flags
& MODE_SETTING_ON_GOING
))
380 dpll_reg
= MRST_DPLL_A
;
381 pipeconf_reg
= PIPECCONF
;
382 dspcntr_reg
= DSPCCNTR
;
383 dspsurf_reg
= DSPCSURF
;
384 reg_offset
= MIPIC_REG_OFFSET
;
387 if (check_hw_on_only
) {
388 if (0/* FIXME!ospm_power_is_hw_on(_DISPLAY_ISLAND)*/) {
389 dev_err(dev
->dev
, "hw begin failed\n");
392 } else if (!gma_power_begin(dev
, true)) {
393 dev_err(dev
->dev
, "hw begin failed\n");
398 reg_val
= REG_READ(dpll_reg
);
399 if (!(reg_val
& DPLL_VCO_ENABLE
)) {
401 if (reg_val
& MDFLD_PWR_GATE_EN
) {
402 reg_val
&= ~MDFLD_PWR_GATE_EN
;
403 REG_WRITE(dpll_reg
, reg_val
);
408 reg_val
|= DPLL_VCO_ENABLE
;
409 REG_WRITE(dpll_reg
, reg_val
);
414 while (!(REG_READ(pipeconf_reg
) & PIPECONF_DSIPLL_LOCK
))
419 reg_val
= REG_READ(pipeconf_reg
);
420 if (!(reg_val
& PIPEACONF_ENABLE
)) {
421 reg_val
|= PIPEACONF_ENABLE
;
422 REG_WRITE(pipeconf_reg
, reg_val
);
423 REG_READ(pipeconf_reg
);
425 mdfldWaitForPipeEnable(dev
, pipe
);
429 reg_val
= REG_READ(dspcntr_reg
);
430 if (!(reg_val
& DISPLAY_PLANE_ENABLE
)) {
431 reg_val
|= DISPLAY_PLANE_ENABLE
;
432 REG_WRITE(dspcntr_reg
, reg_val
);
433 REG_READ(dspcntr_reg
);
437 /* update the surface base address. */
439 REG_WRITE(dspsurf_reg
, *((u32
*)p_surfaceAddr
));
441 if (!check_hw_on_only
)
444 /*enable TE interrupt on this pipe*/
445 mdfld_enable_te(dev
, pipe
);
447 /*clean IN_DSR flag*/
448 dbi_output
->mode_flags
&= ~MODE_SETTING_IN_DSR
;
454 void mdfld_dsi_dbi_exit_dsr(struct drm_device
*dev
, u32 update_src
,
455 void *p_surfaceAddr
, bool check_hw_on_only
)
457 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
458 struct mdfld_dbi_dsr_info
*dsr_info
= dev_priv
->dbi_dsr_info
;
459 struct mdfld_dsi_dbi_output
**dbi_output
;
462 dev_priv
->is_in_idle
= false;
463 dbi_output
= dsr_info
->dbi_outputs
;
465 #ifdef CONFIG_PM_RUNTIME
466 if (!enable_gfx_rtpm
) {
467 /* pm_runtime_allow(&gpDrmDevice->pdev->dev); */
468 /* schedule_delayed_work(&rtpm_work, 120 * 1000); */
472 /*for each output, exit dsr*/
473 for (i
= 0; i
< dsr_info
->dbi_output_num
; i
++) {
474 /*if panel has been turned off, skip*/
475 if (!dbi_output
[i
]->dbi_panel_on
)
477 if (dbi_output
[i
]->mode_flags
& MODE_SETTING_IN_DSR
) {
479 mdfld_dbi_output_exit_dsr(dbi_output
[i
], dbi_output
[i
]->channel_num
? 2 : 0, p_surfaceAddr
, check_hw_on_only
);
482 dev_priv
->dsr_fb_update
|= update_src
;
485 static bool mdfld_dbi_is_in_dsr(struct drm_device
*dev
)
487 if (REG_READ(MRST_DPLL_A
) & DPLL_VCO_ENABLE
)
489 if ((REG_READ(PIPEACONF
) & PIPEACONF_ENABLE
) ||
490 (REG_READ(PIPECCONF
) & PIPEACONF_ENABLE
))
492 if ((REG_READ(DSPACNTR
) & DISPLAY_PLANE_ENABLE
) ||
493 (REG_READ(DSPCCNTR
) & DISPLAY_PLANE_ENABLE
))
499 /* Perodically update dbi panel */
500 void mdfld_dbi_update_panel(struct drm_device
*dev
, int pipe
)
502 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
503 struct mdfld_dbi_dsr_info
*dsr_info
= dev_priv
->dbi_dsr_info
;
504 struct mdfld_dsi_dbi_output
**dbi_outputs
;
505 struct mdfld_dsi_dbi_output
*dbi_output
;
510 dbi_outputs
= dsr_info
->dbi_outputs
;
511 dbi_output
= pipe
? dbi_outputs
[1] : dbi_outputs
[0];
517 damage_mask
= dev_priv
->dsr_fb_update
& (MDFLD_DSR_DAMAGE_MASK_0
);
519 damage_mask
= dev_priv
->dsr_fb_update
& (MDFLD_DSR_DAMAGE_MASK_2
);
523 /*if FB is damaged and panel is on update on-panel FB*/
524 if (damage_mask
&& dbi_output
->dbi_panel_on
) {
525 dbi_output
->dsr_fb_update_done
= false;
527 if (dbi_output
->p_funcs
->update_fb
)
528 dbi_output
->p_funcs
->update_fb(dbi_output
, pipe
);
530 if (dev_priv
->dsr_enable
&& dbi_output
->dsr_fb_update_done
)
531 dev_priv
->dsr_fb_update
&= ~damage_mask
;
533 /*clean IN_DSR flag*/
534 dbi_output
->mode_flags
&= ~MODE_SETTING_IN_DSR
;
536 dbi_output
->dsr_idle_count
= 0;
538 dbi_output
->dsr_idle_count
++;
542 if (dbi_outputs
[0]->dsr_idle_count
> 1
543 && dbi_outputs
[1]->dsr_idle_count
> 1) {
544 for (i
= 0; i
< dsr_info
->dbi_output_num
; i
++) {
545 if (!mdfld_dbi_is_in_dsr(dev
) &&
546 !(dbi_outputs
[i
]->mode_flags
& MODE_SETTING_ON_GOING
)) {
547 mdfld_dsi_dbi_enter_dsr(dbi_outputs
[i
],
548 dbi_outputs
[i
]->channel_num
? 2 : 0);
551 pr_err("%s: enter_dsr = 1\n", __func__
);
555 /*schedule rpm suspend after gfxrtdelay*/
556 #ifdef CONFIG_GFX_RTPM
557 if (!dev_priv
->rpm_enabled
559 /* || (REG_READ(HDMIB_CONTROL) & HDMIB_PORT_EN) */
560 || pm_schedule_suspend(&dev
->pdev
->dev
, gfxrtdelay
))
562 "Runtime PM schedule suspend failed, rpm %d\n",
563 dev_priv
->rpm_enabled
);
569 static void mdfld_dsi_dbi_dsr_timer_func(unsigned long data
)
571 struct drm_device
*dev
= (struct drm_device
*)data
;
572 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
573 struct mdfld_dbi_dsr_info
*dsr_info
= dev_priv
->dbi_dsr_info
;
574 struct timer_list
*dsr_timer
= &dsr_info
->dsr_timer
;
577 mdfld_dbi_update_panel(dev
, 0);
579 if (dsr_info
->dsr_idle_count
> 1)
582 spin_lock_irqsave(&dsr_info
->dsr_timer_lock
, flags
);
583 if (!timer_pending(dsr_timer
)) {
584 dsr_timer
->expires
= jiffies
+ MDFLD_DSR_DELAY
;
585 add_timer(dsr_timer
);
587 spin_unlock_irqrestore(&dsr_info
->dsr_timer_lock
, flags
);
590 static int mdfld_dsi_dbi_dsr_timer_init(struct drm_device
*dev
)
592 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
593 struct mdfld_dbi_dsr_info
*dsr_info
= dev_priv
->dbi_dsr_info
;
594 struct timer_list
*dsr_timer
= &dsr_info
->dsr_timer
;
597 spin_lock_init(&dsr_info
->dsr_timer_lock
);
598 spin_lock_irqsave(&dsr_info
->dsr_timer_lock
, flags
);
600 init_timer(dsr_timer
);
602 dsr_timer
->data
= (unsigned long)dev
;
603 dsr_timer
->function
= mdfld_dsi_dbi_dsr_timer_func
;
604 dsr_timer
->expires
= jiffies
+ MDFLD_DSR_DELAY
;
606 spin_unlock_irqrestore(&dsr_info
->dsr_timer_lock
, flags
);
610 void mdfld_dbi_dsr_timer_start(struct mdfld_dbi_dsr_info
*dsr_info
)
612 struct timer_list
*dsr_timer
= &dsr_info
->dsr_timer
;
615 spin_lock_irqsave(&dsr_info
->dsr_timer_lock
, flags
);
616 if (!timer_pending(dsr_timer
)) {
617 dsr_timer
->expires
= jiffies
+ MDFLD_DSR_DELAY
;
618 add_timer(dsr_timer
);
620 spin_unlock_irqrestore(&dsr_info
->dsr_timer_lock
, flags
);
623 int mdfld_dbi_dsr_init(struct drm_device
*dev
)
625 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
626 struct mdfld_dbi_dsr_info
*dsr_info
= dev_priv
->dbi_dsr_info
;
628 if (!dsr_info
|| IS_ERR(dsr_info
)) {
629 dsr_info
= kzalloc(sizeof(struct mdfld_dbi_dsr_info
),
632 dev_err(dev
->dev
, "No memory\n");
635 dev_priv
->dbi_dsr_info
= dsr_info
;
640 void mdfld_dbi_dsr_exit(struct drm_device
*dev
)
642 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
643 struct mdfld_dbi_dsr_info
*dsr_info
= dev_priv
->dbi_dsr_info
;
646 del_timer_sync(&dsr_info
->dsr_timer
);
648 dev_priv
->dbi_dsr_info
= NULL
;
653 void mdfld_dsi_controller_dbi_init(struct mdfld_dsi_config
*dsi_config
,
656 struct drm_device
*dev
= dsi_config
->dev
;
657 u32 reg_offset
= pipe
? MIPIC_REG_OFFSET
: 0;
658 int lane_count
= dsi_config
->lane_count
;
661 dev_dbg(dev
->dev
, "Init DBI interface on pipe %d...\n", pipe
);
664 REG_WRITE((MIPIA_DEVICE_READY_REG
+ reg_offset
), 0x00000000);
666 /*init dsi adapter before kicking off*/
667 REG_WRITE((MIPIA_CONTROL_REG
+ reg_offset
), 0x00000018);
669 /*TODO: figure out how to setup these registers*/
670 REG_WRITE((MIPIA_DPHY_PARAM_REG
+ reg_offset
), 0x150c3408);
671 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG
+ reg_offset
),
673 REG_WRITE((MIPIA_DBI_BW_CTRL_REG
+ reg_offset
), 0x00000400);
674 REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG
+ reg_offset
), 0x00000001);
675 REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG
+ reg_offset
), 0x00000000);
677 /*enable all interrupts*/
678 REG_WRITE((MIPIA_INTR_EN_REG
+ reg_offset
), 0xffffffff);
679 /*max value: 20 clock cycles of txclkesc*/
680 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG
+ reg_offset
), 0x0000001f);
681 /*min 21 txclkesc, max: ffffh*/
682 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG
+ reg_offset
), 0x0000ffff);
683 /*min: 7d0 max: 4e20*/
684 REG_WRITE((MIPIA_INIT_COUNT_REG
+ reg_offset
), 0x00000fa0);
688 val
|= (dsi_config
->channel_num
<< DSI_DBI_VIRT_CHANNEL_OFFSET
);
689 val
|= DSI_DBI_COLOR_FORMAT_OPTION2
;
690 REG_WRITE((MIPIA_DSI_FUNC_PRG_REG
+ reg_offset
), val
);
692 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG
+ reg_offset
), 0x3fffff);
693 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG
+ reg_offset
), 0xffff);
695 /*de-assert dbi_stall when half of DBI FIFO is empty*/
696 /* REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000000); */
698 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG
+ reg_offset
), 0x46);
699 REG_WRITE((MIPIA_EOT_DISABLE_REG
+ reg_offset
), 0x00000000);
700 REG_WRITE((MIPIA_LP_BYTECLK_REG
+ reg_offset
), 0x00000004);
701 REG_WRITE((MIPIA_DEVICE_READY_REG
+ reg_offset
), 0x00000001);
705 /*DBI encoder helper funcs*/
706 static const struct drm_encoder_helper_funcs mdfld_dsi_dbi_helper_funcs
= {
707 .dpms
= mdfld_dsi_dbi_dpms
,
708 .mode_fixup
= mdfld_dsi_dbi_mode_fixup
,
709 .prepare
= mdfld_dsi_dbi_prepare
,
710 .mode_set
= mdfld_dsi_dbi_mode_set
,
711 .commit
= mdfld_dsi_dbi_commit
,
714 /*DBI encoder funcs*/
715 static const struct drm_encoder_funcs mdfld_dsi_dbi_encoder_funcs
= {
716 .destroy
= drm_encoder_cleanup
,
721 static int mdfld_dbi_panel_reset(struct mdfld_dsi_dbi_output
*output
)
726 switch (output
->channel_num
) {
734 pr_err("Invalid output\n");
738 ret
= gpio_request(gpio
, "gfx");
740 pr_err("gpio_rqueset failed\n");
744 ret
= gpio_direction_output(gpio
, 1);
746 pr_err("gpio_direction_output failed\n");
751 if (gpio_is_valid(gpio
))
758 * Init DSI DBI encoder.
759 * Allocate an mdfld_dsi_encoder and attach it to given @dsi_connector
760 * return pointer of newly allocated DBI encoder, NULL on error
762 struct mdfld_dsi_encoder
*mdfld_dsi_dbi_init(struct drm_device
*dev
,
763 struct mdfld_dsi_connector
*dsi_connector
,
764 struct panel_funcs
*p_funcs
)
766 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
767 struct mdfld_dsi_dbi_output
*dbi_output
= NULL
;
768 struct mdfld_dsi_config
*dsi_config
;
769 struct drm_connector
*connector
= NULL
;
770 struct drm_encoder
*encoder
= NULL
;
771 struct drm_display_mode
*fixed_mode
= NULL
;
772 struct psb_gtt
*pg
= dev_priv
? (dev_priv
->pg
) : NULL
;
774 #ifdef CONFIG_MDFLD_DSI_DPU
775 struct mdfld_dbi_dpu_info
*dpu_info
= dev_priv
? (dev_priv
->dbi_dpu_info
) : NULL
;
777 struct mdfld_dbi_dsr_info
*dsr_info
= dev_priv
? (dev_priv
->dbi_dsr_info
) : NULL
;
781 if (!pg
|| !dsi_connector
) {
786 dbi_output
= kzalloc(sizeof(struct mdfld_dsi_dbi_output
), GFP_KERNEL
);
788 dev_err(dev
->dev
, "No memory\n");
792 if (dsi_connector
->pipe
== 0) {
793 dbi_output
->channel_num
= 0;
794 dev_priv
->dbi_output
= dbi_output
;
795 } else if (dsi_connector
->pipe
== 2) {
796 dbi_output
->channel_num
= 1;
797 dev_priv
->dbi_output2
= dbi_output
;
799 dev_err(dev
->dev
, "only support 2 DSI outputs\n");
803 dbi_output
->dev
= dev
;
804 dbi_output
->p_funcs
= p_funcs
;
807 ret
= mdfld_dbi_panel_reset(dbi_output
);
809 dev_err(dev
->dev
, "reset panel error\n");
813 /*TODO: get panel info from DDB*/
816 dsi_config
= mdfld_dsi_get_config(dsi_connector
);
817 fixed_mode
= dsi_config
->fixed_mode
;
819 dbi_output
->panel_fixed_mode
= fixed_mode
;
821 /*create drm encoder object*/
822 connector
= &dsi_connector
->base
.base
;
823 encoder
= &dbi_output
->base
.base
;
824 drm_encoder_init(dev
,
826 p_funcs
->encoder_funcs
,
827 DRM_MODE_ENCODER_MIPI
);
828 drm_encoder_helper_add(encoder
, p_funcs
->encoder_helper_funcs
);
830 /*attach to given connector*/
831 drm_mode_connector_attach_encoder(connector
, encoder
);
833 /*set possible crtcs and clones*/
834 if (dsi_connector
->pipe
) {
835 encoder
->possible_crtcs
= (1 << 2);
836 encoder
->possible_clones
= (1 << 1);
838 encoder
->possible_crtcs
= (1 << 0);
839 encoder
->possible_clones
= (1 << 0);
842 dev_priv
->dsr_fb_update
= 0;
843 dev_priv
->dsr_enable
= false;
844 dev_priv
->exit_idle
= mdfld_dsi_dbi_exit_dsr
;
845 #if defined(CONFIG_MDFLD_DSI_DPU) || defined(CONFIG_MDFLD_DSI_DSR)
846 dev_priv
->dsr_enable_config
= false;
847 #endif /*CONFIG_MDFLD_DSI_DSR*/
849 dbi_output
->first_boot
= true;
850 dbi_output
->mode_flags
= MODE_SETTING_IN_ENCODER
;
852 #ifdef CONFIG_MDFLD_DSI_DPU
853 /*add this output to dpu_info*/
854 if (dsi_connector
->pipe
== 0)
855 dpu_info
->dbi_outputs
[0] = dbi_output
;
857 dpu_info
->dbi_outputs
[1] = dbi_output
;
859 dpu_info
->dbi_output_num
++;
860 #else /*CONFIG_MDFLD_DSI_DPU*/
861 /*add this output to dsr_info*/
862 if (dsi_connector
->pipe
== 0)
863 dsr_info
->dbi_outputs
[0] = dbi_output
;
865 dsr_info
->dbi_outputs
[1] = dbi_output
;
866 dsr_info
->dbi_output_num
++;
868 return &dbi_output
->base
;